1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
9 extern struct rtl83xx_soc_info soc_info
;
11 extern const struct rtl838x_reg rtl838x_reg
;
12 extern const struct rtl838x_reg rtl839x_reg
;
13 extern const struct rtl838x_reg rtl930x_reg
;
14 extern const struct rtl838x_reg rtl931x_reg
;
16 extern const struct dsa_switch_ops rtl83xx_switch_ops
;
17 extern const struct dsa_switch_ops rtl930x_switch_ops
;
19 DEFINE_MUTEX(smi_lock
);
21 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv
*priv
, int port
)
27 int n
= priv
->port_width
<< 1;
29 /* Ports above or equal CPU port can never be configured */
30 if (port
>= priv
->cpu_port
)
33 mutex_lock(&priv
->reg_mutex
);
35 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
36 if (priv
->family_id
== RTL8390_FAMILY_ID
)
38 if (priv
->family_id
== RTL9300_FAMILY_ID
)
40 if (priv
->family_id
== RTL9310_FAMILY_ID
)
43 index
= n
- (pos
>> 4) - 1;
44 bit
= (pos
<< 1) % 32;
46 priv
->r
->stp_get(priv
, msti
, port_state
);
48 mutex_unlock(&priv
->reg_mutex
);
50 return (port_state
[index
] >> bit
) & 3;
53 static struct table_reg rtl838x_tbl_regs
[] = {
54 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
55 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
56 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
58 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
59 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
60 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
61 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
63 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
64 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
65 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
66 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
67 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
68 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
70 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
71 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
72 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
73 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
74 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
75 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
78 void rtl_table_init(void)
82 for (i
= 0; i
< RTL_TBL_END
; i
++)
83 mutex_init(&rtl838x_tbl_regs
[i
].lock
);
87 * Request access to table t in table access register r
88 * Returns a handle to a lock for that table
90 struct table_reg
*rtl_table_get(rtl838x_tbl_reg_t r
, int t
)
95 if (t
>= BIT(rtl838x_tbl_regs
[r
].c_bit
-rtl838x_tbl_regs
[r
].t_bit
))
98 mutex_lock(&rtl838x_tbl_regs
[r
].lock
);
99 rtl838x_tbl_regs
[r
].tbl
= t
;
101 return &rtl838x_tbl_regs
[r
];
105 * Release a table r, unlock the corresponding lock
107 void rtl_table_release(struct table_reg
*r
)
112 // pr_info("Unlocking %08x\n", (u32)r);
113 mutex_unlock(&r
->lock
);
114 // pr_info("Unlock done\n");
118 * Reads table index idx into the data registers of the table
120 void rtl_table_read(struct table_reg
*r
, int idx
)
122 u32 cmd
= r
->rmode
? BIT(r
->c_bit
) : 0;
124 cmd
|= BIT(r
->c_bit
+ 1) | (r
->tbl
<< r
->t_bit
) | (idx
& (BIT(r
->t_bit
) - 1));
125 sw_w32(cmd
, r
->addr
);
126 do { } while (sw_r32(r
->addr
) & BIT(r
->c_bit
+ 1));
130 * Writes the content of the table data registers into the table at index idx
132 void rtl_table_write(struct table_reg
*r
, int idx
)
134 u32 cmd
= r
->rmode
? 0 : BIT(r
->c_bit
);
136 cmd
|= BIT(r
->c_bit
+ 1) | (r
->tbl
<< r
->t_bit
) | (idx
& (BIT(r
->t_bit
) - 1));
137 sw_w32(cmd
, r
->addr
);
138 do { } while (sw_r32(r
->addr
) & BIT(r
->c_bit
+ 1));
142 * Returns the address of the ith data register of table register r
143 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
145 inline u16
rtl_table_data(struct table_reg
*r
, int i
)
147 if (i
>= r
->max_data
)
149 return r
->data
+ i
* 4;
152 inline u32
rtl_table_data_r(struct table_reg
*r
, int i
)
154 return sw_r32(rtl_table_data(r
, i
));
157 inline void rtl_table_data_w(struct table_reg
*r
, u32 v
, int i
)
159 sw_w32(v
, rtl_table_data(r
, i
));
162 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
163 void rtl838x_mask_port_reg(u64 clear
, u64 set
, int reg
)
165 sw_w32_mask((u32
)clear
, (u32
)set
, reg
);
168 void rtl838x_set_port_reg(u64 set
, int reg
)
170 sw_w32((u32
)set
, reg
);
173 u64
rtl838x_get_port_reg(int reg
)
175 return ((u64
) sw_r32(reg
));
178 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
179 void rtl839x_mask_port_reg_be(u64 clear
, u64 set
, int reg
)
181 sw_w32_mask((u32
)(clear
>> 32), (u32
)(set
>> 32), reg
);
182 sw_w32_mask((u32
)(clear
& 0xffffffff), (u32
)(set
& 0xffffffff), reg
+ 4);
185 u64
rtl839x_get_port_reg_be(int reg
)
190 v
|= sw_r32(reg
+ 4);
194 void rtl839x_set_port_reg_be(u64 set
, int reg
)
196 sw_w32(set
>> 32, reg
);
197 sw_w32(set
& 0xffffffff, reg
+ 4);
200 void rtl839x_mask_port_reg_le(u64 clear
, u64 set
, int reg
)
202 sw_w32_mask((u32
)clear
, (u32
)set
, reg
);
203 sw_w32_mask((u32
)(clear
>> 32), (u32
)(set
>> 32), reg
+ 4);
206 void rtl839x_set_port_reg_le(u64 set
, int reg
)
209 sw_w32(set
>> 32, reg
+ 4);
212 u64
rtl839x_get_port_reg_le(int reg
)
214 u64 v
= sw_r32(reg
+ 4);
221 int read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
223 switch (soc_info
.family
) {
224 case RTL8380_FAMILY_ID
:
225 return rtl838x_read_phy(port
, page
, reg
, val
);
226 case RTL8390_FAMILY_ID
:
227 return rtl839x_read_phy(port
, page
, reg
, val
);
228 case RTL9300_FAMILY_ID
:
229 return rtl930x_read_phy(port
, page
, reg
, val
);
230 case RTL9310_FAMILY_ID
:
231 return rtl931x_read_phy(port
, page
, reg
, val
);
236 int write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
238 switch (soc_info
.family
) {
239 case RTL8380_FAMILY_ID
:
240 return rtl838x_write_phy(port
, page
, reg
, val
);
241 case RTL8390_FAMILY_ID
:
242 return rtl839x_write_phy(port
, page
, reg
, val
);
243 case RTL9300_FAMILY_ID
:
244 return rtl930x_write_phy(port
, page
, reg
, val
);
245 case RTL9310_FAMILY_ID
:
246 return rtl931x_write_phy(port
, page
, reg
, val
);
251 static int __init
rtl83xx_mdio_probe(struct rtl838x_switch_priv
*priv
)
253 struct device
*dev
= priv
->dev
;
254 struct device_node
*dn
, *mii_np
= dev
->of_node
;
259 pr_debug("In %s\n", __func__
);
260 mii_np
= of_find_compatible_node(NULL
, NULL
, "realtek,rtl838x-mdio");
262 pr_debug("Found compatible MDIO node!\n");
264 dev_err(priv
->dev
, "no %s child node found", "mdio-bus");
268 priv
->mii_bus
= of_mdio_find_bus(mii_np
);
269 if (!priv
->mii_bus
) {
270 pr_debug("Deferring probe of mdio bus\n");
271 return -EPROBE_DEFER
;
273 if (!of_device_is_available(mii_np
))
276 bus
= devm_mdiobus_alloc(priv
->ds
->dev
);
280 bus
->name
= "rtl838x slave mii";
283 * Since the NIC driver is loaded first, we can use the mdio rw functions
286 bus
->read
= priv
->mii_bus
->read
;
287 bus
->write
= priv
->mii_bus
->write
;
288 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s-%d", bus
->name
, dev
->id
);
291 priv
->ds
->slave_mii_bus
= bus
;
292 priv
->ds
->slave_mii_bus
->priv
= priv
;
294 ret
= mdiobus_register(priv
->ds
->slave_mii_bus
);
301 for_each_node_by_name(dn
, "ethernet-phy") {
302 if (of_property_read_u32(dn
, "reg", &pn
))
305 // Check for the integrated SerDes of the RTL8380M first
306 if (of_property_read_bool(dn
, "phy-is-integrated")
307 && priv
->id
== 0x8380 && pn
>= 24) {
308 pr_debug("----> FÓUND A SERDES\n");
309 priv
->ports
[pn
].phy
= PHY_RTL838X_SDS
;
313 if (of_property_read_bool(dn
, "phy-is-integrated")
314 && !of_property_read_bool(dn
, "sfp")) {
315 priv
->ports
[pn
].phy
= PHY_RTL8218B_INT
;
319 if (!of_property_read_bool(dn
, "phy-is-integrated")
320 && of_property_read_bool(dn
, "sfp")) {
321 priv
->ports
[pn
].phy
= PHY_RTL8214FC
;
325 if (!of_property_read_bool(dn
, "phy-is-integrated")
326 && !of_property_read_bool(dn
, "sfp")) {
327 priv
->ports
[pn
].phy
= PHY_RTL8218B_EXT
;
332 // TODO: Do this needs to come from the .dts, at least the SerDes number
333 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
334 priv
->ports
[24].is2G5
= true;
335 priv
->ports
[25].is2G5
= true;
336 priv
->ports
[24].sds_num
= 1;
337 priv
->ports
[24].sds_num
= 2;
340 /* Disable MAC polling the PHY so that we can start configuration */
341 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
343 /* Enable PHY control via SoC */
344 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
345 /* Enable SerDes NWAY and PHY control via SoC */
346 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL
);
348 /* Disable PHY polling via SoC */
349 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL
);
352 /* Power on fibre ports and reset them if necessary */
353 if (priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
354 pr_debug("Powering on fibre ports & reset\n");
355 rtl8380_sds_power(24, 1);
356 rtl8380_sds_power(26, 1);
359 // TODO: Only power on SerDes with external PHYs connected
360 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
361 pr_info("RTL9300 Powering on SerDes ports\n");
362 rtl9300_sds_power(24, 1);
363 rtl9300_sds_power(25, 1);
364 rtl9300_sds_power(26, 1);
365 rtl9300_sds_power(27, 1);
368 pr_debug("%s done\n", __func__
);
372 static int __init
rtl83xx_get_l2aging(struct rtl838x_switch_priv
*priv
)
374 int t
= sw_r32(priv
->r
->l2_ctrl_1
);
376 t
&= priv
->family_id
== RTL8380_FAMILY_ID
? 0x7fffff : 0x1FFFFF;
378 if (priv
->family_id
== RTL8380_FAMILY_ID
)
379 t
= t
* 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
383 pr_debug("L2 AGING time: %d sec\n", t
);
384 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv
->r
->l2_port_aging_out
));
388 /* Caller must hold priv->reg_mutex */
389 int rtl83xx_lag_add(struct dsa_switch
*ds
, int group
, int port
)
391 struct rtl838x_switch_priv
*priv
= ds
->priv
;
394 pr_info("%s: Adding port %d to LA-group %d\n", __func__
, port
, group
);
395 if (group
>= priv
->n_lags
) {
396 pr_err("Link Agrregation group too large.\n");
400 if (port
>= priv
->cpu_port
) {
401 pr_err("Invalid port number.\n");
405 for (i
= 0; i
< priv
->n_lags
; i
++) {
406 if (priv
->lags_port_members
[i
] & BIT_ULL(i
))
409 if (i
!= priv
->n_lags
) {
410 pr_err("%s: Port already member of LAG: %d\n", __func__
, i
);
414 priv
->r
->mask_port_reg_be(0, BIT_ULL(port
), priv
->r
->trk_mbr_ctr(group
));
415 priv
->lags_port_members
[group
] |= BIT_ULL(port
);
417 pr_info("lags_port_members %d now %016llx\n", group
, priv
->lags_port_members
[group
]);
421 /* Caller must hold priv->reg_mutex */
422 int rtl83xx_lag_del(struct dsa_switch
*ds
, int group
, int port
)
424 struct rtl838x_switch_priv
*priv
= ds
->priv
;
426 pr_info("%s: Removing port %d from LA-group %d\n", __func__
, port
, group
);
428 if (group
>= priv
->n_lags
) {
429 pr_err("Link Agrregation group too large.\n");
433 if (port
>= priv
->cpu_port
) {
434 pr_err("Invalid port number.\n");
439 if (!(priv
->lags_port_members
[group
] & BIT_ULL(port
))) {
440 pr_err("%s: Port not member of LAG: %d\n", __func__
, group
445 priv
->r
->mask_port_reg_be(BIT_ULL(port
), 0, priv
->r
->trk_mbr_ctr(group
));
446 priv
->lags_port_members
[group
] &= ~BIT_ULL(port
);
448 pr_info("lags_port_members %d now %016llx\n", group
, priv
->lags_port_members
[group
]);
452 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv
*priv
,
453 struct net_device
*ndev
,
454 struct netdev_notifier_changeupper_info
*info
)
456 struct net_device
*upper
= info
->upper_dev
;
459 if (!netif_is_lag_master(upper
))
462 mutex_lock(&priv
->reg_mutex
);
464 for (i
= 0; i
< priv
->n_lags
; i
++) {
465 if ((!priv
->lag_devs
[i
]) || (priv
->lag_devs
[i
] == upper
))
468 for (j
= 0; j
< priv
->cpu_port
; j
++) {
469 if (priv
->ports
[j
].dp
->slave
== ndev
)
472 if (j
>= priv
->cpu_port
) {
478 if (!priv
->lag_devs
[i
])
479 priv
->lag_devs
[i
] = upper
;
480 err
= rtl83xx_lag_add(priv
->ds
, i
, priv
->ports
[j
].dp
->index
);
486 if (!priv
->lag_devs
[i
])
488 err
= rtl83xx_lag_del(priv
->ds
, i
, priv
->ports
[j
].dp
->index
);
493 if (!priv
->lags_port_members
[i
])
494 priv
->lag_devs
[i
] = NULL
;
498 mutex_unlock(&priv
->reg_mutex
);
502 static int rtl83xx_netdevice_event(struct notifier_block
*this,
503 unsigned long event
, void *ptr
)
505 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
506 struct rtl838x_switch_priv
*priv
;
509 pr_debug("In: %s, event: %lu\n", __func__
, event
);
511 if ((event
!= NETDEV_CHANGEUPPER
) && (event
!= NETDEV_CHANGELOWERSTATE
))
514 priv
= container_of(this, struct rtl838x_switch_priv
, nb
);
516 case NETDEV_CHANGEUPPER
:
517 err
= rtl83xx_handle_changeupper(priv
, ndev
, ptr
);
527 static int __init
rtl83xx_sw_probe(struct platform_device
*pdev
)
530 struct rtl838x_switch_priv
*priv
;
531 struct device
*dev
= &pdev
->dev
;
534 pr_debug("Probing RTL838X switch device\n");
535 if (!pdev
->dev
.of_node
) {
536 dev_err(dev
, "No DT found\n");
540 // Initialize access to RTL switch tables
543 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
547 priv
->ds
= devm_kzalloc(dev
, sizeof(*priv
->ds
), GFP_KERNEL
);
552 priv
->ds
->priv
= priv
;
553 priv
->ds
->ops
= &rtl83xx_switch_ops
;
556 priv
->family_id
= soc_info
.family
;
557 priv
->id
= soc_info
.id
;
558 switch(soc_info
.family
) {
559 case RTL8380_FAMILY_ID
:
560 priv
->ds
->ops
= &rtl83xx_switch_ops
;
561 priv
->cpu_port
= RTL838X_CPU_PORT
;
562 priv
->port_mask
= 0x1f;
563 priv
->port_width
= 1;
564 priv
->irq_mask
= 0x0FFFFFFF;
565 priv
->r
= &rtl838x_reg
;
566 priv
->ds
->num_ports
= 29;
567 priv
->fib_entries
= 8192;
568 rtl8380_get_version(priv
);
570 priv
->l2_bucket_size
= 4;
572 case RTL8390_FAMILY_ID
:
573 priv
->ds
->ops
= &rtl83xx_switch_ops
;
574 priv
->cpu_port
= RTL839X_CPU_PORT
;
575 priv
->port_mask
= 0x3f;
576 priv
->port_width
= 2;
577 priv
->irq_mask
= 0xFFFFFFFFFFFFFULL
;
578 priv
->r
= &rtl839x_reg
;
579 priv
->ds
->num_ports
= 53;
580 priv
->fib_entries
= 16384;
581 rtl8390_get_version(priv
);
583 priv
->l2_bucket_size
= 4;
585 case RTL9300_FAMILY_ID
:
586 priv
->ds
->ops
= &rtl930x_switch_ops
;
587 priv
->cpu_port
= RTL930X_CPU_PORT
;
588 priv
->port_mask
= 0x1f;
589 priv
->port_width
= 1;
590 priv
->irq_mask
= 0x0FFFFFFF;
591 priv
->r
= &rtl930x_reg
;
592 priv
->ds
->num_ports
= 29;
593 priv
->fib_entries
= 16384;
594 priv
->version
= RTL8390_VERSION_A
;
596 sw_w32(1, RTL930X_ST_CTRL
);
597 priv
->l2_bucket_size
= 8;
599 case RTL9310_FAMILY_ID
:
600 priv
->ds
->ops
= &rtl930x_switch_ops
;
601 priv
->cpu_port
= RTL931X_CPU_PORT
;
602 priv
->port_mask
= 0x3f;
603 priv
->port_width
= 2;
604 priv
->irq_mask
= 0xFFFFFFFFFFFFFULL
;
605 priv
->r
= &rtl931x_reg
;
606 priv
->ds
->num_ports
= 57;
607 priv
->fib_entries
= 16384;
608 priv
->version
= RTL8390_VERSION_A
;
610 priv
->l2_bucket_size
= 8;
613 pr_debug("Chip version %c\n", priv
->version
);
615 err
= rtl83xx_mdio_probe(priv
);
617 /* Probing fails the 1st time because of missing ethernet driver
618 * initialization. Use this to disable traffic in case the bootloader left if on
622 err
= dsa_register_switch(priv
->ds
);
624 dev_err(dev
, "Error registering switch: %d\n", err
);
629 * dsa_to_port returns dsa_port from the port list in
630 * dsa_switch_tree, the tree is built when the switch
631 * is registered by dsa_register_switch
633 for (i
= 0; i
<= priv
->cpu_port
; i
++)
634 priv
->ports
[i
].dp
= dsa_to_port(priv
->ds
, i
);
636 /* Enable link and media change interrupts. Are the SERDES masks needed? */
637 sw_w32_mask(0, 3, priv
->r
->isr_glb_src
);
639 priv
->r
->set_port_reg_le(priv
->irq_mask
, priv
->r
->isr_port_link_sts_chg
);
640 priv
->r
->set_port_reg_le(priv
->irq_mask
, priv
->r
->imr_port_link_sts_chg
);
642 priv
->link_state_irq
= platform_get_irq(pdev
, 0);
643 pr_info("LINK state irq: %d\n", priv
->link_state_irq
);
644 switch (priv
->family_id
) {
645 case RTL8380_FAMILY_ID
:
646 err
= request_irq(priv
->link_state_irq
, rtl838x_switch_irq
,
647 IRQF_SHARED
, "rtl838x-link-state", priv
->ds
);
649 case RTL8390_FAMILY_ID
:
650 err
= request_irq(priv
->link_state_irq
, rtl839x_switch_irq
,
651 IRQF_SHARED
, "rtl839x-link-state", priv
->ds
);
653 case RTL9300_FAMILY_ID
:
654 err
= request_irq(priv
->link_state_irq
, rtl930x_switch_irq
,
655 IRQF_SHARED
, "rtl930x-link-state", priv
->ds
);
657 case RTL9310_FAMILY_ID
:
658 err
= request_irq(priv
->link_state_irq
, rtl931x_switch_irq
,
659 IRQF_SHARED
, "rtl931x-link-state", priv
->ds
);
663 dev_err(dev
, "Error setting up switch interrupt.\n");
664 /* Need to free allocated switch here */
667 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
668 if (soc_info
.family
!= RTL9310_FAMILY_ID
)
669 sw_w32(0x1, priv
->r
->imr_glb
);
671 rtl83xx_get_l2aging(priv
);
673 rtl83xx_setup_qos(priv
);
675 /* Clear all destination ports for mirror groups */
676 for (i
= 0; i
< 4; i
++)
677 priv
->mirror_group_ports
[i
] = -1;
679 priv
->nb
.notifier_call
= rtl83xx_netdevice_event
;
680 if (register_netdevice_notifier(&priv
->nb
)) {
681 priv
->nb
.notifier_call
= NULL
;
682 dev_err(dev
, "Failed to register LAG netdev notifier\n");
685 // Flood BPDUs to all ports including cpu-port
686 if (soc_info
.family
!= RTL9300_FAMILY_ID
) { // TODO: Port this functionality
687 bpdu_mask
= soc_info
.family
== RTL8380_FAMILY_ID
? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
688 priv
->r
->set_port_reg_be(bpdu_mask
, priv
->r
->rma_bpdu_fld_pmask
);
690 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
691 sw_w32(7, priv
->r
->spcl_trap_eapol_ctrl
);
693 rtl838x_dbgfs_init(priv
);
699 static int rtl83xx_sw_remove(struct platform_device
*pdev
)
702 pr_debug("Removing platform driver for rtl83xx-sw\n");
706 static const struct of_device_id rtl83xx_switch_of_ids
[] = {
707 { .compatible
= "realtek,rtl83xx-switch"},
712 MODULE_DEVICE_TABLE(of
, rtl83xx_switch_of_ids
);
714 static struct platform_driver rtl83xx_switch_driver
= {
715 .probe
= rtl83xx_sw_probe
,
716 .remove
= rtl83xx_sw_remove
,
718 .name
= "rtl83xx-switch",
720 .of_match_table
= rtl83xx_switch_of_ids
,
724 module_platform_driver(rtl83xx_switch_driver
);
726 MODULE_AUTHOR("B. Koblitz");
727 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
728 MODULE_LICENSE("GPL");