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realtek: Improve MDIO bus probing for RTL9300
[openwrt/staging/dedeckeh.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5 #include <net/arp.h>
6 #include <net/nexthop.h>
7 #include <net/neighbour.h>
8 #include <net/netevent.h>
9 #include <linux/inetdevice.h>
10
11 #include <asm/mach-rtl838x/mach-rtl83xx.h>
12 #include "rtl83xx.h"
13
14 extern struct rtl83xx_soc_info soc_info;
15
16 extern const struct rtl838x_reg rtl838x_reg;
17 extern const struct rtl838x_reg rtl839x_reg;
18 extern const struct rtl838x_reg rtl930x_reg;
19 extern const struct rtl838x_reg rtl931x_reg;
20
21 extern const struct dsa_switch_ops rtl83xx_switch_ops;
22 extern const struct dsa_switch_ops rtl930x_switch_ops;
23
24 DEFINE_MUTEX(smi_lock);
25
26 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
27 {
28 u32 msti = 0;
29 u32 port_state[4];
30 int index, bit;
31 int pos = port;
32 int n = priv->port_width << 1;
33
34 /* Ports above or equal CPU port can never be configured */
35 if (port >= priv->cpu_port)
36 return -1;
37
38 mutex_lock(&priv->reg_mutex);
39
40 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
41 if (priv->family_id == RTL8390_FAMILY_ID)
42 pos += 12;
43 if (priv->family_id == RTL9300_FAMILY_ID)
44 pos += 3;
45 if (priv->family_id == RTL9310_FAMILY_ID)
46 pos += 8;
47
48 index = n - (pos >> 4) - 1;
49 bit = (pos << 1) % 32;
50
51 priv->r->stp_get(priv, msti, port_state);
52
53 mutex_unlock(&priv->reg_mutex);
54
55 return (port_state[index] >> bit) & 3;
56 }
57
58 static struct table_reg rtl838x_tbl_regs[] = {
59 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
60 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
61 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
62
63 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
64 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
65 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
66 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
67
68 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
69 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
70 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
71 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
72 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
73 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
74
75 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
76 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
77 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
78 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
79 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
80 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
81 };
82
83 void rtl_table_init(void)
84 {
85 int i;
86
87 for (i = 0; i < RTL_TBL_END; i++)
88 mutex_init(&rtl838x_tbl_regs[i].lock);
89 }
90
91 /*
92 * Request access to table t in table access register r
93 * Returns a handle to a lock for that table
94 */
95 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
96 {
97 if (r >= RTL_TBL_END)
98 return NULL;
99
100 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
101 return NULL;
102
103 mutex_lock(&rtl838x_tbl_regs[r].lock);
104 rtl838x_tbl_regs[r].tbl = t;
105
106 return &rtl838x_tbl_regs[r];
107 }
108
109 /*
110 * Release a table r, unlock the corresponding lock
111 */
112 void rtl_table_release(struct table_reg *r)
113 {
114 if (!r)
115 return;
116
117 // pr_info("Unlocking %08x\n", (u32)r);
118 mutex_unlock(&r->lock);
119 // pr_info("Unlock done\n");
120 }
121
122 /*
123 * Reads table index idx into the data registers of the table
124 */
125 void rtl_table_read(struct table_reg *r, int idx)
126 {
127 u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
128
129 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
130 sw_w32(cmd, r->addr);
131 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
132 }
133
134 /*
135 * Writes the content of the table data registers into the table at index idx
136 */
137 void rtl_table_write(struct table_reg *r, int idx)
138 {
139 u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
140
141 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
142 sw_w32(cmd, r->addr);
143 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
144 }
145
146 /*
147 * Returns the address of the ith data register of table register r
148 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
149 */
150 inline u16 rtl_table_data(struct table_reg *r, int i)
151 {
152 if (i >= r->max_data)
153 i = r->max_data - 1;
154 return r->data + i * 4;
155 }
156
157 inline u32 rtl_table_data_r(struct table_reg *r, int i)
158 {
159 return sw_r32(rtl_table_data(r, i));
160 }
161
162 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
163 {
164 sw_w32(v, rtl_table_data(r, i));
165 }
166
167 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
168 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
169 {
170 sw_w32_mask((u32)clear, (u32)set, reg);
171 }
172
173 void rtl838x_set_port_reg(u64 set, int reg)
174 {
175 sw_w32((u32)set, reg);
176 }
177
178 u64 rtl838x_get_port_reg(int reg)
179 {
180 return ((u64) sw_r32(reg));
181 }
182
183 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
184 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
185 {
186 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
187 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
188 }
189
190 u64 rtl839x_get_port_reg_be(int reg)
191 {
192 u64 v = sw_r32(reg);
193
194 v <<= 32;
195 v |= sw_r32(reg + 4);
196 return v;
197 }
198
199 void rtl839x_set_port_reg_be(u64 set, int reg)
200 {
201 sw_w32(set >> 32, reg);
202 sw_w32(set & 0xffffffff, reg + 4);
203 }
204
205 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
206 {
207 sw_w32_mask((u32)clear, (u32)set, reg);
208 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
209 }
210
211 void rtl839x_set_port_reg_le(u64 set, int reg)
212 {
213 sw_w32(set, reg);
214 sw_w32(set >> 32, reg + 4);
215 }
216
217 u64 rtl839x_get_port_reg_le(int reg)
218 {
219 u64 v = sw_r32(reg + 4);
220
221 v <<= 32;
222 v |= sw_r32(reg);
223 return v;
224 }
225
226 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
227 {
228 switch (soc_info.family) {
229 case RTL8380_FAMILY_ID:
230 return rtl838x_read_phy(port, page, reg, val);
231 case RTL8390_FAMILY_ID:
232 return rtl839x_read_phy(port, page, reg, val);
233 case RTL9300_FAMILY_ID:
234 return rtl930x_read_phy(port, page, reg, val);
235 case RTL9310_FAMILY_ID:
236 return rtl931x_read_phy(port, page, reg, val);
237 }
238 return -1;
239 }
240
241 int write_phy(u32 port, u32 page, u32 reg, u32 val)
242 {
243 switch (soc_info.family) {
244 case RTL8380_FAMILY_ID:
245 return rtl838x_write_phy(port, page, reg, val);
246 case RTL8390_FAMILY_ID:
247 return rtl839x_write_phy(port, page, reg, val);
248 case RTL9300_FAMILY_ID:
249 return rtl930x_write_phy(port, page, reg, val);
250 case RTL9310_FAMILY_ID:
251 return rtl931x_write_phy(port, page, reg, val);
252 }
253 return -1;
254 }
255
256 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
257 {
258 struct device *dev = priv->dev;
259 struct device_node *dn, *mii_np = dev->of_node;
260 struct mii_bus *bus;
261 int ret;
262 u32 pn;
263
264 pr_debug("In %s\n", __func__);
265 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
266 if (mii_np) {
267 pr_debug("Found compatible MDIO node!\n");
268 } else {
269 dev_err(priv->dev, "no %s child node found", "mdio-bus");
270 return -ENODEV;
271 }
272
273 priv->mii_bus = of_mdio_find_bus(mii_np);
274 if (!priv->mii_bus) {
275 pr_debug("Deferring probe of mdio bus\n");
276 return -EPROBE_DEFER;
277 }
278 if (!of_device_is_available(mii_np))
279 ret = -ENODEV;
280
281 bus = devm_mdiobus_alloc(priv->ds->dev);
282 if (!bus)
283 return -ENOMEM;
284
285 bus->name = "rtl838x slave mii";
286
287 /*
288 * Since the NIC driver is loaded first, we can use the mdio rw functions
289 * assigned there.
290 */
291 bus->read = priv->mii_bus->read;
292 bus->write = priv->mii_bus->write;
293 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
294
295 bus->parent = dev;
296 priv->ds->slave_mii_bus = bus;
297 priv->ds->slave_mii_bus->priv = priv;
298
299 ret = mdiobus_register(priv->ds->slave_mii_bus);
300 if (ret && mii_np) {
301 of_node_put(dn);
302 return ret;
303 }
304
305 dn = mii_np;
306 for_each_node_by_name(dn, "ethernet-phy") {
307 if (of_property_read_u32(dn, "reg", &pn))
308 continue;
309
310 // Check for the integrated SerDes of the RTL8380M first
311 if (of_property_read_bool(dn, "phy-is-integrated") && priv->id == 0x8380 && pn >= 24) {
312 pr_debug("----> FÓUND A SERDES\n");
313 priv->ports[pn].phy = PHY_RTL838X_SDS;
314 continue;
315 }
316
317 if (of_property_read_bool(dn, "phy-is-integrated") && !of_property_read_bool(dn, "sfp")) {
318 priv->ports[pn].phy = PHY_RTL8218B_INT;
319 continue;
320 }
321
322 if (!of_property_read_bool(dn, "phy-is-integrated") && of_property_read_bool(dn, "sfp")) {
323 priv->ports[pn].phy = PHY_RTL8214FC;
324 continue;
325 }
326
327 if (!of_property_read_bool(dn, "phy-is-integrated") && !of_property_read_bool(dn, "sfp")) {
328 priv->ports[pn].phy = PHY_RTL8218B_EXT;
329 continue;
330 }
331 }
332
333 // TODO: Do this needs to come from the .dts
334 if (priv->family_id == RTL9300_FAMILY_ID) {
335 priv->ports[24].is2G5 = true;
336 priv->ports[25].is2G5 = true;
337 }
338
339 /* Disable MAC polling the PHY so that we can start configuration */
340 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
341
342 /* Enable PHY control via SoC */
343 if (priv->family_id == RTL8380_FAMILY_ID) {
344 /* Enable SerDes NWAY and PHY control via SoC */
345 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
346 } else if (priv->family_id == RTL8390_FAMILY_ID) {
347 /* Disable PHY polling via SoC */
348 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
349 }
350
351 /* Power on fibre ports and reset them if necessary */
352 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
353 pr_debug("Powering on fibre ports & reset\n");
354 rtl8380_sds_power(24, 1);
355 rtl8380_sds_power(26, 1);
356 }
357
358 pr_debug("%s done\n", __func__);
359 return 0;
360 }
361
362 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
363 {
364 int t = sw_r32(priv->r->l2_ctrl_1);
365
366 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
367
368 if (priv->family_id == RTL8380_FAMILY_ID)
369 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
370 else
371 t = (t * 3) / 5;
372
373 pr_debug("L2 AGING time: %d sec\n", t);
374 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
375 return t;
376 }
377
378 /* Caller must hold priv->reg_mutex */
379 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port)
380 {
381 struct rtl838x_switch_priv *priv = ds->priv;
382 int i;
383
384 pr_info("%s: Adding port %d to LA-group %d\n", __func__, port, group);
385 if (group >= priv->n_lags) {
386 pr_err("Link Agrregation group too large.\n");
387 return -EINVAL;
388 }
389
390 if (port >= priv->cpu_port) {
391 pr_err("Invalid port number.\n");
392 return -EINVAL;
393 }
394
395 for (i = 0; i < priv->n_lags; i++) {
396 if (priv->lags_port_members[i] & BIT_ULL(i))
397 break;
398 }
399 if (i != priv->n_lags) {
400 pr_err("%s: Port already member of LAG: %d\n", __func__, i);
401 return -ENOSPC;
402 }
403
404 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
405 priv->lags_port_members[group] |= BIT_ULL(port);
406
407 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
408 return 0;
409 }
410
411 /* Caller must hold priv->reg_mutex */
412 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
413 {
414 struct rtl838x_switch_priv *priv = ds->priv;
415
416 pr_info("%s: Removing port %d from LA-group %d\n", __func__, port, group);
417
418 if (group >= priv->n_lags) {
419 pr_err("Link Agrregation group too large.\n");
420 return -EINVAL;
421 }
422
423 if (port >= priv->cpu_port) {
424 pr_err("Invalid port number.\n");
425 return -EINVAL;
426 }
427
428
429 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
430 pr_err("%s: Port not member of LAG: %d\n", __func__, group
431 );
432 return -ENOSPC;
433 }
434
435 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
436 priv->lags_port_members[group] &= ~BIT_ULL(port);
437
438 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
439 return 0;
440 }
441
442 /*
443 * Allocate a 64 bit octet counter located in the LOG HW table
444 */
445 static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
446 {
447 int idx;
448
449 mutex_lock(&priv->reg_mutex);
450
451 idx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
452 if (idx >= priv->n_counters) {
453 mutex_unlock(&priv->reg_mutex);
454 return -1;
455 }
456
457 set_bit(idx, priv->octet_cntr_use_bm);
458 mutex_unlock(&priv->reg_mutex);
459
460 return idx;
461 }
462
463 /*
464 * Allocate a 32-bit packet counter
465 * 2 32-bit packet counters share the location of a 64-bit octet counter
466 * Initially there are no free packet counters and 2 new ones need to be freed
467 * by allocating the corresponding octet counter
468 */
469 int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv)
470 {
471 int idx, j;
472
473 mutex_lock(&priv->reg_mutex);
474
475 /* Because initially no packet counters are free, the logic is reversed:
476 * a 0-bit means the counter is already allocated (for octets)
477 */
478 idx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2);
479 if (idx >= priv->n_counters * 2) {
480 j = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
481 if (j >= priv->n_counters) {
482 mutex_unlock(&priv->reg_mutex);
483 return -1;
484 }
485 set_bit(j, priv->octet_cntr_use_bm);
486 idx = j * 2;
487 set_bit(j * 2 + 1, priv->packet_cntr_use_bm);
488
489 } else {
490 clear_bit(idx, priv->packet_cntr_use_bm);
491 }
492
493 mutex_unlock(&priv->reg_mutex);
494
495 return idx;
496 }
497
498 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
499 struct net_device *ndev,
500 struct netdev_notifier_changeupper_info *info)
501 {
502 struct net_device *upper = info->upper_dev;
503 int i, j, err;
504
505 if (!netif_is_lag_master(upper))
506 return 0;
507
508 mutex_lock(&priv->reg_mutex);
509
510 for (i = 0; i < priv->n_lags; i++) {
511 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
512 break;
513 }
514 for (j = 0; j < priv->cpu_port; j++) {
515 if (priv->ports[j].dp->slave == ndev)
516 break;
517 }
518 if (j >= priv->cpu_port) {
519 err = -EINVAL;
520 goto out;
521 }
522
523 if (info->linking) {
524 if (!priv->lag_devs[i])
525 priv->lag_devs[i] = upper;
526 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index);
527 if (err) {
528 err = -EINVAL;
529 goto out;
530 }
531 } else {
532 if (!priv->lag_devs[i])
533 err = -EINVAL;
534 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
535 if (err) {
536 err = -EINVAL;
537 goto out;
538 }
539 if (!priv->lags_port_members[i])
540 priv->lag_devs[i] = NULL;
541 }
542
543 out:
544 mutex_unlock(&priv->reg_mutex);
545 return 0;
546 }
547
548 /*
549 * Is the lower network device a DSA slave network device of our RTL930X-switch?
550 * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the
551 * DSA master device.
552 */
553 int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv)
554 {
555 int i;
556
557 // TODO: On 5.12:
558 // if(!dsa_slave_dev_check(dev)) {
559 // netdev_info(dev, "%s: not a DSA device.\n", __func__);
560 // return -EINVAL;
561 // }
562
563 for (i = 0; i < priv->cpu_port; i++) {
564 if (!priv->ports[i].dp)
565 continue;
566 if (priv->ports[i].dp->slave == dev)
567 return i;
568 }
569 return -EINVAL;
570 }
571
572 static int rtl83xx_netdevice_event(struct notifier_block *this,
573 unsigned long event, void *ptr)
574 {
575 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
576 struct rtl838x_switch_priv *priv;
577 int err;
578
579 pr_debug("In: %s, event: %lu\n", __func__, event);
580
581 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
582 return NOTIFY_DONE;
583
584 priv = container_of(this, struct rtl838x_switch_priv, nb);
585 switch (event) {
586 case NETDEV_CHANGEUPPER:
587 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
588 break;
589 }
590
591 if (err)
592 return err;
593
594 return NOTIFY_DONE;
595 }
596
597 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
598 {
599 int err = 0, i;
600 struct rtl838x_switch_priv *priv;
601 struct device *dev = &pdev->dev;
602 u64 bpdu_mask;
603
604 pr_debug("Probing RTL838X switch device\n");
605 if (!pdev->dev.of_node) {
606 dev_err(dev, "No DT found\n");
607 return -EINVAL;
608 }
609
610 // Initialize access to RTL switch tables
611 rtl_table_init();
612
613 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
614 if (!priv)
615 return -ENOMEM;
616
617 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
618
619 if (!priv->ds)
620 return -ENOMEM;
621 priv->ds->dev = dev;
622 priv->ds->priv = priv;
623 priv->ds->ops = &rtl83xx_switch_ops;
624 priv->dev = dev;
625
626 priv->family_id = soc_info.family;
627 priv->id = soc_info.id;
628 switch(soc_info.family) {
629 case RTL8380_FAMILY_ID:
630 priv->ds->ops = &rtl83xx_switch_ops;
631 priv->cpu_port = RTL838X_CPU_PORT;
632 priv->port_mask = 0x1f;
633 priv->port_width = 1;
634 priv->irq_mask = 0x0FFFFFFF;
635 priv->r = &rtl838x_reg;
636 priv->ds->num_ports = 29;
637 priv->fib_entries = 8192;
638 rtl8380_get_version(priv);
639 priv->n_lags = 8;
640 priv->l2_bucket_size = 4;
641 priv->n_pie_blocks = 12;
642 priv->port_ignore = 0x1f;
643 priv->n_counters = 128;
644 break;
645 case RTL8390_FAMILY_ID:
646 priv->ds->ops = &rtl83xx_switch_ops;
647 priv->cpu_port = RTL839X_CPU_PORT;
648 priv->port_mask = 0x3f;
649 priv->port_width = 2;
650 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
651 priv->r = &rtl839x_reg;
652 priv->ds->num_ports = 53;
653 priv->fib_entries = 16384;
654 rtl8390_get_version(priv);
655 priv->n_lags = 16;
656 priv->l2_bucket_size = 4;
657 priv->n_pie_blocks = 18;
658 priv->port_ignore = 0x3f;
659 priv->n_counters = 1024;
660 break;
661 case RTL9300_FAMILY_ID:
662 priv->ds->ops = &rtl930x_switch_ops;
663 priv->cpu_port = RTL930X_CPU_PORT;
664 priv->port_mask = 0x1f;
665 priv->port_width = 1;
666 priv->irq_mask = 0x0FFFFFFF;
667 priv->r = &rtl930x_reg;
668 priv->ds->num_ports = 29;
669 priv->fib_entries = 16384;
670 priv->version = RTL8390_VERSION_A;
671 priv->n_lags = 16;
672 sw_w32(1, RTL930X_ST_CTRL);
673 priv->l2_bucket_size = 8;
674 priv->n_pie_blocks = 16;
675 priv->port_ignore = 0x3f;
676 priv->n_counters = 2048;
677 break;
678 case RTL9310_FAMILY_ID:
679 priv->ds->ops = &rtl930x_switch_ops;
680 priv->cpu_port = RTL931X_CPU_PORT;
681 priv->port_mask = 0x3f;
682 priv->port_width = 2;
683 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
684 priv->r = &rtl931x_reg;
685 priv->ds->num_ports = 57;
686 priv->fib_entries = 16384;
687 priv->version = RTL8390_VERSION_A;
688 priv->n_lags = 16;
689 priv->l2_bucket_size = 8;
690 break;
691 }
692 pr_debug("Chip version %c\n", priv->version);
693
694 err = rtl83xx_mdio_probe(priv);
695 if (err) {
696 /* Probing fails the 1st time because of missing ethernet driver
697 * initialization. Use this to disable traffic in case the bootloader left if on
698 */
699 return err;
700 }
701 err = dsa_register_switch(priv->ds);
702 if (err) {
703 dev_err(dev, "Error registering switch: %d\n", err);
704 return err;
705 }
706
707 /*
708 * dsa_to_port returns dsa_port from the port list in
709 * dsa_switch_tree, the tree is built when the switch
710 * is registered by dsa_register_switch
711 */
712 for (i = 0; i <= priv->cpu_port; i++)
713 priv->ports[i].dp = dsa_to_port(priv->ds, i);
714
715 /* Enable link and media change interrupts. Are the SERDES masks needed? */
716 sw_w32_mask(0, 3, priv->r->isr_glb_src);
717
718 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
719 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
720
721 priv->link_state_irq = platform_get_irq(pdev, 0);
722 pr_info("LINK state irq: %d\n", priv->link_state_irq);
723 switch (priv->family_id) {
724 case RTL8380_FAMILY_ID:
725 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
726 IRQF_SHARED, "rtl838x-link-state", priv->ds);
727 break;
728 case RTL8390_FAMILY_ID:
729 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
730 IRQF_SHARED, "rtl839x-link-state", priv->ds);
731 break;
732 case RTL9300_FAMILY_ID:
733 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
734 IRQF_SHARED, "rtl930x-link-state", priv->ds);
735 break;
736 case RTL9310_FAMILY_ID:
737 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
738 IRQF_SHARED, "rtl931x-link-state", priv->ds);
739 break;
740 }
741 if (err) {
742 dev_err(dev, "Error setting up switch interrupt.\n");
743 /* Need to free allocated switch here */
744 }
745
746 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
747 if (soc_info.family != RTL9310_FAMILY_ID)
748 sw_w32(0x1, priv->r->imr_glb);
749
750 rtl83xx_get_l2aging(priv);
751
752 rtl83xx_setup_qos(priv);
753
754 /* Clear all destination ports for mirror groups */
755 for (i = 0; i < 4; i++)
756 priv->mirror_group_ports[i] = -1;
757
758 priv->nb.notifier_call = rtl83xx_netdevice_event;
759 if (register_netdevice_notifier(&priv->nb)) {
760 priv->nb.notifier_call = NULL;
761 dev_err(dev, "Failed to register LAG netdev notifier\n");
762 }
763
764 // Flood BPDUs to all ports including cpu-port
765 if (soc_info.family != RTL9300_FAMILY_ID) { // TODO: Port this functionality
766 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
767 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
768
769 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
770 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
771
772 rtl838x_dbgfs_init(priv);
773 }
774
775 return err;
776 }
777
778 static int rtl83xx_sw_remove(struct platform_device *pdev)
779 {
780 // TODO:
781 pr_debug("Removing platform driver for rtl83xx-sw\n");
782 return 0;
783 }
784
785 static const struct of_device_id rtl83xx_switch_of_ids[] = {
786 { .compatible = "realtek,rtl83xx-switch"},
787 { /* sentinel */ }
788 };
789
790
791 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
792
793 static struct platform_driver rtl83xx_switch_driver = {
794 .probe = rtl83xx_sw_probe,
795 .remove = rtl83xx_sw_remove,
796 .driver = {
797 .name = "rtl83xx-switch",
798 .pm = NULL,
799 .of_match_table = rtl83xx_switch_of_ids,
800 },
801 };
802
803 module_platform_driver(rtl83xx_switch_driver);
804
805 MODULE_AUTHOR("B. Koblitz");
806 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
807 MODULE_LICENSE("GPL");
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