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realtek: re-enable IPv6 routing
[openwrt/staging/thess.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5 #include <net/arp.h>
6 #include <net/nexthop.h>
7 #include <net/neighbour.h>
8 #include <net/netevent.h>
9 #include <linux/inetdevice.h>
10 #include <linux/rhashtable.h>
11
12 #include <asm/mach-rtl838x/mach-rtl83xx.h>
13 #include "rtl83xx.h"
14
15 extern struct rtl83xx_soc_info soc_info;
16
17 extern const struct rtl838x_reg rtl838x_reg;
18 extern const struct rtl838x_reg rtl839x_reg;
19 extern const struct rtl838x_reg rtl930x_reg;
20 extern const struct rtl838x_reg rtl931x_reg;
21
22 extern const struct dsa_switch_ops rtl83xx_switch_ops;
23 extern const struct dsa_switch_ops rtl930x_switch_ops;
24
25 DEFINE_MUTEX(smi_lock);
26
27 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
28 {
29 u32 msti = 0;
30 u32 port_state[4];
31 int index, bit;
32 int pos = port;
33 int n = priv->port_width << 1;
34
35 /* Ports above or equal CPU port can never be configured */
36 if (port >= priv->cpu_port)
37 return -1;
38
39 mutex_lock(&priv->reg_mutex);
40
41 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
42 if (priv->family_id == RTL8390_FAMILY_ID)
43 pos += 12;
44 if (priv->family_id == RTL9300_FAMILY_ID)
45 pos += 3;
46 if (priv->family_id == RTL9310_FAMILY_ID)
47 pos += 8;
48
49 index = n - (pos >> 4) - 1;
50 bit = (pos << 1) % 32;
51
52 priv->r->stp_get(priv, msti, port_state);
53
54 mutex_unlock(&priv->reg_mutex);
55
56 return (port_state[index] >> bit) & 3;
57 }
58
59 static struct table_reg rtl838x_tbl_regs[] = {
60 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
61 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
62 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
63
64 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
65 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
66 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
67 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
68
69 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
70 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
71 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
72 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
73 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
74 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
75
76 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
77 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
78 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
79 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
80 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
81 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
82 };
83
84 void rtl_table_init(void)
85 {
86 int i;
87
88 for (i = 0; i < RTL_TBL_END; i++)
89 mutex_init(&rtl838x_tbl_regs[i].lock);
90 }
91
92 /*
93 * Request access to table t in table access register r
94 * Returns a handle to a lock for that table
95 */
96 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
97 {
98 if (r >= RTL_TBL_END)
99 return NULL;
100
101 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
102 return NULL;
103
104 mutex_lock(&rtl838x_tbl_regs[r].lock);
105 rtl838x_tbl_regs[r].tbl = t;
106
107 return &rtl838x_tbl_regs[r];
108 }
109
110 /*
111 * Release a table r, unlock the corresponding lock
112 */
113 void rtl_table_release(struct table_reg *r)
114 {
115 if (!r)
116 return;
117
118 // pr_info("Unlocking %08x\n", (u32)r);
119 mutex_unlock(&r->lock);
120 // pr_info("Unlock done\n");
121 }
122
123 /*
124 * Reads table index idx into the data registers of the table
125 */
126 void rtl_table_read(struct table_reg *r, int idx)
127 {
128 u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
129
130 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
131 sw_w32(cmd, r->addr);
132 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
133 }
134
135 /*
136 * Writes the content of the table data registers into the table at index idx
137 */
138 void rtl_table_write(struct table_reg *r, int idx)
139 {
140 u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
141
142 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
143 sw_w32(cmd, r->addr);
144 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
145 }
146
147 /*
148 * Returns the address of the ith data register of table register r
149 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
150 */
151 inline u16 rtl_table_data(struct table_reg *r, int i)
152 {
153 if (i >= r->max_data)
154 i = r->max_data - 1;
155 return r->data + i * 4;
156 }
157
158 inline u32 rtl_table_data_r(struct table_reg *r, int i)
159 {
160 return sw_r32(rtl_table_data(r, i));
161 }
162
163 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
164 {
165 sw_w32(v, rtl_table_data(r, i));
166 }
167
168 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
169 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
170 {
171 sw_w32_mask((u32)clear, (u32)set, reg);
172 }
173
174 void rtl838x_set_port_reg(u64 set, int reg)
175 {
176 sw_w32((u32)set, reg);
177 }
178
179 u64 rtl838x_get_port_reg(int reg)
180 {
181 return ((u64) sw_r32(reg));
182 }
183
184 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
185 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
186 {
187 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
188 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
189 }
190
191 u64 rtl839x_get_port_reg_be(int reg)
192 {
193 u64 v = sw_r32(reg);
194
195 v <<= 32;
196 v |= sw_r32(reg + 4);
197 return v;
198 }
199
200 void rtl839x_set_port_reg_be(u64 set, int reg)
201 {
202 sw_w32(set >> 32, reg);
203 sw_w32(set & 0xffffffff, reg + 4);
204 }
205
206 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
207 {
208 sw_w32_mask((u32)clear, (u32)set, reg);
209 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
210 }
211
212 void rtl839x_set_port_reg_le(u64 set, int reg)
213 {
214 sw_w32(set, reg);
215 sw_w32(set >> 32, reg + 4);
216 }
217
218 u64 rtl839x_get_port_reg_le(int reg)
219 {
220 u64 v = sw_r32(reg + 4);
221
222 v <<= 32;
223 v |= sw_r32(reg);
224 return v;
225 }
226
227 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
228 {
229 switch (soc_info.family) {
230 case RTL8380_FAMILY_ID:
231 return rtl838x_read_phy(port, page, reg, val);
232 case RTL8390_FAMILY_ID:
233 return rtl839x_read_phy(port, page, reg, val);
234 case RTL9300_FAMILY_ID:
235 return rtl930x_read_phy(port, page, reg, val);
236 case RTL9310_FAMILY_ID:
237 return rtl931x_read_phy(port, page, reg, val);
238 }
239 return -1;
240 }
241
242 int write_phy(u32 port, u32 page, u32 reg, u32 val)
243 {
244 switch (soc_info.family) {
245 case RTL8380_FAMILY_ID:
246 return rtl838x_write_phy(port, page, reg, val);
247 case RTL8390_FAMILY_ID:
248 return rtl839x_write_phy(port, page, reg, val);
249 case RTL9300_FAMILY_ID:
250 return rtl930x_write_phy(port, page, reg, val);
251 case RTL9310_FAMILY_ID:
252 return rtl931x_write_phy(port, page, reg, val);
253 }
254 return -1;
255 }
256
257 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
258 {
259 struct device *dev = priv->dev;
260 struct device_node *dn, *mii_np = dev->of_node;
261 struct mii_bus *bus;
262 int ret;
263 u32 pn;
264
265 pr_debug("In %s\n", __func__);
266 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
267 if (mii_np) {
268 pr_debug("Found compatible MDIO node!\n");
269 } else {
270 dev_err(priv->dev, "no %s child node found", "mdio-bus");
271 return -ENODEV;
272 }
273
274 priv->mii_bus = of_mdio_find_bus(mii_np);
275 if (!priv->mii_bus) {
276 pr_debug("Deferring probe of mdio bus\n");
277 return -EPROBE_DEFER;
278 }
279 if (!of_device_is_available(mii_np))
280 ret = -ENODEV;
281
282 bus = devm_mdiobus_alloc(priv->ds->dev);
283 if (!bus)
284 return -ENOMEM;
285
286 bus->name = "rtl838x slave mii";
287
288 /*
289 * Since the NIC driver is loaded first, we can use the mdio rw functions
290 * assigned there.
291 */
292 bus->read = priv->mii_bus->read;
293 bus->write = priv->mii_bus->write;
294 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
295
296 bus->parent = dev;
297 priv->ds->slave_mii_bus = bus;
298 priv->ds->slave_mii_bus->priv = priv;
299
300 ret = mdiobus_register(priv->ds->slave_mii_bus);
301 if (ret && mii_np) {
302 of_node_put(dn);
303 return ret;
304 }
305
306 dn = mii_np;
307 for_each_node_by_name(dn, "ethernet-phy") {
308 if (of_property_read_u32(dn, "reg", &pn))
309 continue;
310
311 // Check for the integrated SerDes of the RTL8380M first
312 if (of_property_read_bool(dn, "phy-is-integrated") && priv->id == 0x8380 && pn >= 24) {
313 pr_debug("----> FÓUND A SERDES\n");
314 priv->ports[pn].phy = PHY_RTL838X_SDS;
315 continue;
316 }
317
318 if (of_property_read_bool(dn, "phy-is-integrated") && !of_property_read_bool(dn, "sfp")) {
319 priv->ports[pn].phy = PHY_RTL8218B_INT;
320 continue;
321 }
322
323 if (!of_property_read_bool(dn, "phy-is-integrated") && of_property_read_bool(dn, "sfp")) {
324 priv->ports[pn].phy = PHY_RTL8214FC;
325 continue;
326 }
327
328 if (!of_property_read_bool(dn, "phy-is-integrated") && !of_property_read_bool(dn, "sfp")) {
329 priv->ports[pn].phy = PHY_RTL8218B_EXT;
330 continue;
331 }
332 }
333
334 // TODO: Do this needs to come from the .dts
335 if (priv->family_id == RTL9300_FAMILY_ID) {
336 priv->ports[24].is2G5 = true;
337 priv->ports[25].is2G5 = true;
338 }
339
340 /* Disable MAC polling the PHY so that we can start configuration */
341 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
342
343 /* Enable PHY control via SoC */
344 if (priv->family_id == RTL8380_FAMILY_ID) {
345 /* Enable SerDes NWAY and PHY control via SoC */
346 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
347 } else if (priv->family_id == RTL8390_FAMILY_ID) {
348 /* Disable PHY polling via SoC */
349 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
350 }
351
352 /* Power on fibre ports and reset them if necessary */
353 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
354 pr_debug("Powering on fibre ports & reset\n");
355 rtl8380_sds_power(24, 1);
356 rtl8380_sds_power(26, 1);
357 }
358
359 pr_debug("%s done\n", __func__);
360 return 0;
361 }
362
363 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
364 {
365 int t = sw_r32(priv->r->l2_ctrl_1);
366
367 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
368
369 if (priv->family_id == RTL8380_FAMILY_ID)
370 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
371 else
372 t = (t * 3) / 5;
373
374 pr_debug("L2 AGING time: %d sec\n", t);
375 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
376 return t;
377 }
378
379 /* Caller must hold priv->reg_mutex */
380 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port)
381 {
382 struct rtl838x_switch_priv *priv = ds->priv;
383 int i;
384
385 pr_info("%s: Adding port %d to LA-group %d\n", __func__, port, group);
386 if (group >= priv->n_lags) {
387 pr_err("Link Agrregation group too large.\n");
388 return -EINVAL;
389 }
390
391 if (port >= priv->cpu_port) {
392 pr_err("Invalid port number.\n");
393 return -EINVAL;
394 }
395
396 for (i = 0; i < priv->n_lags; i++) {
397 if (priv->lags_port_members[i] & BIT_ULL(i))
398 break;
399 }
400 if (i != priv->n_lags) {
401 pr_err("%s: Port already member of LAG: %d\n", __func__, i);
402 return -ENOSPC;
403 }
404
405 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
406 priv->lags_port_members[group] |= BIT_ULL(port);
407
408 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
409 return 0;
410 }
411
412 /* Caller must hold priv->reg_mutex */
413 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
414 {
415 struct rtl838x_switch_priv *priv = ds->priv;
416
417 pr_info("%s: Removing port %d from LA-group %d\n", __func__, port, group);
418
419 if (group >= priv->n_lags) {
420 pr_err("Link Agrregation group too large.\n");
421 return -EINVAL;
422 }
423
424 if (port >= priv->cpu_port) {
425 pr_err("Invalid port number.\n");
426 return -EINVAL;
427 }
428
429
430 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
431 pr_err("%s: Port not member of LAG: %d\n", __func__, group
432 );
433 return -ENOSPC;
434 }
435
436 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
437 priv->lags_port_members[group] &= ~BIT_ULL(port);
438
439 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
440 return 0;
441 }
442
443 /*
444 * Allocate a 64 bit octet counter located in the LOG HW table
445 */
446 static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
447 {
448 int idx;
449
450 mutex_lock(&priv->reg_mutex);
451
452 idx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
453 if (idx >= priv->n_counters) {
454 mutex_unlock(&priv->reg_mutex);
455 return -1;
456 }
457
458 set_bit(idx, priv->octet_cntr_use_bm);
459 mutex_unlock(&priv->reg_mutex);
460
461 return idx;
462 }
463
464 /*
465 * Allocate a 32-bit packet counter
466 * 2 32-bit packet counters share the location of a 64-bit octet counter
467 * Initially there are no free packet counters and 2 new ones need to be freed
468 * by allocating the corresponding octet counter
469 */
470 int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv)
471 {
472 int idx, j;
473
474 mutex_lock(&priv->reg_mutex);
475
476 /* Because initially no packet counters are free, the logic is reversed:
477 * a 0-bit means the counter is already allocated (for octets)
478 */
479 idx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2);
480 if (idx >= priv->n_counters * 2) {
481 j = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
482 if (j >= priv->n_counters) {
483 mutex_unlock(&priv->reg_mutex);
484 return -1;
485 }
486 set_bit(j, priv->octet_cntr_use_bm);
487 idx = j * 2;
488 set_bit(j * 2 + 1, priv->packet_cntr_use_bm);
489
490 } else {
491 clear_bit(idx, priv->packet_cntr_use_bm);
492 }
493
494 mutex_unlock(&priv->reg_mutex);
495
496 return idx;
497 }
498
499 /*
500 * Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC
501 * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table
502 * or mark an existing entry as a nexthop by setting it's nexthop bit
503 * Called from the L3 layer
504 * The index in the L2 hash table is filled into nh->l2_id;
505 */
506 int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)
507 {
508 struct rtl838x_l2_entry e;
509 u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid);
510 u32 key = priv->r->l2_hash_key(priv, seed);
511 int i, idx = -1;
512 u64 entry;
513
514 pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n",
515 __func__, nh->mac, nh->rvid, key, seed);
516
517 e.type = L2_UNICAST;
518 u64_to_ether_addr(nh->mac, &e.mac[0]);
519 e.port = nh->port;
520
521 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
522 for (i = 0; i < priv->l2_bucket_size; i++) {
523 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
524
525 if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
526 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1
527 : ((key << 2) | i) & 0xffff;
528 break;
529 }
530 }
531
532 if (idx < 0) {
533 pr_err("%s: No more L2 forwarding entries available\n", __func__);
534 return -1;
535 }
536
537 // Found an existing (e->valid is true) or empty entry, make it a nexthop entry
538 nh->l2_id = idx;
539 if (e.valid) {
540 nh->port = e.port;
541 nh->vid = e.vid; // Save VID
542 nh->rvid = e.rvid;
543 nh->dev_id = e.stack_dev;
544 // If the entry is already a valid next hop entry, don't change it
545 if (e.next_hop)
546 return 0;
547 } else {
548 e.valid = true;
549 e.is_static = true;
550 e.rvid = nh->rvid;
551 e.is_ip_mc = false;
552 e.is_ipv6_mc = false;
553 e.block_da = false;
554 e.block_sa = false;
555 e.suspended = false;
556 e.age = 0; // With port-ignore
557 e.port = priv->port_ignore;
558 u64_to_ether_addr(nh->mac, &e.mac[0]);
559 }
560 e.next_hop = true;
561 e.nh_route_id = nh->id; // NH route ID takes place of VID
562 e.nh_vlan_target = false;
563
564 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
565
566 return 0;
567 }
568
569 /*
570 * Removes a Layer 2 next hop entry in the forwarding database
571 * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared
572 * and we wait until the entry ages out
573 */
574 int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)
575 {
576 struct rtl838x_l2_entry e;
577 u32 key = nh->l2_id >> 2;
578 int i = nh->l2_id & 0x3;
579 u64 entry = entry = priv->r->read_l2_entry_using_hash(key, i, &e);
580
581 pr_debug("%s: id %d, key %d, index %d\n", __func__, nh->l2_id, key, i);
582 if (!e.valid) {
583 dev_err(priv->dev, "unknown nexthop, id %x\n", nh->l2_id);
584 return -1;
585 }
586
587 if (e.is_static)
588 e.valid = false;
589 e.next_hop = false;
590 e.vid = nh->vid; // Restore VID
591 e.rvid = nh->rvid;
592
593 priv->r->write_l2_entry_using_hash(key, i, &e);
594
595 return 0;
596 }
597
598 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
599 struct net_device *ndev,
600 struct netdev_notifier_changeupper_info *info)
601 {
602 struct net_device *upper = info->upper_dev;
603 int i, j, err;
604
605 if (!netif_is_lag_master(upper))
606 return 0;
607
608 mutex_lock(&priv->reg_mutex);
609
610 for (i = 0; i < priv->n_lags; i++) {
611 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
612 break;
613 }
614 for (j = 0; j < priv->cpu_port; j++) {
615 if (priv->ports[j].dp->slave == ndev)
616 break;
617 }
618 if (j >= priv->cpu_port) {
619 err = -EINVAL;
620 goto out;
621 }
622
623 if (info->linking) {
624 if (!priv->lag_devs[i])
625 priv->lag_devs[i] = upper;
626 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index);
627 if (err) {
628 err = -EINVAL;
629 goto out;
630 }
631 } else {
632 if (!priv->lag_devs[i])
633 err = -EINVAL;
634 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
635 if (err) {
636 err = -EINVAL;
637 goto out;
638 }
639 if (!priv->lags_port_members[i])
640 priv->lag_devs[i] = NULL;
641 }
642
643 out:
644 mutex_unlock(&priv->reg_mutex);
645 return 0;
646 }
647
648 /*
649 * Is the lower network device a DSA slave network device of our RTL930X-switch?
650 * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the
651 * DSA master device.
652 */
653 int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv)
654 {
655 int i;
656
657 // TODO: On 5.12:
658 // if(!dsa_slave_dev_check(dev)) {
659 // netdev_info(dev, "%s: not a DSA device.\n", __func__);
660 // return -EINVAL;
661 // }
662
663 for (i = 0; i < priv->cpu_port; i++) {
664 if (!priv->ports[i].dp)
665 continue;
666 if (priv->ports[i].dp->slave == dev)
667 return i;
668 }
669 return -EINVAL;
670 }
671
672 static int rtl83xx_netdevice_event(struct notifier_block *this,
673 unsigned long event, void *ptr)
674 {
675 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
676 struct rtl838x_switch_priv *priv;
677 int err;
678
679 pr_debug("In: %s, event: %lu\n", __func__, event);
680
681 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
682 return NOTIFY_DONE;
683
684 priv = container_of(this, struct rtl838x_switch_priv, nb);
685 switch (event) {
686 case NETDEV_CHANGEUPPER:
687 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
688 break;
689 }
690
691 if (err)
692 return err;
693
694 return NOTIFY_DONE;
695 }
696
697 const static struct rhashtable_params route_ht_params = {
698 .key_len = sizeof(u32),
699 .key_offset = offsetof(struct rtl83xx_route, gw_ip),
700 .head_offset = offsetof(struct rtl83xx_route, linkage),
701 };
702
703 /*
704 * Updates an L3 next hop entry in the ROUTING table
705 */
706 static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 ip_addr, u64 mac)
707 {
708 struct rtl83xx_route *r;
709 struct rhlist_head *tmp, *list;
710
711 rcu_read_lock();
712 list = rhltable_lookup(&priv->routes, &ip_addr, route_ht_params);
713 if (!list) {
714 rcu_read_unlock();
715 return -ENOENT;
716 }
717
718 rhl_for_each_entry_rcu(r, tmp, list, linkage) {
719 pr_info("%s: Setting up fwding: ip %pI4, GW mac %016llx\n",
720 __func__, &ip_addr, mac);
721
722 // Reads the ROUTING table entry associated with the route
723 priv->r->route_read(r->id, r);
724 pr_info("Route with id %d to %pI4 / %d\n", r->id, &r->dst_ip, r->prefix_len);
725
726 r->nh.mac = r->nh.gw = mac;
727 r->nh.port = priv->port_ignore;
728 r->nh.id = r->id;
729
730 // Do we need to explicitly add a DMAC entry with the route's nh index?
731 if (priv->r->set_l3_egress_mac)
732 priv->r->set_l3_egress_mac(r->id, mac);
733
734 // Update ROUTING table: map gateway-mac and switch-mac id to route id
735 rtl83xx_l2_nexthop_add(priv, &r->nh);
736
737 r->attr.valid = true;
738 r->attr.action = ROUTE_ACT_FORWARD;
739 r->attr.type = 0;
740 r->attr.hit = false; // Reset route-used indicator
741
742 // Add PIE entry with dst_ip and prefix_len
743 r->pr.dip = r->dst_ip;
744 r->pr.dip_m = inet_make_mask(r->prefix_len);
745
746 if (r->is_host_route) {
747 int slot = priv->r->find_l3_slot(r, false);
748
749 pr_info("%s: Got slot for route: %d\n", __func__, slot);
750 priv->r->host_route_write(slot, r);
751 } else {
752 priv->r->route_write(r->id, r);
753 r->pr.fwd_sel = true;
754 r->pr.fwd_data = r->nh.l2_id;
755 r->pr.fwd_act = PIE_ACT_ROUTE_UC;
756 }
757
758 if (priv->r->set_l3_nexthop)
759 priv->r->set_l3_nexthop(r->nh.id, r->nh.l2_id, r->nh.if_id);
760
761 if (r->pr.id < 0) {
762 r->pr.packet_cntr = rtl83xx_packet_cntr_alloc(priv);
763 if (r->pr.packet_cntr >= 0) {
764 pr_info("Using packet counter %d\n", r->pr.packet_cntr);
765 r->pr.log_sel = true;
766 r->pr.log_data = r->pr.packet_cntr;
767 }
768 priv->r->pie_rule_add(priv, &r->pr);
769 } else {
770 int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr);
771 pr_info("%s: total packets: %d\n", __func__, pkts);
772
773 priv->r->pie_rule_write(priv, r->pr.id, &r->pr);
774 }
775 }
776 rcu_read_unlock();
777 return 0;
778 }
779
780 static int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv,
781 struct net_device *dev, __be32 ip_addr)
782 {
783 struct neighbour *n = neigh_lookup(&arp_tbl, &ip_addr, dev);
784 int err = 0;
785 u64 mac;
786
787 if (!n) {
788 n = neigh_create(&arp_tbl, &ip_addr, dev);
789 if (IS_ERR(n))
790 return PTR_ERR(n);
791 }
792
793 /* If the neigh is already resolved, then go ahead and
794 * install the entry, otherwise start the ARP process to
795 * resolve the neigh.
796 */
797 if (n->nud_state & NUD_VALID) {
798 mac = ether_addr_to_u64(n->ha);
799 pr_info("%s: resolved mac: %016llx\n", __func__, mac);
800 rtl83xx_l3_nexthop_update(priv, ip_addr, mac);
801 } else {
802 pr_info("%s: need to wait\n", __func__);
803 neigh_event_send(n, NULL);
804 }
805
806 neigh_release(n);
807 return err;
808 }
809
810 struct rtl83xx_walk_data {
811 struct rtl838x_switch_priv *priv;
812 int port;
813 };
814
815 static int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_nested_priv *_priv)
816 {
817 struct rtl83xx_walk_data *data = (struct rtl83xx_walk_data *)_priv->data;
818 struct rtl838x_switch_priv *priv = data->priv;
819 int ret = 0;
820 int index;
821
822 index = rtl83xx_port_is_under(lower, priv);
823 data->port = index;
824 if (index >= 0) {
825 pr_debug("Found DSA-port, index %d\n", index);
826 ret = 1;
827 }
828
829 return ret;
830 }
831
832 int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv)
833 {
834 struct rtl83xx_walk_data data;
835 struct netdev_nested_priv _priv;
836
837 data.priv = priv;
838 data.port = 0;
839 _priv.data = (void *)&data;
840
841 netdev_walk_all_lower_dev(dev, rtl83xx_port_lower_walk, &_priv);
842
843 return data.port;
844 }
845
846 static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
847 {
848 struct rtl83xx_route *r;
849 int idx = 0, err;
850
851 mutex_lock(&priv->reg_mutex);
852
853 idx = find_first_zero_bit(priv->route_use_bm, MAX_ROUTES);
854 pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip);
855
856 r = kzalloc(sizeof(*r), GFP_KERNEL);
857 if (!r) {
858 mutex_unlock(&priv->reg_mutex);
859 return r;
860 }
861
862 r->id = idx;
863 r->gw_ip = ip;
864 r->pr.id = -1; // We still need to allocate a rule in HW
865 r->is_host_route = false;
866
867 err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);
868 if (err) {
869 pr_err("Could not insert new rule\n");
870 mutex_unlock(&priv->reg_mutex);
871 goto out_free;
872 }
873
874 set_bit(idx, priv->route_use_bm);
875
876 mutex_unlock(&priv->reg_mutex);
877
878 return r;
879
880 out_free:
881 kfree(r);
882 return NULL;
883 }
884
885
886 static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
887 {
888 struct rtl83xx_route *r;
889 int idx = 0, err;
890
891 mutex_lock(&priv->reg_mutex);
892
893 idx = find_first_zero_bit(priv->host_route_use_bm, MAX_HOST_ROUTES);
894 pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip);
895
896 r = kzalloc(sizeof(*r), GFP_KERNEL);
897 if (!r) {
898 mutex_unlock(&priv->reg_mutex);
899 return r;
900 }
901
902 /* We require a unique route ID irrespective of whether it is a prefix or host
903 * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry */
904 r->id = idx + MAX_ROUTES;
905
906 r->gw_ip = ip;
907 r->pr.id = -1; // We still need to allocate a rule in HW
908 r->is_host_route = true;
909
910 err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);
911 if (err) {
912 pr_err("Could not insert new rule\n");
913 mutex_unlock(&priv->reg_mutex);
914 goto out_free;
915 }
916
917 set_bit(idx, priv->host_route_use_bm);
918
919 mutex_unlock(&priv->reg_mutex);
920
921 return r;
922
923 out_free:
924 kfree(r);
925 return NULL;
926 }
927
928
929
930 static void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_route *r)
931 {
932 int id;
933
934 if (rhltable_remove(&priv->routes, &r->linkage, route_ht_params))
935 dev_warn(priv->dev, "Could not remove route\n");
936
937 if (r->is_host_route) {
938 id = priv->r->find_l3_slot(r, false);
939 pr_debug("%s: Got id for host route: %d\n", __func__, id);
940 r->attr.valid = false;
941 priv->r->host_route_write(id, r);
942 clear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm);
943 } else {
944 // If there is a HW representation of the route, delete it
945 if (priv->r->route_lookup_hw) {
946 id = priv->r->route_lookup_hw(r);
947 pr_info("%s: Got id for prefix route: %d\n", __func__, id);
948 r->attr.valid = false;
949 priv->r->route_write(id, r);
950 }
951 clear_bit(r->id, priv->route_use_bm);
952 }
953
954 kfree(r);
955 }
956
957 static int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv,
958 struct fib_entry_notifier_info *info)
959 {
960 struct fib_nh *nh = fib_info_nh(info->fi, 0);
961 struct rtl83xx_route *r;
962 struct rhlist_head *tmp, *list;
963
964 pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len);
965 rcu_read_lock();
966 list = rhltable_lookup(&priv->routes, &nh->fib_nh_gw4, route_ht_params);
967 if (!list) {
968 rcu_read_unlock();
969 pr_err("%s: no such gateway: %pI4\n", __func__, &nh->fib_nh_gw4);
970 return -ENOENT;
971 }
972 rhl_for_each_entry_rcu(r, tmp, list, linkage) {
973 if (r->dst_ip == info->dst && r->prefix_len == info->dst_len) {
974 pr_info("%s: found a route with id %d, nh-id %d\n",
975 __func__, r->id, r->nh.id);
976 break;
977 }
978 }
979 rcu_read_unlock();
980
981 rtl83xx_l2_nexthop_rm(priv, &r->nh);
982
983 pr_debug("%s: Releasing packet counter %d\n", __func__, r->pr.packet_cntr);
984 set_bit(r->pr.packet_cntr, priv->packet_cntr_use_bm);
985 priv->r->pie_rule_rm(priv, &r->pr);
986
987 rtl83xx_route_rm(priv, r);
988
989 nh->fib_nh_flags &= ~RTNH_F_OFFLOAD;
990
991 return 0;
992 }
993
994 /*
995 * On the RTL93xx, an L3 termination endpoint MAC address on which the router waits
996 * for packets to be routed needs to be allocated.
997 */
998 static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac)
999 {
1000 int i, free_mac = -1;
1001 struct rtl93xx_rt_mac m;
1002
1003 mutex_lock(&priv->reg_mutex);
1004 for (i = 0; i < MAX_ROUTER_MACS; i++) {
1005 priv->r->get_l3_router_mac(i, &m);
1006 if (free_mac < 0 && !m.valid) {
1007 free_mac = i;
1008 continue;
1009 }
1010 if (m.valid && m.mac == mac) {
1011 free_mac = i;
1012 break;
1013 }
1014 }
1015
1016 if (free_mac < 0) {
1017 pr_err("No free router MACs, cannot offload\n");
1018 mutex_unlock(&priv->reg_mutex);
1019 return -1;
1020 }
1021
1022 m.valid = true;
1023 m.mac = mac;
1024 m.p_type = 0; // An individual port, not a trunk port
1025 m.p_id = 0x3f; // Listen on any port
1026 m.p_id_mask = 0;
1027 m.vid = 0; // Listen on any VLAN...
1028 m.vid_mask = 0; // ... so mask needs to be 0
1029 m.mac_mask = 0xffffffffffffULL; // We want an exact match of the interface MAC
1030 m.action = L3_FORWARD; // Route the packet
1031 priv->r->set_l3_router_mac(free_mac, &m);
1032
1033 mutex_unlock(&priv->reg_mutex);
1034
1035 return 0;
1036 }
1037
1038 static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan)
1039 {
1040 int i, free_mac = -1;
1041 struct rtl838x_l3_intf intf;
1042 u64 m;
1043
1044 mutex_lock(&priv->reg_mutex);
1045 for (i = 0; i < MAX_SMACS; i++) {
1046 m = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i);
1047 if (free_mac < 0 && !m) {
1048 free_mac = i;
1049 continue;
1050 }
1051 if (m == mac) {
1052 mutex_unlock(&priv->reg_mutex);
1053 return i;
1054 }
1055 }
1056
1057 if (free_mac < 0) {
1058 pr_err("No free egress interface, cannot offload\n");
1059 return -1;
1060 }
1061
1062 // Set up default egress interface 1
1063 intf.vid = vlan;
1064 intf.smac_idx = free_mac;
1065 intf.ip4_mtu_id = 1;
1066 intf.ip6_mtu_id = 1;
1067 intf.ttl_scope = 1; // TTL
1068 intf.hl_scope = 1; // Hop Limit
1069 intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; // FORWARD
1070 intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; // FORWARD;
1071 priv->r->set_l3_egress_intf(free_mac, &intf);
1072
1073 priv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac);
1074
1075 mutex_unlock(&priv->reg_mutex);
1076
1077 return free_mac;
1078 }
1079
1080 static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv,
1081 struct fib_entry_notifier_info *info)
1082 {
1083 struct fib_nh *nh = fib_info_nh(info->fi, 0);
1084 struct net_device *dev = fib_info_nh(info->fi, 0)->fib_nh_dev;
1085 int port;
1086 struct rtl83xx_route *r;
1087 bool to_localhost;
1088 int vlan = is_vlan_dev(dev) ? vlan_dev_vlan_id(dev) : 0;
1089
1090 pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len);
1091 if (!info->dst) {
1092 pr_info("Not offloading default route for now\n");
1093 return 0;
1094 }
1095
1096 pr_debug("GW: %pI4, interface name %s, mac %016llx, vlan %d\n", &nh->fib_nh_gw4, dev->name,
1097 ether_addr_to_u64(dev->dev_addr), vlan
1098 );
1099
1100 port = rtl83xx_port_dev_lower_find(dev, priv);
1101 if (port < 0)
1102 return -1;
1103
1104 // For now we only work with routes that have a gateway and are not ourself
1105 // if ((!nh->fib_nh_gw4) && (info->dst_len != 32))
1106 // return 0;
1107
1108 if ((info->dst & 0xff) == 0xff)
1109 return 0;
1110
1111 // Do not offload routes to 192.168.100.x
1112 if ((info->dst & 0xffffff00) == 0xc0a86400)
1113 return 0;
1114
1115 // Do not offload routes to 127.x.x.x
1116 if ((info->dst & 0xff000000) == 0x7f000000)
1117 return 0;
1118
1119 // Allocate route or host-route (entry if hardware supports this)
1120 if (info->dst_len == 32 && priv->r->host_route_write)
1121 r = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4);
1122 else
1123 r = rtl83xx_route_alloc(priv, nh->fib_nh_gw4);
1124
1125 if (!r) {
1126 pr_err("%s: No more free route entries\n", __func__);
1127 return -1;
1128 }
1129
1130 r->dst_ip = info->dst;
1131 r->prefix_len = info->dst_len;
1132 r->nh.rvid = vlan;
1133 to_localhost = !nh->fib_nh_gw4;
1134
1135 if (priv->r->set_l3_router_mac) {
1136 u64 mac = ether_addr_to_u64(dev->dev_addr);
1137
1138 pr_debug("Local route and router mac %016llx\n", mac);
1139
1140 if (rtl83xx_alloc_router_mac(priv, mac))
1141 goto out_free_rt;
1142
1143 // vid = 0: Do not care about VID
1144 r->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan);
1145 if (r->nh.if_id < 0)
1146 goto out_free_rmac;
1147
1148 if (to_localhost) {
1149 int slot;
1150
1151 r->nh.mac = mac;
1152 r->nh.port = priv->port_ignore;
1153 r->attr.valid = true;
1154 r->attr.action = ROUTE_ACT_TRAP2CPU;
1155 r->attr.type = 0;
1156
1157 slot = priv->r->find_l3_slot(r, false);
1158 pr_debug("%s: Got slot for route: %d\n", __func__, slot);
1159 priv->r->host_route_write(slot, r);
1160 }
1161 }
1162
1163 // We need to resolve the mac address of the GW
1164 if (!to_localhost)
1165 rtl83xx_port_ipv4_resolve(priv, dev, nh->fib_nh_gw4);
1166
1167 nh->fib_nh_flags |= RTNH_F_OFFLOAD;
1168
1169 return 0;
1170
1171 out_free_rmac:
1172 out_free_rt:
1173 return 0;
1174 }
1175
1176 static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv,
1177 struct fib6_entry_notifier_info *info)
1178 {
1179 pr_debug("In %s\n", __func__);
1180 // nh->fib_nh_flags |= RTNH_F_OFFLOAD;
1181 return 0;
1182 }
1183
1184 struct net_event_work {
1185 struct work_struct work;
1186 struct rtl838x_switch_priv *priv;
1187 u64 mac;
1188 u32 gw_addr;
1189 };
1190
1191 static void rtl83xx_net_event_work_do(struct work_struct *work)
1192 {
1193 struct net_event_work *net_work =
1194 container_of(work, struct net_event_work, work);
1195 struct rtl838x_switch_priv *priv = net_work->priv;
1196
1197 rtl83xx_l3_nexthop_update(priv, net_work->gw_addr, net_work->mac);
1198 }
1199
1200 static int rtl83xx_netevent_event(struct notifier_block *this,
1201 unsigned long event, void *ptr)
1202 {
1203 struct rtl838x_switch_priv *priv;
1204 struct net_device *dev;
1205 struct neighbour *n = ptr;
1206 int err, port;
1207 struct net_event_work *net_work;
1208
1209 priv = container_of(this, struct rtl838x_switch_priv, ne_nb);
1210
1211 net_work = kzalloc(sizeof(*net_work), GFP_ATOMIC);
1212 if (!net_work)
1213 return NOTIFY_BAD;
1214
1215 INIT_WORK(&net_work->work, rtl83xx_net_event_work_do);
1216 net_work->priv = priv;
1217
1218 switch (event) {
1219 case NETEVENT_NEIGH_UPDATE:
1220 if (n->tbl != &arp_tbl)
1221 return NOTIFY_DONE;
1222 dev = n->dev;
1223 port = rtl83xx_port_dev_lower_find(dev, priv);
1224 if (port < 0 || !(n->nud_state & NUD_VALID)) {
1225 pr_debug("%s: Neigbour invalid, not updating\n", __func__);
1226 kfree(net_work);
1227 return NOTIFY_DONE;
1228 }
1229
1230 net_work->mac = ether_addr_to_u64(n->ha);
1231 net_work->gw_addr = *(__be32 *) n->primary_key;
1232
1233 pr_debug("%s: updating neighbour on port %d, mac %016llx\n",
1234 __func__, port, net_work->mac);
1235 schedule_work(&net_work->work);
1236 if (err)
1237 netdev_warn(dev, "failed to handle neigh update (err %d)\n", err);
1238 break;
1239 }
1240
1241 return NOTIFY_DONE;
1242 }
1243
1244 struct rtl83xx_fib_event_work {
1245 struct work_struct work;
1246 union {
1247 struct fib_entry_notifier_info fen_info;
1248 struct fib6_entry_notifier_info fen6_info;
1249 struct fib_rule_notifier_info fr_info;
1250 };
1251 struct rtl838x_switch_priv *priv;
1252 bool is_fib6;
1253 unsigned long event;
1254 };
1255
1256 static void rtl83xx_fib_event_work_do(struct work_struct *work)
1257 {
1258 struct rtl83xx_fib_event_work *fib_work =
1259 container_of(work, struct rtl83xx_fib_event_work, work);
1260 struct rtl838x_switch_priv *priv = fib_work->priv;
1261 struct fib_rule *rule;
1262 int err;
1263
1264 /* Protect internal structures from changes */
1265 rtnl_lock();
1266 pr_debug("%s: doing work, event %ld\n", __func__, fib_work->event);
1267 switch (fib_work->event) {
1268 case FIB_EVENT_ENTRY_ADD:
1269 case FIB_EVENT_ENTRY_REPLACE:
1270 case FIB_EVENT_ENTRY_APPEND:
1271 if (fib_work->is_fib6) {
1272 err = rtl83xx_fib6_add(priv, &fib_work->fen6_info);
1273 } else {
1274 err = rtl83xx_fib4_add(priv, &fib_work->fen_info);
1275 fib_info_put(fib_work->fen_info.fi);
1276 }
1277 if (err)
1278 pr_err("%s: FIB4 failed\n", __func__);
1279 break;
1280 case FIB_EVENT_ENTRY_DEL:
1281 rtl83xx_fib4_del(priv, &fib_work->fen_info);
1282 fib_info_put(fib_work->fen_info.fi);
1283 break;
1284 case FIB_EVENT_RULE_ADD:
1285 case FIB_EVENT_RULE_DEL:
1286 rule = fib_work->fr_info.rule;
1287 if (!fib4_rule_default(rule))
1288 pr_err("%s: FIB4 default rule failed\n", __func__);
1289 fib_rule_put(rule);
1290 break;
1291 }
1292 rtnl_unlock();
1293 kfree(fib_work);
1294 }
1295
1296 /* Called with rcu_read_lock() */
1297 static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, void *ptr)
1298 {
1299 struct fib_notifier_info *info = ptr;
1300 struct rtl838x_switch_priv *priv;
1301 struct rtl83xx_fib_event_work *fib_work;
1302
1303 if ((info->family != AF_INET && info->family != AF_INET6 &&
1304 info->family != RTNL_FAMILY_IPMR &&
1305 info->family != RTNL_FAMILY_IP6MR))
1306 return NOTIFY_DONE;
1307
1308 priv = container_of(this, struct rtl838x_switch_priv, fib_nb);
1309
1310 fib_work = kzalloc(sizeof(*fib_work), GFP_ATOMIC);
1311 if (!fib_work)
1312 return NOTIFY_BAD;
1313
1314 INIT_WORK(&fib_work->work, rtl83xx_fib_event_work_do);
1315 fib_work->priv = priv;
1316 fib_work->event = event;
1317 fib_work->is_fib6 = false;
1318
1319 switch (event) {
1320 case FIB_EVENT_ENTRY_ADD:
1321 case FIB_EVENT_ENTRY_REPLACE:
1322 case FIB_EVENT_ENTRY_APPEND:
1323 case FIB_EVENT_ENTRY_DEL:
1324 pr_debug("%s: FIB_ENTRY ADD/DELL, event %ld\n", __func__, event);
1325 if (info->family == AF_INET) {
1326 struct fib_entry_notifier_info *fen_info = ptr;
1327
1328 if (fen_info->fi->fib_nh_is_v6) {
1329 NL_SET_ERR_MSG_MOD(info->extack,
1330 "IPv6 gateway with IPv4 route is not supported");
1331 kfree(fib_work);
1332 return notifier_from_errno(-EINVAL);
1333 }
1334
1335 memcpy(&fib_work->fen_info, ptr, sizeof(fib_work->fen_info));
1336 /* Take referece on fib_info to prevent it from being
1337 * freed while work is queued. Release it afterwards.
1338 */
1339 fib_info_hold(fib_work->fen_info.fi);
1340
1341 } else if (info->family == AF_INET6) {
1342 struct fib6_entry_notifier_info *fen6_info = ptr;
1343 pr_warn("%s: FIB_RULE ADD/DELL for IPv6 not supported\n", __func__);
1344 kfree(fib_work);
1345 return NOTIFY_DONE;
1346 }
1347 break;
1348
1349 case FIB_EVENT_RULE_ADD:
1350 case FIB_EVENT_RULE_DEL:
1351 pr_debug("%s: FIB_RULE ADD/DELL, event: %ld\n", __func__, event);
1352 memcpy(&fib_work->fr_info, ptr, sizeof(fib_work->fr_info));
1353 fib_rule_get(fib_work->fr_info.rule);
1354 break;
1355 }
1356
1357 schedule_work(&fib_work->work);
1358
1359 return NOTIFY_DONE;
1360 }
1361
1362 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
1363 {
1364 int err = 0, i;
1365 struct rtl838x_switch_priv *priv;
1366 struct device *dev = &pdev->dev;
1367 u64 bpdu_mask;
1368
1369 pr_debug("Probing RTL838X switch device\n");
1370 if (!pdev->dev.of_node) {
1371 dev_err(dev, "No DT found\n");
1372 return -EINVAL;
1373 }
1374
1375 // Initialize access to RTL switch tables
1376 rtl_table_init();
1377
1378 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1379 if (!priv)
1380 return -ENOMEM;
1381
1382 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
1383
1384 if (!priv->ds)
1385 return -ENOMEM;
1386 priv->ds->dev = dev;
1387 priv->ds->priv = priv;
1388 priv->ds->ops = &rtl83xx_switch_ops;
1389 priv->dev = dev;
1390
1391 mutex_init(&priv->reg_mutex);
1392
1393 priv->family_id = soc_info.family;
1394 priv->id = soc_info.id;
1395 switch(soc_info.family) {
1396 case RTL8380_FAMILY_ID:
1397 priv->ds->ops = &rtl83xx_switch_ops;
1398 priv->cpu_port = RTL838X_CPU_PORT;
1399 priv->port_mask = 0x1f;
1400 priv->port_width = 1;
1401 priv->irq_mask = 0x0FFFFFFF;
1402 priv->r = &rtl838x_reg;
1403 priv->ds->num_ports = 29;
1404 priv->fib_entries = 8192;
1405 rtl8380_get_version(priv);
1406 priv->n_lags = 8;
1407 priv->l2_bucket_size = 4;
1408 priv->n_pie_blocks = 12;
1409 priv->port_ignore = 0x1f;
1410 priv->n_counters = 128;
1411 break;
1412 case RTL8390_FAMILY_ID:
1413 priv->ds->ops = &rtl83xx_switch_ops;
1414 priv->cpu_port = RTL839X_CPU_PORT;
1415 priv->port_mask = 0x3f;
1416 priv->port_width = 2;
1417 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
1418 priv->r = &rtl839x_reg;
1419 priv->ds->num_ports = 53;
1420 priv->fib_entries = 16384;
1421 rtl8390_get_version(priv);
1422 priv->n_lags = 16;
1423 priv->l2_bucket_size = 4;
1424 priv->n_pie_blocks = 18;
1425 priv->port_ignore = 0x3f;
1426 priv->n_counters = 1024;
1427 break;
1428 case RTL9300_FAMILY_ID:
1429 priv->ds->ops = &rtl930x_switch_ops;
1430 priv->cpu_port = RTL930X_CPU_PORT;
1431 priv->port_mask = 0x1f;
1432 priv->port_width = 1;
1433 priv->irq_mask = 0x0FFFFFFF;
1434 priv->r = &rtl930x_reg;
1435 priv->ds->num_ports = 29;
1436 priv->fib_entries = 16384;
1437 priv->version = RTL8390_VERSION_A;
1438 priv->n_lags = 16;
1439 sw_w32(1, RTL930X_ST_CTRL);
1440 priv->l2_bucket_size = 8;
1441 priv->n_pie_blocks = 16;
1442 priv->port_ignore = 0x3f;
1443 priv->n_counters = 2048;
1444 break;
1445 case RTL9310_FAMILY_ID:
1446 priv->ds->ops = &rtl930x_switch_ops;
1447 priv->cpu_port = RTL931X_CPU_PORT;
1448 priv->port_mask = 0x3f;
1449 priv->port_width = 2;
1450 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
1451 priv->r = &rtl931x_reg;
1452 priv->ds->num_ports = 57;
1453 priv->fib_entries = 16384;
1454 priv->version = RTL8390_VERSION_A;
1455 priv->n_lags = 16;
1456 priv->l2_bucket_size = 8;
1457 break;
1458 }
1459 pr_debug("Chip version %c\n", priv->version);
1460
1461 err = rtl83xx_mdio_probe(priv);
1462 if (err) {
1463 /* Probing fails the 1st time because of missing ethernet driver
1464 * initialization. Use this to disable traffic in case the bootloader left if on
1465 */
1466 return err;
1467 }
1468 err = dsa_register_switch(priv->ds);
1469 if (err) {
1470 dev_err(dev, "Error registering switch: %d\n", err);
1471 return err;
1472 }
1473
1474 /*
1475 * dsa_to_port returns dsa_port from the port list in
1476 * dsa_switch_tree, the tree is built when the switch
1477 * is registered by dsa_register_switch
1478 */
1479 for (i = 0; i <= priv->cpu_port; i++)
1480 priv->ports[i].dp = dsa_to_port(priv->ds, i);
1481
1482 /* Enable link and media change interrupts. Are the SERDES masks needed? */
1483 sw_w32_mask(0, 3, priv->r->isr_glb_src);
1484
1485 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
1486 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
1487
1488 priv->link_state_irq = platform_get_irq(pdev, 0);
1489 pr_info("LINK state irq: %d\n", priv->link_state_irq);
1490 switch (priv->family_id) {
1491 case RTL8380_FAMILY_ID:
1492 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
1493 IRQF_SHARED, "rtl838x-link-state", priv->ds);
1494 break;
1495 case RTL8390_FAMILY_ID:
1496 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
1497 IRQF_SHARED, "rtl839x-link-state", priv->ds);
1498 break;
1499 case RTL9300_FAMILY_ID:
1500 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
1501 IRQF_SHARED, "rtl930x-link-state", priv->ds);
1502 break;
1503 case RTL9310_FAMILY_ID:
1504 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
1505 IRQF_SHARED, "rtl931x-link-state", priv->ds);
1506 break;
1507 }
1508 if (err) {
1509 dev_err(dev, "Error setting up switch interrupt.\n");
1510 /* Need to free allocated switch here */
1511 }
1512
1513 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
1514 if (soc_info.family != RTL9310_FAMILY_ID)
1515 sw_w32(0x1, priv->r->imr_glb);
1516
1517 rtl83xx_get_l2aging(priv);
1518
1519 rtl83xx_setup_qos(priv);
1520
1521 priv->r->l3_setup(priv);
1522
1523 /* Clear all destination ports for mirror groups */
1524 for (i = 0; i < 4; i++)
1525 priv->mirror_group_ports[i] = -1;
1526
1527 /*
1528 * Register netdevice event callback to catch changes in link aggregation groups
1529 */
1530 priv->nb.notifier_call = rtl83xx_netdevice_event;
1531 if (register_netdevice_notifier(&priv->nb)) {
1532 priv->nb.notifier_call = NULL;
1533 dev_err(dev, "Failed to register LAG netdev notifier\n");
1534 goto err_register_nb;
1535 }
1536
1537 // Initialize hash table for L3 routing
1538 rhltable_init(&priv->routes, &route_ht_params);
1539
1540 /*
1541 * Register netevent notifier callback to catch notifications about neighboring
1542 * changes to update nexthop entries for L3 routing.
1543 */
1544 priv->ne_nb.notifier_call = rtl83xx_netevent_event;
1545 if (register_netevent_notifier(&priv->ne_nb)) {
1546 priv->ne_nb.notifier_call = NULL;
1547 dev_err(dev, "Failed to register netevent notifier\n");
1548 goto err_register_ne_nb;
1549 }
1550
1551 priv->fib_nb.notifier_call = rtl83xx_fib_event;
1552
1553 /*
1554 * Register Forwarding Information Base notifier to offload routes where
1555 * where possible
1556 * Only FIBs pointing to our own netdevs are programmed into
1557 * the device, so no need to pass a callback.
1558 */
1559 err = register_fib_notifier(&init_net, &priv->fib_nb, NULL, NULL);
1560 if (err)
1561 goto err_register_fib_nb;
1562
1563 // TODO: put this into l2_setup()
1564 // Flood BPDUs to all ports including cpu-port
1565 if (soc_info.family != RTL9300_FAMILY_ID) {
1566 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
1567 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
1568
1569 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
1570 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
1571
1572 rtl838x_dbgfs_init(priv);
1573 } else {
1574 rtl930x_dbgfs_init(priv);
1575 }
1576
1577 return 0;
1578
1579 err_register_fib_nb:
1580 unregister_netevent_notifier(&priv->ne_nb);
1581 err_register_ne_nb:
1582 unregister_netdevice_notifier(&priv->nb);
1583 err_register_nb:
1584 return err;
1585 }
1586
1587 static int rtl83xx_sw_remove(struct platform_device *pdev)
1588 {
1589 // TODO:
1590 pr_debug("Removing platform driver for rtl83xx-sw\n");
1591 return 0;
1592 }
1593
1594 static const struct of_device_id rtl83xx_switch_of_ids[] = {
1595 { .compatible = "realtek,rtl83xx-switch"},
1596 { /* sentinel */ }
1597 };
1598
1599
1600 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
1601
1602 static struct platform_driver rtl83xx_switch_driver = {
1603 .probe = rtl83xx_sw_probe,
1604 .remove = rtl83xx_sw_remove,
1605 .driver = {
1606 .name = "rtl83xx-switch",
1607 .pm = NULL,
1608 .of_match_table = rtl83xx_switch_of_ids,
1609 },
1610 };
1611
1612 module_platform_driver(rtl83xx_switch_driver);
1613
1614 MODULE_AUTHOR("B. Koblitz");
1615 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
1616 MODULE_LICENSE("GPL");
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