1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/debugfs.h>
4 #include <linux/kernel.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
9 #define RTL838X_DRIVER_NAME "rtl838x"
11 #define RTL8380_LED_GLB_CTRL (0xA000)
12 #define RTL8380_LED_MODE_SEL (0x1004)
13 #define RTL8380_LED_MODE_CTRL (0xA004)
14 #define RTL8380_LED_P_EN_CTRL (0xA008)
15 #define RTL8380_LED_SW_CTRL (0xA00C)
16 #define RTL8380_LED0_SW_P_EN_CTRL (0xA010)
17 #define RTL8380_LED1_SW_P_EN_CTRL (0xA014)
18 #define RTL8380_LED2_SW_P_EN_CTRL (0xA018)
19 #define RTL8380_LED_SW_P_CTRL(p) (0xA01C + (((p) << 2)))
21 #define RTL8390_LED_GLB_CTRL (0x00E4)
22 #define RTL8390_LED_SET_2_3_CTRL (0x00E8)
23 #define RTL8390_LED_SET_0_1_CTRL (0x00EC)
24 #define RTL8390_LED_COPR_SET_SEL_CTRL(p) (0x00F0 + (((p >> 4) << 2)))
25 #define RTL8390_LED_FIB_SET_SEL_CTRL(p) (0x0100 + (((p >> 4) << 2)))
26 #define RTL8390_LED_COPR_PMASK_CTRL(p) (0x0110 + (((p >> 5) << 2)))
27 #define RTL8390_LED_FIB_PMASK_CTRL(p) (0x00118 + (((p >> 5) << 2)))
28 #define RTL8390_LED_COMBO_CTRL(p) (0x0120 + (((p >> 5) << 2)))
29 #define RTL8390_LED_SW_CTRL (0x0128)
30 #define RTL8390_LED_SW_P_EN_CTRL(p) (0x012C + (((p / 10) << 2)))
31 #define RTL8390_LED_SW_P_CTRL(p) (0x0144 + (((p) << 2)))
33 #define RTL838X_MIR_QID_CTRL(grp) (0xAD44 + (((grp) << 2)))
34 #define RTL838X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2)))
35 #define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp) (0xAA70 + (((grp) << 2)))
36 #define RTL838X_MIR_RSPAN_TX_CTRL (0xA350)
37 #define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL (0xAA80)
38 #define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL (0xAA84)
39 #define RTL839X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2)))
40 #define RTL839X_MIR_RSPAN_TX_CTRL (0x69b0)
41 #define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL (0x2550)
42 #define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL (0x2554)
43 #define RTL839X_MIR_SAMPLE_RATE_CTRL (0x2558)
45 #define RTL838X_STAT_PRVTE_DROP_COUNTERS (0x6A00)
46 #define RTL839X_STAT_PRVTE_DROP_COUNTERS (0x3E00)
47 #define RTL930X_STAT_PRVTE_DROP_COUNTERS (0xB5B8)
48 #define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800)
50 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv
*priv
, int port
);
51 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
);
52 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
);
53 u32
rtl838x_get_egress_rate(struct rtl838x_switch_priv
*priv
, int port
);
54 u32
rtl839x_get_egress_rate(struct rtl838x_switch_priv
*priv
, int port
);
55 int rtl838x_set_egress_rate(struct rtl838x_switch_priv
*priv
, int port
, u32 rate
);
56 int rtl839x_set_egress_rate(struct rtl838x_switch_priv
*priv
, int port
, u32 rate
);
59 const char *rtl838x_drop_cntr
[] = {
60 "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP",
61 "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP",
62 "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP",
63 "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP",
64 "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP",
65 "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP",
66 "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP",
67 "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP",
68 "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP",
69 "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards"
72 const char *rtl839x_drop_cntr
[] = {
73 "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP",
74 "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR",
75 "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW",
76 "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA",
77 "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA",
78 "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING",
79 "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP",
80 "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE",
81 "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL",
82 "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR",
83 "LINK_STATUS_BEFORE_MIRROR",
84 "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR",
85 "LINK_STATUS_AFTER_MIRROR",
89 const char *rtl930x_drop_cntr
[] = {
90 "OAM_PARSER", "UC_RPF", "DEI_CFI", "MAC_IP_SUBNET_BASED_VLAN", "VLAN_IGR_FILTER",
91 "L2_UC_MC", "IPV_IP6_MC_BRIDGE", "PTP", "USER_DEF_0_3", "RESERVED",
92 "RESERVED1", "RESERVED2", "BPDU_RMA", "LACP", "LLDP",
93 "EAPOL", "XX_RMA", "L3_IPUC_NON_IP", "IP4_IP6_HEADER_ERROR", "L3_BAD_IP",
94 "L3_DIP_DMAC_MISMATCH", "IP4_IP_OPTION", "IP_UC_MC_ROUTING_LOOK_UP_MISS", "L3_DST_NULL_INTF",
96 "HOST_NULL_INTF", "ROUTE_NULL_INTF", "BRIDGING_ACTION", "ROUTING_ACTION", "IPMC_RPF",
97 "L2_NEXTHOP_AGE_OUT", "L3_UC_TTL_FAIL", "L3_MC_TTL_FAIL", "L3_UC_MTU_FAIL", "L3_MC_MTU_FAIL",
98 "L3_UC_ICMP_REDIR", "IP6_MLD_OTHER_ACT", "ND", "IP_MC_RESERVED", "IP6_HBH",
99 "INVALID_SA", "L2_HASH_FULL", "NEW_SA", "PORT_MOVE_FORBID", "STATIC_PORT_MOVING",
100 "DYNMIC_PORT_MOVING", "L3_CRC", "MAC_LIMIT", "ATTACK_PREVENT", "ACL_FWD_ACTION",
101 "OAMPDU", "OAM_MUX", "TRUNK_FILTER", "ACL_DROP", "IGR_BW",
102 "ACL_METER", "VLAN_ACCEPT_FRAME_TYPE", "MSTP_SRC_DROP_DISABLED_BLOCKING", "SA_BLOCK", "DA_BLOCK",
103 "STORM_CONTROL", "VLAN_EGR_FILTER", "MSTP_DESTINATION_DROP", "SRC_PORT_FILTER", "PORT_ISOLATION",
104 "TX_MAX_FRAME_SIZE", "EGR_LINK_STATUS", "MAC_TX_DISABLE", "MAC_PAUSE_FRAME", "MAC_RX_DROP",
105 "MIRROR_ISOLATE", "RX_FC", "EGR_QUEUE", "HSM_RUNOUT", "ROUTING_DISABLE", "INVALID_L2_NEXTHOP_ENTRY",
106 "L3_MC_SRC_FLT", "CPUTAG_FLT", "FWD_PMSK_NULL", "IPUC_ROUTING_LOOKUP_MISS", "MY_DEV_DROP",
107 "STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER"
110 const char *rtl931x_drop_cntr
[] = {
111 "ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS",
112 "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", // 10
113 "STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET",
114 "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", // 20
115 "MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK",
116 "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", // 30,
117 "OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN",
118 "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", // 40
119 "L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA",
120 "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", // 50
121 "MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH",
122 "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", // 60
123 "ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER",
124 "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", // 70
125 "L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM",
126 "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM" // 80,
129 static ssize_t
rtl838x_common_read(char __user
*buffer
, size_t count
,
130 loff_t
*ppos
, unsigned int value
)
138 buf
= kasprintf(GFP_KERNEL
, "0x%08x\n", value
);
142 if (count
< strlen(buf
)) {
147 len
= simple_read_from_buffer(buffer
, count
, ppos
, buf
, strlen(buf
));
153 static ssize_t
rtl838x_common_write(const char __user
*buffer
, size_t count
,
154 loff_t
*ppos
, unsigned int *value
)
163 if (count
>= sizeof(b
))
166 len
= simple_write_to_buffer(b
, sizeof(b
) - 1, ppos
,
172 ret
= kstrtouint(b
, 16, value
);
179 static ssize_t
stp_state_read(struct file
*filp
, char __user
*buffer
, size_t count
,
182 struct rtl838x_port
*p
= filp
->private_data
;
183 struct dsa_switch
*ds
= p
->dp
->ds
;
184 int value
= rtl83xx_port_get_stp_state(ds
->priv
, p
->dp
->index
);
189 return rtl838x_common_read(buffer
, count
, ppos
, (u32
)value
);
192 static ssize_t
stp_state_write(struct file
*filp
, const char __user
*buffer
,
193 size_t count
, loff_t
*ppos
)
195 struct rtl838x_port
*p
= filp
->private_data
;
197 size_t res
= rtl838x_common_write(buffer
, count
, ppos
, &value
);
201 rtl83xx_port_stp_state_set(p
->dp
->ds
, p
->dp
->index
, (u8
)value
);
206 static const struct file_operations stp_state_fops
= {
207 .owner
= THIS_MODULE
,
209 .read
= stp_state_read
,
210 .write
= stp_state_write
,
213 static ssize_t
drop_counter_read(struct file
*filp
, char __user
*buffer
, size_t count
,
216 struct rtl838x_switch_priv
*priv
= filp
->private_data
;
221 int n
= 0, len
, offset
;
224 switch (priv
->family_id
) {
225 case RTL8380_FAMILY_ID
:
226 d
= rtl838x_drop_cntr
;
227 offset
= RTL838X_STAT_PRVTE_DROP_COUNTERS
;
230 case RTL8390_FAMILY_ID
:
231 d
= rtl839x_drop_cntr
;
232 offset
= RTL839X_STAT_PRVTE_DROP_COUNTERS
;
235 case RTL9300_FAMILY_ID
:
236 d
= rtl930x_drop_cntr
;
237 offset
= RTL930X_STAT_PRVTE_DROP_COUNTERS
;
240 case RTL9310_FAMILY_ID
:
241 d
= rtl931x_drop_cntr
;
242 offset
= RTL931X_STAT_PRVTE_DROP_COUNTERS
;
247 buf
= kmalloc(30 * num
, GFP_KERNEL
);
251 for (i
= 0; i
< num
; i
++) {
252 v
= sw_r32(offset
+ (i
<< 2)) & 0xffff;
253 n
+= sprintf(buf
+ n
, "%s: %d\n", d
[i
], v
);
256 if (count
< strlen(buf
)) {
261 len
= simple_read_from_buffer(buffer
, count
, ppos
, buf
, strlen(buf
));
267 static const struct file_operations drop_counter_fops
= {
268 .owner
= THIS_MODULE
,
270 .read
= drop_counter_read
,
273 static void l2_table_print_entry(struct seq_file
*m
, struct rtl838x_switch_priv
*priv
,
274 struct rtl838x_l2_entry
*e
)
279 if (e
->type
== L2_UNICAST
) {
280 seq_puts(m
, "L2_UNICAST\n");
282 seq_printf(m
, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n",
283 e
->mac
[0], e
->mac
[1], e
->mac
[2], e
->mac
[3], e
->mac
[4], e
->mac
[5],
286 seq_printf(m
, " port %d age %d", e
->port
, e
->age
);
288 seq_puts(m
, " static");
290 seq_puts(m
, " block_da");
292 seq_puts(m
, " block_sa");
294 seq_puts(m
, " suspended");
296 seq_printf(m
, " next_hop route_id %u", e
->nh_route_id
);
300 if (e
->type
== L2_MULTICAST
) {
301 seq_puts(m
, "L2_MULTICAST\n");
303 seq_printf(m
, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n",
304 e
->mac
[0], e
->mac
[1], e
->mac
[2], e
->mac
[3], e
->mac
[4], e
->mac
[5],
308 if (e
->type
== IP4_MULTICAST
|| e
->type
== IP6_MULTICAST
) {
309 seq_puts(m
, (e
->type
== IP4_MULTICAST
) ?
310 "IP4_MULTICAST\n" : "IP6_MULTICAST\n");
312 seq_printf(m
, " gip %08x sip %08x vid %u rvid %u\n",
313 e
->mc_gip
, e
->mc_sip
, e
->vid
, e
->rvid
);
316 portmask
= priv
->r
->read_mcast_pmask(e
->mc_portmask_index
);
317 seq_printf(m
, " index %u ports", e
->mc_portmask_index
);
318 for (i
= 0; i
< 64; i
++) {
319 if (portmask
& BIT_ULL(i
))
320 seq_printf(m
, " %d", i
);
328 static int l2_table_show(struct seq_file
*m
, void *v
)
330 struct rtl838x_switch_priv
*priv
= m
->private;
331 struct rtl838x_l2_entry e
;
332 int i
, bucket
, index
;
334 mutex_lock(&priv
->reg_mutex
);
336 for (i
= 0; i
< priv
->fib_entries
; i
++) {
339 priv
->r
->read_l2_entry_using_hash(bucket
, index
, &e
);
344 seq_printf(m
, "Hash table bucket %d index %d ", bucket
, index
);
345 l2_table_print_entry(m
, priv
, &e
);
348 for (i
= 0; i
< 64; i
++) {
349 priv
->r
->read_cam(i
, &e
);
354 seq_printf(m
, "CAM index %d ", i
);
355 l2_table_print_entry(m
, priv
, &e
);
358 mutex_unlock(&priv
->reg_mutex
);
363 static int l2_table_open(struct inode
*inode
, struct file
*filp
)
365 return single_open(filp
, l2_table_show
, inode
->i_private
);
368 static const struct file_operations l2_table_fops
= {
369 .owner
= THIS_MODULE
,
370 .open
= l2_table_open
,
373 .release
= single_release
,
376 static ssize_t
age_out_read(struct file
*filp
, char __user
*buffer
, size_t count
,
379 struct rtl838x_port
*p
= filp
->private_data
;
380 struct dsa_switch
*ds
= p
->dp
->ds
;
381 struct rtl838x_switch_priv
*priv
= ds
->priv
;
382 int value
= sw_r32(priv
->r
->l2_port_aging_out
);
387 return rtl838x_common_read(buffer
, count
, ppos
, (u32
)value
);
390 static ssize_t
age_out_write(struct file
*filp
, const char __user
*buffer
,
391 size_t count
, loff_t
*ppos
)
393 struct rtl838x_port
*p
= filp
->private_data
;
395 size_t res
= rtl838x_common_write(buffer
, count
, ppos
, &value
);
399 rtl83xx_fast_age(p
->dp
->ds
, p
->dp
->index
);
404 static const struct file_operations age_out_fops
= {
405 .owner
= THIS_MODULE
,
407 .read
= age_out_read
,
408 .write
= age_out_write
,
411 static ssize_t
port_egress_rate_read(struct file
*filp
, char __user
*buffer
, size_t count
,
414 struct rtl838x_port
*p
= filp
->private_data
;
415 struct dsa_switch
*ds
= p
->dp
->ds
;
416 struct rtl838x_switch_priv
*priv
= ds
->priv
;
418 if (priv
->family_id
== RTL8380_FAMILY_ID
)
419 value
= rtl838x_get_egress_rate(priv
, p
->dp
->index
);
421 value
= rtl839x_get_egress_rate(priv
, p
->dp
->index
);
426 return rtl838x_common_read(buffer
, count
, ppos
, (u32
)value
);
429 static ssize_t
port_egress_rate_write(struct file
*filp
, const char __user
*buffer
,
430 size_t count
, loff_t
*ppos
)
432 struct rtl838x_port
*p
= filp
->private_data
;
433 struct dsa_switch
*ds
= p
->dp
->ds
;
434 struct rtl838x_switch_priv
*priv
= ds
->priv
;
436 size_t res
= rtl838x_common_write(buffer
, count
, ppos
, &value
);
440 if (priv
->family_id
== RTL8380_FAMILY_ID
)
441 rtl838x_set_egress_rate(priv
, p
->dp
->index
, value
);
443 rtl839x_set_egress_rate(priv
, p
->dp
->index
, value
);
448 static const struct file_operations port_egress_fops
= {
449 .owner
= THIS_MODULE
,
451 .read
= port_egress_rate_read
,
452 .write
= port_egress_rate_write
,
456 static const struct debugfs_reg32 port_ctrl_regs
[] = {
457 { .name
= "port_isolation", .offset
= RTL838X_PORT_ISO_CTRL(0), },
458 { .name
= "mac_force_mode", .offset
= RTL838X_MAC_FORCE_MODE_CTRL
, },
461 void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv
*priv
)
463 debugfs_remove_recursive(priv
->dbgfs_dir
);
465 // kfree(priv->dbgfs_entries);
468 static int rtl838x_dbgfs_port_init(struct dentry
*parent
, struct rtl838x_switch_priv
*priv
,
471 struct dentry
*port_dir
;
472 struct debugfs_regset32
*port_ctrl_regset
;
474 port_dir
= debugfs_create_dir(priv
->ports
[port
].dp
->name
, parent
);
476 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
477 debugfs_create_x32("storm_rate_uc", 0644, port_dir
,
478 (u32
*)(RTL838X_SW_BASE
+ RTL838X_STORM_CTRL_PORT_UC(port
)));
480 debugfs_create_x32("storm_rate_mc", 0644, port_dir
,
481 (u32
*)(RTL838X_SW_BASE
+ RTL838X_STORM_CTRL_PORT_MC(port
)));
483 debugfs_create_x32("storm_rate_bc", 0644, port_dir
,
484 (u32
*)(RTL838X_SW_BASE
+ RTL838X_STORM_CTRL_PORT_BC(port
)));
486 debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir
,
487 (u32
*)(RTL838X_SW_BASE
+ RTL838X_VLAN_PORT_TAG_STS_CTRL
490 debugfs_create_x32("storm_rate_uc", 0644, port_dir
,
491 (u32
*)(RTL838X_SW_BASE
+ RTL839X_STORM_CTRL_PORT_UC_0(port
)));
493 debugfs_create_x32("storm_rate_mc", 0644, port_dir
,
494 (u32
*)(RTL838X_SW_BASE
+ RTL839X_STORM_CTRL_PORT_MC_0(port
)));
496 debugfs_create_x32("storm_rate_bc", 0644, port_dir
,
497 (u32
*)(RTL838X_SW_BASE
+ RTL839X_STORM_CTRL_PORT_BC_0(port
)));
499 debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir
,
500 (u32
*)(RTL838X_SW_BASE
+ RTL839X_VLAN_PORT_TAG_STS_CTRL
504 debugfs_create_u32("id", 0444, port_dir
, (u32
*)&priv
->ports
[port
].dp
->index
);
506 port_ctrl_regset
= devm_kzalloc(priv
->dev
, sizeof(*port_ctrl_regset
), GFP_KERNEL
);
507 if (!port_ctrl_regset
)
510 port_ctrl_regset
->regs
= port_ctrl_regs
;
511 port_ctrl_regset
->nregs
= ARRAY_SIZE(port_ctrl_regs
);
512 port_ctrl_regset
->base
= (void *)(RTL838X_SW_BASE
+ (port
<< 2));
513 debugfs_create_regset32("port_ctrl", 0400, port_dir
, port_ctrl_regset
);
515 debugfs_create_file("stp_state", 0600, port_dir
, &priv
->ports
[port
], &stp_state_fops
);
516 debugfs_create_file("age_out", 0600, port_dir
, &priv
->ports
[port
], &age_out_fops
);
517 debugfs_create_file("port_egress_rate", 0600, port_dir
, &priv
->ports
[port
],
522 static int rtl838x_dbgfs_leds(struct dentry
*parent
, struct rtl838x_switch_priv
*priv
)
524 struct dentry
*led_dir
;
526 char led_sw_p_ctrl_name
[20];
527 char port_led_name
[20];
529 led_dir
= debugfs_create_dir("led", parent
);
531 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
532 debugfs_create_x32("led_glb_ctrl", 0644, led_dir
,
533 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED_GLB_CTRL
));
534 debugfs_create_x32("led_mode_sel", 0644, led_dir
,
535 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED_MODE_SEL
));
536 debugfs_create_x32("led_mode_ctrl", 0644, led_dir
,
537 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED_MODE_CTRL
));
538 debugfs_create_x32("led_p_en_ctrl", 0644, led_dir
,
539 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED_P_EN_CTRL
));
540 debugfs_create_x32("led_sw_ctrl", 0644, led_dir
,
541 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED_SW_CTRL
));
542 debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir
,
543 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED0_SW_P_EN_CTRL
));
544 debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir
,
545 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED1_SW_P_EN_CTRL
));
546 debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir
,
547 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED2_SW_P_EN_CTRL
));
548 for (p
= 0; p
< 28; p
++) {
549 snprintf(led_sw_p_ctrl_name
, sizeof(led_sw_p_ctrl_name
),
550 "led_sw_p_ctrl.%02d", p
);
551 debugfs_create_x32(led_sw_p_ctrl_name
, 0644, led_dir
,
552 (u32
*)(RTL838X_SW_BASE
+ RTL8380_LED_SW_P_CTRL(p
)));
554 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
555 debugfs_create_x32("led_glb_ctrl", 0644, led_dir
,
556 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_GLB_CTRL
));
557 debugfs_create_x32("led_set_2_3", 0644, led_dir
,
558 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_SET_2_3_CTRL
));
559 debugfs_create_x32("led_set_0_1", 0644, led_dir
,
560 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_SET_0_1_CTRL
));
561 for (p
= 0; p
< 4; p
++) {
562 snprintf(port_led_name
, sizeof(port_led_name
), "led_copr_set_sel.%1d", p
);
563 debugfs_create_x32(port_led_name
, 0644, led_dir
,
564 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_COPR_SET_SEL_CTRL(p
<< 4)));
565 snprintf(port_led_name
, sizeof(port_led_name
), "led_fib_set_sel.%1d", p
);
566 debugfs_create_x32(port_led_name
, 0644, led_dir
,
567 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_FIB_SET_SEL_CTRL(p
<< 4)));
569 debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir
,
570 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_COPR_PMASK_CTRL(0)));
571 debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir
,
572 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_COPR_PMASK_CTRL(32)));
573 debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir
,
574 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_FIB_PMASK_CTRL(0)));
575 debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir
,
576 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_FIB_PMASK_CTRL(32)));
577 debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir
,
578 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_COMBO_CTRL(0)));
579 debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir
,
580 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_COMBO_CTRL(32)));
581 debugfs_create_x32("led_sw_ctrl", 0644, led_dir
,
582 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_SW_CTRL
));
583 for (p
= 0; p
< 5; p
++) {
584 snprintf(port_led_name
, sizeof(port_led_name
), "led_sw_p_en_ctrl.%1d", p
);
585 debugfs_create_x32(port_led_name
, 0644, led_dir
,
586 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_SW_P_EN_CTRL(p
* 10)));
588 for (p
= 0; p
< 28; p
++) {
589 snprintf(port_led_name
, sizeof(port_led_name
), "led_sw_p_ctrl.%02d", p
);
590 debugfs_create_x32(port_led_name
, 0644, led_dir
,
591 (u32
*)(RTL838X_SW_BASE
+ RTL8390_LED_SW_P_CTRL(p
)));
597 void rtl838x_dbgfs_init(struct rtl838x_switch_priv
*priv
)
599 struct dentry
*rtl838x_dir
;
600 struct dentry
*port_dir
;
601 struct dentry
*mirror_dir
;
602 struct debugfs_regset32
*port_ctrl_regset
;
605 char mirror_name
[10];
607 pr_info("%s called\n", __func__
);
608 rtl838x_dir
= debugfs_lookup(RTL838X_DRIVER_NAME
, NULL
);
610 rtl838x_dir
= debugfs_create_dir(RTL838X_DRIVER_NAME
, NULL
);
612 priv
->dbgfs_dir
= rtl838x_dir
;
614 debugfs_create_u32("soc", 0444, rtl838x_dir
,
615 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MODEL_NAME_INFO
));
617 /* Create one directory per port */
618 for (i
= 0; i
< priv
->cpu_port
; i
++) {
619 if (priv
->ports
[i
].phy
) {
620 ret
= rtl838x_dbgfs_port_init(rtl838x_dir
, priv
, i
);
626 /* Create directory for CPU-port */
627 port_dir
= debugfs_create_dir("cpu_port", rtl838x_dir
);
628 port_ctrl_regset
= devm_kzalloc(priv
->dev
, sizeof(*port_ctrl_regset
), GFP_KERNEL
);
629 if (!port_ctrl_regset
) {
634 port_ctrl_regset
->regs
= port_ctrl_regs
;
635 port_ctrl_regset
->nregs
= ARRAY_SIZE(port_ctrl_regs
);
636 port_ctrl_regset
->base
= (void *)(RTL838X_SW_BASE
+ (priv
->cpu_port
<< 2));
637 debugfs_create_regset32("port_ctrl", 0400, port_dir
, port_ctrl_regset
);
638 debugfs_create_u8("id", 0444, port_dir
, &priv
->cpu_port
);
640 /* Create entries for LAGs */
641 for (i
= 0; i
< priv
->n_lags
; i
++) {
642 snprintf(lag_name
, sizeof(lag_name
), "lag.%02d", i
);
643 if (priv
->family_id
== RTL8380_FAMILY_ID
)
644 debugfs_create_x32(lag_name
, 0644, rtl838x_dir
,
645 (u32
*)(RTL838X_SW_BASE
+ priv
->r
->trk_mbr_ctr(i
)));
647 debugfs_create_x64(lag_name
, 0644, rtl838x_dir
,
648 (u64
*)(RTL838X_SW_BASE
+ priv
->r
->trk_mbr_ctr(i
)));
651 /* Create directories for mirror groups */
652 for (i
= 0; i
< 4; i
++) {
653 snprintf(mirror_name
, sizeof(mirror_name
), "mirror.%1d", i
);
654 mirror_dir
= debugfs_create_dir(mirror_name
, rtl838x_dir
);
655 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
656 debugfs_create_x32("ctrl", 0644, mirror_dir
,
657 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_CTRL
+ i
* 4));
658 debugfs_create_x32("ingress_pm", 0644, mirror_dir
,
659 (u32
*)(RTL838X_SW_BASE
+ priv
->r
->mir_spm
+ i
* 4));
660 debugfs_create_x32("egress_pm", 0644, mirror_dir
,
661 (u32
*)(RTL838X_SW_BASE
+ priv
->r
->mir_dpm
+ i
* 4));
662 debugfs_create_x32("qid", 0644, mirror_dir
,
663 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_QID_CTRL(i
)));
664 debugfs_create_x32("rspan_vlan", 0644, mirror_dir
,
665 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_RSPAN_VLAN_CTRL(i
)));
666 debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir
,
667 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i
)));
668 debugfs_create_x32("rspan_tx", 0644, mirror_dir
,
669 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_RSPAN_TX_CTRL
));
670 debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir
,
671 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL
));
672 debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir
,
673 (u32
*)(RTL838X_SW_BASE
+ RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL
));
675 debugfs_create_x32("ctrl", 0644, mirror_dir
,
676 (u32
*)(RTL838X_SW_BASE
+ RTL839X_MIR_CTRL
+ i
* 4));
677 debugfs_create_x64("ingress_pm", 0644, mirror_dir
,
678 (u64
*)(RTL838X_SW_BASE
+ priv
->r
->mir_spm
+ i
* 8));
679 debugfs_create_x64("egress_pm", 0644, mirror_dir
,
680 (u64
*)(RTL838X_SW_BASE
+ priv
->r
->mir_dpm
+ i
* 8));
681 debugfs_create_x32("rspan_vlan", 0644, mirror_dir
,
682 (u32
*)(RTL838X_SW_BASE
+ RTL839X_MIR_RSPAN_VLAN_CTRL(i
)));
683 debugfs_create_x32("rspan_tx", 0644, mirror_dir
,
684 (u32
*)(RTL838X_SW_BASE
+ RTL839X_MIR_RSPAN_TX_CTRL
));
685 debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir
,
686 (u32
*)(RTL838X_SW_BASE
+ RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL
));
687 debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir
,
688 (u32
*)(RTL838X_SW_BASE
+ RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL
));
689 debugfs_create_x64("sample_rate", 0644, mirror_dir
,
690 (u64
*)(RTL838X_SW_BASE
+ RTL839X_MIR_SAMPLE_RATE_CTRL
));
694 if (priv
->family_id
== RTL8380_FAMILY_ID
)
695 debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir
,
696 (u32
*)(RTL838X_SW_BASE
+ priv
->r
->rma_bpdu_fld_pmask
));
698 debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir
,
699 (u64
*)(RTL838X_SW_BASE
+ priv
->r
->rma_bpdu_fld_pmask
));
701 if (priv
->family_id
== RTL8380_FAMILY_ID
)
702 debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir
,
703 (u32
*)(RTL838X_SW_BASE
+ RTL838X_VLAN_CTRL
));
705 debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir
,
706 (u32
*)(RTL838X_SW_BASE
+ RTL839X_VLAN_CTRL
));
708 ret
= rtl838x_dbgfs_leds(rtl838x_dir
, priv
);
712 debugfs_create_file("drop_counters", 0400, rtl838x_dir
, priv
, &drop_counter_fops
);
714 debugfs_create_file("l2_table", 0400, rtl838x_dir
, priv
, &l2_table_fops
);
718 rtl838x_dbgfs_cleanup(priv
);
721 void rtl930x_dbgfs_init(struct rtl838x_switch_priv
*priv
)
723 struct dentry
*dbg_dir
;
725 pr_info("%s called\n", __func__
);
726 dbg_dir
= debugfs_lookup(RTL838X_DRIVER_NAME
, NULL
);
728 dbg_dir
= debugfs_create_dir(RTL838X_DRIVER_NAME
, NULL
);
730 priv
->dbgfs_dir
= dbg_dir
;
732 debugfs_create_file("drop_counters", 0400, dbg_dir
, priv
, &drop_counter_fops
);
734 debugfs_create_file("l2_table", 0400, dbg_dir
, priv
, &l2_table_fops
);