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12334dff9f351f70b5773a98d6238ff5d620a5cc
[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_debug("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134
135 // Initialize all vlans 0-4095
136 for (i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 // reset PVIDs; defaults to 1 on reset
140 for (i = 0; i <= priv->ds->num_ports; i++)
141 sw_w32(0, priv->r->vlan_port_pb + (i << 2));
142
143 // Set forwarding action based on inner VLAN tag
144 for (i = 0; i < priv->cpu_port; i++)
145 priv->r->vlan_fwd_on_inner(i, true);
146 }
147
148 static int rtl83xx_setup(struct dsa_switch *ds)
149 {
150 int i;
151 struct rtl838x_switch_priv *priv = ds->priv;
152 u64 port_bitmap = BIT_ULL(priv->cpu_port);
153
154 pr_debug("%s called\n", __func__);
155
156 /* Disable MAC polling the PHY so that we can start configuration */
157 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
158
159 for (i = 0; i < ds->num_ports; i++)
160 priv->ports[i].enable = false;
161 priv->ports[priv->cpu_port].enable = true;
162
163 /* Isolate ports from each other: traffic only CPU <-> port */
164 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
165 * traffic from source port i to destination port j
166 */
167 for (i = 0; i < priv->cpu_port; i++) {
168 if (priv->ports[i].phy) {
169 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
170 priv->r->port_iso_ctrl(i));
171 port_bitmap |= BIT_ULL(i);
172 }
173 }
174 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
175
176 if (priv->family_id == RTL8380_FAMILY_ID)
177 rtl838x_print_matrix();
178 else
179 rtl839x_print_matrix();
180
181 rtl83xx_init_stats(priv);
182
183 rtl83xx_vlan_setup(priv);
184
185 ds->configure_vlan_while_not_filtering = true;
186
187 priv->r->l2_learning_setup();
188
189 /* Enable MAC Polling PHY again */
190 rtl83xx_enable_phy_polling(priv);
191 pr_debug("Please wait until PHY is settled\n");
192 msleep(1000);
193 priv->r->pie_init(priv);
194
195 return 0;
196 }
197
198 static int rtl930x_setup(struct dsa_switch *ds)
199 {
200 int i;
201 struct rtl838x_switch_priv *priv = ds->priv;
202 u32 port_bitmap = BIT(priv->cpu_port);
203
204 pr_info("%s called\n", __func__);
205
206 // Enable CSTI STP mode
207 // sw_w32(1, RTL930X_ST_CTRL);
208
209 /* Disable MAC polling the PHY so that we can start configuration */
210 sw_w32(0, RTL930X_SMI_POLL_CTRL);
211
212 // Disable all ports except CPU port
213 for (i = 0; i < ds->num_ports; i++)
214 priv->ports[i].enable = false;
215 priv->ports[priv->cpu_port].enable = true;
216
217 for (i = 0; i < priv->cpu_port; i++) {
218 if (priv->ports[i].phy) {
219 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
220 port_bitmap |= BIT_ULL(i);
221 }
222 }
223 priv->r->traffic_set(priv->cpu_port, port_bitmap);
224
225 rtl930x_print_matrix();
226
227 // TODO: Initialize statistics
228
229 rtl83xx_vlan_setup(priv);
230
231 ds->configure_vlan_while_not_filtering = true;
232
233 priv->r->l2_learning_setup();
234
235 rtl83xx_enable_phy_polling(priv);
236
237 priv->r->pie_init(priv);
238
239 return 0;
240 }
241
242 static int rtl93xx_get_sds(struct phy_device *phydev)
243 {
244 struct device *dev = &phydev->mdio.dev;
245 struct device_node *dn;
246 u32 sds_num;
247
248 if (!dev)
249 return -1;
250 if (dev->of_node) {
251 dn = dev->of_node;
252 if (of_property_read_u32(dn, "sds", &sds_num))
253 sds_num = -1;
254 } else {
255 dev_err(dev, "No DT node.\n");
256 return -1;
257 }
258
259 return sds_num;
260 }
261
262 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
263 unsigned long *supported,
264 struct phylink_link_state *state)
265 {
266 struct rtl838x_switch_priv *priv = ds->priv;
267 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
268
269 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
270
271 if (!phy_interface_mode_is_rgmii(state->interface) &&
272 state->interface != PHY_INTERFACE_MODE_NA &&
273 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
274 state->interface != PHY_INTERFACE_MODE_MII &&
275 state->interface != PHY_INTERFACE_MODE_REVMII &&
276 state->interface != PHY_INTERFACE_MODE_GMII &&
277 state->interface != PHY_INTERFACE_MODE_QSGMII &&
278 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
279 state->interface != PHY_INTERFACE_MODE_SGMII) {
280 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
281 dev_err(ds->dev,
282 "Unsupported interface: %d for port %d\n",
283 state->interface, port);
284 return;
285 }
286
287 /* Allow all the expected bits */
288 phylink_set(mask, Autoneg);
289 phylink_set_port_modes(mask);
290 phylink_set(mask, Pause);
291 phylink_set(mask, Asym_Pause);
292
293 /* With the exclusion of MII and Reverse MII, we support Gigabit,
294 * including Half duplex
295 */
296 if (state->interface != PHY_INTERFACE_MODE_MII &&
297 state->interface != PHY_INTERFACE_MODE_REVMII) {
298 phylink_set(mask, 1000baseT_Full);
299 phylink_set(mask, 1000baseT_Half);
300 }
301
302 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
303 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
304 phylink_set(mask, 1000baseX_Full);
305
306 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
307 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
308 phylink_set(mask, 1000baseX_Full);
309
310 phylink_set(mask, 10baseT_Half);
311 phylink_set(mask, 10baseT_Full);
312 phylink_set(mask, 100baseT_Half);
313 phylink_set(mask, 100baseT_Full);
314
315 bitmap_and(supported, supported, mask,
316 __ETHTOOL_LINK_MODE_MASK_NBITS);
317 bitmap_and(state->advertising, state->advertising, mask,
318 __ETHTOOL_LINK_MODE_MASK_NBITS);
319 }
320
321 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
322 unsigned long *supported,
323 struct phylink_link_state *state)
324 {
325 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
326
327 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
328 phy_modes(state->interface));
329
330 if (!phy_interface_mode_is_rgmii(state->interface) &&
331 state->interface != PHY_INTERFACE_MODE_NA &&
332 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
333 state->interface != PHY_INTERFACE_MODE_MII &&
334 state->interface != PHY_INTERFACE_MODE_REVMII &&
335 state->interface != PHY_INTERFACE_MODE_GMII &&
336 state->interface != PHY_INTERFACE_MODE_QSGMII &&
337 state->interface != PHY_INTERFACE_MODE_XGMII &&
338 state->interface != PHY_INTERFACE_MODE_HSGMII &&
339 state->interface != PHY_INTERFACE_MODE_10GKR &&
340 state->interface != PHY_INTERFACE_MODE_USXGMII &&
341 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
342 state->interface != PHY_INTERFACE_MODE_SGMII) {
343 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
344 dev_err(ds->dev,
345 "Unsupported interface: %d for port %d\n",
346 state->interface, port);
347 return;
348 }
349
350 /* Allow all the expected bits */
351 phylink_set(mask, Autoneg);
352 phylink_set_port_modes(mask);
353 phylink_set(mask, Pause);
354 phylink_set(mask, Asym_Pause);
355
356 /* With the exclusion of MII and Reverse MII, we support Gigabit,
357 * including Half duplex
358 */
359 if (state->interface != PHY_INTERFACE_MODE_MII &&
360 state->interface != PHY_INTERFACE_MODE_REVMII) {
361 phylink_set(mask, 1000baseT_Full);
362 phylink_set(mask, 1000baseT_Half);
363 }
364
365 /* On the RTL9300 family of SoCs, ports 26 to 27 may be SFP ports TODO: take out of .dts */
366 if (port >= 26 && port <= 27)
367 phylink_set(mask, 1000baseX_Full);
368 if (port >= 26 && port <= 27)
369 phylink_set(mask, 10000baseKR_Full);
370
371 phylink_set(mask, 10baseT_Half);
372 phylink_set(mask, 10baseT_Full);
373 phylink_set(mask, 100baseT_Half);
374 phylink_set(mask, 100baseT_Full);
375
376 bitmap_and(supported, supported, mask,
377 __ETHTOOL_LINK_MODE_MASK_NBITS);
378 bitmap_and(state->advertising, state->advertising, mask,
379 __ETHTOOL_LINK_MODE_MASK_NBITS);
380 }
381
382 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
383 struct phylink_link_state *state)
384 {
385 struct rtl838x_switch_priv *priv = ds->priv;
386 u64 speed;
387 u64 link;
388
389 if (port < 0 || port > priv->cpu_port)
390 return -EINVAL;
391
392 state->link = 0;
393 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
394 if (link & BIT_ULL(port))
395 state->link = 1;
396 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
397
398 state->duplex = 0;
399 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
400 state->duplex = 1;
401
402 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
403 speed >>= (port % 16) << 1;
404 switch (speed & 0x3) {
405 case 0:
406 state->speed = SPEED_10;
407 break;
408 case 1:
409 state->speed = SPEED_100;
410 break;
411 case 2:
412 state->speed = SPEED_1000;
413 break;
414 case 3:
415 if (priv->family_id == RTL9300_FAMILY_ID
416 && (port == 24 || port == 26)) /* Internal serdes */
417 state->speed = SPEED_2500;
418 else
419 state->speed = SPEED_100; /* Is in fact 500Mbit */
420 }
421
422 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
423 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
424 state->pause |= MLO_PAUSE_RX;
425 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
426 state->pause |= MLO_PAUSE_TX;
427 return 1;
428 }
429
430 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
431 struct phylink_link_state *state)
432 {
433 struct rtl838x_switch_priv *priv = ds->priv;
434 u64 speed;
435 u64 link;
436
437 if (port < 0 || port > priv->cpu_port)
438 return -EINVAL;
439
440 /*
441 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
442 * state needs to be read twice in order to read a correct result.
443 * This would not be necessary for ports connected e.g. to RTL8218D
444 * PHYs.
445 */
446 state->link = 0;
447 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
448 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
449 if (link & BIT_ULL(port))
450 state->link = 1;
451 pr_debug("%s: link state port %d: %llx, media %08x\n", __func__, port,
452 link & BIT_ULL(port), sw_r32(RTL930X_MAC_LINK_MEDIA_STS));
453
454 state->duplex = 0;
455 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
456 state->duplex = 1;
457
458 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
459 speed >>= (port % 8) << 2;
460 switch (speed & 0xf) {
461 case 0:
462 state->speed = SPEED_10;
463 break;
464 case 1:
465 state->speed = SPEED_100;
466 break;
467 case 2:
468 case 7:
469 state->speed = SPEED_1000;
470 break;
471 case 4:
472 state->speed = SPEED_10000;
473 break;
474 case 5:
475 case 8:
476 state->speed = SPEED_2500;
477 break;
478 case 6:
479 state->speed = SPEED_5000;
480 break;
481 default:
482 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
483 }
484
485 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
486 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
487 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
488 state->pause |= MLO_PAUSE_RX;
489 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
490 state->pause |= MLO_PAUSE_TX;
491 return 1;
492 }
493
494 static void rtl83xx_config_interface(int port, phy_interface_t interface)
495 {
496 u32 old, int_shift, sds_shift;
497
498 switch (port) {
499 case 24:
500 int_shift = 0;
501 sds_shift = 5;
502 break;
503 case 26:
504 int_shift = 3;
505 sds_shift = 0;
506 break;
507 default:
508 return;
509 }
510
511 old = sw_r32(RTL838X_SDS_MODE_SEL);
512 switch (interface) {
513 case PHY_INTERFACE_MODE_1000BASEX:
514 if ((old >> sds_shift & 0x1f) == 4)
515 return;
516 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
517 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
518 break;
519 case PHY_INTERFACE_MODE_SGMII:
520 if ((old >> sds_shift & 0x1f) == 2)
521 return;
522 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
523 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
524 break;
525 default:
526 return;
527 }
528 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
529 }
530
531 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
532 unsigned int mode,
533 const struct phylink_link_state *state)
534 {
535 struct rtl838x_switch_priv *priv = ds->priv;
536 u32 reg;
537 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
538
539 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
540
541 if (port == priv->cpu_port) {
542 /* Set Speed, duplex, flow control
543 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
544 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
545 * | MEDIA_SEL
546 */
547 if (priv->family_id == RTL8380_FAMILY_ID) {
548 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
549 /* allow CRC errors on CPU-port */
550 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
551 } else {
552 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
553 }
554 return;
555 }
556
557 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
558 /* Auto-Negotiation does not work for MAC in RTL8390 */
559 if (priv->family_id == RTL8380_FAMILY_ID) {
560 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
561 pr_debug("PHY autonegotiates\n");
562 reg |= BIT(2);
563 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
564 rtl83xx_config_interface(port, state->interface);
565 return;
566 }
567 }
568
569 if (mode != MLO_AN_FIXED)
570 pr_debug("Fixed state.\n");
571
572 if (priv->family_id == RTL8380_FAMILY_ID) {
573 /* Clear id_mode_dis bit, and the existing port mode, let
574 * RGMII_MODE_EN bet set by mac_link_{up,down}
575 */
576 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
577
578 if (state->pause & MLO_PAUSE_TXRX_MASK) {
579 if (state->pause & MLO_PAUSE_TX)
580 reg |= TX_PAUSE_EN;
581 reg |= RX_PAUSE_EN;
582 }
583 }
584
585 reg &= ~(3 << speed_bit);
586 switch (state->speed) {
587 case SPEED_1000:
588 reg |= 2 << speed_bit;
589 break;
590 case SPEED_100:
591 reg |= 1 << speed_bit;
592 break;
593 }
594
595 if (priv->family_id == RTL8380_FAMILY_ID) {
596 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
597 if (state->link)
598 reg |= FORCE_LINK_EN;
599 if (state->duplex == DUPLEX_FULL)
600 reg |= DUPLX_MODE;
601 }
602
603 // Disable AN
604 if (priv->family_id == RTL8380_FAMILY_ID)
605 reg &= ~BIT(2);
606 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
607 }
608
609 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
610 unsigned int mode,
611 const struct phylink_link_state *state)
612 {
613 struct rtl838x_switch_priv *priv = ds->priv;
614 int sds_num, sds_mode;
615 u32 reg;
616
617 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
618 port, mode, phy_modes(state->interface), state->speed, state->link);
619
620 // Nothing to be done for the CPU-port
621 if (port == priv->cpu_port)
622 return;
623
624 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
625 reg &= ~(0xf << 3);
626
627 sds_num = priv->ports[port].sds_num;
628 pr_info("%s SDS is %d\n", __func__, sds_num);
629 if (sds_num >= 0) {
630 switch (state->interface) {
631 case PHY_INTERFACE_MODE_HSGMII:
632 sds_mode = 0x12;
633 break;
634 case PHY_INTERFACE_MODE_1000BASEX:
635 sds_mode = 0x1b; // 10G 1000X Auto
636 break;
637 case PHY_INTERFACE_MODE_XGMII:
638 sds_mode = 0x10;
639 break;
640 case PHY_INTERFACE_MODE_10GKR:
641 sds_mode = 0x1a;
642 // We need to use media sel for fibre media:
643 reg |= BIT(16);
644 break;
645 case PHY_INTERFACE_MODE_USXGMII:
646 sds_mode = 0x0d;
647 break;
648 default:
649 pr_err("%s: unknown serdes mode: %s\n",
650 __func__, phy_modes(state->interface));
651 return;
652 }
653 rtl9300_sds_rst(sds_num, sds_mode);
654 }
655
656 switch (state->speed) {
657 case SPEED_10000:
658 reg |= 4 << 3;
659 break;
660 case SPEED_5000:
661 reg |= 6 << 3;
662 break;
663 case SPEED_2500:
664 reg |= 5 << 3;
665 break;
666 case SPEED_1000:
667 reg |= 2 << 3;
668 break;
669 default:
670 reg |= 2 << 3;
671 break;
672 }
673
674 if (state->link)
675 reg |= FORCE_LINK_EN;
676
677 if (state->duplex == DUPLEX_FULL)
678 reg |= BIT(2);
679
680 reg |= 1; // Force Link up
681 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
682 }
683
684 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
685 unsigned int mode,
686 phy_interface_t interface)
687 {
688 struct rtl838x_switch_priv *priv = ds->priv;
689 /* Stop TX/RX to port */
690 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
691 }
692
693 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
694 unsigned int mode,
695 phy_interface_t interface)
696 {
697 struct rtl838x_switch_priv *priv = ds->priv;
698 /* Stop TX/RX to port */
699 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
700
701 // No longer force link
702 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
703 }
704
705 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
706 unsigned int mode,
707 phy_interface_t interface,
708 struct phy_device *phydev,
709 int speed, int duplex,
710 bool tx_pause, bool rx_pause)
711 {
712 struct rtl838x_switch_priv *priv = ds->priv;
713 /* Restart TX/RX to port */
714 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
715 // TODO: Set speed/duplex/pauses
716 }
717
718 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
719 unsigned int mode,
720 phy_interface_t interface,
721 struct phy_device *phydev,
722 int speed, int duplex,
723 bool tx_pause, bool rx_pause)
724 {
725 struct rtl838x_switch_priv *priv = ds->priv;
726
727 /* Restart TX/RX to port */
728 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
729 // TODO: Set speed/duplex/pauses
730 }
731
732 static void rtl83xx_get_strings(struct dsa_switch *ds,
733 int port, u32 stringset, u8 *data)
734 {
735 int i;
736
737 if (stringset != ETH_SS_STATS)
738 return;
739
740 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
741 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
742 ETH_GSTRING_LEN);
743 }
744
745 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
746 uint64_t *data)
747 {
748 struct rtl838x_switch_priv *priv = ds->priv;
749 const struct rtl83xx_mib_desc *mib;
750 int i;
751 u64 h;
752
753 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
754 mib = &rtl83xx_mib[i];
755
756 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
757 if (mib->size == 2) {
758 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
759 data[i] |= h << 32;
760 }
761 }
762 }
763
764 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
765 {
766 if (sset != ETH_SS_STATS)
767 return 0;
768
769 return ARRAY_SIZE(rtl83xx_mib);
770 }
771
772 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
773 struct phy_device *phydev)
774 {
775 struct rtl838x_switch_priv *priv = ds->priv;
776 u64 v;
777
778 pr_debug("%s: %x %d", __func__, (u32) priv, port);
779 priv->ports[port].enable = true;
780
781 /* enable inner tagging on egress, do not keep any tags */
782 if (priv->family_id == RTL9310_FAMILY_ID)
783 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
784 else
785 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
786
787 if (dsa_is_cpu_port(ds, port))
788 return 0;
789
790 /* add port to switch mask of CPU_PORT */
791 priv->r->traffic_enable(priv->cpu_port, port);
792
793 /* add all other ports in the same bridge to switch mask of port */
794 v = priv->r->traffic_get(port);
795 v |= priv->ports[port].pm;
796 priv->r->traffic_set(port, v);
797
798 // TODO: Figure out if this is necessary
799 if (priv->family_id == RTL9300_FAMILY_ID) {
800 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
801 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
802 }
803
804 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
805
806 return 0;
807 }
808
809 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
810 {
811 struct rtl838x_switch_priv *priv = ds->priv;
812 u64 v;
813
814 pr_debug("%s %x: %d", __func__, (u32)priv, port);
815 /* you can only disable user ports */
816 if (!dsa_is_user_port(ds, port))
817 return;
818
819 // BUG: This does not work on RTL931X
820 /* remove port from switch mask of CPU_PORT */
821 priv->r->traffic_disable(priv->cpu_port, port);
822
823 /* remove all other ports in the same bridge from switch mask of port */
824 v = priv->r->traffic_get(port);
825 v &= ~priv->ports[port].pm;
826 priv->r->traffic_set(port, v);
827
828 priv->ports[port].enable = false;
829 }
830
831 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
832 struct ethtool_eee *e)
833 {
834 struct rtl838x_switch_priv *priv = ds->priv;
835
836 if (e->eee_enabled && !priv->eee_enabled) {
837 pr_info("Globally enabling EEE\n");
838 priv->r->init_eee(priv, true);
839 }
840
841 priv->r->port_eee_set(priv, port, e->eee_enabled);
842
843 if (e->eee_enabled)
844 pr_info("Enabled EEE for port %d\n", port);
845 else
846 pr_info("Disabled EEE for port %d\n", port);
847 return 0;
848 }
849
850 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
851 struct ethtool_eee *e)
852 {
853 struct rtl838x_switch_priv *priv = ds->priv;
854
855 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
856
857 priv->r->eee_port_ability(priv, e, port);
858
859 e->eee_enabled = priv->ports[port].eee_enabled;
860
861 e->eee_active = !!(e->advertised & e->lp_advertised);
862
863 return 0;
864 }
865
866 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
867 struct ethtool_eee *e)
868 {
869 struct rtl838x_switch_priv *priv = ds->priv;
870
871 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
872 | SUPPORTED_2500baseX_Full;
873
874 priv->r->eee_port_ability(priv, e, port);
875
876 e->eee_enabled = priv->ports[port].eee_enabled;
877
878 e->eee_active = !!(e->advertised & e->lp_advertised);
879
880 return 0;
881 }
882
883 /*
884 * Set Switch L2 Aging time, t is time in milliseconds
885 * t = 0: aging is disabled
886 */
887 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
888 {
889 struct rtl838x_switch_priv *priv = ds->priv;
890 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
891
892 /* Convert time in mseconds to internal value */
893 if (t > 0x10000000) { /* Set to maximum */
894 t = t_max;
895 } else {
896 if (priv->family_id == RTL8380_FAMILY_ID)
897 t = ((t * 625) / 1000 + 127) / 128;
898 else
899 t = (t * 5 + 2) / 3;
900 }
901 sw_w32(t, priv->r->l2_ctrl_1);
902 return 0;
903 }
904
905 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
906 struct net_device *bridge)
907 {
908 struct rtl838x_switch_priv *priv = ds->priv;
909 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
910 int i;
911
912 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
913 mutex_lock(&priv->reg_mutex);
914 for (i = 0; i < ds->num_ports; i++) {
915 /* Add this port to the port matrix of the other ports in the
916 * same bridge. If the port is disabled, port matrix is kept
917 * and not being setup until the port becomes enabled.
918 */
919 if (dsa_is_user_port(ds, i) && i != port) {
920 if (dsa_to_port(ds, i)->bridge_dev != bridge)
921 continue;
922 if (priv->ports[i].enable)
923 priv->r->traffic_enable(i, port);
924
925 priv->ports[i].pm |= BIT_ULL(port);
926 port_bitmap |= BIT_ULL(i);
927 }
928 }
929
930 /* Add all other ports to this port matrix. */
931 if (priv->ports[port].enable) {
932 priv->r->traffic_enable(priv->cpu_port, port);
933 v = priv->r->traffic_get(port);
934 v |= port_bitmap;
935 priv->r->traffic_set(port, v);
936 }
937 priv->ports[port].pm |= port_bitmap;
938 mutex_unlock(&priv->reg_mutex);
939
940 return 0;
941 }
942
943 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
944 struct net_device *bridge)
945 {
946 struct rtl838x_switch_priv *priv = ds->priv;
947 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
948 int i;
949
950 pr_debug("%s %x: %d", __func__, (u32)priv, port);
951 mutex_lock(&priv->reg_mutex);
952 for (i = 0; i < ds->num_ports; i++) {
953 /* Remove this port from the port matrix of the other ports
954 * in the same bridge. If the port is disabled, port matrix
955 * is kept and not being setup until the port becomes enabled.
956 * And the other port's port matrix cannot be broken when the
957 * other port is still a VLAN-aware port.
958 */
959 if (dsa_is_user_port(ds, i) && i != port) {
960 if (dsa_to_port(ds, i)->bridge_dev != bridge)
961 continue;
962 if (priv->ports[i].enable)
963 priv->r->traffic_disable(i, port);
964
965 priv->ports[i].pm |= BIT_ULL(port);
966 port_bitmap &= ~BIT_ULL(i);
967 }
968 }
969
970 /* Add all other ports to this port matrix. */
971 if (priv->ports[port].enable) {
972 v = priv->r->traffic_get(port);
973 v |= port_bitmap;
974 priv->r->traffic_set(port, v);
975 }
976 priv->ports[port].pm &= ~port_bitmap;
977
978 mutex_unlock(&priv->reg_mutex);
979 }
980
981 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
982 {
983 u32 msti = 0;
984 u32 port_state[4];
985 int index, bit;
986 int pos = port;
987 struct rtl838x_switch_priv *priv = ds->priv;
988 int n = priv->port_width << 1;
989
990 /* Ports above or equal CPU port can never be configured */
991 if (port >= priv->cpu_port)
992 return;
993
994 mutex_lock(&priv->reg_mutex);
995
996 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
997 * have 64 bit fields, 839x and 931x have 128 bit fields
998 */
999 if (priv->family_id == RTL8390_FAMILY_ID)
1000 pos += 12;
1001 if (priv->family_id == RTL9300_FAMILY_ID)
1002 pos += 3;
1003 if (priv->family_id == RTL9310_FAMILY_ID)
1004 pos += 8;
1005
1006 index = n - (pos >> 4) - 1;
1007 bit = (pos << 1) % 32;
1008
1009 priv->r->stp_get(priv, msti, port_state);
1010
1011 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1012 port_state[index] &= ~(3 << bit);
1013
1014 switch (state) {
1015 case BR_STATE_DISABLED: /* 0 */
1016 port_state[index] |= (0 << bit);
1017 break;
1018 case BR_STATE_BLOCKING: /* 4 */
1019 case BR_STATE_LISTENING: /* 1 */
1020 port_state[index] |= (1 << bit);
1021 break;
1022 case BR_STATE_LEARNING: /* 2 */
1023 port_state[index] |= (2 << bit);
1024 break;
1025 case BR_STATE_FORWARDING: /* 3*/
1026 port_state[index] |= (3 << bit);
1027 default:
1028 break;
1029 }
1030
1031 priv->r->stp_set(priv, msti, port_state);
1032
1033 mutex_unlock(&priv->reg_mutex);
1034 }
1035
1036 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1037 {
1038 struct rtl838x_switch_priv *priv = ds->priv;
1039 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1040
1041 pr_debug("FAST AGE port %d\n", port);
1042 mutex_lock(&priv->reg_mutex);
1043 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1044 * port fields:
1045 * 0-4: Replacing port
1046 * 5-9: Flushed/replaced port
1047 * 10-21: FVID
1048 * 22: Entry types: 1: dynamic, 0: also static
1049 * 23: Match flush port
1050 * 24: Match FVID
1051 * 25: Flush (0) or replace (1) L2 entries
1052 * 26: Status of action (1: Start, 0: Done)
1053 */
1054 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1055
1056 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1057
1058 mutex_unlock(&priv->reg_mutex);
1059 }
1060
1061 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1062 {
1063 struct rtl838x_switch_priv *priv = ds->priv;
1064
1065 pr_debug("FAST AGE port %d\n", port);
1066 mutex_lock(&priv->reg_mutex);
1067 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1068
1069 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1070
1071 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1072
1073 mutex_unlock(&priv->reg_mutex);
1074 }
1075
1076 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1077 bool vlan_filtering,
1078 struct switchdev_trans *trans)
1079 {
1080 struct rtl838x_switch_priv *priv = ds->priv;
1081
1082 pr_debug("%s: port %d\n", __func__, port);
1083 mutex_lock(&priv->reg_mutex);
1084
1085 if (vlan_filtering) {
1086 /* Enable ingress and egress filtering
1087 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1088 * the filter action:
1089 * 0: Always Forward
1090 * 1: Drop packet
1091 * 2: Trap packet to CPU port
1092 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1093 */
1094 if (port != priv->cpu_port)
1095 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
1096 priv->r->vlan_port_igr_filter + ((port >> 4) << 2));
1097 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 5) << 2));
1098 } else {
1099 /* Disable ingress and egress filtering */
1100 if (port != priv->cpu_port)
1101 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
1102 priv->r->vlan_port_igr_filter + ((port >> 4) << 2));
1103 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 5) << 2));
1104 }
1105
1106 /* Do we need to do something to the CPU-Port, too? */
1107 mutex_unlock(&priv->reg_mutex);
1108
1109 return 0;
1110 }
1111
1112 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1113 const struct switchdev_obj_port_vlan *vlan)
1114 {
1115 struct rtl838x_vlan_info info;
1116 struct rtl838x_switch_priv *priv = ds->priv;
1117
1118 priv->r->vlan_tables_read(0, &info);
1119
1120 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1121 info.tagged_ports, info.untagged_ports, info.profile_id,
1122 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1123
1124 priv->r->vlan_tables_read(1, &info);
1125 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1126 info.tagged_ports, info.untagged_ports, info.profile_id,
1127 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1128 priv->r->vlan_set_untagged(1, info.untagged_ports);
1129 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1130
1131 priv->r->vlan_set_tagged(1, &info);
1132 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1133
1134 mutex_unlock(&priv->reg_mutex);
1135 return 0;
1136 }
1137
1138 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1139 const struct switchdev_obj_port_vlan *vlan)
1140 {
1141 struct rtl838x_vlan_info info;
1142 struct rtl838x_switch_priv *priv = ds->priv;
1143 int v;
1144
1145 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1146 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1147
1148 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1149 dev_err(priv->dev, "VLAN out of range: %d - %d",
1150 vlan->vid_begin, vlan->vid_end);
1151 return;
1152 }
1153
1154 mutex_lock(&priv->reg_mutex);
1155
1156 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1157 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1158 if (!v)
1159 continue;
1160 /* Set both inner and outer PVID of the port */
1161 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
1162 priv->ports[port].pvid = vlan->vid_end;
1163 }
1164 }
1165
1166 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1167 /* Get port memberships of this vlan */
1168 priv->r->vlan_tables_read(v, &info);
1169
1170 /* new VLAN? */
1171 if (!info.tagged_ports) {
1172 info.fid = 0;
1173 info.hash_mc_fid = false;
1174 info.hash_uc_fid = false;
1175 info.profile_id = 0;
1176 }
1177
1178 /* sanitize untagged_ports - must be a subset */
1179 if (info.untagged_ports & ~info.tagged_ports)
1180 info.untagged_ports = 0;
1181
1182 info.tagged_ports |= BIT_ULL(port);
1183 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1184 info.untagged_ports |= BIT_ULL(port);
1185
1186 priv->r->vlan_set_untagged(v, info.untagged_ports);
1187 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1188
1189 priv->r->vlan_set_tagged(v, &info);
1190 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1191 }
1192
1193 mutex_unlock(&priv->reg_mutex);
1194 }
1195
1196 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1197 const struct switchdev_obj_port_vlan *vlan)
1198 {
1199 struct rtl838x_vlan_info info;
1200 struct rtl838x_switch_priv *priv = ds->priv;
1201 int v;
1202 u16 pvid;
1203
1204 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1205 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1206
1207 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1208 dev_err(priv->dev, "VLAN out of range: %d - %d",
1209 vlan->vid_begin, vlan->vid_end);
1210 return -ENOTSUPP;
1211 }
1212
1213 mutex_lock(&priv->reg_mutex);
1214 pvid = priv->ports[port].pvid;
1215
1216 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1217 /* Reset to default if removing the current PVID */
1218 if (v == pvid)
1219 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
1220
1221 /* Get port memberships of this vlan */
1222 priv->r->vlan_tables_read(v, &info);
1223
1224 /* remove port from both tables */
1225 info.untagged_ports &= (~BIT_ULL(port));
1226 info.tagged_ports &= (~BIT_ULL(port));
1227
1228 priv->r->vlan_set_untagged(v, info.untagged_ports);
1229 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1230
1231 priv->r->vlan_set_tagged(v, &info);
1232 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1233 }
1234 mutex_unlock(&priv->reg_mutex);
1235
1236 return 0;
1237 }
1238
1239 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1240 {
1241 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1242 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1243 e->vid, e->rvid, e->port, e->valid);
1244
1245 if (e->type != L2_MULTICAST) {
1246 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1247 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1248 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1249 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1250 }
1251 if (e->type == L2_MULTICAST)
1252 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1253 if (e->is_ip_mc || e->is_ipv6_mc)
1254 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1255 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1256 pr_info(" stack_dev: %d\n", e->stack_dev);
1257 if (e->next_hop)
1258 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1259 }
1260
1261 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1262 {
1263 e->is_ip_mc = e->is_ipv6_mc = false;
1264 e->valid = true;
1265 e->age = 3;
1266 e->port = port,
1267 e->vid = vid;
1268 u64_to_ether_addr(mac, e->mac);
1269 }
1270
1271 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1272 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1273 {
1274 e->is_ip_mc = e->is_ipv6_mc = false;
1275 e->valid = true;
1276 e->mc_portmask_index = mc_group;
1277 e->type = L2_MULTICAST;
1278 e->rvid = e->vid = vid;
1279 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1280 u64_to_ether_addr(mac, e->mac);
1281 }
1282
1283 /*
1284 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1285 * over the entries in the bucket until either a matching entry is found or an empty slot
1286 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1287 * when an empty slot was found and must exist is false, the index of the slot is returned
1288 * when no slots are available returns -1
1289 */
1290 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1291 bool must_exist, struct rtl838x_l2_entry *e)
1292 {
1293 int i, idx = -1;
1294 u32 key = priv->r->l2_hash_key(priv, seed);
1295 u64 entry;
1296
1297 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1298 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1299 for (i = 0; i < priv->l2_bucket_size; i++) {
1300 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1301 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1302 if (must_exist && !e->valid)
1303 continue;
1304 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1305 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1306 break;
1307 }
1308 }
1309
1310 return idx;
1311 }
1312
1313 /*
1314 * Uses the seed to identify an entry in the CAM by looping over all its entries
1315 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1316 * when an empty slot was found the index of the slot is returned
1317 * when no slots are available returns -1
1318 */
1319 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1320 bool must_exist, struct rtl838x_l2_entry *e)
1321 {
1322 int i, idx = -1;
1323 u64 entry;
1324
1325 for (i = 0; i < 64; i++) {
1326 entry = priv->r->read_cam(i, e);
1327 if (!must_exist && !e->valid) {
1328 if (idx < 0) /* First empty entry? */
1329 idx = i;
1330 break;
1331 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1332 pr_debug("Found entry in CAM\n");
1333 idx = i;
1334 break;
1335 }
1336 }
1337 return idx;
1338 }
1339
1340 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1341 const unsigned char *addr, u16 vid)
1342 {
1343 struct rtl838x_switch_priv *priv = ds->priv;
1344 u64 mac = ether_addr_to_u64(addr);
1345 struct rtl838x_l2_entry e;
1346 int err = 0, idx;
1347 u64 seed = priv->r->l2_hash_seed(mac, vid);
1348
1349 mutex_lock(&priv->reg_mutex);
1350
1351 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1352
1353 // Found an existing or empty entry
1354 if (idx >= 0) {
1355 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1356 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1357 goto out;
1358 }
1359
1360 // Hash buckets full, try CAM
1361 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1362
1363 if (idx >= 0) {
1364 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1365 priv->r->write_cam(idx, &e);
1366 goto out;
1367 }
1368
1369 err = -ENOTSUPP;
1370 out:
1371 mutex_unlock(&priv->reg_mutex);
1372 return err;
1373 }
1374
1375 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1376 const unsigned char *addr, u16 vid)
1377 {
1378 struct rtl838x_switch_priv *priv = ds->priv;
1379 u64 mac = ether_addr_to_u64(addr);
1380 struct rtl838x_l2_entry e;
1381 int err = 0, idx;
1382 u64 seed = priv->r->l2_hash_seed(mac, vid);
1383
1384 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1385 mutex_lock(&priv->reg_mutex);
1386
1387 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1388
1389 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1390 if (idx >= 0) {
1391 e.valid = false;
1392 dump_l2_entry(&e);
1393 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1394 goto out;
1395 }
1396
1397 /* Check CAM for spillover from hash buckets */
1398 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1399
1400 if (idx >= 0) {
1401 e.valid = false;
1402 priv->r->write_cam(idx, &e);
1403 goto out;
1404 }
1405 err = -ENOENT;
1406 out:
1407 mutex_unlock(&priv->reg_mutex);
1408 return err;
1409 }
1410
1411 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1412 dsa_fdb_dump_cb_t *cb, void *data)
1413 {
1414 struct rtl838x_l2_entry e;
1415 struct rtl838x_switch_priv *priv = ds->priv;
1416 int i;
1417 u32 fid, pkey;
1418 u64 mac;
1419
1420 mutex_lock(&priv->reg_mutex);
1421
1422 for (i = 0; i < priv->fib_entries; i++) {
1423 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1424
1425 if (!e.valid)
1426 continue;
1427
1428 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1429 u64 seed;
1430 u32 key;
1431
1432 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1433 mac = ether_addr_to_u64(&e.mac[0]);
1434 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1435 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1436 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1437 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1438 dump_l2_entry(&e);
1439 seed = priv->r->l2_hash_seed(mac, e.rvid);
1440 key = priv->r->l2_hash_key(priv, seed);
1441 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1442 cb(e.mac, e.vid, e.is_static, data);
1443 }
1444 if (e.type == L2_MULTICAST) {
1445 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1446
1447 if (portmask & BIT_ULL(port)) {
1448 dump_l2_entry(&e);
1449 pr_info(" PM: %016llx\n", portmask);
1450 }
1451 }
1452 }
1453
1454 for (i = 0; i < 64; i++) {
1455 priv->r->read_cam(i, &e);
1456
1457 if (!e.valid)
1458 continue;
1459
1460 if (e.port == port)
1461 cb(e.mac, e.vid, e.is_static, data);
1462 }
1463
1464 mutex_unlock(&priv->reg_mutex);
1465 return 0;
1466 }
1467
1468 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1469 const struct switchdev_obj_port_mdb *mdb)
1470 {
1471 struct rtl838x_switch_priv *priv = ds->priv;
1472
1473 if (priv->id >= 0x9300)
1474 return -EOPNOTSUPP;
1475
1476 return 0;
1477 }
1478
1479 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1480 {
1481 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1482 u64 portmask;
1483
1484 if (mc_group >= MAX_MC_GROUPS - 1)
1485 return -1;
1486
1487 pr_debug("Using MC group %d\n", mc_group);
1488 set_bit(mc_group, priv->mc_group_bm);
1489 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1490 portmask = BIT_ULL(port);
1491 priv->r->write_mcast_pmask(mc_group, portmask);
1492
1493 return mc_group;
1494 }
1495
1496 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1497 {
1498 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1499
1500 portmask |= BIT_ULL(port);
1501 priv->r->write_mcast_pmask(mc_group, portmask);
1502
1503 return portmask;
1504 }
1505
1506 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1507 {
1508 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1509
1510 portmask &= ~BIT_ULL(port);
1511 priv->r->write_mcast_pmask(mc_group, portmask);
1512 if (!portmask)
1513 clear_bit(mc_group, priv->mc_group_bm);
1514
1515 return portmask;
1516 }
1517
1518 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1519 const struct switchdev_obj_port_mdb *mdb)
1520 {
1521 struct rtl838x_switch_priv *priv = ds->priv;
1522 u64 mac = ether_addr_to_u64(mdb->addr);
1523 struct rtl838x_l2_entry e;
1524 int err = 0, idx;
1525 int vid = mdb->vid;
1526 u64 seed = priv->r->l2_hash_seed(mac, vid);
1527 int mc_group;
1528
1529 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1530 mutex_lock(&priv->reg_mutex);
1531
1532 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1533
1534 // Found an existing or empty entry
1535 if (idx >= 0) {
1536 if (e.valid) {
1537 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1538 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1539 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1540 } else {
1541 pr_debug("New entry for seed %016llx\n", seed);
1542 mc_group = rtl83xx_mc_group_alloc(priv, port);
1543 if (mc_group < 0) {
1544 err = -ENOTSUPP;
1545 goto out;
1546 }
1547 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1548 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1549 }
1550 goto out;
1551 }
1552
1553 // Hash buckets full, try CAM
1554 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1555
1556 if (idx >= 0) {
1557 if (e.valid) {
1558 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1559 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1560 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1561 } else {
1562 pr_debug("New entry\n");
1563 mc_group = rtl83xx_mc_group_alloc(priv, port);
1564 if (mc_group < 0) {
1565 err = -ENOTSUPP;
1566 goto out;
1567 }
1568 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1569 priv->r->write_cam(idx, &e);
1570 }
1571 goto out;
1572 }
1573
1574 err = -ENOTSUPP;
1575 out:
1576 mutex_unlock(&priv->reg_mutex);
1577 if (err)
1578 dev_err(ds->dev, "failed to add MDB entry\n");
1579 }
1580
1581 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1582 const struct switchdev_obj_port_mdb *mdb)
1583 {
1584 struct rtl838x_switch_priv *priv = ds->priv;
1585 u64 mac = ether_addr_to_u64(mdb->addr);
1586 struct rtl838x_l2_entry e;
1587 int err = 0, idx;
1588 int vid = mdb->vid;
1589 u64 seed = priv->r->l2_hash_seed(mac, vid);
1590 u64 portmask;
1591
1592 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1593 mutex_lock(&priv->reg_mutex);
1594
1595 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1596
1597 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1598 if (idx >= 0) {
1599 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1600 if (!portmask) {
1601 e.valid = false;
1602 // dump_l2_entry(&e);
1603 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1604 }
1605 goto out;
1606 }
1607
1608 /* Check CAM for spillover from hash buckets */
1609 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1610
1611 if (idx >= 0) {
1612 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1613 if (!portmask) {
1614 e.valid = false;
1615 // dump_l2_entry(&e);
1616 priv->r->write_cam(idx, &e);
1617 }
1618 goto out;
1619 }
1620 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1621 out:
1622 mutex_unlock(&priv->reg_mutex);
1623 return err;
1624 }
1625
1626 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1627 struct dsa_mall_mirror_tc_entry *mirror,
1628 bool ingress)
1629 {
1630 /* We support 4 mirror groups, one destination port per group */
1631 int group;
1632 struct rtl838x_switch_priv *priv = ds->priv;
1633 int ctrl_reg, dpm_reg, spm_reg;
1634
1635 pr_debug("In %s\n", __func__);
1636
1637 for (group = 0; group < 4; group++) {
1638 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1639 break;
1640 }
1641 if (group >= 4) {
1642 for (group = 0; group < 4; group++) {
1643 if (priv->mirror_group_ports[group] < 0)
1644 break;
1645 }
1646 }
1647
1648 if (group >= 4)
1649 return -ENOSPC;
1650
1651 ctrl_reg = priv->r->mir_ctrl + group * 4;
1652 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1653 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1654
1655 pr_debug("Using group %d\n", group);
1656 mutex_lock(&priv->reg_mutex);
1657
1658 if (priv->family_id == RTL8380_FAMILY_ID) {
1659 /* Enable mirroring to port across VLANs (bit 11) */
1660 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1661 } else {
1662 /* Enable mirroring to destination port */
1663 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1664 }
1665
1666 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1667 mutex_unlock(&priv->reg_mutex);
1668 return -EEXIST;
1669 }
1670 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1671 mutex_unlock(&priv->reg_mutex);
1672 return -EEXIST;
1673 }
1674
1675 if (ingress)
1676 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1677 else
1678 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1679
1680 priv->mirror_group_ports[group] = mirror->to_local_port;
1681 mutex_unlock(&priv->reg_mutex);
1682 return 0;
1683 }
1684
1685 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1686 struct dsa_mall_mirror_tc_entry *mirror)
1687 {
1688 int group = 0;
1689 struct rtl838x_switch_priv *priv = ds->priv;
1690 int ctrl_reg, dpm_reg, spm_reg;
1691
1692 pr_debug("In %s\n", __func__);
1693 for (group = 0; group < 4; group++) {
1694 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1695 break;
1696 }
1697 if (group >= 4)
1698 return;
1699
1700 ctrl_reg = priv->r->mir_ctrl + group * 4;
1701 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1702 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1703
1704 mutex_lock(&priv->reg_mutex);
1705 if (mirror->ingress) {
1706 /* Ingress, clear source port matrix */
1707 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1708 } else {
1709 /* Egress, clear destination port matrix */
1710 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1711 }
1712
1713 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1714 priv->mirror_group_ports[group] = -1;
1715 sw_w32(0, ctrl_reg);
1716 }
1717
1718 mutex_unlock(&priv->reg_mutex);
1719 }
1720
1721 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1722 {
1723 u32 val;
1724 u32 offset = 0;
1725 struct rtl838x_switch_priv *priv = ds->priv;
1726
1727 if (phy_addr >= 24 && phy_addr <= 27
1728 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1729 if (phy_addr == 26)
1730 offset = 0x100;
1731 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1732 return val;
1733 }
1734
1735 read_phy(phy_addr, 0, phy_reg, &val);
1736 return val;
1737 }
1738
1739 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1740 {
1741 u32 offset = 0;
1742 struct rtl838x_switch_priv *priv = ds->priv;
1743
1744 if (phy_addr >= 24 && phy_addr <= 27
1745 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1746 if (phy_addr == 26)
1747 offset = 0x100;
1748 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1749 return 0;
1750 }
1751 return write_phy(phy_addr, 0, phy_reg, val);
1752 }
1753
1754 const struct dsa_switch_ops rtl83xx_switch_ops = {
1755 .get_tag_protocol = rtl83xx_get_tag_protocol,
1756 .setup = rtl83xx_setup,
1757
1758 .phy_read = dsa_phy_read,
1759 .phy_write = dsa_phy_write,
1760
1761 .phylink_validate = rtl83xx_phylink_validate,
1762 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1763 .phylink_mac_config = rtl83xx_phylink_mac_config,
1764 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1765 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1766
1767 .get_strings = rtl83xx_get_strings,
1768 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1769 .get_sset_count = rtl83xx_get_sset_count,
1770
1771 .port_enable = rtl83xx_port_enable,
1772 .port_disable = rtl83xx_port_disable,
1773
1774 .get_mac_eee = rtl83xx_get_mac_eee,
1775 .set_mac_eee = rtl83xx_set_mac_eee,
1776
1777 .set_ageing_time = rtl83xx_set_l2aging,
1778 .port_bridge_join = rtl83xx_port_bridge_join,
1779 .port_bridge_leave = rtl83xx_port_bridge_leave,
1780 .port_stp_state_set = rtl83xx_port_stp_state_set,
1781 .port_fast_age = rtl83xx_fast_age,
1782
1783 .port_vlan_filtering = rtl83xx_vlan_filtering,
1784 .port_vlan_prepare = rtl83xx_vlan_prepare,
1785 .port_vlan_add = rtl83xx_vlan_add,
1786 .port_vlan_del = rtl83xx_vlan_del,
1787
1788 .port_fdb_add = rtl83xx_port_fdb_add,
1789 .port_fdb_del = rtl83xx_port_fdb_del,
1790 .port_fdb_dump = rtl83xx_port_fdb_dump,
1791
1792 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1793 .port_mdb_add = rtl83xx_port_mdb_add,
1794 .port_mdb_del = rtl83xx_port_mdb_del,
1795
1796 .port_mirror_add = rtl83xx_port_mirror_add,
1797 .port_mirror_del = rtl83xx_port_mirror_del,
1798 };
1799
1800 const struct dsa_switch_ops rtl930x_switch_ops = {
1801 .get_tag_protocol = rtl83xx_get_tag_protocol,
1802 .setup = rtl930x_setup,
1803
1804 .phy_read = dsa_phy_read,
1805 .phy_write = dsa_phy_write,
1806
1807 .phylink_validate = rtl93xx_phylink_validate,
1808 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
1809 .phylink_mac_config = rtl93xx_phylink_mac_config,
1810 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
1811 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
1812
1813 .get_strings = rtl83xx_get_strings,
1814 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1815 .get_sset_count = rtl83xx_get_sset_count,
1816
1817 .port_enable = rtl83xx_port_enable,
1818 .port_disable = rtl83xx_port_disable,
1819
1820 .get_mac_eee = rtl93xx_get_mac_eee,
1821 .set_mac_eee = rtl83xx_set_mac_eee,
1822
1823 .set_ageing_time = rtl83xx_set_l2aging,
1824 .port_bridge_join = rtl83xx_port_bridge_join,
1825 .port_bridge_leave = rtl83xx_port_bridge_leave,
1826 .port_stp_state_set = rtl83xx_port_stp_state_set,
1827 .port_fast_age = rtl930x_fast_age,
1828
1829 .port_vlan_filtering = rtl83xx_vlan_filtering,
1830 .port_vlan_prepare = rtl83xx_vlan_prepare,
1831 .port_vlan_add = rtl83xx_vlan_add,
1832 .port_vlan_del = rtl83xx_vlan_del,
1833
1834 .port_fdb_add = rtl83xx_port_fdb_add,
1835 .port_fdb_del = rtl83xx_port_fdb_del,
1836 .port_fdb_dump = rtl83xx_port_fdb_dump,
1837
1838 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1839 .port_mdb_add = rtl83xx_port_mdb_add,
1840 .port_mdb_del = rtl83xx_port_mdb_del,
1841
1842 };
Staging tree of Christian Lamparter