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realtek: Store and Restore MC memberships for port enable/disable
[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static int rtl83xx_setup(struct dsa_switch *ds)
166 {
167 int i;
168 struct rtl838x_switch_priv *priv = ds->priv;
169 u64 port_bitmap = BIT_ULL(priv->cpu_port);
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Isolate ports from each other: traffic only CPU <-> port */
181 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
182 * traffic from source port i to destination port j
183 */
184 for (i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
187 priv->r->port_iso_ctrl(i));
188 port_bitmap |= BIT_ULL(i);
189 }
190 }
191 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
192
193 if (priv->family_id == RTL8380_FAMILY_ID)
194 rtl838x_print_matrix();
195 else
196 rtl839x_print_matrix();
197
198 rtl83xx_init_stats(priv);
199
200 rtl83xx_vlan_setup(priv);
201
202 rtl83xx_setup_bpdu_traps(priv);
203
204 ds->configure_vlan_while_not_filtering = true;
205
206 priv->r->l2_learning_setup();
207
208 /* Enable MAC Polling PHY again */
209 rtl83xx_enable_phy_polling(priv);
210 pr_debug("Please wait until PHY is settled\n");
211 msleep(1000);
212 priv->r->pie_init(priv);
213
214 return 0;
215 }
216
217 static int rtl93xx_setup(struct dsa_switch *ds)
218 {
219 int i;
220 struct rtl838x_switch_priv *priv = ds->priv;
221 u32 port_bitmap = BIT(priv->cpu_port);
222
223 pr_info("%s called\n", __func__);
224
225 /* Disable MAC polling the PHY so that we can start configuration */
226 if (priv->family_id == RTL9300_FAMILY_ID)
227 sw_w32(0, RTL930X_SMI_POLL_CTRL);
228
229 if (priv->family_id == RTL9310_FAMILY_ID) {
230 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
231 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
232 }
233
234 // Disable all ports except CPU port
235 for (i = 0; i < ds->num_ports; i++)
236 priv->ports[i].enable = false;
237 priv->ports[priv->cpu_port].enable = true;
238
239 for (i = 0; i < priv->cpu_port; i++) {
240 if (priv->ports[i].phy) {
241 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
242 port_bitmap |= BIT_ULL(i);
243 }
244 }
245 priv->r->traffic_set(priv->cpu_port, port_bitmap);
246
247 rtl930x_print_matrix();
248
249 // TODO: Initialize statistics
250
251 rtl83xx_vlan_setup(priv);
252
253 ds->configure_vlan_while_not_filtering = true;
254
255 priv->r->l2_learning_setup();
256
257 rtl83xx_enable_phy_polling(priv);
258
259 priv->r->pie_init(priv);
260
261 return 0;
262 }
263
264 static int rtl93xx_get_sds(struct phy_device *phydev)
265 {
266 struct device *dev = &phydev->mdio.dev;
267 struct device_node *dn;
268 u32 sds_num;
269
270 if (!dev)
271 return -1;
272 if (dev->of_node) {
273 dn = dev->of_node;
274 if (of_property_read_u32(dn, "sds", &sds_num))
275 sds_num = -1;
276 } else {
277 dev_err(dev, "No DT node.\n");
278 return -1;
279 }
280
281 return sds_num;
282 }
283
284 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
285 unsigned long *supported,
286 struct phylink_link_state *state)
287 {
288 struct rtl838x_switch_priv *priv = ds->priv;
289 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
290
291 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
292
293 if (!phy_interface_mode_is_rgmii(state->interface) &&
294 state->interface != PHY_INTERFACE_MODE_NA &&
295 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
296 state->interface != PHY_INTERFACE_MODE_MII &&
297 state->interface != PHY_INTERFACE_MODE_REVMII &&
298 state->interface != PHY_INTERFACE_MODE_GMII &&
299 state->interface != PHY_INTERFACE_MODE_QSGMII &&
300 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
301 state->interface != PHY_INTERFACE_MODE_SGMII) {
302 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
303 dev_err(ds->dev,
304 "Unsupported interface: %d for port %d\n",
305 state->interface, port);
306 return;
307 }
308
309 /* Allow all the expected bits */
310 phylink_set(mask, Autoneg);
311 phylink_set_port_modes(mask);
312 phylink_set(mask, Pause);
313 phylink_set(mask, Asym_Pause);
314
315 /* With the exclusion of MII and Reverse MII, we support Gigabit,
316 * including Half duplex
317 */
318 if (state->interface != PHY_INTERFACE_MODE_MII &&
319 state->interface != PHY_INTERFACE_MODE_REVMII) {
320 phylink_set(mask, 1000baseT_Full);
321 phylink_set(mask, 1000baseT_Half);
322 }
323
324 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
325 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
326 phylink_set(mask, 1000baseX_Full);
327
328 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
329 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
330 phylink_set(mask, 1000baseX_Full);
331
332 phylink_set(mask, 10baseT_Half);
333 phylink_set(mask, 10baseT_Full);
334 phylink_set(mask, 100baseT_Half);
335 phylink_set(mask, 100baseT_Full);
336
337 bitmap_and(supported, supported, mask,
338 __ETHTOOL_LINK_MODE_MASK_NBITS);
339 bitmap_and(state->advertising, state->advertising, mask,
340 __ETHTOOL_LINK_MODE_MASK_NBITS);
341 }
342
343 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
344 unsigned long *supported,
345 struct phylink_link_state *state)
346 {
347 struct rtl838x_switch_priv *priv = ds->priv;
348 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
349
350 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
351 phy_modes(state->interface));
352
353 if (!phy_interface_mode_is_rgmii(state->interface) &&
354 state->interface != PHY_INTERFACE_MODE_NA &&
355 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
356 state->interface != PHY_INTERFACE_MODE_MII &&
357 state->interface != PHY_INTERFACE_MODE_REVMII &&
358 state->interface != PHY_INTERFACE_MODE_GMII &&
359 state->interface != PHY_INTERFACE_MODE_QSGMII &&
360 state->interface != PHY_INTERFACE_MODE_XGMII &&
361 state->interface != PHY_INTERFACE_MODE_HSGMII &&
362 state->interface != PHY_INTERFACE_MODE_10GBASER &&
363 state->interface != PHY_INTERFACE_MODE_10GKR &&
364 state->interface != PHY_INTERFACE_MODE_USXGMII &&
365 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
366 state->interface != PHY_INTERFACE_MODE_SGMII) {
367 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
368 dev_err(ds->dev,
369 "Unsupported interface: %d for port %d\n",
370 state->interface, port);
371 return;
372 }
373
374 /* Allow all the expected bits */
375 phylink_set(mask, Autoneg);
376 phylink_set_port_modes(mask);
377 phylink_set(mask, Pause);
378 phylink_set(mask, Asym_Pause);
379
380 /* With the exclusion of MII and Reverse MII, we support Gigabit,
381 * including Half duplex
382 */
383 if (state->interface != PHY_INTERFACE_MODE_MII &&
384 state->interface != PHY_INTERFACE_MODE_REVMII) {
385 phylink_set(mask, 1000baseT_Full);
386 phylink_set(mask, 1000baseT_Half);
387 }
388
389 // Internal phys of the RTL93xx family provide 10G
390 if (priv->ports[port].phy_is_integrated
391 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
392 phylink_set(mask, 1000baseX_Full);
393 } else if (priv->ports[port].phy_is_integrated) {
394 phylink_set(mask, 1000baseX_Full);
395 phylink_set(mask, 10000baseKR_Full);
396 phylink_set(mask, 10000baseSR_Full);
397 phylink_set(mask, 10000baseCR_Full);
398 }
399 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
400 phylink_set(mask, 1000baseX_Full);
401 phylink_set(mask, 1000baseT_Full);
402 phylink_set(mask, 10000baseKR_Full);
403 phylink_set(mask, 10000baseT_Full);
404 phylink_set(mask, 10000baseSR_Full);
405 phylink_set(mask, 10000baseCR_Full);
406 }
407
408 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
409 phylink_set(mask, 10000baseT_Full);
410
411 phylink_set(mask, 10baseT_Half);
412 phylink_set(mask, 10baseT_Full);
413 phylink_set(mask, 100baseT_Half);
414 phylink_set(mask, 100baseT_Full);
415
416 bitmap_and(supported, supported, mask,
417 __ETHTOOL_LINK_MODE_MASK_NBITS);
418 bitmap_and(state->advertising, state->advertising, mask,
419 __ETHTOOL_LINK_MODE_MASK_NBITS);
420 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
421 }
422
423 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
424 struct phylink_link_state *state)
425 {
426 struct rtl838x_switch_priv *priv = ds->priv;
427 u64 speed;
428 u64 link;
429
430 if (port < 0 || port > priv->cpu_port)
431 return -EINVAL;
432
433 state->link = 0;
434 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
435 if (link & BIT_ULL(port))
436 state->link = 1;
437 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
438
439 state->duplex = 0;
440 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
441 state->duplex = 1;
442
443 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
444 speed >>= (port % 16) << 1;
445 switch (speed & 0x3) {
446 case 0:
447 state->speed = SPEED_10;
448 break;
449 case 1:
450 state->speed = SPEED_100;
451 break;
452 case 2:
453 state->speed = SPEED_1000;
454 break;
455 case 3:
456 if (priv->family_id == RTL9300_FAMILY_ID
457 && (port == 24 || port == 26)) /* Internal serdes */
458 state->speed = SPEED_2500;
459 else
460 state->speed = SPEED_100; /* Is in fact 500Mbit */
461 }
462
463 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
464 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
465 state->pause |= MLO_PAUSE_RX;
466 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
467 state->pause |= MLO_PAUSE_TX;
468 return 1;
469 }
470
471 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
472 struct phylink_link_state *state)
473 {
474 struct rtl838x_switch_priv *priv = ds->priv;
475 u64 speed;
476 u64 link;
477
478 if (port < 0 || port > priv->cpu_port)
479 return -EINVAL;
480
481 /*
482 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
483 * state needs to be read twice in order to read a correct result.
484 * This would not be necessary for ports connected e.g. to RTL8218D
485 * PHYs.
486 */
487 state->link = 0;
488 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
489 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
490 if (link & BIT_ULL(port))
491 state->link = 1;
492 pr_debug("%s: link state port %d: %llx, media %08x\n", __func__, port,
493 link & BIT_ULL(port), sw_r32(RTL930X_MAC_LINK_MEDIA_STS));
494
495 state->duplex = 0;
496 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
497 state->duplex = 1;
498
499 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
500 speed >>= (port % 8) << 2;
501 switch (speed & 0xf) {
502 case 0:
503 state->speed = SPEED_10;
504 break;
505 case 1:
506 state->speed = SPEED_100;
507 break;
508 case 2:
509 case 7:
510 state->speed = SPEED_1000;
511 break;
512 case 4:
513 state->speed = SPEED_10000;
514 break;
515 case 5:
516 case 8:
517 state->speed = SPEED_2500;
518 break;
519 case 6:
520 state->speed = SPEED_5000;
521 break;
522 default:
523 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
524 }
525
526 if (priv->family_id == RTL9310_FAMILY_ID
527 && (port >= 52 || port <= 55)) { /* Internal serdes */
528 state->speed = SPEED_10000;
529 state->link = 1;
530 state->duplex = 1;
531 }
532
533 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
534 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
535 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
536 state->pause |= MLO_PAUSE_RX;
537 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
538 state->pause |= MLO_PAUSE_TX;
539 return 1;
540 }
541
542 static void rtl83xx_config_interface(int port, phy_interface_t interface)
543 {
544 u32 old, int_shift, sds_shift;
545
546 switch (port) {
547 case 24:
548 int_shift = 0;
549 sds_shift = 5;
550 break;
551 case 26:
552 int_shift = 3;
553 sds_shift = 0;
554 break;
555 default:
556 return;
557 }
558
559 old = sw_r32(RTL838X_SDS_MODE_SEL);
560 switch (interface) {
561 case PHY_INTERFACE_MODE_1000BASEX:
562 if ((old >> sds_shift & 0x1f) == 4)
563 return;
564 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
565 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
566 break;
567 case PHY_INTERFACE_MODE_SGMII:
568 if ((old >> sds_shift & 0x1f) == 2)
569 return;
570 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
571 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
572 break;
573 default:
574 return;
575 }
576 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
577 }
578
579 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
580 unsigned int mode,
581 const struct phylink_link_state *state)
582 {
583 struct rtl838x_switch_priv *priv = ds->priv;
584 u32 reg;
585 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
586
587 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
588
589 if (port == priv->cpu_port) {
590 /* Set Speed, duplex, flow control
591 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
592 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
593 * | MEDIA_SEL
594 */
595 if (priv->family_id == RTL8380_FAMILY_ID) {
596 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
597 /* allow CRC errors on CPU-port */
598 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
599 } else {
600 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
601 }
602 return;
603 }
604
605 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
606 /* Auto-Negotiation does not work for MAC in RTL8390 */
607 if (priv->family_id == RTL8380_FAMILY_ID) {
608 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
609 pr_debug("PHY autonegotiates\n");
610 reg |= RTL838X_NWAY_EN;
611 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
612 rtl83xx_config_interface(port, state->interface);
613 return;
614 }
615 }
616
617 if (mode != MLO_AN_FIXED)
618 pr_debug("Fixed state.\n");
619
620 /* Clear id_mode_dis bit, and the existing port mode, let
621 * RGMII_MODE_EN bet set by mac_link_{up,down} */
622 if (priv->family_id == RTL8380_FAMILY_ID) {
623 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
624 if (state->pause & MLO_PAUSE_TXRX_MASK) {
625 if (state->pause & MLO_PAUSE_TX)
626 reg |= RTL838X_TX_PAUSE_EN;
627 reg |= RTL838X_RX_PAUSE_EN;
628 }
629 } else if (priv->family_id == RTL8390_FAMILY_ID) {
630 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
631 if (state->pause & MLO_PAUSE_TXRX_MASK) {
632 if (state->pause & MLO_PAUSE_TX)
633 reg |= RTL839X_TX_PAUSE_EN;
634 reg |= RTL839X_RX_PAUSE_EN;
635 }
636 }
637
638
639 reg &= ~(3 << speed_bit);
640 switch (state->speed) {
641 case SPEED_1000:
642 reg |= 2 << speed_bit;
643 break;
644 case SPEED_100:
645 reg |= 1 << speed_bit;
646 break;
647 default:
648 break; // Ignore, including 10MBit which has a speed value of 0
649 }
650
651 if (priv->family_id == RTL8380_FAMILY_ID) {
652 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
653 if (state->link)
654 reg |= RTL838X_FORCE_LINK_EN;
655 if (state->duplex == RTL838X_DUPLEX_MODE)
656 reg |= RTL838X_DUPLEX_MODE;
657 } else if (priv->family_id == RTL8390_FAMILY_ID) {
658 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
659 if (state->link)
660 reg |= RTL839X_FORCE_LINK_EN;
661 if (state->duplex == RTL839X_DUPLEX_MODE)
662 reg |= RTL839X_DUPLEX_MODE;
663 }
664
665 // LAG members must use DUPLEX and we need to enable the link
666 if (priv->lagmembers & BIT_ULL(port)) {
667 switch(priv->family_id) {
668 case RTL8380_FAMILY_ID:
669 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
670 break;
671 case RTL8390_FAMILY_ID:
672 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
673 break;
674 }
675 }
676
677 // Disable AN
678 if (priv->family_id == RTL8380_FAMILY_ID)
679 reg &= ~RTL838X_NWAY_EN;
680 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
681 }
682
683 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
684 unsigned int mode,
685 const struct phylink_link_state *state)
686 {
687 struct rtl838x_switch_priv *priv = ds->priv;
688 int sds_num;
689 u32 reg, band;
690
691 sds_num = priv->ports[port].sds_num;
692 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
693
694 switch (state->interface) {
695 case PHY_INTERFACE_MODE_HSGMII:
696 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
697 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
698 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
699 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
700 break;
701 case PHY_INTERFACE_MODE_1000BASEX:
702 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
703 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
704 break;
705 case PHY_INTERFACE_MODE_XGMII:
706 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
707 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
708 break;
709 case PHY_INTERFACE_MODE_10GBASER:
710 case PHY_INTERFACE_MODE_10GKR:
711 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
712 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
713 break;
714 case PHY_INTERFACE_MODE_USXGMII:
715 // Translates to MII_USXGMII_10GSXGMII
716 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
717 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
718 break;
719 case PHY_INTERFACE_MODE_SGMII:
720 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
721 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
722 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
723 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
724 break;
725 case PHY_INTERFACE_MODE_QSGMII:
726 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
727 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
728 break;
729 default:
730 pr_err("%s: unknown serdes mode: %s\n",
731 __func__, phy_modes(state->interface));
732 return;
733 }
734
735 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
736 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
737
738 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
739
740 reg &= ~(0xf << 12);
741 reg |= 0x2 << 12; // Set SMI speed to 0x2
742
743 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
744
745 if (priv->lagmembers & BIT_ULL(port))
746 reg |= RTL931X_DUPLEX_MODE;
747
748 if (state->duplex == DUPLEX_FULL)
749 reg |= RTL931X_DUPLEX_MODE;
750
751 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
752
753 }
754
755 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
756 unsigned int mode,
757 const struct phylink_link_state *state)
758 {
759 struct rtl838x_switch_priv *priv = ds->priv;
760 int sds_num, sds_mode;
761 u32 reg;
762
763 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
764 port, mode, phy_modes(state->interface), state->speed, state->link);
765
766 // Nothing to be done for the CPU-port
767 if (port == priv->cpu_port)
768 return;
769
770 if (priv->family_id == RTL9310_FAMILY_ID)
771 return rtl931x_phylink_mac_config(ds, port, mode, state);
772
773 sds_num = priv->ports[port].sds_num;
774 pr_info("%s SDS is %d\n", __func__, sds_num);
775 if (sds_num >= 0) {
776 switch (state->interface) {
777 case PHY_INTERFACE_MODE_HSGMII:
778 sds_mode = 0x12;
779 break;
780 case PHY_INTERFACE_MODE_1000BASEX:
781 sds_mode = 0x04;
782 break;
783 case PHY_INTERFACE_MODE_XGMII:
784 sds_mode = 0x10;
785 break;
786 case PHY_INTERFACE_MODE_10GBASER:
787 case PHY_INTERFACE_MODE_10GKR:
788 sds_mode = 0x1b; // 10G 1000X Auto
789 break;
790 case PHY_INTERFACE_MODE_USXGMII:
791 sds_mode = 0x0d;
792 break;
793 default:
794 pr_err("%s: unknown serdes mode: %s\n",
795 __func__, phy_modes(state->interface));
796 return;
797 }
798 rtl9300_sds_rst(sds_num, sds_mode);
799 }
800
801 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
802 reg &= ~(0xf << 3);
803
804 switch (state->speed) {
805 case SPEED_10000:
806 reg |= 4 << 3;
807 break;
808 case SPEED_5000:
809 reg |= 6 << 3;
810 break;
811 case SPEED_2500:
812 reg |= 5 << 3;
813 break;
814 case SPEED_1000:
815 reg |= 2 << 3;
816 break;
817 default:
818 reg |= 2 << 3;
819 break;
820 }
821
822 if (state->link)
823 reg |= RTL930X_FORCE_LINK_EN;
824
825 if (priv->lagmembers & BIT_ULL(port))
826 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
827
828 if (state->duplex == DUPLEX_FULL)
829 reg |= RTL930X_DUPLEX_MODE;
830
831 if (priv->ports[port].phy_is_integrated)
832 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
833 else
834 reg |= RTL930X_FORCE_EN;
835
836 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
837 }
838
839 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
840 unsigned int mode,
841 phy_interface_t interface)
842 {
843 struct rtl838x_switch_priv *priv = ds->priv;
844 u32 v;
845
846 /* Stop TX/RX to port */
847 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
848
849 // No longer force link
850 if (priv->family_id == RTL9300_FAMILY_ID)
851 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
852 else if (priv->family_id == RTL9310_FAMILY_ID)
853 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
854 sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));
855 }
856
857 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
858 unsigned int mode,
859 phy_interface_t interface)
860 {
861 struct rtl838x_switch_priv *priv = ds->priv;
862 /* Stop TX/RX to port */
863 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
864
865 // No longer force link
866 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
867 }
868
869 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
870 unsigned int mode,
871 phy_interface_t interface,
872 struct phy_device *phydev,
873 int speed, int duplex,
874 bool tx_pause, bool rx_pause)
875 {
876 struct rtl838x_switch_priv *priv = ds->priv;
877 /* Restart TX/RX to port */
878 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
879 // TODO: Set speed/duplex/pauses
880 }
881
882 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
883 unsigned int mode,
884 phy_interface_t interface,
885 struct phy_device *phydev,
886 int speed, int duplex,
887 bool tx_pause, bool rx_pause)
888 {
889 struct rtl838x_switch_priv *priv = ds->priv;
890
891 /* Restart TX/RX to port */
892 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
893 // TODO: Set speed/duplex/pauses
894 }
895
896 static void rtl83xx_get_strings(struct dsa_switch *ds,
897 int port, u32 stringset, u8 *data)
898 {
899 int i;
900
901 if (stringset != ETH_SS_STATS)
902 return;
903
904 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
905 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
906 ETH_GSTRING_LEN);
907 }
908
909 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
910 uint64_t *data)
911 {
912 struct rtl838x_switch_priv *priv = ds->priv;
913 const struct rtl83xx_mib_desc *mib;
914 int i;
915 u64 h;
916
917 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
918 mib = &rtl83xx_mib[i];
919
920 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
921 if (mib->size == 2) {
922 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
923 data[i] |= h << 32;
924 }
925 }
926 }
927
928 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
929 {
930 if (sset != ETH_SS_STATS)
931 return 0;
932
933 return ARRAY_SIZE(rtl83xx_mib);
934 }
935
936 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
937 {
938 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
939 u64 portmask;
940
941 if (mc_group >= MAX_MC_GROUPS - 1)
942 return -1;
943
944 if (priv->is_lagmember[port]) {
945 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
946 return 0;
947 }
948
949 set_bit(mc_group, priv->mc_group_bm);
950 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
951 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
952 priv->r->write_mcast_pmask(mc_group, portmask);
953
954 return mc_group;
955 }
956
957 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
958 {
959 u64 portmask = priv->r->read_mcast_pmask(mc_group);
960
961 pr_debug("%s: %d\n", __func__, port);
962 if (priv->is_lagmember[port]) {
963 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
964 return portmask;
965 }
966 portmask |= BIT_ULL(port);
967 priv->r->write_mcast_pmask(mc_group, portmask);
968
969 return portmask;
970 }
971
972 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
973 {
974 u64 portmask = priv->r->read_mcast_pmask(mc_group);
975
976 pr_debug("%s: %d\n", __func__, port);
977 if (priv->is_lagmember[port]) {
978 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
979 return portmask;
980 }
981 priv->r->write_mcast_pmask(mc_group, portmask);
982 if (portmask == BIT_ULL(priv->cpu_port)) {
983 portmask &= ~BIT_ULL(priv->cpu_port);
984 priv->r->write_mcast_pmask(mc_group, portmask);
985 clear_bit(mc_group, priv->mc_group_bm);
986 }
987
988 return portmask;
989 }
990
991 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
992 {
993 int mc_group;
994
995 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
996 u64 portmask = priv->r->read_mcast_pmask(mc_group);
997 if (portmask & BIT_ULL(port)) {
998 priv->mc_group_saves[mc_group] = port;
999 rtl83xx_mc_group_del_port(priv, mc_group, port);
1000 }
1001 }
1002 }
1003
1004 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1005 {
1006 int mc_group;
1007
1008 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1009 if (priv->mc_group_saves[mc_group] == port) {
1010 rtl83xx_mc_group_add_port(priv, mc_group, port);
1011 priv->mc_group_saves[mc_group] = -1;
1012 }
1013 }
1014 }
1015
1016 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1017 struct phy_device *phydev)
1018 {
1019 struct rtl838x_switch_priv *priv = ds->priv;
1020 u64 v;
1021
1022 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1023 priv->ports[port].enable = true;
1024
1025 /* enable inner tagging on egress, do not keep any tags */
1026 if (priv->family_id == RTL9310_FAMILY_ID)
1027 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1028 else
1029 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1030
1031 if (dsa_is_cpu_port(ds, port))
1032 return 0;
1033
1034 /* add port to switch mask of CPU_PORT */
1035 priv->r->traffic_enable(priv->cpu_port, port);
1036
1037 load_mcgroups(priv, port);
1038
1039 if (priv->is_lagmember[port]) {
1040 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1041 return 0;
1042 }
1043
1044 /* add all other ports in the same bridge to switch mask of port */
1045 v = priv->r->traffic_get(port);
1046 v |= priv->ports[port].pm;
1047 priv->r->traffic_set(port, v);
1048
1049 // TODO: Figure out if this is necessary
1050 if (priv->family_id == RTL9300_FAMILY_ID) {
1051 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1052 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1053 }
1054
1055 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1056
1057 return 0;
1058 }
1059
1060 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1061 {
1062 struct rtl838x_switch_priv *priv = ds->priv;
1063 u64 v;
1064
1065 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1066 /* you can only disable user ports */
1067 if (!dsa_is_user_port(ds, port))
1068 return;
1069
1070 // BUG: This does not work on RTL931X
1071 /* remove port from switch mask of CPU_PORT */
1072 priv->r->traffic_disable(priv->cpu_port, port);
1073 store_mcgroups(priv, port);
1074
1075 /* remove all other ports in the same bridge from switch mask of port */
1076 v = priv->r->traffic_get(port);
1077 v &= ~priv->ports[port].pm;
1078 priv->r->traffic_set(port, v);
1079
1080 priv->ports[port].enable = false;
1081 }
1082
1083 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1084 struct ethtool_eee *e)
1085 {
1086 struct rtl838x_switch_priv *priv = ds->priv;
1087
1088 if (e->eee_enabled && !priv->eee_enabled) {
1089 pr_info("Globally enabling EEE\n");
1090 priv->r->init_eee(priv, true);
1091 }
1092
1093 priv->r->port_eee_set(priv, port, e->eee_enabled);
1094
1095 if (e->eee_enabled)
1096 pr_info("Enabled EEE for port %d\n", port);
1097 else
1098 pr_info("Disabled EEE for port %d\n", port);
1099 return 0;
1100 }
1101
1102 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1103 struct ethtool_eee *e)
1104 {
1105 struct rtl838x_switch_priv *priv = ds->priv;
1106
1107 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1108
1109 priv->r->eee_port_ability(priv, e, port);
1110
1111 e->eee_enabled = priv->ports[port].eee_enabled;
1112
1113 e->eee_active = !!(e->advertised & e->lp_advertised);
1114
1115 return 0;
1116 }
1117
1118 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1119 struct ethtool_eee *e)
1120 {
1121 struct rtl838x_switch_priv *priv = ds->priv;
1122
1123 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1124 | SUPPORTED_2500baseX_Full;
1125
1126 priv->r->eee_port_ability(priv, e, port);
1127
1128 e->eee_enabled = priv->ports[port].eee_enabled;
1129
1130 e->eee_active = !!(e->advertised & e->lp_advertised);
1131
1132 return 0;
1133 }
1134
1135 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1136 {
1137 struct rtl838x_switch_priv *priv = ds->priv;
1138
1139 priv->r->set_ageing_time(msec);
1140 return 0;
1141 }
1142
1143 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1144 struct net_device *bridge)
1145 {
1146 struct rtl838x_switch_priv *priv = ds->priv;
1147 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1148 int i;
1149
1150 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1151
1152 if (priv->is_lagmember[port]) {
1153 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1154 return 0;
1155 }
1156
1157 mutex_lock(&priv->reg_mutex);
1158 for (i = 0; i < ds->num_ports; i++) {
1159 /* Add this port to the port matrix of the other ports in the
1160 * same bridge. If the port is disabled, port matrix is kept
1161 * and not being setup until the port becomes enabled.
1162 */
1163 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1164 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1165 continue;
1166 if (priv->ports[i].enable)
1167 priv->r->traffic_enable(i, port);
1168
1169 priv->ports[i].pm |= BIT_ULL(port);
1170 port_bitmap |= BIT_ULL(i);
1171 }
1172 }
1173 load_mcgroups(priv, port);
1174
1175 /* Add all other ports to this port matrix. */
1176 if (priv->ports[port].enable) {
1177 priv->r->traffic_enable(priv->cpu_port, port);
1178 v = priv->r->traffic_get(port);
1179 v |= port_bitmap;
1180 priv->r->traffic_set(port, v);
1181 }
1182 priv->ports[port].pm |= port_bitmap;
1183 mutex_unlock(&priv->reg_mutex);
1184
1185 return 0;
1186 }
1187
1188 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1189 struct net_device *bridge)
1190 {
1191 struct rtl838x_switch_priv *priv = ds->priv;
1192 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1193 int i;
1194
1195 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1196 mutex_lock(&priv->reg_mutex);
1197 for (i = 0; i < ds->num_ports; i++) {
1198 /* Remove this port from the port matrix of the other ports
1199 * in the same bridge. If the port is disabled, port matrix
1200 * is kept and not being setup until the port becomes enabled.
1201 * And the other port's port matrix cannot be broken when the
1202 * other port is still a VLAN-aware port.
1203 */
1204 if (dsa_is_user_port(ds, i) && i != port) {
1205 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1206 continue;
1207 if (priv->ports[i].enable)
1208 priv->r->traffic_disable(i, port);
1209
1210 priv->ports[i].pm |= BIT_ULL(port);
1211 port_bitmap &= ~BIT_ULL(i);
1212 }
1213 }
1214 store_mcgroups(priv, port);
1215
1216 /* Add all other ports to this port matrix. */
1217 if (priv->ports[port].enable) {
1218 v = priv->r->traffic_get(port);
1219 v |= port_bitmap;
1220 priv->r->traffic_set(port, v);
1221 }
1222 priv->ports[port].pm &= ~port_bitmap;
1223
1224 mutex_unlock(&priv->reg_mutex);
1225 }
1226
1227 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1228 {
1229 u32 msti = 0;
1230 u32 port_state[4];
1231 int index, bit;
1232 int pos = port;
1233 struct rtl838x_switch_priv *priv = ds->priv;
1234 int n = priv->port_width << 1;
1235
1236 /* Ports above or equal CPU port can never be configured */
1237 if (port >= priv->cpu_port)
1238 return;
1239
1240 mutex_lock(&priv->reg_mutex);
1241
1242 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1243 * have 64 bit fields, 839x and 931x have 128 bit fields
1244 */
1245 if (priv->family_id == RTL8390_FAMILY_ID)
1246 pos += 12;
1247 if (priv->family_id == RTL9300_FAMILY_ID)
1248 pos += 3;
1249 if (priv->family_id == RTL9310_FAMILY_ID)
1250 pos += 8;
1251
1252 index = n - (pos >> 4) - 1;
1253 bit = (pos << 1) % 32;
1254
1255 priv->r->stp_get(priv, msti, port_state);
1256
1257 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1258 port_state[index] &= ~(3 << bit);
1259
1260 switch (state) {
1261 case BR_STATE_DISABLED: /* 0 */
1262 port_state[index] |= (0 << bit);
1263 break;
1264 case BR_STATE_BLOCKING: /* 4 */
1265 case BR_STATE_LISTENING: /* 1 */
1266 port_state[index] |= (1 << bit);
1267 break;
1268 case BR_STATE_LEARNING: /* 2 */
1269 port_state[index] |= (2 << bit);
1270 break;
1271 case BR_STATE_FORWARDING: /* 3*/
1272 port_state[index] |= (3 << bit);
1273 default:
1274 break;
1275 }
1276
1277 priv->r->stp_set(priv, msti, port_state);
1278
1279 mutex_unlock(&priv->reg_mutex);
1280 }
1281
1282 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1283 {
1284 struct rtl838x_switch_priv *priv = ds->priv;
1285 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1286
1287 pr_debug("FAST AGE port %d\n", port);
1288 mutex_lock(&priv->reg_mutex);
1289 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1290 * port fields:
1291 * 0-4: Replacing port
1292 * 5-9: Flushed/replaced port
1293 * 10-21: FVID
1294 * 22: Entry types: 1: dynamic, 0: also static
1295 * 23: Match flush port
1296 * 24: Match FVID
1297 * 25: Flush (0) or replace (1) L2 entries
1298 * 26: Status of action (1: Start, 0: Done)
1299 */
1300 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1301
1302 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1303
1304 mutex_unlock(&priv->reg_mutex);
1305 }
1306
1307 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1308 {
1309 struct rtl838x_switch_priv *priv = ds->priv;
1310
1311 pr_debug("FAST AGE port %d\n", port);
1312 mutex_lock(&priv->reg_mutex);
1313 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1314
1315 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1316
1317 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1318
1319 mutex_unlock(&priv->reg_mutex);
1320 }
1321
1322 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1323 bool vlan_filtering,
1324 struct switchdev_trans *trans)
1325 {
1326 struct rtl838x_switch_priv *priv = ds->priv;
1327
1328 pr_debug("%s: port %d\n", __func__, port);
1329 mutex_lock(&priv->reg_mutex);
1330
1331 if (vlan_filtering) {
1332 /* Enable ingress and egress filtering
1333 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1334 * the filter action:
1335 * 0: Always Forward
1336 * 1: Drop packet
1337 * 2: Trap packet to CPU port
1338 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1339 */
1340 if (port != priv->cpu_port)
1341 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1342
1343 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1344 } else {
1345 /* Disable ingress and egress filtering */
1346 if (port != priv->cpu_port)
1347 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1348
1349 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1350 }
1351
1352 /* Do we need to do something to the CPU-Port, too? */
1353 mutex_unlock(&priv->reg_mutex);
1354
1355 return 0;
1356 }
1357
1358 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1359 const struct switchdev_obj_port_vlan *vlan)
1360 {
1361 struct rtl838x_vlan_info info;
1362 struct rtl838x_switch_priv *priv = ds->priv;
1363
1364 priv->r->vlan_tables_read(0, &info);
1365
1366 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1367 info.tagged_ports, info.untagged_ports, info.profile_id,
1368 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1369
1370 priv->r->vlan_tables_read(1, &info);
1371 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1372 info.tagged_ports, info.untagged_ports, info.profile_id,
1373 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1374 priv->r->vlan_set_untagged(1, info.untagged_ports);
1375 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1376
1377 priv->r->vlan_set_tagged(1, &info);
1378 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1379
1380 mutex_unlock(&priv->reg_mutex);
1381 return 0;
1382 }
1383
1384 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1385 const struct switchdev_obj_port_vlan *vlan)
1386 {
1387 struct rtl838x_vlan_info info;
1388 struct rtl838x_switch_priv *priv = ds->priv;
1389 int v;
1390
1391 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1392 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1393
1394 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1395 dev_err(priv->dev, "VLAN out of range: %d - %d",
1396 vlan->vid_begin, vlan->vid_end);
1397 return;
1398 }
1399
1400 mutex_lock(&priv->reg_mutex);
1401
1402 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1403 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1404 if (!v)
1405 continue;
1406 /* Set both inner and outer PVID of the port */
1407 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1408 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1409 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1410 PBVLAN_MODE_UNTAG_AND_PRITAG);
1411 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1412 PBVLAN_MODE_UNTAG_AND_PRITAG);
1413
1414 priv->ports[port].pvid = vlan->vid_end;
1415 }
1416 }
1417
1418 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1419 /* Get port memberships of this vlan */
1420 priv->r->vlan_tables_read(v, &info);
1421
1422 /* new VLAN? */
1423 if (!info.tagged_ports) {
1424 info.fid = 0;
1425 info.hash_mc_fid = false;
1426 info.hash_uc_fid = false;
1427 info.profile_id = 0;
1428 }
1429
1430 /* sanitize untagged_ports - must be a subset */
1431 if (info.untagged_ports & ~info.tagged_ports)
1432 info.untagged_ports = 0;
1433
1434 info.tagged_ports |= BIT_ULL(port);
1435 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1436 info.untagged_ports |= BIT_ULL(port);
1437
1438 priv->r->vlan_set_untagged(v, info.untagged_ports);
1439 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1440
1441 priv->r->vlan_set_tagged(v, &info);
1442 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1443 }
1444
1445 mutex_unlock(&priv->reg_mutex);
1446 }
1447
1448 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1449 const struct switchdev_obj_port_vlan *vlan)
1450 {
1451 struct rtl838x_vlan_info info;
1452 struct rtl838x_switch_priv *priv = ds->priv;
1453 int v;
1454 u16 pvid;
1455
1456 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1457 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1458
1459 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1460 dev_err(priv->dev, "VLAN out of range: %d - %d",
1461 vlan->vid_begin, vlan->vid_end);
1462 return -ENOTSUPP;
1463 }
1464
1465 mutex_lock(&priv->reg_mutex);
1466 pvid = priv->ports[port].pvid;
1467
1468 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1469 /* Reset to default if removing the current PVID */
1470 if (v == pvid) {
1471 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1472 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1473 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1474 PBVLAN_MODE_UNTAG_AND_PRITAG);
1475 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1476 PBVLAN_MODE_UNTAG_AND_PRITAG);
1477 }
1478 /* Get port memberships of this vlan */
1479 priv->r->vlan_tables_read(v, &info);
1480
1481 /* remove port from both tables */
1482 info.untagged_ports &= (~BIT_ULL(port));
1483 info.tagged_ports &= (~BIT_ULL(port));
1484
1485 priv->r->vlan_set_untagged(v, info.untagged_ports);
1486 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1487
1488 priv->r->vlan_set_tagged(v, &info);
1489 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1490 }
1491 mutex_unlock(&priv->reg_mutex);
1492
1493 return 0;
1494 }
1495
1496 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1497 {
1498 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1499 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1500 e->vid, e->rvid, e->port, e->valid);
1501
1502 if (e->type != L2_MULTICAST) {
1503 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1504 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1505 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1506 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1507 }
1508 if (e->type == L2_MULTICAST)
1509 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1510 if (e->is_ip_mc || e->is_ipv6_mc)
1511 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1512 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1513 pr_info(" stack_dev: %d\n", e->stack_dev);
1514 if (e->next_hop)
1515 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1516 }
1517
1518 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1519 {
1520 e->is_ip_mc = e->is_ipv6_mc = false;
1521 e->valid = true;
1522 e->age = 3;
1523 e->port = port,
1524 e->vid = vid;
1525 u64_to_ether_addr(mac, e->mac);
1526 }
1527
1528 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1529 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1530 {
1531 e->is_ip_mc = e->is_ipv6_mc = false;
1532 e->valid = true;
1533 e->mc_portmask_index = mc_group;
1534 e->type = L2_MULTICAST;
1535 e->rvid = e->vid = vid;
1536 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1537 u64_to_ether_addr(mac, e->mac);
1538 }
1539
1540 /*
1541 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1542 * over the entries in the bucket until either a matching entry is found or an empty slot
1543 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1544 * when an empty slot was found and must exist is false, the index of the slot is returned
1545 * when no slots are available returns -1
1546 */
1547 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1548 bool must_exist, struct rtl838x_l2_entry *e)
1549 {
1550 int i, idx = -1;
1551 u32 key = priv->r->l2_hash_key(priv, seed);
1552 u64 entry;
1553
1554 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1555 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1556 for (i = 0; i < priv->l2_bucket_size; i++) {
1557 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1558 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1559 if (must_exist && !e->valid)
1560 continue;
1561 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1562 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1563 break;
1564 }
1565 }
1566
1567 return idx;
1568 }
1569
1570 /*
1571 * Uses the seed to identify an entry in the CAM by looping over all its entries
1572 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1573 * when an empty slot was found the index of the slot is returned
1574 * when no slots are available returns -1
1575 */
1576 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1577 bool must_exist, struct rtl838x_l2_entry *e)
1578 {
1579 int i, idx = -1;
1580 u64 entry;
1581
1582 for (i = 0; i < 64; i++) {
1583 entry = priv->r->read_cam(i, e);
1584 if (!must_exist && !e->valid) {
1585 if (idx < 0) /* First empty entry? */
1586 idx = i;
1587 break;
1588 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1589 pr_debug("Found entry in CAM\n");
1590 idx = i;
1591 break;
1592 }
1593 }
1594 return idx;
1595 }
1596
1597 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1598 const unsigned char *addr, u16 vid)
1599 {
1600 struct rtl838x_switch_priv *priv = ds->priv;
1601 u64 mac = ether_addr_to_u64(addr);
1602 struct rtl838x_l2_entry e;
1603 int err = 0, idx;
1604 u64 seed = priv->r->l2_hash_seed(mac, vid);
1605
1606 if (priv->is_lagmember[port]) {
1607 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1608 return 0;
1609 }
1610
1611 mutex_lock(&priv->reg_mutex);
1612
1613 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1614
1615 // Found an existing or empty entry
1616 if (idx >= 0) {
1617 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1618 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1619 goto out;
1620 }
1621
1622 // Hash buckets full, try CAM
1623 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1624
1625 if (idx >= 0) {
1626 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1627 priv->r->write_cam(idx, &e);
1628 goto out;
1629 }
1630
1631 err = -ENOTSUPP;
1632 out:
1633 mutex_unlock(&priv->reg_mutex);
1634 return err;
1635 }
1636
1637 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1638 const unsigned char *addr, u16 vid)
1639 {
1640 struct rtl838x_switch_priv *priv = ds->priv;
1641 u64 mac = ether_addr_to_u64(addr);
1642 struct rtl838x_l2_entry e;
1643 int err = 0, idx;
1644 u64 seed = priv->r->l2_hash_seed(mac, vid);
1645
1646 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1647 mutex_lock(&priv->reg_mutex);
1648
1649 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1650
1651 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1652 if (idx >= 0) {
1653 e.valid = false;
1654 dump_l2_entry(&e);
1655 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1656 goto out;
1657 }
1658
1659 /* Check CAM for spillover from hash buckets */
1660 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1661
1662 if (idx >= 0) {
1663 e.valid = false;
1664 priv->r->write_cam(idx, &e);
1665 goto out;
1666 }
1667 err = -ENOENT;
1668 out:
1669 mutex_unlock(&priv->reg_mutex);
1670 return err;
1671 }
1672
1673 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1674 dsa_fdb_dump_cb_t *cb, void *data)
1675 {
1676 struct rtl838x_l2_entry e;
1677 struct rtl838x_switch_priv *priv = ds->priv;
1678 int i;
1679 u32 fid, pkey;
1680 u64 mac;
1681
1682 mutex_lock(&priv->reg_mutex);
1683
1684 for (i = 0; i < priv->fib_entries; i++) {
1685 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1686
1687 if (!e.valid)
1688 continue;
1689
1690 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1691 u64 seed;
1692 u32 key;
1693
1694 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1695 mac = ether_addr_to_u64(&e.mac[0]);
1696 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1697 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1698 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1699 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1700 dump_l2_entry(&e);
1701 seed = priv->r->l2_hash_seed(mac, e.rvid);
1702 key = priv->r->l2_hash_key(priv, seed);
1703 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1704 cb(e.mac, e.vid, e.is_static, data);
1705 }
1706 if (e.type == L2_MULTICAST) {
1707 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1708
1709 if (portmask & BIT_ULL(port)) {
1710 dump_l2_entry(&e);
1711 pr_info(" PM: %016llx\n", portmask);
1712 }
1713 }
1714 }
1715
1716 for (i = 0; i < 64; i++) {
1717 priv->r->read_cam(i, &e);
1718
1719 if (!e.valid)
1720 continue;
1721
1722 if (e.port == port)
1723 cb(e.mac, e.vid, e.is_static, data);
1724 }
1725
1726 mutex_unlock(&priv->reg_mutex);
1727 return 0;
1728 }
1729
1730 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1731 const struct switchdev_obj_port_mdb *mdb)
1732 {
1733 struct rtl838x_switch_priv *priv = ds->priv;
1734
1735 if (priv->id >= 0x9300)
1736 return -EOPNOTSUPP;
1737
1738 return 0;
1739 }
1740
1741 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1742 const struct switchdev_obj_port_mdb *mdb)
1743 {
1744 struct rtl838x_switch_priv *priv = ds->priv;
1745 u64 mac = ether_addr_to_u64(mdb->addr);
1746 struct rtl838x_l2_entry e;
1747 int err = 0, idx;
1748 int vid = mdb->vid;
1749 u64 seed = priv->r->l2_hash_seed(mac, vid);
1750 int mc_group;
1751
1752 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1753
1754 if (priv->is_lagmember[port]) {
1755 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1756 return;
1757 }
1758
1759 mutex_lock(&priv->reg_mutex);
1760
1761 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1762
1763 // Found an existing or empty entry
1764 if (idx >= 0) {
1765 if (e.valid) {
1766 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1767 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1768 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1769 } else {
1770 pr_debug("New entry for seed %016llx\n", seed);
1771 mc_group = rtl83xx_mc_group_alloc(priv, port);
1772 if (mc_group < 0) {
1773 err = -ENOTSUPP;
1774 goto out;
1775 }
1776 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1777 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1778 }
1779 goto out;
1780 }
1781
1782 // Hash buckets full, try CAM
1783 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1784
1785 if (idx >= 0) {
1786 if (e.valid) {
1787 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1788 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1789 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1790 } else {
1791 pr_debug("New entry\n");
1792 mc_group = rtl83xx_mc_group_alloc(priv, port);
1793 if (mc_group < 0) {
1794 err = -ENOTSUPP;
1795 goto out;
1796 }
1797 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1798 priv->r->write_cam(idx, &e);
1799 }
1800 goto out;
1801 }
1802
1803 err = -ENOTSUPP;
1804 out:
1805 mutex_unlock(&priv->reg_mutex);
1806 if (err)
1807 dev_err(ds->dev, "failed to add MDB entry\n");
1808 }
1809
1810 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1811 const struct switchdev_obj_port_mdb *mdb)
1812 {
1813 struct rtl838x_switch_priv *priv = ds->priv;
1814 u64 mac = ether_addr_to_u64(mdb->addr);
1815 struct rtl838x_l2_entry e;
1816 int err = 0, idx;
1817 int vid = mdb->vid;
1818 u64 seed = priv->r->l2_hash_seed(mac, vid);
1819 u64 portmask;
1820
1821 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1822
1823 if (priv->is_lagmember[port]) {
1824 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1825 return 0;
1826 }
1827
1828 mutex_lock(&priv->reg_mutex);
1829
1830 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1831
1832 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1833 if (idx >= 0) {
1834 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1835 if (!portmask) {
1836 e.valid = false;
1837 // dump_l2_entry(&e);
1838 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1839 }
1840 goto out;
1841 }
1842
1843 /* Check CAM for spillover from hash buckets */
1844 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1845
1846 if (idx >= 0) {
1847 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1848 if (!portmask) {
1849 e.valid = false;
1850 // dump_l2_entry(&e);
1851 priv->r->write_cam(idx, &e);
1852 }
1853 goto out;
1854 }
1855 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1856 out:
1857 mutex_unlock(&priv->reg_mutex);
1858 return err;
1859 }
1860
1861 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1862 struct dsa_mall_mirror_tc_entry *mirror,
1863 bool ingress)
1864 {
1865 /* We support 4 mirror groups, one destination port per group */
1866 int group;
1867 struct rtl838x_switch_priv *priv = ds->priv;
1868 int ctrl_reg, dpm_reg, spm_reg;
1869
1870 pr_debug("In %s\n", __func__);
1871
1872 for (group = 0; group < 4; group++) {
1873 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1874 break;
1875 }
1876 if (group >= 4) {
1877 for (group = 0; group < 4; group++) {
1878 if (priv->mirror_group_ports[group] < 0)
1879 break;
1880 }
1881 }
1882
1883 if (group >= 4)
1884 return -ENOSPC;
1885
1886 ctrl_reg = priv->r->mir_ctrl + group * 4;
1887 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1888 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1889
1890 pr_debug("Using group %d\n", group);
1891 mutex_lock(&priv->reg_mutex);
1892
1893 if (priv->family_id == RTL8380_FAMILY_ID) {
1894 /* Enable mirroring to port across VLANs (bit 11) */
1895 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1896 } else {
1897 /* Enable mirroring to destination port */
1898 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1899 }
1900
1901 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1902 mutex_unlock(&priv->reg_mutex);
1903 return -EEXIST;
1904 }
1905 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1906 mutex_unlock(&priv->reg_mutex);
1907 return -EEXIST;
1908 }
1909
1910 if (ingress)
1911 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1912 else
1913 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1914
1915 priv->mirror_group_ports[group] = mirror->to_local_port;
1916 mutex_unlock(&priv->reg_mutex);
1917 return 0;
1918 }
1919
1920 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1921 struct dsa_mall_mirror_tc_entry *mirror)
1922 {
1923 int group = 0;
1924 struct rtl838x_switch_priv *priv = ds->priv;
1925 int ctrl_reg, dpm_reg, spm_reg;
1926
1927 pr_debug("In %s\n", __func__);
1928 for (group = 0; group < 4; group++) {
1929 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1930 break;
1931 }
1932 if (group >= 4)
1933 return;
1934
1935 ctrl_reg = priv->r->mir_ctrl + group * 4;
1936 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1937 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1938
1939 mutex_lock(&priv->reg_mutex);
1940 if (mirror->ingress) {
1941 /* Ingress, clear source port matrix */
1942 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1943 } else {
1944 /* Egress, clear destination port matrix */
1945 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1946 }
1947
1948 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1949 priv->mirror_group_ports[group] = -1;
1950 sw_w32(0, ctrl_reg);
1951 }
1952
1953 mutex_unlock(&priv->reg_mutex);
1954 }
1955
1956 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1957 {
1958 struct rtl838x_switch_priv *priv = ds->priv;
1959 unsigned long features = 0;
1960 pr_debug("%s: %d %lX\n", __func__, port, flags);
1961 if (priv->r->enable_learning)
1962 features |= BR_LEARNING;
1963 if (priv->r->enable_flood)
1964 features |= BR_FLOOD;
1965 if (priv->r->enable_mcast_flood)
1966 features |= BR_MCAST_FLOOD;
1967 if (priv->r->enable_bcast_flood)
1968 features |= BR_BCAST_FLOOD;
1969 if (flags & ~(features))
1970 return -EINVAL;
1971
1972 return 0;
1973 }
1974
1975 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1976 {
1977 struct rtl838x_switch_priv *priv = ds->priv;
1978
1979 pr_debug("%s: %d %lX\n", __func__, port, flags);
1980 if (priv->r->enable_learning)
1981 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
1982
1983 if (priv->r->enable_flood)
1984 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
1985
1986 if (priv->r->enable_mcast_flood)
1987 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
1988
1989 if (priv->r->enable_bcast_flood)
1990 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
1991
1992 return 0;
1993 }
1994
1995 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1996 struct net_device *lag,
1997 struct netdev_lag_upper_info *info)
1998 {
1999 int id;
2000
2001 id = dsa_lag_id(ds->dst, lag);
2002 if (id < 0 || id >= ds->num_lag_ids)
2003 return false;
2004
2005 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2006 return false;
2007 }
2008 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2009 return false;
2010
2011 return true;
2012 }
2013
2014 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2015 {
2016 struct rtl838x_switch_priv *priv = ds->priv;
2017
2018 pr_debug("%s: %d\n", __func__, port);
2019 // Nothing to be done...
2020
2021 return 0;
2022 }
2023
2024 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2025 struct net_device *lag,
2026 struct netdev_lag_upper_info *info)
2027 {
2028 struct rtl838x_switch_priv *priv = ds->priv;
2029 int i, err = 0;
2030
2031 if (!rtl83xx_lag_can_offload(ds, lag, info))
2032 return -EOPNOTSUPP;
2033
2034 mutex_lock(&priv->reg_mutex);
2035
2036 for (i = 0; i < priv->n_lags; i++) {
2037 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2038 break;
2039 }
2040 if (port >= priv->cpu_port) {
2041 err = -EINVAL;
2042 goto out;
2043 }
2044 pr_info("port_lag_join: group %d, port %d\n",i, port);
2045 if (!priv->lag_devs[i])
2046 priv->lag_devs[i] = lag;
2047
2048 if (priv->lag_primary[i]==-1) {
2049 priv->lag_primary[i]=port;
2050 } else
2051 priv->is_lagmember[port] = 1;
2052
2053 priv->lagmembers |= (1ULL << port);
2054
2055 pr_debug("lag_members = %llX\n", priv->lagmembers);
2056 err = rtl83xx_lag_add(priv->ds, i, port, info);
2057 if (err) {
2058 err = -EINVAL;
2059 goto out;
2060 }
2061
2062 out:
2063 mutex_unlock(&priv->reg_mutex);
2064 return err;
2065
2066 }
2067
2068 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2069 struct net_device *lag)
2070 {
2071 int i, group = -1, err;
2072 struct rtl838x_switch_priv *priv = ds->priv;
2073
2074 mutex_lock(&priv->reg_mutex);
2075 for (i=0;i<priv->n_lags;i++) {
2076 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2077 group = i;
2078 break;
2079 }
2080 }
2081
2082 if (group == -1) {
2083 pr_info("port_lag_leave: port %d is not a member\n", port);
2084 err = -EINVAL;
2085 goto out;
2086 }
2087
2088 if (port >= priv->cpu_port) {
2089 err = -EINVAL;
2090 goto out;
2091 }
2092 pr_info("port_lag_del: group %d, port %d\n",group, port);
2093 priv->lagmembers &=~ (1ULL << port);
2094 priv->lag_primary[i] = -1;
2095 priv->is_lagmember[port] = 0;
2096 pr_debug("lag_members = %llX\n", priv->lagmembers);
2097 err = rtl83xx_lag_del(priv->ds, group, port);
2098 if (err) {
2099 err = -EINVAL;
2100 goto out;
2101 }
2102 if (!priv->lags_port_members[i])
2103 priv->lag_devs[i] = NULL;
2104
2105 out:
2106 mutex_unlock(&priv->reg_mutex);
2107 return 0;
2108 }
2109
2110 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2111 {
2112 u32 val;
2113 u32 offset = 0;
2114 struct rtl838x_switch_priv *priv = ds->priv;
2115
2116 if (phy_addr >= 24 && phy_addr <= 27
2117 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2118 if (phy_addr == 26)
2119 offset = 0x100;
2120 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2121 return val;
2122 }
2123
2124 read_phy(phy_addr, 0, phy_reg, &val);
2125 return val;
2126 }
2127
2128 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2129 {
2130 u32 offset = 0;
2131 struct rtl838x_switch_priv *priv = ds->priv;
2132
2133 if (phy_addr >= 24 && phy_addr <= 27
2134 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2135 if (phy_addr == 26)
2136 offset = 0x100;
2137 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2138 return 0;
2139 }
2140 return write_phy(phy_addr, 0, phy_reg, val);
2141 }
2142
2143 const struct dsa_switch_ops rtl83xx_switch_ops = {
2144 .get_tag_protocol = rtl83xx_get_tag_protocol,
2145 .setup = rtl83xx_setup,
2146
2147 .phy_read = dsa_phy_read,
2148 .phy_write = dsa_phy_write,
2149
2150 .phylink_validate = rtl83xx_phylink_validate,
2151 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2152 .phylink_mac_config = rtl83xx_phylink_mac_config,
2153 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2154 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2155
2156 .get_strings = rtl83xx_get_strings,
2157 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2158 .get_sset_count = rtl83xx_get_sset_count,
2159
2160 .port_enable = rtl83xx_port_enable,
2161 .port_disable = rtl83xx_port_disable,
2162
2163 .get_mac_eee = rtl83xx_get_mac_eee,
2164 .set_mac_eee = rtl83xx_set_mac_eee,
2165
2166 .set_ageing_time = rtl83xx_set_ageing_time,
2167 .port_bridge_join = rtl83xx_port_bridge_join,
2168 .port_bridge_leave = rtl83xx_port_bridge_leave,
2169 .port_stp_state_set = rtl83xx_port_stp_state_set,
2170 .port_fast_age = rtl83xx_fast_age,
2171
2172 .port_vlan_filtering = rtl83xx_vlan_filtering,
2173 .port_vlan_prepare = rtl83xx_vlan_prepare,
2174 .port_vlan_add = rtl83xx_vlan_add,
2175 .port_vlan_del = rtl83xx_vlan_del,
2176
2177 .port_fdb_add = rtl83xx_port_fdb_add,
2178 .port_fdb_del = rtl83xx_port_fdb_del,
2179 .port_fdb_dump = rtl83xx_port_fdb_dump,
2180
2181 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2182 .port_mdb_add = rtl83xx_port_mdb_add,
2183 .port_mdb_del = rtl83xx_port_mdb_del,
2184
2185 .port_mirror_add = rtl83xx_port_mirror_add,
2186 .port_mirror_del = rtl83xx_port_mirror_del,
2187
2188 .port_lag_change = rtl83xx_port_lag_change,
2189 .port_lag_join = rtl83xx_port_lag_join,
2190 .port_lag_leave = rtl83xx_port_lag_leave,
2191
2192 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2193 .port_bridge_flags = rtl83xx_port_bridge_flags,
2194 };
2195
2196 const struct dsa_switch_ops rtl930x_switch_ops = {
2197 .get_tag_protocol = rtl83xx_get_tag_protocol,
2198 .setup = rtl93xx_setup,
2199
2200 .phy_read = dsa_phy_read,
2201 .phy_write = dsa_phy_write,
2202
2203 .phylink_validate = rtl93xx_phylink_validate,
2204 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2205 .phylink_mac_config = rtl93xx_phylink_mac_config,
2206 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2207 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2208
2209 .get_strings = rtl83xx_get_strings,
2210 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2211 .get_sset_count = rtl83xx_get_sset_count,
2212
2213 .port_enable = rtl83xx_port_enable,
2214 .port_disable = rtl83xx_port_disable,
2215
2216 .get_mac_eee = rtl93xx_get_mac_eee,
2217 .set_mac_eee = rtl83xx_set_mac_eee,
2218
2219 .set_ageing_time = rtl83xx_set_ageing_time,
2220 .port_bridge_join = rtl83xx_port_bridge_join,
2221 .port_bridge_leave = rtl83xx_port_bridge_leave,
2222 .port_stp_state_set = rtl83xx_port_stp_state_set,
2223 .port_fast_age = rtl930x_fast_age,
2224
2225 .port_vlan_filtering = rtl83xx_vlan_filtering,
2226 .port_vlan_prepare = rtl83xx_vlan_prepare,
2227 .port_vlan_add = rtl83xx_vlan_add,
2228 .port_vlan_del = rtl83xx_vlan_del,
2229
2230 .port_fdb_add = rtl83xx_port_fdb_add,
2231 .port_fdb_del = rtl83xx_port_fdb_del,
2232 .port_fdb_dump = rtl83xx_port_fdb_dump,
2233
2234 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2235 .port_mdb_add = rtl83xx_port_mdb_add,
2236 .port_mdb_del = rtl83xx_port_mdb_del,
2237
2238 .port_lag_change = rtl83xx_port_lag_change,
2239 .port_lag_join = rtl83xx_port_lag_join,
2240 .port_lag_leave = rtl83xx_port_lag_leave,
2241
2242 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2243 .port_bridge_flags = rtl83xx_port_bridge_flags,
2244 };
Staging tree of Christian Lamparter