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realtek: fix writing/deletion of CAM entries
[openwrt/staging/hauke.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
166 int port, bool enable)
167 {
168 int shift = SALRN_PORT_SHIFT(port);
169 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
170
171 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
172 priv->r->l2_port_new_salrn(port));
173 }
174
175 static int rtl83xx_setup(struct dsa_switch *ds)
176 {
177 int i;
178 struct rtl838x_switch_priv *priv = ds->priv;
179
180 pr_debug("%s called\n", __func__);
181
182 /* Disable MAC polling the PHY so that we can start configuration */
183 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
184
185 for (i = 0; i < ds->num_ports; i++)
186 priv->ports[i].enable = false;
187 priv->ports[priv->cpu_port].enable = true;
188
189 /* Configure ports so they are disabled by default, but once enabled
190 * they will work in isolated mode (only traffic between port and CPU).
191 */
192 for (i = 0; i < priv->cpu_port; i++) {
193 if (priv->ports[i].phy) {
194 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
195 priv->r->traffic_set(i, BIT_ULL(i));
196 }
197 }
198 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
199
200 /* For standalone ports, forward packets even if a static fdb
201 * entry for the source address exists on another port.
202 */
203 if (priv->r->set_static_move_action) {
204 for (i = 0; i <= priv->cpu_port; i++)
205 priv->r->set_static_move_action(i, true);
206 }
207
208 if (priv->family_id == RTL8380_FAMILY_ID)
209 rtl838x_print_matrix();
210 else
211 rtl839x_print_matrix();
212
213 rtl83xx_init_stats(priv);
214
215 rtl83xx_vlan_setup(priv);
216
217 rtl83xx_setup_bpdu_traps(priv);
218
219 ds->configure_vlan_while_not_filtering = true;
220
221 priv->r->l2_learning_setup();
222
223 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
224 ds->assisted_learning_on_cpu_port = true;
225
226 /*
227 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
228 * 0: FWD, 1: DROP, 2: TRAP2CPU
229 */
230 if (priv->family_id == RTL8380_FAMILY_ID)
231 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
232 else
233 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
234
235 /* Enable MAC Polling PHY again */
236 rtl83xx_enable_phy_polling(priv);
237 pr_debug("Please wait until PHY is settled\n");
238 msleep(1000);
239 priv->r->pie_init(priv);
240
241 return 0;
242 }
243
244 static int rtl93xx_setup(struct dsa_switch *ds)
245 {
246 int i;
247 struct rtl838x_switch_priv *priv = ds->priv;
248
249 pr_info("%s called\n", __func__);
250
251 /* Disable MAC polling the PHY so that we can start configuration */
252 if (priv->family_id == RTL9300_FAMILY_ID)
253 sw_w32(0, RTL930X_SMI_POLL_CTRL);
254
255 if (priv->family_id == RTL9310_FAMILY_ID) {
256 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
257 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
258 }
259
260 // Disable all ports except CPU port
261 for (i = 0; i < ds->num_ports; i++)
262 priv->ports[i].enable = false;
263 priv->ports[priv->cpu_port].enable = true;
264
265 /* Configure ports so they are disabled by default, but once enabled
266 * they will work in isolated mode (only traffic between port and CPU).
267 */
268 for (i = 0; i < priv->cpu_port; i++) {
269 if (priv->ports[i].phy) {
270 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
271 priv->r->traffic_set(i, BIT_ULL(i));
272 }
273 }
274 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
275
276 rtl930x_print_matrix();
277
278 // TODO: Initialize statistics
279
280 rtl83xx_vlan_setup(priv);
281
282 ds->configure_vlan_while_not_filtering = true;
283
284 priv->r->l2_learning_setup();
285
286 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
287 ds->assisted_learning_on_cpu_port = true;
288
289 rtl83xx_enable_phy_polling(priv);
290
291 priv->r->pie_init(priv);
292
293 priv->r->led_init(priv);
294
295 return 0;
296 }
297
298 static int rtl93xx_get_sds(struct phy_device *phydev)
299 {
300 struct device *dev = &phydev->mdio.dev;
301 struct device_node *dn;
302 u32 sds_num;
303
304 if (!dev)
305 return -1;
306 if (dev->of_node) {
307 dn = dev->of_node;
308 if (of_property_read_u32(dn, "sds", &sds_num))
309 sds_num = -1;
310 } else {
311 dev_err(dev, "No DT node.\n");
312 return -1;
313 }
314
315 return sds_num;
316 }
317
318 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
319 unsigned long *supported,
320 struct phylink_link_state *state)
321 {
322 struct rtl838x_switch_priv *priv = ds->priv;
323 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
324
325 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
326
327 if (!phy_interface_mode_is_rgmii(state->interface) &&
328 state->interface != PHY_INTERFACE_MODE_NA &&
329 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
330 state->interface != PHY_INTERFACE_MODE_MII &&
331 state->interface != PHY_INTERFACE_MODE_REVMII &&
332 state->interface != PHY_INTERFACE_MODE_GMII &&
333 state->interface != PHY_INTERFACE_MODE_QSGMII &&
334 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
335 state->interface != PHY_INTERFACE_MODE_SGMII) {
336 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
337 dev_err(ds->dev,
338 "Unsupported interface: %d for port %d\n",
339 state->interface, port);
340 return;
341 }
342
343 /* Allow all the expected bits */
344 phylink_set(mask, Autoneg);
345 phylink_set_port_modes(mask);
346 phylink_set(mask, Pause);
347 phylink_set(mask, Asym_Pause);
348
349 /* With the exclusion of MII and Reverse MII, we support Gigabit,
350 * including Half duplex
351 */
352 if (state->interface != PHY_INTERFACE_MODE_MII &&
353 state->interface != PHY_INTERFACE_MODE_REVMII) {
354 phylink_set(mask, 1000baseT_Full);
355 phylink_set(mask, 1000baseT_Half);
356 }
357
358 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
359 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
360 phylink_set(mask, 1000baseX_Full);
361
362 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
363 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
364 phylink_set(mask, 1000baseX_Full);
365
366 phylink_set(mask, 10baseT_Half);
367 phylink_set(mask, 10baseT_Full);
368 phylink_set(mask, 100baseT_Half);
369 phylink_set(mask, 100baseT_Full);
370
371 bitmap_and(supported, supported, mask,
372 __ETHTOOL_LINK_MODE_MASK_NBITS);
373 bitmap_and(state->advertising, state->advertising, mask,
374 __ETHTOOL_LINK_MODE_MASK_NBITS);
375 }
376
377 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
378 unsigned long *supported,
379 struct phylink_link_state *state)
380 {
381 struct rtl838x_switch_priv *priv = ds->priv;
382 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
383
384 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
385 phy_modes(state->interface));
386
387 if (!phy_interface_mode_is_rgmii(state->interface) &&
388 state->interface != PHY_INTERFACE_MODE_NA &&
389 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
390 state->interface != PHY_INTERFACE_MODE_MII &&
391 state->interface != PHY_INTERFACE_MODE_REVMII &&
392 state->interface != PHY_INTERFACE_MODE_GMII &&
393 state->interface != PHY_INTERFACE_MODE_QSGMII &&
394 state->interface != PHY_INTERFACE_MODE_XGMII &&
395 state->interface != PHY_INTERFACE_MODE_HSGMII &&
396 state->interface != PHY_INTERFACE_MODE_10GBASER &&
397 state->interface != PHY_INTERFACE_MODE_10GKR &&
398 state->interface != PHY_INTERFACE_MODE_USXGMII &&
399 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
400 state->interface != PHY_INTERFACE_MODE_SGMII) {
401 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
402 dev_err(ds->dev,
403 "Unsupported interface: %d for port %d\n",
404 state->interface, port);
405 return;
406 }
407
408 /* Allow all the expected bits */
409 phylink_set(mask, Autoneg);
410 phylink_set_port_modes(mask);
411 phylink_set(mask, Pause);
412 phylink_set(mask, Asym_Pause);
413
414 /* With the exclusion of MII and Reverse MII, we support Gigabit,
415 * including Half duplex
416 */
417 if (state->interface != PHY_INTERFACE_MODE_MII &&
418 state->interface != PHY_INTERFACE_MODE_REVMII) {
419 phylink_set(mask, 1000baseT_Full);
420 phylink_set(mask, 1000baseT_Half);
421 }
422
423 // Internal phys of the RTL93xx family provide 10G
424 if (priv->ports[port].phy_is_integrated
425 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
426 phylink_set(mask, 1000baseX_Full);
427 } else if (priv->ports[port].phy_is_integrated) {
428 phylink_set(mask, 1000baseX_Full);
429 phylink_set(mask, 10000baseKR_Full);
430 phylink_set(mask, 10000baseSR_Full);
431 phylink_set(mask, 10000baseCR_Full);
432 }
433 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
434 phylink_set(mask, 1000baseX_Full);
435 phylink_set(mask, 1000baseT_Full);
436 phylink_set(mask, 10000baseKR_Full);
437 phylink_set(mask, 10000baseT_Full);
438 phylink_set(mask, 10000baseSR_Full);
439 phylink_set(mask, 10000baseCR_Full);
440 }
441
442 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
443 phylink_set(mask, 10000baseT_Full);
444
445 phylink_set(mask, 10baseT_Half);
446 phylink_set(mask, 10baseT_Full);
447 phylink_set(mask, 100baseT_Half);
448 phylink_set(mask, 100baseT_Full);
449
450 bitmap_and(supported, supported, mask,
451 __ETHTOOL_LINK_MODE_MASK_NBITS);
452 bitmap_and(state->advertising, state->advertising, mask,
453 __ETHTOOL_LINK_MODE_MASK_NBITS);
454 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
455 }
456
457 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
458 struct phylink_link_state *state)
459 {
460 struct rtl838x_switch_priv *priv = ds->priv;
461 u64 speed;
462 u64 link;
463
464 if (port < 0 || port > priv->cpu_port)
465 return -EINVAL;
466
467 state->link = 0;
468 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
469 if (link & BIT_ULL(port))
470 state->link = 1;
471 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
472
473 state->duplex = 0;
474 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
475 state->duplex = 1;
476
477 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
478 speed >>= (port % 16) << 1;
479 switch (speed & 0x3) {
480 case 0:
481 state->speed = SPEED_10;
482 break;
483 case 1:
484 state->speed = SPEED_100;
485 break;
486 case 2:
487 state->speed = SPEED_1000;
488 break;
489 case 3:
490 if (priv->family_id == RTL9300_FAMILY_ID
491 && (port == 24 || port == 26)) /* Internal serdes */
492 state->speed = SPEED_2500;
493 else
494 state->speed = SPEED_100; /* Is in fact 500Mbit */
495 }
496
497 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
498 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
499 state->pause |= MLO_PAUSE_RX;
500 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
501 state->pause |= MLO_PAUSE_TX;
502 return 1;
503 }
504
505 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
506 struct phylink_link_state *state)
507 {
508 struct rtl838x_switch_priv *priv = ds->priv;
509 u64 speed;
510 u64 link;
511 u64 media;
512
513 if (port < 0 || port > priv->cpu_port)
514 return -EINVAL;
515
516 /*
517 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
518 * state needs to be read twice in order to read a correct result.
519 * This would not be necessary for ports connected e.g. to RTL8218D
520 * PHYs.
521 */
522 state->link = 0;
523 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
524 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
525 if (link & BIT_ULL(port))
526 state->link = 1;
527
528 if (priv->family_id == RTL9310_FAMILY_ID)
529 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
530
531 if (priv->family_id == RTL9300_FAMILY_ID)
532 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
533
534 if (media & BIT_ULL(port))
535 state->link = 1;
536
537 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
538 link & BIT_ULL(port), media);
539
540 state->duplex = 0;
541 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
542 state->duplex = 1;
543
544 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
545 speed >>= (port % 8) << 2;
546 switch (speed & 0xf) {
547 case 0:
548 state->speed = SPEED_10;
549 break;
550 case 1:
551 state->speed = SPEED_100;
552 break;
553 case 2:
554 case 7:
555 state->speed = SPEED_1000;
556 break;
557 case 4:
558 state->speed = SPEED_10000;
559 break;
560 case 5:
561 case 8:
562 state->speed = SPEED_2500;
563 break;
564 case 6:
565 state->speed = SPEED_5000;
566 break;
567 default:
568 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
569 }
570
571 if (priv->family_id == RTL9310_FAMILY_ID
572 && (port >= 52 || port <= 55)) { /* Internal serdes */
573 state->speed = SPEED_10000;
574 state->link = 1;
575 state->duplex = 1;
576 }
577
578 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
579 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
580 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
581 state->pause |= MLO_PAUSE_RX;
582 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
583 state->pause |= MLO_PAUSE_TX;
584 return 1;
585 }
586
587 static void rtl83xx_config_interface(int port, phy_interface_t interface)
588 {
589 u32 old, int_shift, sds_shift;
590
591 switch (port) {
592 case 24:
593 int_shift = 0;
594 sds_shift = 5;
595 break;
596 case 26:
597 int_shift = 3;
598 sds_shift = 0;
599 break;
600 default:
601 return;
602 }
603
604 old = sw_r32(RTL838X_SDS_MODE_SEL);
605 switch (interface) {
606 case PHY_INTERFACE_MODE_1000BASEX:
607 if ((old >> sds_shift & 0x1f) == 4)
608 return;
609 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
610 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
611 break;
612 case PHY_INTERFACE_MODE_SGMII:
613 if ((old >> sds_shift & 0x1f) == 2)
614 return;
615 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
616 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
617 break;
618 default:
619 return;
620 }
621 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
622 }
623
624 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
625 unsigned int mode,
626 const struct phylink_link_state *state)
627 {
628 struct rtl838x_switch_priv *priv = ds->priv;
629 u32 reg;
630 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
631
632 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
633
634 if (port == priv->cpu_port) {
635 /* Set Speed, duplex, flow control
636 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
637 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
638 * | MEDIA_SEL
639 */
640 if (priv->family_id == RTL8380_FAMILY_ID) {
641 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
642 /* allow CRC errors on CPU-port */
643 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
644 } else {
645 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
646 }
647 return;
648 }
649
650 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
651 /* Auto-Negotiation does not work for MAC in RTL8390 */
652 if (priv->family_id == RTL8380_FAMILY_ID) {
653 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
654 pr_debug("PHY autonegotiates\n");
655 reg |= RTL838X_NWAY_EN;
656 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
657 rtl83xx_config_interface(port, state->interface);
658 return;
659 }
660 }
661
662 if (mode != MLO_AN_FIXED)
663 pr_debug("Fixed state.\n");
664
665 /* Clear id_mode_dis bit, and the existing port mode, let
666 * RGMII_MODE_EN bet set by mac_link_{up,down} */
667 if (priv->family_id == RTL8380_FAMILY_ID) {
668 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
669 if (state->pause & MLO_PAUSE_TXRX_MASK) {
670 if (state->pause & MLO_PAUSE_TX)
671 reg |= RTL838X_TX_PAUSE_EN;
672 reg |= RTL838X_RX_PAUSE_EN;
673 }
674 } else if (priv->family_id == RTL8390_FAMILY_ID) {
675 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
676 if (state->pause & MLO_PAUSE_TXRX_MASK) {
677 if (state->pause & MLO_PAUSE_TX)
678 reg |= RTL839X_TX_PAUSE_EN;
679 reg |= RTL839X_RX_PAUSE_EN;
680 }
681 }
682
683
684 reg &= ~(3 << speed_bit);
685 switch (state->speed) {
686 case SPEED_1000:
687 reg |= 2 << speed_bit;
688 break;
689 case SPEED_100:
690 reg |= 1 << speed_bit;
691 break;
692 default:
693 break; // Ignore, including 10MBit which has a speed value of 0
694 }
695
696 if (priv->family_id == RTL8380_FAMILY_ID) {
697 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
698 if (state->link)
699 reg |= RTL838X_FORCE_LINK_EN;
700 if (state->duplex == RTL838X_DUPLEX_MODE)
701 reg |= RTL838X_DUPLEX_MODE;
702 } else if (priv->family_id == RTL8390_FAMILY_ID) {
703 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
704 if (state->link)
705 reg |= RTL839X_FORCE_LINK_EN;
706 if (state->duplex == RTL839X_DUPLEX_MODE)
707 reg |= RTL839X_DUPLEX_MODE;
708 }
709
710 // LAG members must use DUPLEX and we need to enable the link
711 if (priv->lagmembers & BIT_ULL(port)) {
712 switch(priv->family_id) {
713 case RTL8380_FAMILY_ID:
714 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
715 break;
716 case RTL8390_FAMILY_ID:
717 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
718 break;
719 }
720 }
721
722 // Disable AN
723 if (priv->family_id == RTL8380_FAMILY_ID)
724 reg &= ~RTL838X_NWAY_EN;
725 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
726 }
727
728 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
729 unsigned int mode,
730 const struct phylink_link_state *state)
731 {
732 struct rtl838x_switch_priv *priv = ds->priv;
733 int sds_num;
734 u32 reg, band;
735
736 sds_num = priv->ports[port].sds_num;
737 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
738
739 switch (state->interface) {
740 case PHY_INTERFACE_MODE_HSGMII:
741 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
742 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
743 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
744 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
745 break;
746 case PHY_INTERFACE_MODE_1000BASEX:
747 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
748 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
749 break;
750 case PHY_INTERFACE_MODE_XGMII:
751 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
752 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
753 break;
754 case PHY_INTERFACE_MODE_10GBASER:
755 case PHY_INTERFACE_MODE_10GKR:
756 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
757 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
758 break;
759 case PHY_INTERFACE_MODE_USXGMII:
760 // Translates to MII_USXGMII_10GSXGMII
761 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
762 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
763 break;
764 case PHY_INTERFACE_MODE_SGMII:
765 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
766 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
767 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
768 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
769 break;
770 case PHY_INTERFACE_MODE_QSGMII:
771 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
772 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
773 break;
774 default:
775 pr_err("%s: unknown serdes mode: %s\n",
776 __func__, phy_modes(state->interface));
777 return;
778 }
779
780 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
781 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
782
783 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
784
785 reg &= ~(0xf << 12);
786 reg |= 0x2 << 12; // Set SMI speed to 0x2
787
788 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
789
790 if (priv->lagmembers & BIT_ULL(port))
791 reg |= RTL931X_DUPLEX_MODE;
792
793 if (state->duplex == DUPLEX_FULL)
794 reg |= RTL931X_DUPLEX_MODE;
795
796 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
797
798 }
799
800 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
801 unsigned int mode,
802 const struct phylink_link_state *state)
803 {
804 struct rtl838x_switch_priv *priv = ds->priv;
805 int sds_num, sds_mode;
806 u32 reg;
807
808 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
809 port, mode, phy_modes(state->interface), state->speed, state->link);
810
811 // Nothing to be done for the CPU-port
812 if (port == priv->cpu_port)
813 return;
814
815 if (priv->family_id == RTL9310_FAMILY_ID)
816 return rtl931x_phylink_mac_config(ds, port, mode, state);
817
818 sds_num = priv->ports[port].sds_num;
819 pr_info("%s SDS is %d\n", __func__, sds_num);
820 if (sds_num >= 0) {
821 switch (state->interface) {
822 case PHY_INTERFACE_MODE_HSGMII:
823 sds_mode = 0x12;
824 break;
825 case PHY_INTERFACE_MODE_1000BASEX:
826 sds_mode = 0x04;
827 break;
828 case PHY_INTERFACE_MODE_XGMII:
829 sds_mode = 0x10;
830 break;
831 case PHY_INTERFACE_MODE_10GBASER:
832 case PHY_INTERFACE_MODE_10GKR:
833 sds_mode = 0x1b; // 10G 1000X Auto
834 break;
835 case PHY_INTERFACE_MODE_USXGMII:
836 sds_mode = 0x0d;
837 break;
838 default:
839 pr_err("%s: unknown serdes mode: %s\n",
840 __func__, phy_modes(state->interface));
841 return;
842 }
843 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
844 rtl9300_serdes_setup(sds_num, state->interface);
845 }
846
847 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
848 reg &= ~(0xf << 3);
849
850 switch (state->speed) {
851 case SPEED_10000:
852 reg |= 4 << 3;
853 break;
854 case SPEED_5000:
855 reg |= 6 << 3;
856 break;
857 case SPEED_2500:
858 reg |= 5 << 3;
859 break;
860 case SPEED_1000:
861 reg |= 2 << 3;
862 break;
863 default:
864 reg |= 2 << 3;
865 break;
866 }
867
868 if (state->link)
869 reg |= RTL930X_FORCE_LINK_EN;
870
871 if (priv->lagmembers & BIT_ULL(port))
872 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
873
874 if (state->duplex == DUPLEX_FULL)
875 reg |= RTL930X_DUPLEX_MODE;
876
877 if (priv->ports[port].phy_is_integrated)
878 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
879 else
880 reg |= RTL930X_FORCE_EN;
881
882 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
883 }
884
885 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
886 unsigned int mode,
887 phy_interface_t interface)
888 {
889 struct rtl838x_switch_priv *priv = ds->priv;
890
891 /* Stop TX/RX to port */
892 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
893
894 // No longer force link
895 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
896 }
897
898 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
899 unsigned int mode,
900 phy_interface_t interface)
901 {
902 struct rtl838x_switch_priv *priv = ds->priv;
903 u32 v = 0;
904
905 /* Stop TX/RX to port */
906 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
907
908 // No longer force link
909 if (priv->family_id == RTL9300_FAMILY_ID)
910 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
911 else if (priv->family_id == RTL9310_FAMILY_ID)
912 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
913 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
914 }
915
916 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
917 unsigned int mode,
918 phy_interface_t interface,
919 struct phy_device *phydev,
920 int speed, int duplex,
921 bool tx_pause, bool rx_pause)
922 {
923 struct rtl838x_switch_priv *priv = ds->priv;
924 /* Restart TX/RX to port */
925 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
926 // TODO: Set speed/duplex/pauses
927 }
928
929 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
930 unsigned int mode,
931 phy_interface_t interface,
932 struct phy_device *phydev,
933 int speed, int duplex,
934 bool tx_pause, bool rx_pause)
935 {
936 struct rtl838x_switch_priv *priv = ds->priv;
937
938 /* Restart TX/RX to port */
939 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
940 // TODO: Set speed/duplex/pauses
941 }
942
943 static void rtl83xx_get_strings(struct dsa_switch *ds,
944 int port, u32 stringset, u8 *data)
945 {
946 int i;
947
948 if (stringset != ETH_SS_STATS)
949 return;
950
951 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
952 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
953 ETH_GSTRING_LEN);
954 }
955
956 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
957 uint64_t *data)
958 {
959 struct rtl838x_switch_priv *priv = ds->priv;
960 const struct rtl83xx_mib_desc *mib;
961 int i;
962 u64 h;
963
964 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
965 mib = &rtl83xx_mib[i];
966
967 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
968 if (mib->size == 2) {
969 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
970 data[i] |= h << 32;
971 }
972 }
973 }
974
975 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
976 {
977 if (sset != ETH_SS_STATS)
978 return 0;
979
980 return ARRAY_SIZE(rtl83xx_mib);
981 }
982
983 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
984 {
985 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
986 u64 portmask;
987
988 if (mc_group >= MAX_MC_GROUPS - 1)
989 return -1;
990
991 if (priv->is_lagmember[port]) {
992 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
993 return 0;
994 }
995
996 set_bit(mc_group, priv->mc_group_bm);
997 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
998 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
999 priv->r->write_mcast_pmask(mc_group, portmask);
1000
1001 return mc_group;
1002 }
1003
1004 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1005 {
1006 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1007
1008 pr_debug("%s: %d\n", __func__, port);
1009 if (priv->is_lagmember[port]) {
1010 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1011 return portmask;
1012 }
1013 portmask |= BIT_ULL(port);
1014 priv->r->write_mcast_pmask(mc_group, portmask);
1015
1016 return portmask;
1017 }
1018
1019 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1020 {
1021 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1022
1023 pr_debug("%s: %d\n", __func__, port);
1024 if (priv->is_lagmember[port]) {
1025 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1026 return portmask;
1027 }
1028 priv->r->write_mcast_pmask(mc_group, portmask);
1029 if (portmask == BIT_ULL(priv->cpu_port)) {
1030 portmask &= ~BIT_ULL(priv->cpu_port);
1031 priv->r->write_mcast_pmask(mc_group, portmask);
1032 clear_bit(mc_group, priv->mc_group_bm);
1033 }
1034
1035 return portmask;
1036 }
1037
1038 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1039 {
1040 int mc_group;
1041
1042 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1043 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1044 if (portmask & BIT_ULL(port)) {
1045 priv->mc_group_saves[mc_group] = port;
1046 rtl83xx_mc_group_del_port(priv, mc_group, port);
1047 }
1048 }
1049 }
1050
1051 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1052 {
1053 int mc_group;
1054
1055 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1056 if (priv->mc_group_saves[mc_group] == port) {
1057 rtl83xx_mc_group_add_port(priv, mc_group, port);
1058 priv->mc_group_saves[mc_group] = -1;
1059 }
1060 }
1061 }
1062
1063 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1064 struct phy_device *phydev)
1065 {
1066 struct rtl838x_switch_priv *priv = ds->priv;
1067 u64 v;
1068
1069 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1070 priv->ports[port].enable = true;
1071
1072 /* enable inner tagging on egress, do not keep any tags */
1073 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1074
1075 if (dsa_is_cpu_port(ds, port))
1076 return 0;
1077
1078 /* add port to switch mask of CPU_PORT */
1079 priv->r->traffic_enable(priv->cpu_port, port);
1080
1081 load_mcgroups(priv, port);
1082
1083 if (priv->is_lagmember[port]) {
1084 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1085 return 0;
1086 }
1087
1088 /* add all other ports in the same bridge to switch mask of port */
1089 v = priv->r->traffic_get(port);
1090 v |= priv->ports[port].pm;
1091 priv->r->traffic_set(port, v);
1092
1093 // TODO: Figure out if this is necessary
1094 if (priv->family_id == RTL9300_FAMILY_ID) {
1095 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1096 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1097 }
1098
1099 if (priv->ports[port].sds_num < 0)
1100 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1101
1102 return 0;
1103 }
1104
1105 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1106 {
1107 struct rtl838x_switch_priv *priv = ds->priv;
1108 u64 v;
1109
1110 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1111 /* you can only disable user ports */
1112 if (!dsa_is_user_port(ds, port))
1113 return;
1114
1115 // BUG: This does not work on RTL931X
1116 /* remove port from switch mask of CPU_PORT */
1117 priv->r->traffic_disable(priv->cpu_port, port);
1118 store_mcgroups(priv, port);
1119
1120 /* remove all other ports in the same bridge from switch mask of port */
1121 v = priv->r->traffic_get(port);
1122 v &= ~priv->ports[port].pm;
1123 priv->r->traffic_set(port, v);
1124
1125 priv->ports[port].enable = false;
1126 }
1127
1128 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1129 struct ethtool_eee *e)
1130 {
1131 struct rtl838x_switch_priv *priv = ds->priv;
1132
1133 if (e->eee_enabled && !priv->eee_enabled) {
1134 pr_info("Globally enabling EEE\n");
1135 priv->r->init_eee(priv, true);
1136 }
1137
1138 priv->r->port_eee_set(priv, port, e->eee_enabled);
1139
1140 if (e->eee_enabled)
1141 pr_info("Enabled EEE for port %d\n", port);
1142 else
1143 pr_info("Disabled EEE for port %d\n", port);
1144 return 0;
1145 }
1146
1147 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1148 struct ethtool_eee *e)
1149 {
1150 struct rtl838x_switch_priv *priv = ds->priv;
1151
1152 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1153
1154 priv->r->eee_port_ability(priv, e, port);
1155
1156 e->eee_enabled = priv->ports[port].eee_enabled;
1157
1158 e->eee_active = !!(e->advertised & e->lp_advertised);
1159
1160 return 0;
1161 }
1162
1163 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1164 struct ethtool_eee *e)
1165 {
1166 struct rtl838x_switch_priv *priv = ds->priv;
1167
1168 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1169 | SUPPORTED_2500baseX_Full;
1170
1171 priv->r->eee_port_ability(priv, e, port);
1172
1173 e->eee_enabled = priv->ports[port].eee_enabled;
1174
1175 e->eee_active = !!(e->advertised & e->lp_advertised);
1176
1177 return 0;
1178 }
1179
1180 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1181 {
1182 struct rtl838x_switch_priv *priv = ds->priv;
1183
1184 priv->r->set_ageing_time(msec);
1185 return 0;
1186 }
1187
1188 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1189 struct net_device *bridge)
1190 {
1191 struct rtl838x_switch_priv *priv = ds->priv;
1192 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1193 int i;
1194
1195 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1196
1197 if (priv->is_lagmember[port]) {
1198 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1199 return 0;
1200 }
1201
1202 mutex_lock(&priv->reg_mutex);
1203 for (i = 0; i < ds->num_ports; i++) {
1204 /* Add this port to the port matrix of the other ports in the
1205 * same bridge. If the port is disabled, port matrix is kept
1206 * and not being setup until the port becomes enabled.
1207 */
1208 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1209 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1210 continue;
1211 if (priv->ports[i].enable)
1212 priv->r->traffic_enable(i, port);
1213
1214 priv->ports[i].pm |= BIT_ULL(port);
1215 port_bitmap |= BIT_ULL(i);
1216 }
1217 }
1218 load_mcgroups(priv, port);
1219
1220 /* Add all other ports to this port matrix. */
1221 if (priv->ports[port].enable) {
1222 priv->r->traffic_enable(priv->cpu_port, port);
1223 v = priv->r->traffic_get(port);
1224 v |= port_bitmap;
1225 priv->r->traffic_set(port, v);
1226 }
1227 priv->ports[port].pm |= port_bitmap;
1228
1229 if (priv->r->set_static_move_action)
1230 priv->r->set_static_move_action(port, false);
1231
1232 mutex_unlock(&priv->reg_mutex);
1233
1234 return 0;
1235 }
1236
1237 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1238 struct net_device *bridge)
1239 {
1240 struct rtl838x_switch_priv *priv = ds->priv;
1241 u64 port_bitmap = 0, v;
1242 int i;
1243
1244 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1245 mutex_lock(&priv->reg_mutex);
1246 for (i = 0; i < ds->num_ports; i++) {
1247 /* Remove this port from the port matrix of the other ports
1248 * in the same bridge. If the port is disabled, port matrix
1249 * is kept and not being setup until the port becomes enabled.
1250 * And the other port's port matrix cannot be broken when the
1251 * other port is still a VLAN-aware port.
1252 */
1253 if (dsa_is_user_port(ds, i) && i != port) {
1254 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1255 continue;
1256 if (priv->ports[i].enable)
1257 priv->r->traffic_disable(i, port);
1258
1259 priv->ports[i].pm &= ~BIT_ULL(port);
1260 port_bitmap |= BIT_ULL(i);
1261 }
1262 }
1263 store_mcgroups(priv, port);
1264
1265 /* Remove all other ports from this port matrix. */
1266 if (priv->ports[port].enable) {
1267 v = priv->r->traffic_get(port);
1268 v &= ~port_bitmap;
1269 priv->r->traffic_set(port, v);
1270 }
1271 priv->ports[port].pm &= ~port_bitmap;
1272
1273 if (priv->r->set_static_move_action)
1274 priv->r->set_static_move_action(port, true);
1275
1276 mutex_unlock(&priv->reg_mutex);
1277 }
1278
1279 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1280 {
1281 u32 msti = 0;
1282 u32 port_state[4];
1283 int index, bit;
1284 int pos = port;
1285 struct rtl838x_switch_priv *priv = ds->priv;
1286 int n = priv->port_width << 1;
1287
1288 /* Ports above or equal CPU port can never be configured */
1289 if (port >= priv->cpu_port)
1290 return;
1291
1292 mutex_lock(&priv->reg_mutex);
1293
1294 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1295 * have 64 bit fields, 839x and 931x have 128 bit fields
1296 */
1297 if (priv->family_id == RTL8390_FAMILY_ID)
1298 pos += 12;
1299 if (priv->family_id == RTL9300_FAMILY_ID)
1300 pos += 3;
1301 if (priv->family_id == RTL9310_FAMILY_ID)
1302 pos += 8;
1303
1304 index = n - (pos >> 4) - 1;
1305 bit = (pos << 1) % 32;
1306
1307 priv->r->stp_get(priv, msti, port_state);
1308
1309 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1310 port_state[index] &= ~(3 << bit);
1311
1312 switch (state) {
1313 case BR_STATE_DISABLED: /* 0 */
1314 port_state[index] |= (0 << bit);
1315 break;
1316 case BR_STATE_BLOCKING: /* 4 */
1317 case BR_STATE_LISTENING: /* 1 */
1318 port_state[index] |= (1 << bit);
1319 break;
1320 case BR_STATE_LEARNING: /* 2 */
1321 port_state[index] |= (2 << bit);
1322 break;
1323 case BR_STATE_FORWARDING: /* 3*/
1324 port_state[index] |= (3 << bit);
1325 default:
1326 break;
1327 }
1328
1329 priv->r->stp_set(priv, msti, port_state);
1330
1331 mutex_unlock(&priv->reg_mutex);
1332 }
1333
1334 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1335 {
1336 struct rtl838x_switch_priv *priv = ds->priv;
1337 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1338
1339 pr_debug("FAST AGE port %d\n", port);
1340 mutex_lock(&priv->reg_mutex);
1341 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1342 * port fields:
1343 * 0-4: Replacing port
1344 * 5-9: Flushed/replaced port
1345 * 10-21: FVID
1346 * 22: Entry types: 1: dynamic, 0: also static
1347 * 23: Match flush port
1348 * 24: Match FVID
1349 * 25: Flush (0) or replace (1) L2 entries
1350 * 26: Status of action (1: Start, 0: Done)
1351 */
1352 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1353
1354 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1355
1356 mutex_unlock(&priv->reg_mutex);
1357 }
1358
1359 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1360 {
1361 struct rtl838x_switch_priv *priv = ds->priv;
1362
1363 pr_info("%s port %d\n", __func__, port);
1364 mutex_lock(&priv->reg_mutex);
1365 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1366
1367 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1368
1369 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1370
1371 mutex_unlock(&priv->reg_mutex);
1372 }
1373
1374 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1375 {
1376 struct rtl838x_switch_priv *priv = ds->priv;
1377
1378 if (priv->family_id == RTL9310_FAMILY_ID)
1379 return rtl931x_fast_age(ds, port);
1380
1381 pr_debug("FAST AGE port %d\n", port);
1382 mutex_lock(&priv->reg_mutex);
1383 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1384
1385 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1386
1387 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1388
1389 mutex_unlock(&priv->reg_mutex);
1390 }
1391
1392 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1393 bool vlan_filtering,
1394 struct switchdev_trans *trans)
1395 {
1396 struct rtl838x_switch_priv *priv = ds->priv;
1397
1398 pr_debug("%s: port %d\n", __func__, port);
1399 mutex_lock(&priv->reg_mutex);
1400
1401 if (vlan_filtering) {
1402 /* Enable ingress and egress filtering
1403 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1404 * the filter action:
1405 * 0: Always Forward
1406 * 1: Drop packet
1407 * 2: Trap packet to CPU port
1408 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1409 */
1410 if (port != priv->cpu_port)
1411 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1412
1413 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1414 } else {
1415 /* Disable ingress and egress filtering */
1416 if (port != priv->cpu_port)
1417 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1418
1419 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1420 }
1421
1422 /* Do we need to do something to the CPU-Port, too? */
1423 mutex_unlock(&priv->reg_mutex);
1424
1425 return 0;
1426 }
1427
1428 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1429 const struct switchdev_obj_port_vlan *vlan)
1430 {
1431 struct rtl838x_vlan_info info;
1432 struct rtl838x_switch_priv *priv = ds->priv;
1433
1434 priv->r->vlan_tables_read(0, &info);
1435
1436 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1437 info.tagged_ports, info.untagged_ports, info.profile_id,
1438 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1439
1440 priv->r->vlan_tables_read(1, &info);
1441 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1442 info.tagged_ports, info.untagged_ports, info.profile_id,
1443 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1444 priv->r->vlan_set_untagged(1, info.untagged_ports);
1445 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1446
1447 priv->r->vlan_set_tagged(1, &info);
1448 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1449
1450 return 0;
1451 }
1452
1453 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1454 int port, int pvid)
1455 {
1456 /* Set both inner and outer PVID of the port */
1457 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1458 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1459 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1460 PBVLAN_MODE_UNTAG_AND_PRITAG);
1461 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1462 PBVLAN_MODE_UNTAG_AND_PRITAG);
1463
1464 priv->ports[port].pvid = pvid;
1465 }
1466
1467 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1468 const struct switchdev_obj_port_vlan *vlan)
1469 {
1470 struct rtl838x_vlan_info info;
1471 struct rtl838x_switch_priv *priv = ds->priv;
1472 int v;
1473
1474 pr_debug("%s port %d, vid_begin %d, vid_end %d, flags %x\n", __func__,
1475 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1476
1477 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1478 dev_err(priv->dev, "VLAN out of range: %d - %d",
1479 vlan->vid_begin, vlan->vid_end);
1480 return;
1481 }
1482
1483 mutex_lock(&priv->reg_mutex);
1484
1485 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1486 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1487 rtl83xx_vlan_set_pvid(priv, port, v);
1488 else if (priv->ports[port].pvid == v)
1489 rtl83xx_vlan_set_pvid(priv, port, 0);
1490 }
1491
1492 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1493 /* Get port memberships of this vlan */
1494 priv->r->vlan_tables_read(v, &info);
1495
1496 /* new VLAN? */
1497 if (!info.tagged_ports) {
1498 info.fid = 0;
1499 info.hash_mc_fid = false;
1500 info.hash_uc_fid = false;
1501 info.profile_id = 0;
1502 }
1503
1504 /* sanitize untagged_ports - must be a subset */
1505 if (info.untagged_ports & ~info.tagged_ports)
1506 info.untagged_ports = 0;
1507
1508 info.tagged_ports |= BIT_ULL(port);
1509 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1510 info.untagged_ports |= BIT_ULL(port);
1511 else
1512 info.untagged_ports &= ~BIT_ULL(port);
1513
1514 priv->r->vlan_set_untagged(v, info.untagged_ports);
1515 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1516
1517 priv->r->vlan_set_tagged(v, &info);
1518 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1519 }
1520
1521 mutex_unlock(&priv->reg_mutex);
1522 }
1523
1524 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1525 const struct switchdev_obj_port_vlan *vlan)
1526 {
1527 struct rtl838x_vlan_info info;
1528 struct rtl838x_switch_priv *priv = ds->priv;
1529 int v;
1530 u16 pvid;
1531
1532 pr_debug("%s: port %d, vid_begin %d, vid_end %d, flags %x\n", __func__,
1533 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1534
1535 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1536 dev_err(priv->dev, "VLAN out of range: %d - %d",
1537 vlan->vid_begin, vlan->vid_end);
1538 return -ENOTSUPP;
1539 }
1540
1541 mutex_lock(&priv->reg_mutex);
1542 pvid = priv->ports[port].pvid;
1543
1544 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1545 /* Reset to default if removing the current PVID */
1546 if (v == pvid) {
1547 rtl83xx_vlan_set_pvid(priv, port, 0);
1548 }
1549 /* Get port memberships of this vlan */
1550 priv->r->vlan_tables_read(v, &info);
1551
1552 /* remove port from both tables */
1553 info.untagged_ports &= (~BIT_ULL(port));
1554 info.tagged_ports &= (~BIT_ULL(port));
1555
1556 priv->r->vlan_set_untagged(v, info.untagged_ports);
1557 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1558
1559 priv->r->vlan_set_tagged(v, &info);
1560 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1561 }
1562 mutex_unlock(&priv->reg_mutex);
1563
1564 return 0;
1565 }
1566
1567 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1568 {
1569 memset(e, 0, sizeof(*e));
1570
1571 e->type = L2_UNICAST;
1572 e->valid = true;
1573
1574 e->age = 3;
1575 e->is_static = true;
1576
1577 e->port = port;
1578
1579 e->rvid = e->vid = vid;
1580 e->is_ip_mc = e->is_ipv6_mc = false;
1581 u64_to_ether_addr(mac, e->mac);
1582 }
1583
1584 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1585 {
1586 memset(e, 0, sizeof(*e));
1587
1588 e->type = L2_MULTICAST;
1589 e->valid = true;
1590
1591 e->mc_portmask_index = mc_group;
1592
1593 e->rvid = e->vid = vid;
1594 e->is_ip_mc = e->is_ipv6_mc = false;
1595 u64_to_ether_addr(mac, e->mac);
1596 }
1597
1598 /*
1599 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1600 * over the entries in the bucket until either a matching entry is found or an empty slot
1601 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1602 * when an empty slot was found and must exist is false, the index of the slot is returned
1603 * when no slots are available returns -1
1604 */
1605 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1606 bool must_exist, struct rtl838x_l2_entry *e)
1607 {
1608 int i, idx = -1;
1609 u32 key = priv->r->l2_hash_key(priv, seed);
1610 u64 entry;
1611
1612 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1613 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1614 for (i = 0; i < priv->l2_bucket_size; i++) {
1615 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1616 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1617 if (must_exist && !e->valid)
1618 continue;
1619 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1620 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1621 break;
1622 }
1623 }
1624
1625 return idx;
1626 }
1627
1628 /*
1629 * Uses the seed to identify an entry in the CAM by looping over all its entries
1630 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1631 * when an empty slot was found the index of the slot is returned
1632 * when no slots are available returns -1
1633 */
1634 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1635 bool must_exist, struct rtl838x_l2_entry *e)
1636 {
1637 int i, idx = -1;
1638 u64 entry;
1639
1640 for (i = 0; i < 64; i++) {
1641 entry = priv->r->read_cam(i, e);
1642 if (!must_exist && !e->valid) {
1643 if (idx < 0) /* First empty entry? */
1644 idx = i;
1645 break;
1646 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1647 pr_debug("Found entry in CAM\n");
1648 idx = i;
1649 break;
1650 }
1651 }
1652 return idx;
1653 }
1654
1655 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1656 const unsigned char *addr, u16 vid)
1657 {
1658 struct rtl838x_switch_priv *priv = ds->priv;
1659 u64 mac = ether_addr_to_u64(addr);
1660 struct rtl838x_l2_entry e;
1661 int err = 0, idx;
1662 u64 seed = priv->r->l2_hash_seed(mac, vid);
1663
1664 if (priv->is_lagmember[port]) {
1665 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1666 return 0;
1667 }
1668
1669 mutex_lock(&priv->reg_mutex);
1670
1671 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1672
1673 // Found an existing or empty entry
1674 if (idx >= 0) {
1675 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1676 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1677 goto out;
1678 }
1679
1680 // Hash buckets full, try CAM
1681 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1682
1683 if (idx >= 0) {
1684 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1685 priv->r->write_cam(idx, &e);
1686 goto out;
1687 }
1688
1689 err = -ENOTSUPP;
1690 out:
1691 mutex_unlock(&priv->reg_mutex);
1692 return err;
1693 }
1694
1695 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1696 const unsigned char *addr, u16 vid)
1697 {
1698 struct rtl838x_switch_priv *priv = ds->priv;
1699 u64 mac = ether_addr_to_u64(addr);
1700 struct rtl838x_l2_entry e;
1701 int err = 0, idx;
1702 u64 seed = priv->r->l2_hash_seed(mac, vid);
1703
1704 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1705 mutex_lock(&priv->reg_mutex);
1706
1707 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1708
1709 if (idx >= 0) {
1710 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1711 e.valid = false;
1712 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1713 goto out;
1714 }
1715
1716 /* Check CAM for spillover from hash buckets */
1717 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1718
1719 if (idx >= 0) {
1720 e.valid = false;
1721 priv->r->write_cam(idx, &e);
1722 goto out;
1723 }
1724 err = -ENOENT;
1725 out:
1726 mutex_unlock(&priv->reg_mutex);
1727 return err;
1728 }
1729
1730 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1731 dsa_fdb_dump_cb_t *cb, void *data)
1732 {
1733 struct rtl838x_l2_entry e;
1734 struct rtl838x_switch_priv *priv = ds->priv;
1735 int i;
1736
1737 mutex_lock(&priv->reg_mutex);
1738
1739 for (i = 0; i < priv->fib_entries; i++) {
1740 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1741
1742 if (!e.valid)
1743 continue;
1744
1745 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1746 cb(e.mac, e.vid, e.is_static, data);
1747
1748 if (!((i + 1) % 64))
1749 cond_resched();
1750 }
1751
1752 for (i = 0; i < 64; i++) {
1753 priv->r->read_cam(i, &e);
1754
1755 if (!e.valid)
1756 continue;
1757
1758 if (e.port == port)
1759 cb(e.mac, e.vid, e.is_static, data);
1760 }
1761
1762 mutex_unlock(&priv->reg_mutex);
1763 return 0;
1764 }
1765
1766 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1767 const struct switchdev_obj_port_mdb *mdb)
1768 {
1769 struct rtl838x_switch_priv *priv = ds->priv;
1770
1771 if (priv->id >= 0x9300)
1772 return -EOPNOTSUPP;
1773
1774 return 0;
1775 }
1776
1777 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1778 const struct switchdev_obj_port_mdb *mdb)
1779 {
1780 struct rtl838x_switch_priv *priv = ds->priv;
1781 u64 mac = ether_addr_to_u64(mdb->addr);
1782 struct rtl838x_l2_entry e;
1783 int err = 0, idx;
1784 int vid = mdb->vid;
1785 u64 seed = priv->r->l2_hash_seed(mac, vid);
1786 int mc_group;
1787
1788 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1789
1790 if (priv->is_lagmember[port]) {
1791 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1792 return;
1793 }
1794
1795 mutex_lock(&priv->reg_mutex);
1796
1797 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1798
1799 // Found an existing or empty entry
1800 if (idx >= 0) {
1801 if (e.valid) {
1802 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1803 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1804 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1805 } else {
1806 pr_debug("New entry for seed %016llx\n", seed);
1807 mc_group = rtl83xx_mc_group_alloc(priv, port);
1808 if (mc_group < 0) {
1809 err = -ENOTSUPP;
1810 goto out;
1811 }
1812 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1813 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1814 }
1815 goto out;
1816 }
1817
1818 // Hash buckets full, try CAM
1819 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1820
1821 if (idx >= 0) {
1822 if (e.valid) {
1823 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1824 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1825 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1826 } else {
1827 pr_debug("New entry\n");
1828 mc_group = rtl83xx_mc_group_alloc(priv, port);
1829 if (mc_group < 0) {
1830 err = -ENOTSUPP;
1831 goto out;
1832 }
1833 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1834 priv->r->write_cam(idx, &e);
1835 }
1836 goto out;
1837 }
1838
1839 err = -ENOTSUPP;
1840 out:
1841 mutex_unlock(&priv->reg_mutex);
1842 if (err)
1843 dev_err(ds->dev, "failed to add MDB entry\n");
1844 }
1845
1846 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1847 const struct switchdev_obj_port_mdb *mdb)
1848 {
1849 struct rtl838x_switch_priv *priv = ds->priv;
1850 u64 mac = ether_addr_to_u64(mdb->addr);
1851 struct rtl838x_l2_entry e;
1852 int err = 0, idx;
1853 int vid = mdb->vid;
1854 u64 seed = priv->r->l2_hash_seed(mac, vid);
1855 u64 portmask;
1856
1857 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1858
1859 if (priv->is_lagmember[port]) {
1860 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1861 return 0;
1862 }
1863
1864 mutex_lock(&priv->reg_mutex);
1865
1866 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1867
1868 if (idx >= 0) {
1869 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1870 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1871 if (!portmask) {
1872 e.valid = false;
1873 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1874 }
1875 goto out;
1876 }
1877
1878 /* Check CAM for spillover from hash buckets */
1879 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1880
1881 if (idx >= 0) {
1882 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1883 if (!portmask) {
1884 e.valid = false;
1885 priv->r->write_cam(idx, &e);
1886 }
1887 goto out;
1888 }
1889 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1890 out:
1891 mutex_unlock(&priv->reg_mutex);
1892 return err;
1893 }
1894
1895 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1896 struct dsa_mall_mirror_tc_entry *mirror,
1897 bool ingress)
1898 {
1899 /* We support 4 mirror groups, one destination port per group */
1900 int group;
1901 struct rtl838x_switch_priv *priv = ds->priv;
1902 int ctrl_reg, dpm_reg, spm_reg;
1903
1904 pr_debug("In %s\n", __func__);
1905
1906 for (group = 0; group < 4; group++) {
1907 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1908 break;
1909 }
1910 if (group >= 4) {
1911 for (group = 0; group < 4; group++) {
1912 if (priv->mirror_group_ports[group] < 0)
1913 break;
1914 }
1915 }
1916
1917 if (group >= 4)
1918 return -ENOSPC;
1919
1920 ctrl_reg = priv->r->mir_ctrl + group * 4;
1921 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1922 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1923
1924 pr_debug("Using group %d\n", group);
1925 mutex_lock(&priv->reg_mutex);
1926
1927 if (priv->family_id == RTL8380_FAMILY_ID) {
1928 /* Enable mirroring to port across VLANs (bit 11) */
1929 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1930 } else {
1931 /* Enable mirroring to destination port */
1932 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1933 }
1934
1935 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1936 mutex_unlock(&priv->reg_mutex);
1937 return -EEXIST;
1938 }
1939 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1940 mutex_unlock(&priv->reg_mutex);
1941 return -EEXIST;
1942 }
1943
1944 if (ingress)
1945 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1946 else
1947 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1948
1949 priv->mirror_group_ports[group] = mirror->to_local_port;
1950 mutex_unlock(&priv->reg_mutex);
1951 return 0;
1952 }
1953
1954 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1955 struct dsa_mall_mirror_tc_entry *mirror)
1956 {
1957 int group = 0;
1958 struct rtl838x_switch_priv *priv = ds->priv;
1959 int ctrl_reg, dpm_reg, spm_reg;
1960
1961 pr_debug("In %s\n", __func__);
1962 for (group = 0; group < 4; group++) {
1963 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1964 break;
1965 }
1966 if (group >= 4)
1967 return;
1968
1969 ctrl_reg = priv->r->mir_ctrl + group * 4;
1970 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1971 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1972
1973 mutex_lock(&priv->reg_mutex);
1974 if (mirror->ingress) {
1975 /* Ingress, clear source port matrix */
1976 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1977 } else {
1978 /* Egress, clear destination port matrix */
1979 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1980 }
1981
1982 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1983 priv->mirror_group_ports[group] = -1;
1984 sw_w32(0, ctrl_reg);
1985 }
1986
1987 mutex_unlock(&priv->reg_mutex);
1988 }
1989
1990 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1991 {
1992 struct rtl838x_switch_priv *priv = ds->priv;
1993 unsigned long features = 0;
1994 pr_debug("%s: %d %lX\n", __func__, port, flags);
1995 if (priv->r->enable_learning)
1996 features |= BR_LEARNING;
1997 if (priv->r->enable_flood)
1998 features |= BR_FLOOD;
1999 if (priv->r->enable_mcast_flood)
2000 features |= BR_MCAST_FLOOD;
2001 if (priv->r->enable_bcast_flood)
2002 features |= BR_BCAST_FLOOD;
2003 if (flags & ~(features))
2004 return -EINVAL;
2005
2006 return 0;
2007 }
2008
2009 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
2010 {
2011 struct rtl838x_switch_priv *priv = ds->priv;
2012
2013 pr_debug("%s: %d %lX\n", __func__, port, flags);
2014 if (priv->r->enable_learning)
2015 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
2016
2017 if (priv->r->enable_flood)
2018 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
2019
2020 if (priv->r->enable_mcast_flood)
2021 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
2022
2023 if (priv->r->enable_bcast_flood)
2024 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
2025
2026 return 0;
2027 }
2028
2029 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2030 struct net_device *lag,
2031 struct netdev_lag_upper_info *info)
2032 {
2033 int id;
2034
2035 id = dsa_lag_id(ds->dst, lag);
2036 if (id < 0 || id >= ds->num_lag_ids)
2037 return false;
2038
2039 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2040 return false;
2041 }
2042 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2043 return false;
2044
2045 return true;
2046 }
2047
2048 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2049 {
2050 struct rtl838x_switch_priv *priv = ds->priv;
2051
2052 pr_debug("%s: %d\n", __func__, port);
2053 // Nothing to be done...
2054
2055 return 0;
2056 }
2057
2058 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2059 struct net_device *lag,
2060 struct netdev_lag_upper_info *info)
2061 {
2062 struct rtl838x_switch_priv *priv = ds->priv;
2063 int i, err = 0;
2064
2065 if (!rtl83xx_lag_can_offload(ds, lag, info))
2066 return -EOPNOTSUPP;
2067
2068 mutex_lock(&priv->reg_mutex);
2069
2070 for (i = 0; i < priv->n_lags; i++) {
2071 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2072 break;
2073 }
2074 if (port >= priv->cpu_port) {
2075 err = -EINVAL;
2076 goto out;
2077 }
2078 pr_info("port_lag_join: group %d, port %d\n",i, port);
2079 if (!priv->lag_devs[i])
2080 priv->lag_devs[i] = lag;
2081
2082 if (priv->lag_primary[i]==-1) {
2083 priv->lag_primary[i]=port;
2084 } else
2085 priv->is_lagmember[port] = 1;
2086
2087 priv->lagmembers |= (1ULL << port);
2088
2089 pr_debug("lag_members = %llX\n", priv->lagmembers);
2090 err = rtl83xx_lag_add(priv->ds, i, port, info);
2091 if (err) {
2092 err = -EINVAL;
2093 goto out;
2094 }
2095
2096 out:
2097 mutex_unlock(&priv->reg_mutex);
2098 return err;
2099
2100 }
2101
2102 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2103 struct net_device *lag)
2104 {
2105 int i, group = -1, err;
2106 struct rtl838x_switch_priv *priv = ds->priv;
2107
2108 mutex_lock(&priv->reg_mutex);
2109 for (i=0;i<priv->n_lags;i++) {
2110 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2111 group = i;
2112 break;
2113 }
2114 }
2115
2116 if (group == -1) {
2117 pr_info("port_lag_leave: port %d is not a member\n", port);
2118 err = -EINVAL;
2119 goto out;
2120 }
2121
2122 if (port >= priv->cpu_port) {
2123 err = -EINVAL;
2124 goto out;
2125 }
2126 pr_info("port_lag_del: group %d, port %d\n",group, port);
2127 priv->lagmembers &=~ (1ULL << port);
2128 priv->lag_primary[i] = -1;
2129 priv->is_lagmember[port] = 0;
2130 pr_debug("lag_members = %llX\n", priv->lagmembers);
2131 err = rtl83xx_lag_del(priv->ds, group, port);
2132 if (err) {
2133 err = -EINVAL;
2134 goto out;
2135 }
2136 if (!priv->lags_port_members[i])
2137 priv->lag_devs[i] = NULL;
2138
2139 out:
2140 mutex_unlock(&priv->reg_mutex);
2141 return 0;
2142 }
2143
2144 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2145 {
2146 u32 val;
2147 u32 offset = 0;
2148 struct rtl838x_switch_priv *priv = ds->priv;
2149
2150 if (phy_addr >= 24 && phy_addr <= 27
2151 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2152 if (phy_addr == 26)
2153 offset = 0x100;
2154 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2155 return val;
2156 }
2157
2158 read_phy(phy_addr, 0, phy_reg, &val);
2159 return val;
2160 }
2161
2162 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2163 {
2164 u32 offset = 0;
2165 struct rtl838x_switch_priv *priv = ds->priv;
2166
2167 if (phy_addr >= 24 && phy_addr <= 27
2168 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2169 if (phy_addr == 26)
2170 offset = 0x100;
2171 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2172 return 0;
2173 }
2174 return write_phy(phy_addr, 0, phy_reg, val);
2175 }
2176
2177 const struct dsa_switch_ops rtl83xx_switch_ops = {
2178 .get_tag_protocol = rtl83xx_get_tag_protocol,
2179 .setup = rtl83xx_setup,
2180
2181 .phy_read = dsa_phy_read,
2182 .phy_write = dsa_phy_write,
2183
2184 .phylink_validate = rtl83xx_phylink_validate,
2185 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2186 .phylink_mac_config = rtl83xx_phylink_mac_config,
2187 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2188 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2189
2190 .get_strings = rtl83xx_get_strings,
2191 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2192 .get_sset_count = rtl83xx_get_sset_count,
2193
2194 .port_enable = rtl83xx_port_enable,
2195 .port_disable = rtl83xx_port_disable,
2196
2197 .get_mac_eee = rtl83xx_get_mac_eee,
2198 .set_mac_eee = rtl83xx_set_mac_eee,
2199
2200 .set_ageing_time = rtl83xx_set_ageing_time,
2201 .port_bridge_join = rtl83xx_port_bridge_join,
2202 .port_bridge_leave = rtl83xx_port_bridge_leave,
2203 .port_stp_state_set = rtl83xx_port_stp_state_set,
2204 .port_fast_age = rtl83xx_fast_age,
2205
2206 .port_vlan_filtering = rtl83xx_vlan_filtering,
2207 .port_vlan_prepare = rtl83xx_vlan_prepare,
2208 .port_vlan_add = rtl83xx_vlan_add,
2209 .port_vlan_del = rtl83xx_vlan_del,
2210
2211 .port_fdb_add = rtl83xx_port_fdb_add,
2212 .port_fdb_del = rtl83xx_port_fdb_del,
2213 .port_fdb_dump = rtl83xx_port_fdb_dump,
2214
2215 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2216 .port_mdb_add = rtl83xx_port_mdb_add,
2217 .port_mdb_del = rtl83xx_port_mdb_del,
2218
2219 .port_mirror_add = rtl83xx_port_mirror_add,
2220 .port_mirror_del = rtl83xx_port_mirror_del,
2221
2222 .port_lag_change = rtl83xx_port_lag_change,
2223 .port_lag_join = rtl83xx_port_lag_join,
2224 .port_lag_leave = rtl83xx_port_lag_leave,
2225
2226 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2227 .port_bridge_flags = rtl83xx_port_bridge_flags,
2228 };
2229
2230 const struct dsa_switch_ops rtl930x_switch_ops = {
2231 .get_tag_protocol = rtl83xx_get_tag_protocol,
2232 .setup = rtl93xx_setup,
2233
2234 .phy_read = dsa_phy_read,
2235 .phy_write = dsa_phy_write,
2236
2237 .phylink_validate = rtl93xx_phylink_validate,
2238 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2239 .phylink_mac_config = rtl93xx_phylink_mac_config,
2240 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2241 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2242
2243 .get_strings = rtl83xx_get_strings,
2244 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2245 .get_sset_count = rtl83xx_get_sset_count,
2246
2247 .port_enable = rtl83xx_port_enable,
2248 .port_disable = rtl83xx_port_disable,
2249
2250 .get_mac_eee = rtl93xx_get_mac_eee,
2251 .set_mac_eee = rtl83xx_set_mac_eee,
2252
2253 .set_ageing_time = rtl83xx_set_ageing_time,
2254 .port_bridge_join = rtl83xx_port_bridge_join,
2255 .port_bridge_leave = rtl83xx_port_bridge_leave,
2256 .port_stp_state_set = rtl83xx_port_stp_state_set,
2257 .port_fast_age = rtl930x_fast_age,
2258
2259 .port_vlan_filtering = rtl83xx_vlan_filtering,
2260 .port_vlan_prepare = rtl83xx_vlan_prepare,
2261 .port_vlan_add = rtl83xx_vlan_add,
2262 .port_vlan_del = rtl83xx_vlan_del,
2263
2264 .port_fdb_add = rtl83xx_port_fdb_add,
2265 .port_fdb_del = rtl83xx_port_fdb_del,
2266 .port_fdb_dump = rtl83xx_port_fdb_dump,
2267
2268 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2269 .port_mdb_add = rtl83xx_port_mdb_add,
2270 .port_mdb_del = rtl83xx_port_mdb_del,
2271
2272 .port_lag_change = rtl83xx_port_lag_change,
2273 .port_lag_join = rtl83xx_port_lag_join,
2274 .port_lag_leave = rtl83xx_port_lag_leave,
2275
2276 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2277 .port_bridge_flags = rtl83xx_port_bridge_flags,
2278 };
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