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[openwrt/staging/hauke.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_debug("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /*
113 * Initialize all VLANS
114 */
115 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
116 {
117 struct rtl838x_vlan_info info;
118 int i;
119
120 pr_info("In %s\n", __func__);
121
122 priv->r->vlan_profile_setup(0);
123 priv->r->vlan_profile_setup(1);
124 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
125 priv->r->vlan_profile_dump(0);
126
127 info.fid = 0; // Default Forwarding ID / MSTI
128 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
129 info.hash_mc_fid = false; // Do the same for Multicast packets
130 info.profile_id = 0; // Use default Vlan Profile 0
131 info.tagged_ports = 0; // Initially no port members
132
133 // Initialize all vlans 0-4095
134 for (i = 0; i < MAX_VLANS; i ++)
135 priv->r->vlan_set_tagged(i, &info);
136
137 // reset PVIDs; defaults to 1 on reset
138 for (i = 0; i <= priv->ds->num_ports; i++)
139 sw_w32(0, priv->r->vlan_port_pb + (i << 2));
140
141 // Set forwarding action based on inner VLAN tag
142 for (i = 0; i < priv->cpu_port; i++)
143 priv->r->vlan_fwd_on_inner(i, true);
144 }
145
146 static int rtl83xx_setup(struct dsa_switch *ds)
147 {
148 int i;
149 struct rtl838x_switch_priv *priv = ds->priv;
150 u64 port_bitmap = BIT_ULL(priv->cpu_port);
151
152 pr_debug("%s called\n", __func__);
153
154 /* Disable MAC polling the PHY so that we can start configuration */
155 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
156
157 for (i = 0; i < ds->num_ports; i++)
158 priv->ports[i].enable = false;
159 priv->ports[priv->cpu_port].enable = true;
160
161 /* Isolate ports from each other: traffic only CPU <-> port */
162 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
163 * traffic from source port i to destination port j
164 */
165 for (i = 0; i < priv->cpu_port; i++) {
166 if (priv->ports[i].phy) {
167 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
168 priv->r->port_iso_ctrl(i));
169 port_bitmap |= BIT_ULL(i);
170 }
171 }
172 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
173
174 if (priv->family_id == RTL8380_FAMILY_ID)
175 rtl838x_print_matrix();
176 else
177 rtl839x_print_matrix();
178
179 rtl83xx_init_stats(priv);
180
181 rtl83xx_vlan_setup(priv);
182
183 ds->configure_vlan_while_not_filtering = true;
184
185 /* Enable MAC Polling PHY again */
186 rtl83xx_enable_phy_polling(priv);
187 pr_debug("Please wait until PHY is settled\n");
188 msleep(1000);
189 return 0;
190 }
191
192 static int rtl930x_setup(struct dsa_switch *ds)
193 {
194 int i;
195 struct rtl838x_switch_priv *priv = ds->priv;
196 u32 port_bitmap = BIT(priv->cpu_port);
197
198 pr_info("%s called\n", __func__);
199
200 // Enable CSTI STP mode
201 // sw_w32(1, RTL930X_ST_CTRL);
202
203 /* Disable MAC polling the PHY so that we can start configuration */
204 sw_w32(0, RTL930X_SMI_POLL_CTRL);
205
206 // Disable all ports except CPU port
207 for (i = 0; i < ds->num_ports; i++)
208 priv->ports[i].enable = false;
209 priv->ports[priv->cpu_port].enable = true;
210
211 for (i = 0; i < priv->cpu_port; i++) {
212 if (priv->ports[i].phy) {
213 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
214 port_bitmap |= BIT_ULL(i);
215 }
216 }
217 priv->r->traffic_set(priv->cpu_port, port_bitmap);
218
219 rtl930x_print_matrix();
220
221 // TODO: Initialize statistics
222
223 rtl83xx_vlan_setup(priv);
224
225 ds->configure_vlan_while_not_filtering = true;
226
227 rtl83xx_enable_phy_polling(priv);
228
229 return 0;
230 }
231
232 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
233 unsigned long *supported,
234 struct phylink_link_state *state)
235 {
236 struct rtl838x_switch_priv *priv = ds->priv;
237 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
238
239 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
240
241 if (!phy_interface_mode_is_rgmii(state->interface) &&
242 state->interface != PHY_INTERFACE_MODE_NA &&
243 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
244 state->interface != PHY_INTERFACE_MODE_MII &&
245 state->interface != PHY_INTERFACE_MODE_REVMII &&
246 state->interface != PHY_INTERFACE_MODE_GMII &&
247 state->interface != PHY_INTERFACE_MODE_QSGMII &&
248 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
249 state->interface != PHY_INTERFACE_MODE_SGMII) {
250 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
251 dev_err(ds->dev,
252 "Unsupported interface: %d for port %d\n",
253 state->interface, port);
254 return;
255 }
256
257 /* Allow all the expected bits */
258 phylink_set(mask, Autoneg);
259 phylink_set_port_modes(mask);
260 phylink_set(mask, Pause);
261 phylink_set(mask, Asym_Pause);
262
263 /* With the exclusion of MII and Reverse MII, we support Gigabit,
264 * including Half duplex
265 */
266 if (state->interface != PHY_INTERFACE_MODE_MII &&
267 state->interface != PHY_INTERFACE_MODE_REVMII) {
268 phylink_set(mask, 1000baseT_Full);
269 phylink_set(mask, 1000baseT_Half);
270 }
271
272 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
273 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
274 phylink_set(mask, 1000baseX_Full);
275
276 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
277 if (port >=48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
278 phylink_set(mask, 1000baseX_Full);
279
280 phylink_set(mask, 10baseT_Half);
281 phylink_set(mask, 10baseT_Full);
282 phylink_set(mask, 100baseT_Half);
283 phylink_set(mask, 100baseT_Full);
284
285 bitmap_and(supported, supported, mask,
286 __ETHTOOL_LINK_MODE_MASK_NBITS);
287 bitmap_and(state->advertising, state->advertising, mask,
288 __ETHTOOL_LINK_MODE_MASK_NBITS);
289 }
290
291 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
292 struct phylink_link_state *state)
293 {
294 struct rtl838x_switch_priv *priv = ds->priv;
295 u64 speed;
296 u64 link;
297
298 if (port < 0 || port > priv->cpu_port)
299 return -EINVAL;
300
301 /*
302 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
303 * state needs to be read twice in order to read a correct result.
304 * This would not be necessary for ports connected e.g. to RTL8218D
305 * PHYs.
306 */
307 state->link = 0;
308 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
309 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
310 if (link & BIT_ULL(port))
311 state->link = 1;
312 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
313
314 state->duplex = 0;
315 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
316 state->duplex = 1;
317
318 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
319 speed >>= (port % 16) << 1;
320 switch (speed & 0x3) {
321 case 0:
322 state->speed = SPEED_10;
323 break;
324 case 1:
325 state->speed = SPEED_100;
326 break;
327 case 2:
328 state->speed = SPEED_1000;
329 break;
330 case 3:
331 if (priv->family_id == RTL9300_FAMILY_ID
332 && (port == 24 || port == 26)) /* Internal serdes */
333 state->speed = SPEED_2500;
334 else
335 state->speed = SPEED_100; /* Is in fact 500Mbit */
336 }
337
338 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
339 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
340 state->pause |= MLO_PAUSE_RX;
341 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
342 state->pause |= MLO_PAUSE_TX;
343 return 1;
344 }
345
346 static void rtl83xx_config_interface(int port, phy_interface_t interface)
347 {
348 u32 old, int_shift, sds_shift;
349
350 switch (port) {
351 case 24:
352 int_shift = 0;
353 sds_shift = 5;
354 break;
355 case 26:
356 int_shift = 3;
357 sds_shift = 0;
358 break;
359 default:
360 return;
361 }
362
363 old = sw_r32(RTL838X_SDS_MODE_SEL);
364 switch (interface) {
365 case PHY_INTERFACE_MODE_1000BASEX:
366 if ((old >> sds_shift & 0x1f) == 4)
367 return;
368 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
369 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
370 break;
371 case PHY_INTERFACE_MODE_SGMII:
372 if ((old >> sds_shift & 0x1f) == 2)
373 return;
374 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
375 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
376 break;
377 default:
378 return;
379 }
380 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
381 }
382
383 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
384 unsigned int mode,
385 const struct phylink_link_state *state)
386 {
387 struct rtl838x_switch_priv *priv = ds->priv;
388 u32 reg;
389 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
390
391 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
392
393 // BUG: Make this work on RTL93XX
394 if (priv->family_id >= RTL9300_FAMILY_ID)
395 return;
396
397 if (port == priv->cpu_port) {
398 /* Set Speed, duplex, flow control
399 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
400 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
401 * | MEDIA_SEL
402 */
403 if (priv->family_id == RTL8380_FAMILY_ID) {
404 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
405 /* allow CRC errors on CPU-port */
406 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
407 } else {
408 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
409 }
410 return;
411 }
412
413 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
414 /* Auto-Negotiation does not work for MAC in RTL8390 */
415 if (priv->family_id == RTL8380_FAMILY_ID) {
416 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
417 pr_debug("PHY autonegotiates\n");
418 reg |= BIT(2);
419 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
420 rtl83xx_config_interface(port, state->interface);
421 return;
422 }
423 }
424
425 if (mode != MLO_AN_FIXED)
426 pr_debug("Fixed state.\n");
427
428 if (priv->family_id == RTL8380_FAMILY_ID) {
429 /* Clear id_mode_dis bit, and the existing port mode, let
430 * RGMII_MODE_EN bet set by mac_link_{up,down}
431 */
432 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
433
434 if (state->pause & MLO_PAUSE_TXRX_MASK) {
435 if (state->pause & MLO_PAUSE_TX)
436 reg |= TX_PAUSE_EN;
437 reg |= RX_PAUSE_EN;
438 }
439 }
440
441 reg &= ~(3 << speed_bit);
442 switch (state->speed) {
443 case SPEED_1000:
444 reg |= 2 << speed_bit;
445 break;
446 case SPEED_100:
447 reg |= 1 << speed_bit;
448 break;
449 }
450
451 if (priv->family_id == RTL8380_FAMILY_ID) {
452 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
453 if (state->link)
454 reg |= FORCE_LINK_EN;
455 if (state->duplex == DUPLEX_FULL)
456 reg |= DUPLX_MODE;
457 }
458
459 // Disable AN
460 if (priv->family_id == RTL8380_FAMILY_ID)
461 reg &= ~BIT(2);
462 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
463 }
464
465 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
466 unsigned int mode,
467 phy_interface_t interface)
468 {
469 struct rtl838x_switch_priv *priv = ds->priv;
470 /* Stop TX/RX to port */
471 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
472 }
473
474 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
475 unsigned int mode,
476 phy_interface_t interface,
477 struct phy_device *phydev)
478 {
479 struct rtl838x_switch_priv *priv = ds->priv;
480 /* Restart TX/RX to port */
481 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
482 }
483
484 static void rtl83xx_get_strings(struct dsa_switch *ds,
485 int port, u32 stringset, u8 *data)
486 {
487 int i;
488
489 if (stringset != ETH_SS_STATS)
490 return;
491
492 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
493 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
494 ETH_GSTRING_LEN);
495 }
496
497 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
498 uint64_t *data)
499 {
500 struct rtl838x_switch_priv *priv = ds->priv;
501 const struct rtl83xx_mib_desc *mib;
502 int i;
503 u64 h;
504
505 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
506 mib = &rtl83xx_mib[i];
507
508 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
509 if (mib->size == 2) {
510 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
511 data[i] |= h << 32;
512 }
513 }
514 }
515
516 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
517 {
518 if (sset != ETH_SS_STATS)
519 return 0;
520
521 return ARRAY_SIZE(rtl83xx_mib);
522 }
523
524 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
525 struct phy_device *phydev)
526 {
527 struct rtl838x_switch_priv *priv = ds->priv;
528 u64 v;
529
530 pr_debug("%s: %x %d", __func__, (u32) priv, port);
531 priv->ports[port].enable = true;
532
533 /* enable inner tagging on egress, do not keep any tags */
534 if (priv->family_id == RTL9310_FAMILY_ID)
535 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
536 else
537 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
538
539 if (dsa_is_cpu_port(ds, port))
540 return 0;
541
542 /* add port to switch mask of CPU_PORT */
543 priv->r->traffic_enable(priv->cpu_port, port);
544
545 /* add all other ports in the same bridge to switch mask of port */
546 v = priv->r->traffic_get(port);
547 v |= priv->ports[port].pm;
548 priv->r->traffic_set(port, v);
549
550 // TODO: Figure out if this is necessary
551 if (priv->family_id == RTL9300_FAMILY_ID) {
552 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
553 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
554 }
555
556 return 0;
557 }
558
559 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
560 {
561 struct rtl838x_switch_priv *priv = ds->priv;
562 u64 v;
563
564 pr_debug("%s %x: %d", __func__, (u32)priv, port);
565 /* you can only disable user ports */
566 if (!dsa_is_user_port(ds, port))
567 return;
568
569 // BUG: This does not work on RTL931X
570 /* remove port from switch mask of CPU_PORT */
571 priv->r->traffic_disable(priv->cpu_port, port);
572
573 /* remove all other ports in the same bridge from switch mask of port */
574 v = priv->r->traffic_get(port);
575 v &= ~priv->ports[port].pm;
576 priv->r->traffic_set(port, v);
577
578 priv->ports[port].enable = false;
579 }
580
581 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
582 struct ethtool_eee *e)
583 {
584 struct rtl838x_switch_priv *priv = ds->priv;
585
586 if (e->eee_enabled && !priv->eee_enabled) {
587 pr_info("Globally enabling EEE\n");
588 priv->r->init_eee(priv, true);
589 }
590
591 priv->r->port_eee_set(priv, port, e->eee_enabled);
592
593 if (e->eee_enabled)
594 pr_info("Enabled EEE for port %d\n", port);
595 else
596 pr_info("Disabled EEE for port %d\n", port);
597 return 0;
598 }
599
600 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
601 struct ethtool_eee *e)
602 {
603 struct rtl838x_switch_priv *priv = ds->priv;
604
605 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
606
607 priv->r->eee_port_ability(priv, e, port);
608
609 e->eee_enabled = priv->ports[port].eee_enabled;
610
611 e->eee_active = !!(e->advertised & e->lp_advertised);
612
613 return 0;
614 }
615
616 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
617 struct ethtool_eee *e)
618 {
619 struct rtl838x_switch_priv *priv = ds->priv;
620
621 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
622 | SUPPORTED_2500baseX_Full;
623
624 priv->r->eee_port_ability(priv, e, port);
625
626 e->eee_enabled = priv->ports[port].eee_enabled;
627
628 e->eee_active = !!(e->advertised & e->lp_advertised);
629
630 return 0;
631 }
632
633 /*
634 * Set Switch L2 Aging time, t is time in milliseconds
635 * t = 0: aging is disabled
636 */
637 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
638 {
639 struct rtl838x_switch_priv *priv = ds->priv;
640 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
641
642 /* Convert time in mseconds to internal value */
643 if (t > 0x10000000) { /* Set to maximum */
644 t = t_max;
645 } else {
646 if (priv->family_id == RTL8380_FAMILY_ID)
647 t = ((t * 625) / 1000 + 127) / 128;
648 else
649 t = (t * 5 + 2) / 3;
650 }
651 sw_w32(t, priv->r->l2_ctrl_1);
652 return 0;
653 }
654
655 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
656 struct net_device *bridge)
657 {
658 struct rtl838x_switch_priv *priv = ds->priv;
659 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
660 int i;
661
662 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
663 mutex_lock(&priv->reg_mutex);
664 for (i = 0; i < ds->num_ports; i++) {
665 /* Add this port to the port matrix of the other ports in the
666 * same bridge. If the port is disabled, port matrix is kept
667 * and not being setup until the port becomes enabled.
668 */
669 if (dsa_is_user_port(ds, i) && i != port) {
670 if (dsa_to_port(ds, i)->bridge_dev != bridge)
671 continue;
672 if (priv->ports[i].enable)
673 priv->r->traffic_enable(i, port);
674
675 priv->ports[i].pm |= BIT_ULL(port);
676 port_bitmap |= BIT_ULL(i);
677 }
678 }
679
680 /* Add all other ports to this port matrix. */
681 if (priv->ports[port].enable) {
682 priv->r->traffic_enable(priv->cpu_port, port);
683 v = priv->r->traffic_get(port);
684 v |= port_bitmap;
685 priv->r->traffic_set(port, v);
686 }
687 priv->ports[port].pm |= port_bitmap;
688 mutex_unlock(&priv->reg_mutex);
689
690 return 0;
691 }
692
693 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
694 struct net_device *bridge)
695 {
696 struct rtl838x_switch_priv *priv = ds->priv;
697 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
698 int i;
699
700 pr_debug("%s %x: %d", __func__, (u32)priv, port);
701 mutex_lock(&priv->reg_mutex);
702 for (i = 0; i < ds->num_ports; i++) {
703 /* Remove this port from the port matrix of the other ports
704 * in the same bridge. If the port is disabled, port matrix
705 * is kept and not being setup until the port becomes enabled.
706 * And the other port's port matrix cannot be broken when the
707 * other port is still a VLAN-aware port.
708 */
709 if (dsa_is_user_port(ds, i) && i != port) {
710 if (dsa_to_port(ds, i)->bridge_dev != bridge)
711 continue;
712 if (priv->ports[i].enable)
713 priv->r->traffic_disable(i, port);
714
715 priv->ports[i].pm |= BIT_ULL(port);
716 port_bitmap &= ~BIT_ULL(i);
717 }
718 }
719
720 /* Add all other ports to this port matrix. */
721 if (priv->ports[port].enable) {
722 v = priv->r->traffic_get(port);
723 v |= port_bitmap;
724 priv->r->traffic_set(port, v);
725 }
726 priv->ports[port].pm &= ~port_bitmap;
727
728 mutex_unlock(&priv->reg_mutex);
729 }
730
731 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
732 {
733 u32 msti = 0;
734 u32 port_state[4];
735 int index, bit;
736 int pos = port;
737 struct rtl838x_switch_priv *priv = ds->priv;
738 int n = priv->port_width << 1;
739
740 /* Ports above or equal CPU port can never be configured */
741 if (port >= priv->cpu_port)
742 return;
743
744 mutex_lock(&priv->reg_mutex);
745
746 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
747 * have 64 bit fields, 839x and 931x have 128 bit fields
748 */
749 if (priv->family_id == RTL8390_FAMILY_ID)
750 pos += 12;
751 if (priv->family_id == RTL9300_FAMILY_ID)
752 pos += 3;
753 if (priv->family_id == RTL9310_FAMILY_ID)
754 pos += 8;
755
756 index = n - (pos >> 4) - 1;
757 bit = (pos << 1) % 32;
758
759 priv->r->stp_get(priv, msti, port_state);
760
761 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
762 port_state[index] &= ~(3 << bit);
763
764 switch (state) {
765 case BR_STATE_DISABLED: /* 0 */
766 port_state[index] |= (0 << bit);
767 break;
768 case BR_STATE_BLOCKING: /* 4 */
769 case BR_STATE_LISTENING: /* 1 */
770 port_state[index] |= (1 << bit);
771 break;
772 case BR_STATE_LEARNING: /* 2 */
773 port_state[index] |= (2 << bit);
774 break;
775 case BR_STATE_FORWARDING: /* 3*/
776 port_state[index] |= (3 << bit);
777 default:
778 break;
779 }
780
781 priv->r->stp_set(priv, msti, port_state);
782
783 mutex_unlock(&priv->reg_mutex);
784 }
785
786 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
787 {
788 struct rtl838x_switch_priv *priv = ds->priv;
789 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
790
791 pr_debug("FAST AGE port %d\n", port);
792 mutex_lock(&priv->reg_mutex);
793 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
794 * port fields:
795 * 0-4: Replacing port
796 * 5-9: Flushed/replaced port
797 * 10-21: FVID
798 * 22: Entry types: 1: dynamic, 0: also static
799 * 23: Match flush port
800 * 24: Match FVID
801 * 25: Flush (0) or replace (1) L2 entries
802 * 26: Status of action (1: Start, 0: Done)
803 */
804 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
805
806 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
807
808 mutex_unlock(&priv->reg_mutex);
809 }
810
811 void rtl930x_fast_age(struct dsa_switch *ds, int port)
812 {
813 struct rtl838x_switch_priv *priv = ds->priv;
814
815 pr_debug("FAST AGE port %d\n", port);
816 mutex_lock(&priv->reg_mutex);
817 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
818
819 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
820
821 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
822
823 mutex_unlock(&priv->reg_mutex);
824 }
825
826 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
827 bool vlan_filtering)
828 {
829 struct rtl838x_switch_priv *priv = ds->priv;
830
831 pr_debug("%s: port %d\n", __func__, port);
832 mutex_lock(&priv->reg_mutex);
833
834 if (vlan_filtering) {
835 /* Enable ingress and egress filtering
836 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
837 * the filter action:
838 * 0: Always Forward
839 * 1: Drop packet
840 * 2: Trap packet to CPU port
841 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
842 */
843 if (port != priv->cpu_port)
844 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
845 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
846 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
847 } else {
848 /* Disable ingress and egress filtering */
849 if (port != priv->cpu_port)
850 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
851 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
852 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
853 }
854
855 /* Do we need to do something to the CPU-Port, too? */
856 mutex_unlock(&priv->reg_mutex);
857
858 return 0;
859 }
860
861 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
862 const struct switchdev_obj_port_vlan *vlan)
863 {
864 struct rtl838x_vlan_info info;
865 struct rtl838x_switch_priv *priv = ds->priv;
866
867 priv->r->vlan_tables_read(0, &info);
868
869 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
870 info.tagged_ports, info.untagged_ports, info.profile_id,
871 info.hash_mc_fid, info.hash_uc_fid, info.fid);
872
873 priv->r->vlan_tables_read(1, &info);
874 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
875 info.tagged_ports, info.untagged_ports, info.profile_id,
876 info.hash_mc_fid, info.hash_uc_fid, info.fid);
877 priv->r->vlan_set_untagged(1, info.untagged_ports);
878 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
879
880 priv->r->vlan_set_tagged(1, &info);
881 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
882
883 mutex_unlock(&priv->reg_mutex);
884 return 0;
885 }
886
887 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
888 const struct switchdev_obj_port_vlan *vlan)
889 {
890 struct rtl838x_vlan_info info;
891 struct rtl838x_switch_priv *priv = ds->priv;
892 int v;
893
894 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
895 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
896
897 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
898 dev_err(priv->dev, "VLAN out of range: %d - %d",
899 vlan->vid_begin, vlan->vid_end);
900 return;
901 }
902
903 mutex_lock(&priv->reg_mutex);
904
905 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
906 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
907 if (!v)
908 continue;
909 /* Set both inner and outer PVID of the port */
910 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
911 priv->ports[port].pvid = vlan->vid_end;
912 }
913 }
914
915 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
916 /* Get port memberships of this vlan */
917 priv->r->vlan_tables_read(v, &info);
918
919 /* new VLAN? */
920 if (!info.tagged_ports) {
921 info.fid = 0;
922 info.hash_mc_fid = false;
923 info.hash_uc_fid = false;
924 info.profile_id = 0;
925 }
926
927 /* sanitize untagged_ports - must be a subset */
928 if (info.untagged_ports & ~info.tagged_ports)
929 info.untagged_ports = 0;
930
931 info.tagged_ports |= BIT_ULL(port);
932 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
933 info.untagged_ports |= BIT_ULL(port);
934
935 priv->r->vlan_set_untagged(v, info.untagged_ports);
936 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
937
938 priv->r->vlan_set_tagged(v, &info);
939 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
940 }
941
942 mutex_unlock(&priv->reg_mutex);
943 }
944
945 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
946 const struct switchdev_obj_port_vlan *vlan)
947 {
948 struct rtl838x_vlan_info info;
949 struct rtl838x_switch_priv *priv = ds->priv;
950 int v;
951 u16 pvid;
952
953 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
954 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
955
956 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
957 dev_err(priv->dev, "VLAN out of range: %d - %d",
958 vlan->vid_begin, vlan->vid_end);
959 return -ENOTSUPP;
960 }
961
962 mutex_lock(&priv->reg_mutex);
963 pvid = priv->ports[port].pvid;
964
965 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
966 /* Reset to default if removing the current PVID */
967 if (v == pvid)
968 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
969
970 /* Get port memberships of this vlan */
971 priv->r->vlan_tables_read(v, &info);
972
973 /* remove port from both tables */
974 info.untagged_ports &= (~BIT_ULL(port));
975 info.tagged_ports &= (~BIT_ULL(port));
976
977 priv->r->vlan_set_untagged(v, info.untagged_ports);
978 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
979
980 priv->r->vlan_set_tagged(v, &info);
981 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
982 }
983 mutex_unlock(&priv->reg_mutex);
984
985 return 0;
986 }
987
988 static void dump_l2_entry(struct rtl838x_l2_entry *e)
989 {
990 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
991 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
992 e->vid, e->rvid, e->port, e->valid);
993
994 if (e->type != L2_MULTICAST) {
995 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
996 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
997 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
998 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
999 }
1000 if (e->type == L2_MULTICAST)
1001 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1002 if (e->is_ip_mc || e->is_ipv6_mc)
1003 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1004 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1005 pr_info(" stack_dev: %d\n", e->stack_dev);
1006 if (e->next_hop)
1007 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1008 }
1009
1010 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1011 {
1012 e->is_ip_mc = e->is_ipv6_mc = false;
1013 e->valid = true;
1014 e->age = 3;
1015 e->port = port,
1016 e->vid = vid;
1017 u64_to_ether_addr(mac, e->mac);
1018 }
1019
1020 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1021 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1022 {
1023 e->is_ip_mc = e->is_ipv6_mc = false;
1024 e->valid = true;
1025 e->mc_portmask_index = mc_group;
1026 e->type = L2_MULTICAST;
1027 e->rvid = e->vid = vid;
1028 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1029 u64_to_ether_addr(mac, e->mac);
1030 }
1031
1032 /*
1033 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1034 * over the entries in the bucket until either a matching entry is found or an empty slot
1035 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1036 * when an empty slot was found and must exist is false, the index of the slot is returned
1037 * when no slots are available returns -1
1038 */
1039 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1040 bool must_exist, struct rtl838x_l2_entry *e)
1041 {
1042 int i, idx = -1;
1043 u32 key = priv->r->l2_hash_key(priv, seed);
1044 u64 entry;
1045
1046 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1047 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1048 for (i = 0; i < priv->l2_bucket_size; i++) {
1049 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1050 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1051 if (must_exist && !e->valid)
1052 continue;
1053 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1054 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1055 break;
1056 }
1057 }
1058
1059 return idx;
1060 }
1061
1062 /*
1063 * Uses the seed to identify an entry in the CAM by looping over all its entries
1064 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1065 * when an empty slot was found the index of the slot is returned
1066 * when no slots are available returns -1
1067 */
1068 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1069 bool must_exist, struct rtl838x_l2_entry *e)
1070 {
1071 int i, idx = -1;
1072 u64 entry;
1073
1074 for (i = 0; i < 64; i++) {
1075 entry = priv->r->read_cam(i, e);
1076 if (!must_exist && !e->valid) {
1077 if (idx < 0) /* First empty entry? */
1078 idx = i;
1079 break;
1080 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1081 pr_debug("Found entry in CAM\n");
1082 idx = i;
1083 break;
1084 }
1085 }
1086 return idx;
1087 }
1088
1089 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1090 const unsigned char *addr, u16 vid)
1091 {
1092 struct rtl838x_switch_priv *priv = ds->priv;
1093 u64 mac = ether_addr_to_u64(addr);
1094 struct rtl838x_l2_entry e;
1095 int err = 0, idx;
1096 u64 seed = priv->r->l2_hash_seed(mac, vid);
1097
1098 mutex_lock(&priv->reg_mutex);
1099
1100 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1101
1102 // Found an existing or empty entry
1103 if (idx >= 0) {
1104 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1105 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1106 goto out;
1107 }
1108
1109 // Hash buckets full, try CAM
1110 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1111
1112 if (idx >= 0) {
1113 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1114 priv->r->write_cam(idx, &e);
1115 goto out;
1116 }
1117
1118 err = -ENOTSUPP;
1119 out:
1120 mutex_unlock(&priv->reg_mutex);
1121 return err;
1122 }
1123
1124 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1125 const unsigned char *addr, u16 vid)
1126 {
1127 struct rtl838x_switch_priv *priv = ds->priv;
1128 u64 mac = ether_addr_to_u64(addr);
1129 struct rtl838x_l2_entry e;
1130 int err = 0, idx;
1131 u64 seed = priv->r->l2_hash_seed(mac, vid);
1132
1133 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1134 mutex_lock(&priv->reg_mutex);
1135
1136 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1137
1138 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1139 if (idx >= 0) {
1140 e.valid = false;
1141 dump_l2_entry(&e);
1142 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1143 goto out;
1144 }
1145
1146 /* Check CAM for spillover from hash buckets */
1147 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1148
1149 if (idx >= 0) {
1150 e.valid = false;
1151 priv->r->write_cam(idx, &e);
1152 goto out;
1153 }
1154 err = -ENOENT;
1155 out:
1156 mutex_unlock(&priv->reg_mutex);
1157 return err;
1158 }
1159
1160 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1161 dsa_fdb_dump_cb_t *cb, void *data)
1162 {
1163 struct rtl838x_l2_entry e;
1164 struct rtl838x_switch_priv *priv = ds->priv;
1165 int i;
1166 u32 fid, pkey;
1167 u64 mac;
1168
1169 mutex_lock(&priv->reg_mutex);
1170
1171 for (i = 0; i < priv->fib_entries; i++) {
1172 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1173
1174 if (!e.valid)
1175 continue;
1176
1177 if (e.port == port) {
1178 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1179 mac = ether_addr_to_u64(&e.mac[0]);
1180 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1181 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1182 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1183 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1184 dump_l2_entry(&e);
1185 u64 seed = priv->r->l2_hash_seed(mac, e.rvid);
1186 u32 key = priv->r->l2_hash_key(priv, seed);
1187 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1188 cb(e.mac, e.vid, e.is_static, data);
1189 }
1190 if (e.type == L2_MULTICAST) {
1191 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1192 if (portmask & BIT_ULL(port)) {
1193 dump_l2_entry(&e);
1194 pr_info(" PM: %016llx\n", portmask);
1195 }
1196 }
1197 }
1198
1199 for (i = 0; i < 64; i++) {
1200 priv->r->read_cam(i, &e);
1201
1202 if (!e.valid)
1203 continue;
1204
1205 if (e.port == port)
1206 cb(e.mac, e.vid, e.is_static, data);
1207 }
1208
1209 mutex_unlock(&priv->reg_mutex);
1210 return 0;
1211 }
1212
1213 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1214 const struct switchdev_obj_port_mdb *mdb)
1215 {
1216 struct rtl838x_switch_priv *priv = ds->priv;
1217
1218 if (priv->id >= 0x9300)
1219 return -EOPNOTSUPP;
1220
1221 return 0;
1222 }
1223
1224 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1225 {
1226 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1227 u64 portmask;
1228
1229 if (mc_group >= MAX_MC_GROUPS - 1)
1230 return -1;
1231
1232 pr_debug("Using MC group %d\n", mc_group);
1233 set_bit(mc_group, priv->mc_group_bm);
1234 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1235 portmask = BIT_ULL(port);
1236 priv->r->write_mcast_pmask(mc_group, portmask);
1237
1238 return mc_group;
1239 }
1240
1241 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1242 {
1243 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1244
1245 portmask |= BIT_ULL(port);
1246 priv->r->write_mcast_pmask(mc_group, portmask);
1247
1248 return portmask;
1249 }
1250
1251 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1252 {
1253 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1254
1255 portmask &= ~BIT_ULL(port);
1256 priv->r->write_mcast_pmask(mc_group, portmask);
1257 if (!portmask)
1258 clear_bit(mc_group, priv->mc_group_bm);
1259
1260 return portmask;
1261 }
1262
1263 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1264 const struct switchdev_obj_port_mdb *mdb)
1265 {
1266 struct rtl838x_switch_priv *priv = ds->priv;
1267 u64 mac = ether_addr_to_u64(mdb->addr);
1268 struct rtl838x_l2_entry e;
1269 int err = 0, idx;
1270 int vid = mdb->vid;
1271 u64 seed = priv->r->l2_hash_seed(mac, vid);
1272 int mc_group;
1273
1274 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1275 mutex_lock(&priv->reg_mutex);
1276
1277 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1278
1279 // Found an existing or empty entry
1280 if (idx >= 0) {
1281 if (e.valid) {
1282 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1283 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1284 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1285 } else {
1286 pr_debug("New entry for seed %016llx\n", seed);
1287 mc_group = rtl83xx_mc_group_alloc(priv, port);
1288 if (mc_group < 0) {
1289 err = -ENOTSUPP;
1290 goto out;
1291 }
1292 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1293 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1294 }
1295 goto out;
1296 }
1297
1298 // Hash buckets full, try CAM
1299 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1300
1301 if (idx >= 0) {
1302 if (e.valid) {
1303 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1304 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1305 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1306 } else {
1307 pr_debug("New entry\n");
1308 mc_group = rtl83xx_mc_group_alloc(priv, port);
1309 if (mc_group < 0) {
1310 err = -ENOTSUPP;
1311 goto out;
1312 }
1313 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1314 priv->r->write_cam(idx, &e);
1315 }
1316 goto out;
1317 }
1318
1319 err = -ENOTSUPP;
1320 out:
1321 mutex_unlock(&priv->reg_mutex);
1322 if (err)
1323 dev_err(ds->dev, "failed to add MDB entry\n");
1324 }
1325
1326 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1327 const struct switchdev_obj_port_mdb *mdb)
1328 {
1329 struct rtl838x_switch_priv *priv = ds->priv;
1330 u64 mac = ether_addr_to_u64(mdb->addr);
1331 struct rtl838x_l2_entry e;
1332 int err = 0, idx;
1333 int vid = mdb->vid;
1334 u64 seed = priv->r->l2_hash_seed(mac, vid);
1335 u64 portmask;
1336
1337 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1338 mutex_lock(&priv->reg_mutex);
1339
1340 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1341
1342 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1343 if (idx >= 0) {
1344 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1345 if (!portmask) {
1346 e.valid = false;
1347 // dump_l2_entry(&e);
1348 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1349 }
1350 goto out;
1351 }
1352
1353 /* Check CAM for spillover from hash buckets */
1354 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1355
1356 if (idx >= 0) {
1357 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1358 if (!portmask) {
1359 e.valid = false;
1360 // dump_l2_entry(&e);
1361 priv->r->write_cam(idx, &e);
1362 }
1363 goto out;
1364 }
1365 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1366 out:
1367 mutex_unlock(&priv->reg_mutex);
1368 return err;
1369 }
1370
1371 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1372 struct dsa_mall_mirror_tc_entry *mirror,
1373 bool ingress)
1374 {
1375 /* We support 4 mirror groups, one destination port per group */
1376 int group;
1377 struct rtl838x_switch_priv *priv = ds->priv;
1378 int ctrl_reg, dpm_reg, spm_reg;
1379
1380 pr_debug("In %s\n", __func__);
1381
1382 for (group = 0; group < 4; group++) {
1383 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1384 break;
1385 }
1386 if (group >= 4) {
1387 for (group = 0; group < 4; group++) {
1388 if (priv->mirror_group_ports[group] < 0)
1389 break;
1390 }
1391 }
1392
1393 if (group >= 4)
1394 return -ENOSPC;
1395
1396 ctrl_reg = priv->r->mir_ctrl + group * 4;
1397 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1398 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1399
1400 pr_debug("Using group %d\n", group);
1401 mutex_lock(&priv->reg_mutex);
1402
1403 if (priv->family_id == RTL8380_FAMILY_ID) {
1404 /* Enable mirroring to port across VLANs (bit 11) */
1405 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1406 } else {
1407 /* Enable mirroring to destination port */
1408 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1409 }
1410
1411 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1412 mutex_unlock(&priv->reg_mutex);
1413 return -EEXIST;
1414 }
1415 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1416 mutex_unlock(&priv->reg_mutex);
1417 return -EEXIST;
1418 }
1419
1420 if (ingress)
1421 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1422 else
1423 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1424
1425 priv->mirror_group_ports[group] = mirror->to_local_port;
1426 mutex_unlock(&priv->reg_mutex);
1427 return 0;
1428 }
1429
1430 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1431 struct dsa_mall_mirror_tc_entry *mirror)
1432 {
1433 int group = 0;
1434 struct rtl838x_switch_priv *priv = ds->priv;
1435 int ctrl_reg, dpm_reg, spm_reg;
1436
1437 pr_debug("In %s\n", __func__);
1438 for (group = 0; group < 4; group++) {
1439 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1440 break;
1441 }
1442 if (group >= 4)
1443 return;
1444
1445 ctrl_reg = priv->r->mir_ctrl + group * 4;
1446 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1447 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1448
1449 mutex_lock(&priv->reg_mutex);
1450 if (mirror->ingress) {
1451 /* Ingress, clear source port matrix */
1452 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1453 } else {
1454 /* Egress, clear destination port matrix */
1455 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1456 }
1457
1458 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1459 priv->mirror_group_ports[group] = -1;
1460 sw_w32(0, ctrl_reg);
1461 }
1462
1463 mutex_unlock(&priv->reg_mutex);
1464 }
1465
1466 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1467 {
1468 u32 val;
1469 u32 offset = 0;
1470 struct rtl838x_switch_priv *priv = ds->priv;
1471
1472 if (phy_addr >= 24 && phy_addr <= 27
1473 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1474 if (phy_addr == 26)
1475 offset = 0x100;
1476 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1477 return val;
1478 }
1479
1480 read_phy(phy_addr, 0, phy_reg, &val);
1481 return val;
1482 }
1483
1484 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1485 {
1486 u32 offset = 0;
1487 struct rtl838x_switch_priv *priv = ds->priv;
1488
1489 if (phy_addr >= 24 && phy_addr <= 27
1490 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1491 if (phy_addr == 26)
1492 offset = 0x100;
1493 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1494 return 0;
1495 }
1496 return write_phy(phy_addr, 0, phy_reg, val);
1497 }
1498
1499 const struct dsa_switch_ops rtl83xx_switch_ops = {
1500 .get_tag_protocol = rtl83xx_get_tag_protocol,
1501 .setup = rtl83xx_setup,
1502
1503 .phy_read = dsa_phy_read,
1504 .phy_write = dsa_phy_write,
1505
1506 .phylink_validate = rtl83xx_phylink_validate,
1507 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1508 .phylink_mac_config = rtl83xx_phylink_mac_config,
1509 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1510 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1511
1512 .get_strings = rtl83xx_get_strings,
1513 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1514 .get_sset_count = rtl83xx_get_sset_count,
1515
1516 .port_enable = rtl83xx_port_enable,
1517 .port_disable = rtl83xx_port_disable,
1518
1519 .get_mac_eee = rtl83xx_get_mac_eee,
1520 .set_mac_eee = rtl83xx_set_mac_eee,
1521
1522 .set_ageing_time = rtl83xx_set_l2aging,
1523 .port_bridge_join = rtl83xx_port_bridge_join,
1524 .port_bridge_leave = rtl83xx_port_bridge_leave,
1525 .port_stp_state_set = rtl83xx_port_stp_state_set,
1526 .port_fast_age = rtl83xx_fast_age,
1527
1528 .port_vlan_filtering = rtl83xx_vlan_filtering,
1529 .port_vlan_prepare = rtl83xx_vlan_prepare,
1530 .port_vlan_add = rtl83xx_vlan_add,
1531 .port_vlan_del = rtl83xx_vlan_del,
1532
1533 .port_fdb_add = rtl83xx_port_fdb_add,
1534 .port_fdb_del = rtl83xx_port_fdb_del,
1535 .port_fdb_dump = rtl83xx_port_fdb_dump,
1536
1537 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1538 .port_mdb_add = rtl83xx_port_mdb_add,
1539 .port_mdb_del = rtl83xx_port_mdb_del,
1540
1541 .port_mirror_add = rtl83xx_port_mirror_add,
1542 .port_mirror_del = rtl83xx_port_mirror_del,
1543 };
1544
1545 const struct dsa_switch_ops rtl930x_switch_ops = {
1546 .get_tag_protocol = rtl83xx_get_tag_protocol,
1547 .setup = rtl930x_setup,
1548
1549 .phy_read = dsa_phy_read,
1550 .phy_write = dsa_phy_write,
1551
1552 .phylink_validate = rtl83xx_phylink_validate,
1553 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1554 .phylink_mac_config = rtl83xx_phylink_mac_config,
1555 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1556 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1557
1558 .get_strings = rtl83xx_get_strings,
1559 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1560 .get_sset_count = rtl83xx_get_sset_count,
1561
1562 .port_enable = rtl83xx_port_enable,
1563 .port_disable = rtl83xx_port_disable,
1564
1565 .get_mac_eee = rtl93xx_get_mac_eee,
1566 .set_mac_eee = rtl83xx_set_mac_eee,
1567
1568 .set_ageing_time = rtl83xx_set_l2aging,
1569 .port_bridge_join = rtl83xx_port_bridge_join,
1570 .port_bridge_leave = rtl83xx_port_bridge_leave,
1571 .port_stp_state_set = rtl83xx_port_stp_state_set,
1572 .port_fast_age = rtl930x_fast_age,
1573
1574 .port_vlan_filtering = rtl83xx_vlan_filtering,
1575 .port_vlan_prepare = rtl83xx_vlan_prepare,
1576 .port_vlan_add = rtl83xx_vlan_add,
1577 .port_vlan_del = rtl83xx_vlan_del,
1578
1579 .port_fdb_add = rtl83xx_port_fdb_add,
1580 .port_fdb_del = rtl83xx_port_fdb_del,
1581 .port_fdb_dump = rtl83xx_port_fdb_dump,
1582
1583 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1584 .port_mdb_add = rtl83xx_port_mdb_add,
1585 .port_mdb_del = rtl83xx_port_mdb_del,
1586
1587 };
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