1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
10 extern struct rtl83xx_soc_info soc_info
;
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv
*priv
)
15 mutex_lock(&priv
->reg_mutex
);
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
20 if (priv
->family_id
== RTL8380_FAMILY_ID
)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
26 mutex_unlock(&priv
->reg_mutex
);
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i
= 0; i
< priv
->cpu_port
; i
++) {
37 if (priv
->ports
[i
].phy
)
41 pr_info("%s: %16llx\n", __func__
, v
);
42 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv
->family_id
== RTL8390_FAMILY_ID
)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL
);
47 else if(priv
->family_id
== RTL9300_FAMILY_ID
)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
51 const struct rtl83xx_mib_desc rtl83xx_mib
[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
104 static enum dsa_tag_protocol
rtl83xx_get_tag_protocol(struct dsa_switch
*ds
,
106 enum dsa_tag_protocol mprot
)
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
111 return DSA_TAG_PROTO_TRAILER
;
115 * Initialize all VLANS
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv
*priv
)
119 struct rtl838x_vlan_info info
;
122 pr_info("In %s\n", __func__
);
124 priv
->r
->vlan_profile_setup(0);
125 priv
->r
->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv
->r
->read_mcast_pmask(UNKNOWN_MC_PMASK
));
127 priv
->r
->vlan_profile_dump(0);
129 info
.fid
= 0; // Default Forwarding ID / MSTI
130 info
.hash_uc_fid
= false; // Do not build the L2 lookup hash with FID, but VID
131 info
.hash_mc_fid
= false; // Do the same for Multicast packets
132 info
.profile_id
= 0; // Use default Vlan Profile 0
133 info
.tagged_ports
= 0; // Initially no port members
134 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
136 info
.multicast_grp_mask
= 0;
137 info
.l2_tunnel_list_id
= -1;
140 // Initialize all vlans 0-4095
141 for (i
= 0; i
< MAX_VLANS
; i
++)
142 priv
->r
->vlan_set_tagged(i
, &info
);
144 // reset PVIDs; defaults to 1 on reset
145 for (i
= 0; i
<= priv
->ds
->num_ports
; i
++) {
146 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_INNER
, 0);
147 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_OUTER
, 0);
148 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_INNER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
149 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_OUTER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
152 // Set forwarding action based on inner VLAN tag
153 for (i
= 0; i
< priv
->cpu_port
; i
++)
154 priv
->r
->vlan_fwd_on_inner(i
, true);
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv
*priv
)
161 for (i
= 0; i
< priv
->cpu_port
; i
++)
162 priv
->r
->set_receive_management_action(i
, BPDU
, COPY2CPU
);
165 static int rtl83xx_setup(struct dsa_switch
*ds
)
168 struct rtl838x_switch_priv
*priv
= ds
->priv
;
169 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
);
171 pr_debug("%s called\n", __func__
);
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
176 for (i
= 0; i
< ds
->num_ports
; i
++)
177 priv
->ports
[i
].enable
= false;
178 priv
->ports
[priv
->cpu_port
].enable
= true;
180 /* Isolate ports from each other: traffic only CPU <-> port */
181 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
182 * traffic from source port i to destination port j
184 for (i
= 0; i
< priv
->cpu_port
; i
++) {
185 if (priv
->ports
[i
].phy
) {
186 priv
->r
->set_port_reg_be(BIT_ULL(priv
->cpu_port
) | BIT_ULL(i
),
187 priv
->r
->port_iso_ctrl(i
));
188 port_bitmap
|= BIT_ULL(i
);
191 priv
->r
->set_port_reg_be(port_bitmap
, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
193 if (priv
->family_id
== RTL8380_FAMILY_ID
)
194 rtl838x_print_matrix();
196 rtl839x_print_matrix();
198 rtl83xx_init_stats(priv
);
200 rtl83xx_vlan_setup(priv
);
202 rtl83xx_setup_bpdu_traps(priv
);
204 ds
->configure_vlan_while_not_filtering
= true;
206 priv
->r
->l2_learning_setup();
209 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
210 * 0: FWD, 1: DROP, 2: TRAP2CPU
212 if (priv
->family_id
== RTL8380_FAMILY_ID
)
213 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL
);
215 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL
);
217 /* Enable MAC Polling PHY again */
218 rtl83xx_enable_phy_polling(priv
);
219 pr_debug("Please wait until PHY is settled\n");
221 priv
->r
->pie_init(priv
);
226 static int rtl93xx_setup(struct dsa_switch
*ds
)
229 struct rtl838x_switch_priv
*priv
= ds
->priv
;
230 u32 port_bitmap
= BIT(priv
->cpu_port
);
232 pr_info("%s called\n", __func__
);
234 /* Disable MAC polling the PHY so that we can start configuration */
235 if (priv
->family_id
== RTL9300_FAMILY_ID
)
236 sw_w32(0, RTL930X_SMI_POLL_CTRL
);
238 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
239 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
);
240 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
243 // Disable all ports except CPU port
244 for (i
= 0; i
< ds
->num_ports
; i
++)
245 priv
->ports
[i
].enable
= false;
246 priv
->ports
[priv
->cpu_port
].enable
= true;
248 for (i
= 0; i
< priv
->cpu_port
; i
++) {
249 if (priv
->ports
[i
].phy
) {
250 priv
->r
->traffic_set(i
, BIT_ULL(priv
->cpu_port
) | BIT_ULL(i
));
251 port_bitmap
|= BIT_ULL(i
);
254 priv
->r
->traffic_set(priv
->cpu_port
, port_bitmap
);
256 rtl930x_print_matrix();
258 // TODO: Initialize statistics
260 rtl83xx_vlan_setup(priv
);
262 ds
->configure_vlan_while_not_filtering
= true;
264 priv
->r
->l2_learning_setup();
266 rtl83xx_enable_phy_polling(priv
);
268 priv
->r
->pie_init(priv
);
270 priv
->r
->led_init(priv
);
275 static int rtl93xx_get_sds(struct phy_device
*phydev
)
277 struct device
*dev
= &phydev
->mdio
.dev
;
278 struct device_node
*dn
;
285 if (of_property_read_u32(dn
, "sds", &sds_num
))
288 dev_err(dev
, "No DT node.\n");
295 static void rtl83xx_phylink_validate(struct dsa_switch
*ds
, int port
,
296 unsigned long *supported
,
297 struct phylink_link_state
*state
)
299 struct rtl838x_switch_priv
*priv
= ds
->priv
;
300 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
302 pr_debug("In %s port %d, state is %d", __func__
, port
, state
->interface
);
304 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
305 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
306 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
307 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
308 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
309 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
310 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
311 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
312 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
313 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
315 "Unsupported interface: %d for port %d\n",
316 state
->interface
, port
);
320 /* Allow all the expected bits */
321 phylink_set(mask
, Autoneg
);
322 phylink_set_port_modes(mask
);
323 phylink_set(mask
, Pause
);
324 phylink_set(mask
, Asym_Pause
);
326 /* With the exclusion of MII and Reverse MII, we support Gigabit,
327 * including Half duplex
329 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
330 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
331 phylink_set(mask
, 1000baseT_Full
);
332 phylink_set(mask
, 1000baseT_Half
);
335 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
336 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
337 phylink_set(mask
, 1000baseX_Full
);
339 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
340 if (port
>= 48 && port
<= 51 && priv
->family_id
== RTL8390_FAMILY_ID
)
341 phylink_set(mask
, 1000baseX_Full
);
343 phylink_set(mask
, 10baseT_Half
);
344 phylink_set(mask
, 10baseT_Full
);
345 phylink_set(mask
, 100baseT_Half
);
346 phylink_set(mask
, 100baseT_Full
);
348 bitmap_and(supported
, supported
, mask
,
349 __ETHTOOL_LINK_MODE_MASK_NBITS
);
350 bitmap_and(state
->advertising
, state
->advertising
, mask
,
351 __ETHTOOL_LINK_MODE_MASK_NBITS
);
354 static void rtl93xx_phylink_validate(struct dsa_switch
*ds
, int port
,
355 unsigned long *supported
,
356 struct phylink_link_state
*state
)
358 struct rtl838x_switch_priv
*priv
= ds
->priv
;
359 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
361 pr_debug("In %s port %d, state is %d (%s)", __func__
, port
, state
->interface
,
362 phy_modes(state
->interface
));
364 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
365 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
366 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
367 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
368 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
369 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
370 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
371 state
->interface
!= PHY_INTERFACE_MODE_XGMII
&&
372 state
->interface
!= PHY_INTERFACE_MODE_HSGMII
&&
373 state
->interface
!= PHY_INTERFACE_MODE_10GBASER
&&
374 state
->interface
!= PHY_INTERFACE_MODE_10GKR
&&
375 state
->interface
!= PHY_INTERFACE_MODE_USXGMII
&&
376 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
377 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
378 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
380 "Unsupported interface: %d for port %d\n",
381 state
->interface
, port
);
385 /* Allow all the expected bits */
386 phylink_set(mask
, Autoneg
);
387 phylink_set_port_modes(mask
);
388 phylink_set(mask
, Pause
);
389 phylink_set(mask
, Asym_Pause
);
391 /* With the exclusion of MII and Reverse MII, we support Gigabit,
392 * including Half duplex
394 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
395 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
396 phylink_set(mask
, 1000baseT_Full
);
397 phylink_set(mask
, 1000baseT_Half
);
400 // Internal phys of the RTL93xx family provide 10G
401 if (priv
->ports
[port
].phy_is_integrated
402 && state
->interface
== PHY_INTERFACE_MODE_1000BASEX
) {
403 phylink_set(mask
, 1000baseX_Full
);
404 } else if (priv
->ports
[port
].phy_is_integrated
) {
405 phylink_set(mask
, 1000baseX_Full
);
406 phylink_set(mask
, 10000baseKR_Full
);
407 phylink_set(mask
, 10000baseSR_Full
);
408 phylink_set(mask
, 10000baseCR_Full
);
410 if (state
->interface
== PHY_INTERFACE_MODE_INTERNAL
) {
411 phylink_set(mask
, 1000baseX_Full
);
412 phylink_set(mask
, 1000baseT_Full
);
413 phylink_set(mask
, 10000baseKR_Full
);
414 phylink_set(mask
, 10000baseT_Full
);
415 phylink_set(mask
, 10000baseSR_Full
);
416 phylink_set(mask
, 10000baseCR_Full
);
419 if (state
->interface
== PHY_INTERFACE_MODE_USXGMII
)
420 phylink_set(mask
, 10000baseT_Full
);
422 phylink_set(mask
, 10baseT_Half
);
423 phylink_set(mask
, 10baseT_Full
);
424 phylink_set(mask
, 100baseT_Half
);
425 phylink_set(mask
, 100baseT_Full
);
427 bitmap_and(supported
, supported
, mask
,
428 __ETHTOOL_LINK_MODE_MASK_NBITS
);
429 bitmap_and(state
->advertising
, state
->advertising
, mask
,
430 __ETHTOOL_LINK_MODE_MASK_NBITS
);
431 pr_debug("%s leaving supported: %*pb", __func__
, __ETHTOOL_LINK_MODE_MASK_NBITS
, supported
);
434 static int rtl83xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
435 struct phylink_link_state
*state
)
437 struct rtl838x_switch_priv
*priv
= ds
->priv
;
441 if (port
< 0 || port
> priv
->cpu_port
)
445 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
446 if (link
& BIT_ULL(port
))
448 pr_debug("%s: link state port %d: %llx\n", __func__
, port
, link
& BIT_ULL(port
));
451 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
454 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
455 speed
>>= (port
% 16) << 1;
456 switch (speed
& 0x3) {
458 state
->speed
= SPEED_10
;
461 state
->speed
= SPEED_100
;
464 state
->speed
= SPEED_1000
;
467 if (priv
->family_id
== RTL9300_FAMILY_ID
468 && (port
== 24 || port
== 26)) /* Internal serdes */
469 state
->speed
= SPEED_2500
;
471 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
474 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
475 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
476 state
->pause
|= MLO_PAUSE_RX
;
477 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
478 state
->pause
|= MLO_PAUSE_TX
;
482 static int rtl93xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
483 struct phylink_link_state
*state
)
485 struct rtl838x_switch_priv
*priv
= ds
->priv
;
490 if (port
< 0 || port
> priv
->cpu_port
)
494 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
495 * state needs to be read twice in order to read a correct result.
496 * This would not be necessary for ports connected e.g. to RTL8218D
500 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
501 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
502 if (link
& BIT_ULL(port
))
505 if (priv
->family_id
== RTL9310_FAMILY_ID
)
506 media
= priv
->r
->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS
);
508 if (priv
->family_id
== RTL9300_FAMILY_ID
)
509 media
= sw_r32(RTL930X_MAC_LINK_MEDIA_STS
);
511 if (media
& BIT_ULL(port
))
514 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__
, port
,
515 link
& BIT_ULL(port
), media
);
518 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
521 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
522 speed
>>= (port
% 8) << 2;
523 switch (speed
& 0xf) {
525 state
->speed
= SPEED_10
;
528 state
->speed
= SPEED_100
;
532 state
->speed
= SPEED_1000
;
535 state
->speed
= SPEED_10000
;
539 state
->speed
= SPEED_2500
;
542 state
->speed
= SPEED_5000
;
545 pr_err("%s: unknown speed: %d\n", __func__
, (u32
)speed
& 0xf);
548 if (priv
->family_id
== RTL9310_FAMILY_ID
549 && (port
>= 52 || port
<= 55)) { /* Internal serdes */
550 state
->speed
= SPEED_10000
;
555 pr_debug("%s: speed is: %d %d\n", __func__
, (u32
)speed
& 0xf, state
->speed
);
556 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
557 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
558 state
->pause
|= MLO_PAUSE_RX
;
559 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
560 state
->pause
|= MLO_PAUSE_TX
;
564 static void rtl83xx_config_interface(int port
, phy_interface_t interface
)
566 u32 old
, int_shift
, sds_shift
;
581 old
= sw_r32(RTL838X_SDS_MODE_SEL
);
583 case PHY_INTERFACE_MODE_1000BASEX
:
584 if ((old
>> sds_shift
& 0x1f) == 4)
586 sw_w32_mask(0x7 << int_shift
, 1 << int_shift
, RTL838X_INT_MODE_CTRL
);
587 sw_w32_mask(0x1f << sds_shift
, 4 << sds_shift
, RTL838X_SDS_MODE_SEL
);
589 case PHY_INTERFACE_MODE_SGMII
:
590 if ((old
>> sds_shift
& 0x1f) == 2)
592 sw_w32_mask(0x7 << int_shift
, 2 << int_shift
, RTL838X_INT_MODE_CTRL
);
593 sw_w32_mask(0x1f << sds_shift
, 2 << sds_shift
, RTL838X_SDS_MODE_SEL
);
598 pr_debug("configured port %d for interface %s\n", port
, phy_modes(interface
));
601 static void rtl83xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
603 const struct phylink_link_state
*state
)
605 struct rtl838x_switch_priv
*priv
= ds
->priv
;
607 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
609 pr_debug("%s port %d, mode %x\n", __func__
, port
, mode
);
611 if (port
== priv
->cpu_port
) {
612 /* Set Speed, duplex, flow control
613 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
614 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
617 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
618 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
619 /* allow CRC errors on CPU-port */
620 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
622 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
627 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
628 /* Auto-Negotiation does not work for MAC in RTL8390 */
629 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
630 if (mode
== MLO_AN_PHY
|| phylink_autoneg_inband(mode
)) {
631 pr_debug("PHY autonegotiates\n");
632 reg
|= RTL838X_NWAY_EN
;
633 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
634 rtl83xx_config_interface(port
, state
->interface
);
639 if (mode
!= MLO_AN_FIXED
)
640 pr_debug("Fixed state.\n");
642 /* Clear id_mode_dis bit, and the existing port mode, let
643 * RGMII_MODE_EN bet set by mac_link_{up,down} */
644 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
645 reg
&= ~(RTL838X_RX_PAUSE_EN
| RTL838X_TX_PAUSE_EN
);
646 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
647 if (state
->pause
& MLO_PAUSE_TX
)
648 reg
|= RTL838X_TX_PAUSE_EN
;
649 reg
|= RTL838X_RX_PAUSE_EN
;
651 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
652 reg
&= ~(RTL839X_RX_PAUSE_EN
| RTL839X_TX_PAUSE_EN
);
653 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
654 if (state
->pause
& MLO_PAUSE_TX
)
655 reg
|= RTL839X_TX_PAUSE_EN
;
656 reg
|= RTL839X_RX_PAUSE_EN
;
661 reg
&= ~(3 << speed_bit
);
662 switch (state
->speed
) {
664 reg
|= 2 << speed_bit
;
667 reg
|= 1 << speed_bit
;
670 break; // Ignore, including 10MBit which has a speed value of 0
673 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
674 reg
&= ~(RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
676 reg
|= RTL838X_FORCE_LINK_EN
;
677 if (state
->duplex
== RTL838X_DUPLEX_MODE
)
678 reg
|= RTL838X_DUPLEX_MODE
;
679 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
680 reg
&= ~(RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
682 reg
|= RTL839X_FORCE_LINK_EN
;
683 if (state
->duplex
== RTL839X_DUPLEX_MODE
)
684 reg
|= RTL839X_DUPLEX_MODE
;
687 // LAG members must use DUPLEX and we need to enable the link
688 if (priv
->lagmembers
& BIT_ULL(port
)) {
689 switch(priv
->family_id
) {
690 case RTL8380_FAMILY_ID
:
691 reg
|= (RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
693 case RTL8390_FAMILY_ID
:
694 reg
|= (RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
700 if (priv
->family_id
== RTL8380_FAMILY_ID
)
701 reg
&= ~RTL838X_NWAY_EN
;
702 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
705 static void rtl931x_phylink_mac_config(struct dsa_switch
*ds
, int port
,
707 const struct phylink_link_state
*state
)
709 struct rtl838x_switch_priv
*priv
= ds
->priv
;
713 sds_num
= priv
->ports
[port
].sds_num
;
714 pr_info("%s: speed %d sds_num %d\n", __func__
, state
->speed
, sds_num
);
716 switch (state
->interface
) {
717 case PHY_INTERFACE_MODE_HSGMII
:
718 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__
);
719 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
720 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
721 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_HSGMII
);
723 case PHY_INTERFACE_MODE_1000BASEX
:
724 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
725 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
727 case PHY_INTERFACE_MODE_XGMII
:
728 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_XGMII
);
729 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_XGMII
);
731 case PHY_INTERFACE_MODE_10GBASER
:
732 case PHY_INTERFACE_MODE_10GKR
:
733 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
734 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
736 case PHY_INTERFACE_MODE_USXGMII
:
737 // Translates to MII_USXGMII_10GSXGMII
738 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
739 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
741 case PHY_INTERFACE_MODE_SGMII
:
742 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__
);
743 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_SGMII
);
744 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_SGMII
);
745 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_SGMII
);
747 case PHY_INTERFACE_MODE_QSGMII
:
748 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
749 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
752 pr_err("%s: unknown serdes mode: %s\n",
753 __func__
, phy_modes(state
->interface
));
757 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
758 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__
, reg
);
760 reg
&= ~(RTL931X_DUPLEX_MODE
| RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
);
763 reg
|= 0x2 << 12; // Set SMI speed to 0x2
765 reg
|= RTL931X_TX_PAUSE_EN
| RTL931X_RX_PAUSE_EN
;
767 if (priv
->lagmembers
& BIT_ULL(port
))
768 reg
|= RTL931X_DUPLEX_MODE
;
770 if (state
->duplex
== DUPLEX_FULL
)
771 reg
|= RTL931X_DUPLEX_MODE
;
773 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
777 static void rtl93xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
779 const struct phylink_link_state
*state
)
781 struct rtl838x_switch_priv
*priv
= ds
->priv
;
782 int sds_num
, sds_mode
;
785 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__
,
786 port
, mode
, phy_modes(state
->interface
), state
->speed
, state
->link
);
788 // Nothing to be done for the CPU-port
789 if (port
== priv
->cpu_port
)
792 if (priv
->family_id
== RTL9310_FAMILY_ID
)
793 return rtl931x_phylink_mac_config(ds
, port
, mode
, state
);
795 sds_num
= priv
->ports
[port
].sds_num
;
796 pr_info("%s SDS is %d\n", __func__
, sds_num
);
798 switch (state
->interface
) {
799 case PHY_INTERFACE_MODE_HSGMII
:
802 case PHY_INTERFACE_MODE_1000BASEX
:
805 case PHY_INTERFACE_MODE_XGMII
:
808 case PHY_INTERFACE_MODE_10GBASER
:
809 case PHY_INTERFACE_MODE_10GKR
:
810 sds_mode
= 0x1b; // 10G 1000X Auto
812 case PHY_INTERFACE_MODE_USXGMII
:
816 pr_err("%s: unknown serdes mode: %s\n",
817 __func__
, phy_modes(state
->interface
));
820 if (state
->interface
== PHY_INTERFACE_MODE_10GBASER
)
821 rtl9300_serdes_setup(sds_num
, state
->interface
);
824 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
827 switch (state
->speed
) {
846 reg
|= RTL930X_FORCE_LINK_EN
;
848 if (priv
->lagmembers
& BIT_ULL(port
))
849 reg
|= RTL930X_DUPLEX_MODE
| RTL930X_FORCE_LINK_EN
;
851 if (state
->duplex
== DUPLEX_FULL
)
852 reg
|= RTL930X_DUPLEX_MODE
;
854 if (priv
->ports
[port
].phy_is_integrated
)
855 reg
&= ~RTL930X_FORCE_EN
; // Clear MAC_FORCE_EN to allow SDS-MAC link
857 reg
|= RTL930X_FORCE_EN
;
859 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
862 static void rtl83xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
864 phy_interface_t interface
)
866 struct rtl838x_switch_priv
*priv
= ds
->priv
;
869 /* Stop TX/RX to port */
870 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
872 // No longer force link
873 if (priv
->family_id
== RTL9300_FAMILY_ID
)
874 v
= RTL930X_FORCE_EN
| RTL930X_FORCE_LINK_EN
;
875 else if (priv
->family_id
== RTL9310_FAMILY_ID
)
876 v
= RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
;
877 sw_w32_mask(v
, 0, priv
->r
->mac_port_ctrl(port
));
880 static void rtl93xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
882 phy_interface_t interface
)
884 struct rtl838x_switch_priv
*priv
= ds
->priv
;
885 /* Stop TX/RX to port */
886 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
888 // No longer force link
889 sw_w32_mask(3, 0, priv
->r
->mac_force_mode_ctrl(port
));
892 static void rtl83xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
894 phy_interface_t interface
,
895 struct phy_device
*phydev
,
896 int speed
, int duplex
,
897 bool tx_pause
, bool rx_pause
)
899 struct rtl838x_switch_priv
*priv
= ds
->priv
;
900 /* Restart TX/RX to port */
901 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
902 // TODO: Set speed/duplex/pauses
905 static void rtl93xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
907 phy_interface_t interface
,
908 struct phy_device
*phydev
,
909 int speed
, int duplex
,
910 bool tx_pause
, bool rx_pause
)
912 struct rtl838x_switch_priv
*priv
= ds
->priv
;
914 /* Restart TX/RX to port */
915 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
916 // TODO: Set speed/duplex/pauses
919 static void rtl83xx_get_strings(struct dsa_switch
*ds
,
920 int port
, u32 stringset
, u8
*data
)
924 if (stringset
!= ETH_SS_STATS
)
927 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++)
928 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl83xx_mib
[i
].name
,
932 static void rtl83xx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
935 struct rtl838x_switch_priv
*priv
= ds
->priv
;
936 const struct rtl83xx_mib_desc
*mib
;
940 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++) {
941 mib
= &rtl83xx_mib
[i
];
943 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 252 - mib
->offset
);
944 if (mib
->size
== 2) {
945 h
= sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 248 - mib
->offset
);
951 static int rtl83xx_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
953 if (sset
!= ETH_SS_STATS
)
956 return ARRAY_SIZE(rtl83xx_mib
);
959 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv
*priv
, int port
)
961 int mc_group
= find_first_zero_bit(priv
->mc_group_bm
, MAX_MC_GROUPS
- 1);
964 if (mc_group
>= MAX_MC_GROUPS
- 1)
967 if (priv
->is_lagmember
[port
]) {
968 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
972 set_bit(mc_group
, priv
->mc_group_bm
);
973 mc_group
++; // We cannot use group 0, as this is used for lookup miss flooding
974 portmask
= BIT_ULL(port
) | BIT_ULL(priv
->cpu_port
);
975 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
980 static u64
rtl83xx_mc_group_add_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
982 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
984 pr_debug("%s: %d\n", __func__
, port
);
985 if (priv
->is_lagmember
[port
]) {
986 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
989 portmask
|= BIT_ULL(port
);
990 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
995 static u64
rtl83xx_mc_group_del_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
997 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
999 pr_debug("%s: %d\n", __func__
, port
);
1000 if (priv
->is_lagmember
[port
]) {
1001 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1004 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1005 if (portmask
== BIT_ULL(priv
->cpu_port
)) {
1006 portmask
&= ~BIT_ULL(priv
->cpu_port
);
1007 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1008 clear_bit(mc_group
, priv
->mc_group_bm
);
1014 static void store_mcgroups(struct rtl838x_switch_priv
*priv
, int port
)
1018 for (mc_group
= 0; mc_group
< MAX_MC_GROUPS
; mc_group
++) {
1019 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
1020 if (portmask
& BIT_ULL(port
)) {
1021 priv
->mc_group_saves
[mc_group
] = port
;
1022 rtl83xx_mc_group_del_port(priv
, mc_group
, port
);
1027 static void load_mcgroups(struct rtl838x_switch_priv
*priv
, int port
)
1031 for (mc_group
= 0; mc_group
< MAX_MC_GROUPS
; mc_group
++) {
1032 if (priv
->mc_group_saves
[mc_group
] == port
) {
1033 rtl83xx_mc_group_add_port(priv
, mc_group
, port
);
1034 priv
->mc_group_saves
[mc_group
] = -1;
1039 static int rtl83xx_port_enable(struct dsa_switch
*ds
, int port
,
1040 struct phy_device
*phydev
)
1042 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1045 pr_debug("%s: %x %d", __func__
, (u32
) priv
, port
);
1046 priv
->ports
[port
].enable
= true;
1048 /* enable inner tagging on egress, do not keep any tags */
1049 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1050 sw_w32(BIT(4), priv
->r
->vlan_port_tag_sts_ctrl
+ (port
<< 2));
1052 sw_w32(1, priv
->r
->vlan_port_tag_sts_ctrl
+ (port
<< 2));
1054 if (dsa_is_cpu_port(ds
, port
))
1057 /* add port to switch mask of CPU_PORT */
1058 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1060 load_mcgroups(priv
, port
);
1062 if (priv
->is_lagmember
[port
]) {
1063 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1067 /* add all other ports in the same bridge to switch mask of port */
1068 v
= priv
->r
->traffic_get(port
);
1069 v
|= priv
->ports
[port
].pm
;
1070 priv
->r
->traffic_set(port
, v
);
1072 // TODO: Figure out if this is necessary
1073 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
1074 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_SABLK_CTRL
);
1075 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_DABLK_CTRL
);
1078 if (priv
->ports
[port
].sds_num
< 0)
1079 priv
->ports
[port
].sds_num
= rtl93xx_get_sds(phydev
);
1084 static void rtl83xx_port_disable(struct dsa_switch
*ds
, int port
)
1086 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1089 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1090 /* you can only disable user ports */
1091 if (!dsa_is_user_port(ds
, port
))
1094 // BUG: This does not work on RTL931X
1095 /* remove port from switch mask of CPU_PORT */
1096 priv
->r
->traffic_disable(priv
->cpu_port
, port
);
1097 store_mcgroups(priv
, port
);
1099 /* remove all other ports in the same bridge from switch mask of port */
1100 v
= priv
->r
->traffic_get(port
);
1101 v
&= ~priv
->ports
[port
].pm
;
1102 priv
->r
->traffic_set(port
, v
);
1104 priv
->ports
[port
].enable
= false;
1107 static int rtl83xx_set_mac_eee(struct dsa_switch
*ds
, int port
,
1108 struct ethtool_eee
*e
)
1110 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1112 if (e
->eee_enabled
&& !priv
->eee_enabled
) {
1113 pr_info("Globally enabling EEE\n");
1114 priv
->r
->init_eee(priv
, true);
1117 priv
->r
->port_eee_set(priv
, port
, e
->eee_enabled
);
1120 pr_info("Enabled EEE for port %d\n", port
);
1122 pr_info("Disabled EEE for port %d\n", port
);
1126 static int rtl83xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1127 struct ethtool_eee
*e
)
1129 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1131 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
1133 priv
->r
->eee_port_ability(priv
, e
, port
);
1135 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1137 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1142 static int rtl93xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1143 struct ethtool_eee
*e
)
1145 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1147 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
1148 | SUPPORTED_2500baseX_Full
;
1150 priv
->r
->eee_port_ability(priv
, e
, port
);
1152 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1154 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1159 static int rtl83xx_set_ageing_time(struct dsa_switch
*ds
, unsigned int msec
)
1161 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1163 priv
->r
->set_ageing_time(msec
);
1167 static int rtl83xx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1168 struct net_device
*bridge
)
1170 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1171 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
), v
;
1174 pr_debug("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
1176 if (priv
->is_lagmember
[port
]) {
1177 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1181 mutex_lock(&priv
->reg_mutex
);
1182 for (i
= 0; i
< ds
->num_ports
; i
++) {
1183 /* Add this port to the port matrix of the other ports in the
1184 * same bridge. If the port is disabled, port matrix is kept
1185 * and not being setup until the port becomes enabled.
1187 if (dsa_is_user_port(ds
, i
) && !priv
->is_lagmember
[i
] && i
!= port
) {
1188 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1190 if (priv
->ports
[i
].enable
)
1191 priv
->r
->traffic_enable(i
, port
);
1193 priv
->ports
[i
].pm
|= BIT_ULL(port
);
1194 port_bitmap
|= BIT_ULL(i
);
1197 load_mcgroups(priv
, port
);
1199 /* Add all other ports to this port matrix. */
1200 if (priv
->ports
[port
].enable
) {
1201 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1202 v
= priv
->r
->traffic_get(port
);
1204 priv
->r
->traffic_set(port
, v
);
1206 priv
->ports
[port
].pm
|= port_bitmap
;
1207 mutex_unlock(&priv
->reg_mutex
);
1212 static void rtl83xx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1213 struct net_device
*bridge
)
1215 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1216 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
), v
;
1219 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1220 mutex_lock(&priv
->reg_mutex
);
1221 for (i
= 0; i
< ds
->num_ports
; i
++) {
1222 /* Remove this port from the port matrix of the other ports
1223 * in the same bridge. If the port is disabled, port matrix
1224 * is kept and not being setup until the port becomes enabled.
1225 * And the other port's port matrix cannot be broken when the
1226 * other port is still a VLAN-aware port.
1228 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
1229 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1231 if (priv
->ports
[i
].enable
)
1232 priv
->r
->traffic_disable(i
, port
);
1234 priv
->ports
[i
].pm
|= BIT_ULL(port
);
1235 port_bitmap
&= ~BIT_ULL(i
);
1238 store_mcgroups(priv
, port
);
1240 /* Add all other ports to this port matrix. */
1241 if (priv
->ports
[port
].enable
) {
1242 v
= priv
->r
->traffic_get(port
);
1244 priv
->r
->traffic_set(port
, v
);
1246 priv
->ports
[port
].pm
&= ~port_bitmap
;
1248 mutex_unlock(&priv
->reg_mutex
);
1251 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1257 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1258 int n
= priv
->port_width
<< 1;
1260 /* Ports above or equal CPU port can never be configured */
1261 if (port
>= priv
->cpu_port
)
1264 mutex_lock(&priv
->reg_mutex
);
1266 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1267 * have 64 bit fields, 839x and 931x have 128 bit fields
1269 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1271 if (priv
->family_id
== RTL9300_FAMILY_ID
)
1273 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1276 index
= n
- (pos
>> 4) - 1;
1277 bit
= (pos
<< 1) % 32;
1279 priv
->r
->stp_get(priv
, msti
, port_state
);
1281 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
1282 port_state
[index
] &= ~(3 << bit
);
1285 case BR_STATE_DISABLED
: /* 0 */
1286 port_state
[index
] |= (0 << bit
);
1288 case BR_STATE_BLOCKING
: /* 4 */
1289 case BR_STATE_LISTENING
: /* 1 */
1290 port_state
[index
] |= (1 << bit
);
1292 case BR_STATE_LEARNING
: /* 2 */
1293 port_state
[index
] |= (2 << bit
);
1295 case BR_STATE_FORWARDING
: /* 3*/
1296 port_state
[index
] |= (3 << bit
);
1301 priv
->r
->stp_set(priv
, msti
, port_state
);
1303 mutex_unlock(&priv
->reg_mutex
);
1306 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
)
1308 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1309 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
1311 pr_debug("FAST AGE port %d\n", port
);
1312 mutex_lock(&priv
->reg_mutex
);
1313 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1315 * 0-4: Replacing port
1316 * 5-9: Flushed/replaced port
1318 * 22: Entry types: 1: dynamic, 0: also static
1319 * 23: Match flush port
1321 * 25: Flush (0) or replace (1) L2 entries
1322 * 26: Status of action (1: Start, 0: Done)
1324 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
1326 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(26 + s
));
1328 mutex_unlock(&priv
->reg_mutex
);
1331 void rtl931x_fast_age(struct dsa_switch
*ds
, int port
)
1333 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1335 pr_info("%s port %d\n", __func__
, port
);
1336 mutex_lock(&priv
->reg_mutex
);
1337 sw_w32(port
<< 11, RTL931X_L2_TBL_FLUSH_CTRL
+ 4);
1339 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL
);
1341 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL
) & BIT (28));
1343 mutex_unlock(&priv
->reg_mutex
);
1346 void rtl930x_fast_age(struct dsa_switch
*ds
, int port
)
1348 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1350 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1351 return rtl931x_fast_age(ds
, port
);
1353 pr_debug("FAST AGE port %d\n", port
);
1354 mutex_lock(&priv
->reg_mutex
);
1355 sw_w32(port
<< 11, RTL930X_L2_TBL_FLUSH_CTRL
+ 4);
1357 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL
);
1359 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(30));
1361 mutex_unlock(&priv
->reg_mutex
);
1364 static int rtl83xx_vlan_filtering(struct dsa_switch
*ds
, int port
,
1365 bool vlan_filtering
,
1366 struct switchdev_trans
*trans
)
1368 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1370 pr_debug("%s: port %d\n", __func__
, port
);
1371 mutex_lock(&priv
->reg_mutex
);
1373 if (vlan_filtering
) {
1374 /* Enable ingress and egress filtering
1375 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1376 * the filter action:
1379 * 2: Trap packet to CPU port
1380 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1382 if (port
!= priv
->cpu_port
)
1383 priv
->r
->set_vlan_igr_filter(port
, IGR_DROP
);
1385 priv
->r
->set_vlan_egr_filter(port
, EGR_ENABLE
);
1387 /* Disable ingress and egress filtering */
1388 if (port
!= priv
->cpu_port
)
1389 priv
->r
->set_vlan_igr_filter(port
, IGR_FORWARD
);
1391 priv
->r
->set_vlan_egr_filter(port
, EGR_DISABLE
);
1394 /* Do we need to do something to the CPU-Port, too? */
1395 mutex_unlock(&priv
->reg_mutex
);
1400 static int rtl83xx_vlan_prepare(struct dsa_switch
*ds
, int port
,
1401 const struct switchdev_obj_port_vlan
*vlan
)
1403 struct rtl838x_vlan_info info
;
1404 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1406 priv
->r
->vlan_tables_read(0, &info
);
1408 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1409 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1410 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1412 priv
->r
->vlan_tables_read(1, &info
);
1413 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1414 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1415 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1416 priv
->r
->vlan_set_untagged(1, info
.untagged_ports
);
1417 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info
.untagged_ports
);
1419 priv
->r
->vlan_set_tagged(1, &info
);
1420 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info
.tagged_ports
);
1425 static void rtl83xx_vlan_add(struct dsa_switch
*ds
, int port
,
1426 const struct switchdev_obj_port_vlan
*vlan
)
1428 struct rtl838x_vlan_info info
;
1429 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1432 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
1433 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
1435 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
1436 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
1437 vlan
->vid_begin
, vlan
->vid_end
);
1441 mutex_lock(&priv
->reg_mutex
);
1443 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
) {
1444 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1447 /* Set both inner and outer PVID of the port */
1448 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_INNER
, v
);
1449 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_OUTER
, v
);
1450 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_INNER
,
1451 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1452 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_OUTER
,
1453 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1455 priv
->ports
[port
].pvid
= vlan
->vid_end
;
1459 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1460 /* Get port memberships of this vlan */
1461 priv
->r
->vlan_tables_read(v
, &info
);
1464 if (!info
.tagged_ports
) {
1466 info
.hash_mc_fid
= false;
1467 info
.hash_uc_fid
= false;
1468 info
.profile_id
= 0;
1471 /* sanitize untagged_ports - must be a subset */
1472 if (info
.untagged_ports
& ~info
.tagged_ports
)
1473 info
.untagged_ports
= 0;
1475 info
.tagged_ports
|= BIT_ULL(port
);
1476 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
1477 info
.untagged_ports
|= BIT_ULL(port
);
1479 priv
->r
->vlan_set_untagged(v
, info
.untagged_ports
);
1480 pr_debug("Untagged ports, VLAN %d: %llx\n", v
, info
.untagged_ports
);
1482 priv
->r
->vlan_set_tagged(v
, &info
);
1483 pr_debug("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
1486 mutex_unlock(&priv
->reg_mutex
);
1489 static int rtl83xx_vlan_del(struct dsa_switch
*ds
, int port
,
1490 const struct switchdev_obj_port_vlan
*vlan
)
1492 struct rtl838x_vlan_info info
;
1493 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1497 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
1498 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
1500 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
1501 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
1502 vlan
->vid_begin
, vlan
->vid_end
);
1506 mutex_lock(&priv
->reg_mutex
);
1507 pvid
= priv
->ports
[port
].pvid
;
1509 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1510 /* Reset to default if removing the current PVID */
1512 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_INNER
, 0);
1513 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_OUTER
, 0);
1514 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_INNER
,
1515 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1516 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_OUTER
,
1517 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1519 /* Get port memberships of this vlan */
1520 priv
->r
->vlan_tables_read(v
, &info
);
1522 /* remove port from both tables */
1523 info
.untagged_ports
&= (~BIT_ULL(port
));
1524 info
.tagged_ports
&= (~BIT_ULL(port
));
1526 priv
->r
->vlan_set_untagged(v
, info
.untagged_ports
);
1527 pr_debug("Untagged ports, VLAN %d: %llx\n", v
, info
.untagged_ports
);
1529 priv
->r
->vlan_set_tagged(v
, &info
);
1530 pr_debug("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
1532 mutex_unlock(&priv
->reg_mutex
);
1537 static void dump_l2_entry(struct rtl838x_l2_entry
*e
)
1539 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1540 e
->mac
[0], e
->mac
[1], e
->mac
[2], e
->mac
[3], e
->mac
[4], e
->mac
[5],
1541 e
->vid
, e
->rvid
, e
->port
, e
->valid
);
1543 if (e
->type
!= L2_MULTICAST
) {
1544 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1545 e
->type
, e
->is_static
, e
->is_ip_mc
, e
->is_ipv6_mc
, e
->block_da
);
1546 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1547 e
->block_sa
, e
->suspended
, e
->next_hop
, e
->age
, e
->is_trunk
, e
->trunk
);
1549 if (e
->type
== L2_MULTICAST
)
1550 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e
->mc_portmask_index
);
1551 if (e
->is_ip_mc
|| e
->is_ipv6_mc
)
1552 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1553 e
->mc_portmask_index
, e
->mc_gip
, e
->mc_sip
);
1554 pr_info(" stack_dev: %d\n", e
->stack_dev
);
1556 pr_info(" nh_route_id: %d\n", e
->nh_route_id
);
1559 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry
*e
, int port
, int vid
, u64 mac
)
1561 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1566 u64_to_ether_addr(mac
, e
->mac
);
1569 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv
*priv
,
1570 struct rtl838x_l2_entry
*e
, int vid
, u64 mac
, int mc_group
)
1572 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1574 e
->mc_portmask_index
= mc_group
;
1575 e
->type
= L2_MULTICAST
;
1576 e
->rvid
= e
->vid
= vid
;
1577 pr_debug("%s: vid: %d, rvid: %d\n", __func__
, e
->vid
, e
->rvid
);
1578 u64_to_ether_addr(mac
, e
->mac
);
1582 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1583 * over the entries in the bucket until either a matching entry is found or an empty slot
1584 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1585 * when an empty slot was found and must exist is false, the index of the slot is returned
1586 * when no slots are available returns -1
1588 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1589 bool must_exist
, struct rtl838x_l2_entry
*e
)
1592 u32 key
= priv
->r
->l2_hash_key(priv
, seed
);
1595 pr_debug("%s: using key %x, for seed %016llx\n", __func__
, key
, seed
);
1596 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1597 for (i
= 0; i
< priv
->l2_bucket_size
; i
++) {
1598 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, e
);
1599 pr_debug("valid %d, mac %016llx\n", e
->valid
, ether_addr_to_u64(&e
->mac
[0]));
1600 if (must_exist
&& !e
->valid
)
1602 if (!e
->valid
|| ((entry
& 0x0fffffffffffffffULL
) == seed
)) {
1603 idx
= i
> 3 ? ((key
>> 14) & 0xffff) | i
>> 1 : ((key
<< 2) | i
) & 0xffff;
1612 * Uses the seed to identify an entry in the CAM by looping over all its entries
1613 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1614 * when an empty slot was found the index of the slot is returned
1615 * when no slots are available returns -1
1617 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1618 bool must_exist
, struct rtl838x_l2_entry
*e
)
1623 for (i
= 0; i
< 64; i
++) {
1624 entry
= priv
->r
->read_cam(i
, e
);
1625 if (!must_exist
&& !e
->valid
) {
1626 if (idx
< 0) /* First empty entry? */
1629 } else if ((entry
& 0x0fffffffffffffffULL
) == seed
) {
1630 pr_debug("Found entry in CAM\n");
1638 static int rtl83xx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1639 const unsigned char *addr
, u16 vid
)
1641 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1642 u64 mac
= ether_addr_to_u64(addr
);
1643 struct rtl838x_l2_entry e
;
1645 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1647 if (priv
->is_lagmember
[port
]) {
1648 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1652 mutex_lock(&priv
->reg_mutex
);
1654 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1656 // Found an existing or empty entry
1658 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1659 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1663 // Hash buckets full, try CAM
1664 rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1667 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1668 priv
->r
->write_cam(idx
, &e
);
1674 mutex_unlock(&priv
->reg_mutex
);
1678 static int rtl83xx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1679 const unsigned char *addr
, u16 vid
)
1681 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1682 u64 mac
= ether_addr_to_u64(addr
);
1683 struct rtl838x_l2_entry e
;
1685 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1687 pr_info("In %s, mac %llx, vid: %d\n", __func__
, mac
, vid
);
1688 mutex_lock(&priv
->reg_mutex
);
1690 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1693 pr_info("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1696 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1700 /* Check CAM for spillover from hash buckets */
1701 rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1705 priv
->r
->write_cam(idx
, &e
);
1710 mutex_unlock(&priv
->reg_mutex
);
1714 static int rtl83xx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1715 dsa_fdb_dump_cb_t
*cb
, void *data
)
1717 struct rtl838x_l2_entry e
;
1718 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1723 mutex_lock(&priv
->reg_mutex
);
1725 for (i
= 0; i
< priv
->fib_entries
; i
++) {
1726 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1731 if (e
.port
== port
|| e
.port
== RTL930X_PORT_IGNORE
) {
1735 fid
= ((i
>> 2) & 0x3ff) | (e
.rvid
& ~0x3ff);
1736 mac
= ether_addr_to_u64(&e
.mac
[0]);
1737 pkey
= priv
->r
->l2_hash_key(priv
, priv
->r
->l2_hash_seed(mac
, fid
));
1738 fid
= (pkey
& 0x3ff) | (fid
& ~0x3ff);
1739 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1740 i
, i
>> 2, i
& 0x3, mac
, fid
, e
.rvid
);
1742 seed
= priv
->r
->l2_hash_seed(mac
, e
.rvid
);
1743 key
= priv
->r
->l2_hash_key(priv
, seed
);
1744 pr_info("seed: %016llx, key based on rvid: %08x\n", seed
, key
);
1745 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1747 if (e
.type
== L2_MULTICAST
) {
1748 u64 portmask
= priv
->r
->read_mcast_pmask(e
.mc_portmask_index
);
1750 if (portmask
& BIT_ULL(port
)) {
1752 pr_info(" PM: %016llx\n", portmask
);
1757 for (i
= 0; i
< 64; i
++) {
1758 priv
->r
->read_cam(i
, &e
);
1764 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1767 mutex_unlock(&priv
->reg_mutex
);
1771 static int rtl83xx_port_mdb_prepare(struct dsa_switch
*ds
, int port
,
1772 const struct switchdev_obj_port_mdb
*mdb
)
1774 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1776 if (priv
->id
>= 0x9300)
1782 static void rtl83xx_port_mdb_add(struct dsa_switch
*ds
, int port
,
1783 const struct switchdev_obj_port_mdb
*mdb
)
1785 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1786 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1787 struct rtl838x_l2_entry e
;
1790 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1793 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1795 if (priv
->is_lagmember
[port
]) {
1796 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1800 mutex_lock(&priv
->reg_mutex
);
1802 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1804 // Found an existing or empty entry
1807 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1808 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1809 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1811 pr_debug("New entry for seed %016llx\n", seed
);
1812 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1817 rtl83xx_setup_l2_mc_entry(priv
, &e
, vid
, mac
, mc_group
);
1818 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1823 // Hash buckets full, try CAM
1824 rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1828 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1829 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1830 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1832 pr_debug("New entry\n");
1833 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1838 rtl83xx_setup_l2_mc_entry(priv
, &e
, vid
, mac
, mc_group
);
1839 priv
->r
->write_cam(idx
, &e
);
1846 mutex_unlock(&priv
->reg_mutex
);
1848 dev_err(ds
->dev
, "failed to add MDB entry\n");
1851 int rtl83xx_port_mdb_del(struct dsa_switch
*ds
, int port
,
1852 const struct switchdev_obj_port_mdb
*mdb
)
1854 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1855 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1856 struct rtl838x_l2_entry e
;
1859 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1862 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1864 if (priv
->is_lagmember
[port
]) {
1865 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1869 mutex_lock(&priv
->reg_mutex
);
1871 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1874 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1875 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1878 // dump_l2_entry(&e);
1879 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1884 /* Check CAM for spillover from hash buckets */
1885 rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1888 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1891 // dump_l2_entry(&e);
1892 priv
->r
->write_cam(idx
, &e
);
1896 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1898 mutex_unlock(&priv
->reg_mutex
);
1902 static int rtl83xx_port_mirror_add(struct dsa_switch
*ds
, int port
,
1903 struct dsa_mall_mirror_tc_entry
*mirror
,
1906 /* We support 4 mirror groups, one destination port per group */
1908 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1909 int ctrl_reg
, dpm_reg
, spm_reg
;
1911 pr_debug("In %s\n", __func__
);
1913 for (group
= 0; group
< 4; group
++) {
1914 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1918 for (group
= 0; group
< 4; group
++) {
1919 if (priv
->mirror_group_ports
[group
] < 0)
1927 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1928 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1929 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1931 pr_debug("Using group %d\n", group
);
1932 mutex_lock(&priv
->reg_mutex
);
1934 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1935 /* Enable mirroring to port across VLANs (bit 11) */
1936 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1938 /* Enable mirroring to destination port */
1939 sw_w32((mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1942 if (ingress
&& (priv
->r
->get_port_reg_be(spm_reg
) & (1ULL << port
))) {
1943 mutex_unlock(&priv
->reg_mutex
);
1946 if ((!ingress
) && (priv
->r
->get_port_reg_be(dpm_reg
) & (1ULL << port
))) {
1947 mutex_unlock(&priv
->reg_mutex
);
1952 priv
->r
->mask_port_reg_be(0, 1ULL << port
, spm_reg
);
1954 priv
->r
->mask_port_reg_be(0, 1ULL << port
, dpm_reg
);
1956 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1957 mutex_unlock(&priv
->reg_mutex
);
1961 static void rtl83xx_port_mirror_del(struct dsa_switch
*ds
, int port
,
1962 struct dsa_mall_mirror_tc_entry
*mirror
)
1965 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1966 int ctrl_reg
, dpm_reg
, spm_reg
;
1968 pr_debug("In %s\n", __func__
);
1969 for (group
= 0; group
< 4; group
++) {
1970 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1976 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1977 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1978 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1980 mutex_lock(&priv
->reg_mutex
);
1981 if (mirror
->ingress
) {
1982 /* Ingress, clear source port matrix */
1983 priv
->r
->mask_port_reg_be(1ULL << port
, 0, spm_reg
);
1985 /* Egress, clear destination port matrix */
1986 priv
->r
->mask_port_reg_be(1ULL << port
, 0, dpm_reg
);
1989 if (!(sw_r32(spm_reg
) || sw_r32(dpm_reg
))) {
1990 priv
->mirror_group_ports
[group
] = -1;
1991 sw_w32(0, ctrl_reg
);
1994 mutex_unlock(&priv
->reg_mutex
);
1997 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch
*ds
, int port
, unsigned long flags
, struct netlink_ext_ack
*extack
)
1999 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2000 unsigned long features
= 0;
2001 pr_debug("%s: %d %lX\n", __func__
, port
, flags
);
2002 if (priv
->r
->enable_learning
)
2003 features
|= BR_LEARNING
;
2004 if (priv
->r
->enable_flood
)
2005 features
|= BR_FLOOD
;
2006 if (priv
->r
->enable_mcast_flood
)
2007 features
|= BR_MCAST_FLOOD
;
2008 if (priv
->r
->enable_bcast_flood
)
2009 features
|= BR_BCAST_FLOOD
;
2010 if (flags
& ~(features
))
2016 static int rtl83xx_port_bridge_flags(struct dsa_switch
*ds
, int port
, unsigned long flags
, struct netlink_ext_ack
*extack
)
2018 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2020 pr_debug("%s: %d %lX\n", __func__
, port
, flags
);
2021 if (priv
->r
->enable_learning
)
2022 priv
->r
->enable_learning(port
, !!(flags
& BR_LEARNING
));
2024 if (priv
->r
->enable_flood
)
2025 priv
->r
->enable_flood(port
, !!(flags
& BR_FLOOD
));
2027 if (priv
->r
->enable_mcast_flood
)
2028 priv
->r
->enable_mcast_flood(port
, !!(flags
& BR_MCAST_FLOOD
));
2030 if (priv
->r
->enable_bcast_flood
)
2031 priv
->r
->enable_bcast_flood(port
, !!(flags
& BR_BCAST_FLOOD
));
2036 static bool rtl83xx_lag_can_offload(struct dsa_switch
*ds
,
2037 struct net_device
*lag
,
2038 struct netdev_lag_upper_info
*info
)
2042 id
= dsa_lag_id(ds
->dst
, lag
);
2043 if (id
< 0 || id
>= ds
->num_lag_ids
)
2046 if (info
->tx_type
!= NETDEV_LAG_TX_TYPE_HASH
) {
2049 if (info
->hash_type
!= NETDEV_LAG_HASH_L2
&& info
->hash_type
!= NETDEV_LAG_HASH_L23
)
2055 static int rtl83xx_port_lag_change(struct dsa_switch
*ds
, int port
)
2057 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2059 pr_debug("%s: %d\n", __func__
, port
);
2060 // Nothing to be done...
2065 static int rtl83xx_port_lag_join(struct dsa_switch
*ds
, int port
,
2066 struct net_device
*lag
,
2067 struct netdev_lag_upper_info
*info
)
2069 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2072 if (!rtl83xx_lag_can_offload(ds
, lag
, info
))
2075 mutex_lock(&priv
->reg_mutex
);
2077 for (i
= 0; i
< priv
->n_lags
; i
++) {
2078 if ((!priv
->lag_devs
[i
]) || (priv
->lag_devs
[i
] == lag
))
2081 if (port
>= priv
->cpu_port
) {
2085 pr_info("port_lag_join: group %d, port %d\n",i
, port
);
2086 if (!priv
->lag_devs
[i
])
2087 priv
->lag_devs
[i
] = lag
;
2089 if (priv
->lag_primary
[i
]==-1) {
2090 priv
->lag_primary
[i
]=port
;
2092 priv
->is_lagmember
[port
] = 1;
2094 priv
->lagmembers
|= (1ULL << port
);
2096 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2097 err
= rtl83xx_lag_add(priv
->ds
, i
, port
, info
);
2104 mutex_unlock(&priv
->reg_mutex
);
2109 static int rtl83xx_port_lag_leave(struct dsa_switch
*ds
, int port
,
2110 struct net_device
*lag
)
2112 int i
, group
= -1, err
;
2113 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2115 mutex_lock(&priv
->reg_mutex
);
2116 for (i
=0;i
<priv
->n_lags
;i
++) {
2117 if (priv
->lags_port_members
[i
] & BIT_ULL(port
)) {
2124 pr_info("port_lag_leave: port %d is not a member\n", port
);
2129 if (port
>= priv
->cpu_port
) {
2133 pr_info("port_lag_del: group %d, port %d\n",group
, port
);
2134 priv
->lagmembers
&=~ (1ULL << port
);
2135 priv
->lag_primary
[i
] = -1;
2136 priv
->is_lagmember
[port
] = 0;
2137 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2138 err
= rtl83xx_lag_del(priv
->ds
, group
, port
);
2143 if (!priv
->lags_port_members
[i
])
2144 priv
->lag_devs
[i
] = NULL
;
2147 mutex_unlock(&priv
->reg_mutex
);
2151 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
2155 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2157 if (phy_addr
>= 24 && phy_addr
<= 27
2158 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
2161 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
2165 read_phy(phy_addr
, 0, phy_reg
, &val
);
2169 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
2172 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2174 if (phy_addr
>= 24 && phy_addr
<= 27
2175 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
2178 sw_w32(val
, RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2));
2181 return write_phy(phy_addr
, 0, phy_reg
, val
);
2184 const struct dsa_switch_ops rtl83xx_switch_ops
= {
2185 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2186 .setup
= rtl83xx_setup
,
2188 .phy_read
= dsa_phy_read
,
2189 .phy_write
= dsa_phy_write
,
2191 .phylink_validate
= rtl83xx_phylink_validate
,
2192 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
2193 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
2194 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
2195 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
2197 .get_strings
= rtl83xx_get_strings
,
2198 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2199 .get_sset_count
= rtl83xx_get_sset_count
,
2201 .port_enable
= rtl83xx_port_enable
,
2202 .port_disable
= rtl83xx_port_disable
,
2204 .get_mac_eee
= rtl83xx_get_mac_eee
,
2205 .set_mac_eee
= rtl83xx_set_mac_eee
,
2207 .set_ageing_time
= rtl83xx_set_ageing_time
,
2208 .port_bridge_join
= rtl83xx_port_bridge_join
,
2209 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2210 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2211 .port_fast_age
= rtl83xx_fast_age
,
2213 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2214 .port_vlan_prepare
= rtl83xx_vlan_prepare
,
2215 .port_vlan_add
= rtl83xx_vlan_add
,
2216 .port_vlan_del
= rtl83xx_vlan_del
,
2218 .port_fdb_add
= rtl83xx_port_fdb_add
,
2219 .port_fdb_del
= rtl83xx_port_fdb_del
,
2220 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2222 .port_mdb_prepare
= rtl83xx_port_mdb_prepare
,
2223 .port_mdb_add
= rtl83xx_port_mdb_add
,
2224 .port_mdb_del
= rtl83xx_port_mdb_del
,
2226 .port_mirror_add
= rtl83xx_port_mirror_add
,
2227 .port_mirror_del
= rtl83xx_port_mirror_del
,
2229 .port_lag_change
= rtl83xx_port_lag_change
,
2230 .port_lag_join
= rtl83xx_port_lag_join
,
2231 .port_lag_leave
= rtl83xx_port_lag_leave
,
2233 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2234 .port_bridge_flags
= rtl83xx_port_bridge_flags
,
2237 const struct dsa_switch_ops rtl930x_switch_ops
= {
2238 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2239 .setup
= rtl93xx_setup
,
2241 .phy_read
= dsa_phy_read
,
2242 .phy_write
= dsa_phy_write
,
2244 .phylink_validate
= rtl93xx_phylink_validate
,
2245 .phylink_mac_link_state
= rtl93xx_phylink_mac_link_state
,
2246 .phylink_mac_config
= rtl93xx_phylink_mac_config
,
2247 .phylink_mac_link_down
= rtl93xx_phylink_mac_link_down
,
2248 .phylink_mac_link_up
= rtl93xx_phylink_mac_link_up
,
2250 .get_strings
= rtl83xx_get_strings
,
2251 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2252 .get_sset_count
= rtl83xx_get_sset_count
,
2254 .port_enable
= rtl83xx_port_enable
,
2255 .port_disable
= rtl83xx_port_disable
,
2257 .get_mac_eee
= rtl93xx_get_mac_eee
,
2258 .set_mac_eee
= rtl83xx_set_mac_eee
,
2260 .set_ageing_time
= rtl83xx_set_ageing_time
,
2261 .port_bridge_join
= rtl83xx_port_bridge_join
,
2262 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2263 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2264 .port_fast_age
= rtl930x_fast_age
,
2266 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2267 .port_vlan_prepare
= rtl83xx_vlan_prepare
,
2268 .port_vlan_add
= rtl83xx_vlan_add
,
2269 .port_vlan_del
= rtl83xx_vlan_del
,
2271 .port_fdb_add
= rtl83xx_port_fdb_add
,
2272 .port_fdb_del
= rtl83xx_port_fdb_del
,
2273 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2275 .port_mdb_prepare
= rtl83xx_port_mdb_prepare
,
2276 .port_mdb_add
= rtl83xx_port_mdb_add
,
2277 .port_mdb_del
= rtl83xx_port_mdb_del
,
2279 .port_lag_change
= rtl83xx_port_lag_change
,
2280 .port_lag_join
= rtl83xx_port_lag_join
,
2281 .port_lag_leave
= rtl83xx_port_lag_leave
,
2283 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2284 .port_bridge_flags
= rtl83xx_port_bridge_flags
,