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realtek: Add L2 aging configuration functions for all SoC families
[openwrt/staging/jow.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static int rtl83xx_setup(struct dsa_switch *ds)
158 {
159 int i;
160 struct rtl838x_switch_priv *priv = ds->priv;
161 u64 port_bitmap = BIT_ULL(priv->cpu_port);
162
163 pr_debug("%s called\n", __func__);
164
165 /* Disable MAC polling the PHY so that we can start configuration */
166 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
167
168 for (i = 0; i < ds->num_ports; i++)
169 priv->ports[i].enable = false;
170 priv->ports[priv->cpu_port].enable = true;
171
172 /* Isolate ports from each other: traffic only CPU <-> port */
173 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
174 * traffic from source port i to destination port j
175 */
176 for (i = 0; i < priv->cpu_port; i++) {
177 if (priv->ports[i].phy) {
178 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
179 priv->r->port_iso_ctrl(i));
180 port_bitmap |= BIT_ULL(i);
181 }
182 }
183 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
184
185 if (priv->family_id == RTL8380_FAMILY_ID)
186 rtl838x_print_matrix();
187 else
188 rtl839x_print_matrix();
189
190 rtl83xx_init_stats(priv);
191
192 rtl83xx_vlan_setup(priv);
193
194 ds->configure_vlan_while_not_filtering = true;
195
196 priv->r->l2_learning_setup();
197
198 /* Enable MAC Polling PHY again */
199 rtl83xx_enable_phy_polling(priv);
200 pr_debug("Please wait until PHY is settled\n");
201 msleep(1000);
202 priv->r->pie_init(priv);
203
204 return 0;
205 }
206
207 static int rtl93xx_setup(struct dsa_switch *ds)
208 {
209 int i;
210 struct rtl838x_switch_priv *priv = ds->priv;
211 u32 port_bitmap = BIT(priv->cpu_port);
212
213 pr_info("%s called\n", __func__);
214
215 /* Disable MAC polling the PHY so that we can start configuration */
216 if (priv->family_id == RTL9300_FAMILY_ID)
217 sw_w32(0, RTL930X_SMI_POLL_CTRL);
218
219 if (priv->family_id == RTL9310_FAMILY_ID) {
220 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
221 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
222 }
223
224 // Disable all ports except CPU port
225 for (i = 0; i < ds->num_ports; i++)
226 priv->ports[i].enable = false;
227 priv->ports[priv->cpu_port].enable = true;
228
229 for (i = 0; i < priv->cpu_port; i++) {
230 if (priv->ports[i].phy) {
231 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
232 port_bitmap |= BIT_ULL(i);
233 }
234 }
235 priv->r->traffic_set(priv->cpu_port, port_bitmap);
236
237 rtl930x_print_matrix();
238
239 // TODO: Initialize statistics
240
241 rtl83xx_vlan_setup(priv);
242
243 ds->configure_vlan_while_not_filtering = true;
244
245 priv->r->l2_learning_setup();
246
247 rtl83xx_enable_phy_polling(priv);
248
249 priv->r->pie_init(priv);
250
251 return 0;
252 }
253
254 static int rtl93xx_get_sds(struct phy_device *phydev)
255 {
256 struct device *dev = &phydev->mdio.dev;
257 struct device_node *dn;
258 u32 sds_num;
259
260 if (!dev)
261 return -1;
262 if (dev->of_node) {
263 dn = dev->of_node;
264 if (of_property_read_u32(dn, "sds", &sds_num))
265 sds_num = -1;
266 } else {
267 dev_err(dev, "No DT node.\n");
268 return -1;
269 }
270
271 return sds_num;
272 }
273
274 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
275 unsigned long *supported,
276 struct phylink_link_state *state)
277 {
278 struct rtl838x_switch_priv *priv = ds->priv;
279 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
280
281 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
282
283 if (!phy_interface_mode_is_rgmii(state->interface) &&
284 state->interface != PHY_INTERFACE_MODE_NA &&
285 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
286 state->interface != PHY_INTERFACE_MODE_MII &&
287 state->interface != PHY_INTERFACE_MODE_REVMII &&
288 state->interface != PHY_INTERFACE_MODE_GMII &&
289 state->interface != PHY_INTERFACE_MODE_QSGMII &&
290 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
291 state->interface != PHY_INTERFACE_MODE_SGMII) {
292 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
293 dev_err(ds->dev,
294 "Unsupported interface: %d for port %d\n",
295 state->interface, port);
296 return;
297 }
298
299 /* Allow all the expected bits */
300 phylink_set(mask, Autoneg);
301 phylink_set_port_modes(mask);
302 phylink_set(mask, Pause);
303 phylink_set(mask, Asym_Pause);
304
305 /* With the exclusion of MII and Reverse MII, we support Gigabit,
306 * including Half duplex
307 */
308 if (state->interface != PHY_INTERFACE_MODE_MII &&
309 state->interface != PHY_INTERFACE_MODE_REVMII) {
310 phylink_set(mask, 1000baseT_Full);
311 phylink_set(mask, 1000baseT_Half);
312 }
313
314 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
315 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
316 phylink_set(mask, 1000baseX_Full);
317
318 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
319 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
320 phylink_set(mask, 1000baseX_Full);
321
322 phylink_set(mask, 10baseT_Half);
323 phylink_set(mask, 10baseT_Full);
324 phylink_set(mask, 100baseT_Half);
325 phylink_set(mask, 100baseT_Full);
326
327 bitmap_and(supported, supported, mask,
328 __ETHTOOL_LINK_MODE_MASK_NBITS);
329 bitmap_and(state->advertising, state->advertising, mask,
330 __ETHTOOL_LINK_MODE_MASK_NBITS);
331 }
332
333 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
334 unsigned long *supported,
335 struct phylink_link_state *state)
336 {
337 struct rtl838x_switch_priv *priv = ds->priv;
338 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
339
340 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
341 phy_modes(state->interface));
342
343 if (!phy_interface_mode_is_rgmii(state->interface) &&
344 state->interface != PHY_INTERFACE_MODE_NA &&
345 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
346 state->interface != PHY_INTERFACE_MODE_MII &&
347 state->interface != PHY_INTERFACE_MODE_REVMII &&
348 state->interface != PHY_INTERFACE_MODE_GMII &&
349 state->interface != PHY_INTERFACE_MODE_QSGMII &&
350 state->interface != PHY_INTERFACE_MODE_XGMII &&
351 state->interface != PHY_INTERFACE_MODE_HSGMII &&
352 state->interface != PHY_INTERFACE_MODE_10GBASER &&
353 state->interface != PHY_INTERFACE_MODE_10GKR &&
354 state->interface != PHY_INTERFACE_MODE_USXGMII &&
355 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
356 state->interface != PHY_INTERFACE_MODE_SGMII) {
357 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
358 dev_err(ds->dev,
359 "Unsupported interface: %d for port %d\n",
360 state->interface, port);
361 return;
362 }
363
364 /* Allow all the expected bits */
365 phylink_set(mask, Autoneg);
366 phylink_set_port_modes(mask);
367 phylink_set(mask, Pause);
368 phylink_set(mask, Asym_Pause);
369
370 /* With the exclusion of MII and Reverse MII, we support Gigabit,
371 * including Half duplex
372 */
373 if (state->interface != PHY_INTERFACE_MODE_MII &&
374 state->interface != PHY_INTERFACE_MODE_REVMII) {
375 phylink_set(mask, 1000baseT_Full);
376 phylink_set(mask, 1000baseT_Half);
377 }
378
379 // Internal phys of the RTL93xx family provide 10G
380 if (priv->ports[port].phy_is_integrated
381 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
382 phylink_set(mask, 1000baseX_Full);
383 } else if (priv->ports[port].phy_is_integrated) {
384 phylink_set(mask, 1000baseX_Full);
385 phylink_set(mask, 10000baseKR_Full);
386 phylink_set(mask, 10000baseSR_Full);
387 phylink_set(mask, 10000baseCR_Full);
388 }
389 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
390 phylink_set(mask, 1000baseX_Full);
391 phylink_set(mask, 1000baseT_Full);
392 phylink_set(mask, 10000baseKR_Full);
393 phylink_set(mask, 10000baseT_Full);
394 phylink_set(mask, 10000baseSR_Full);
395 phylink_set(mask, 10000baseCR_Full);
396 }
397
398 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
399 phylink_set(mask, 10000baseT_Full);
400
401 phylink_set(mask, 10baseT_Half);
402 phylink_set(mask, 10baseT_Full);
403 phylink_set(mask, 100baseT_Half);
404 phylink_set(mask, 100baseT_Full);
405
406 bitmap_and(supported, supported, mask,
407 __ETHTOOL_LINK_MODE_MASK_NBITS);
408 bitmap_and(state->advertising, state->advertising, mask,
409 __ETHTOOL_LINK_MODE_MASK_NBITS);
410 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
411 }
412
413 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
414 struct phylink_link_state *state)
415 {
416 struct rtl838x_switch_priv *priv = ds->priv;
417 u64 speed;
418 u64 link;
419
420 if (port < 0 || port > priv->cpu_port)
421 return -EINVAL;
422
423 state->link = 0;
424 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
425 if (link & BIT_ULL(port))
426 state->link = 1;
427 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
428
429 state->duplex = 0;
430 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
431 state->duplex = 1;
432
433 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
434 speed >>= (port % 16) << 1;
435 switch (speed & 0x3) {
436 case 0:
437 state->speed = SPEED_10;
438 break;
439 case 1:
440 state->speed = SPEED_100;
441 break;
442 case 2:
443 state->speed = SPEED_1000;
444 break;
445 case 3:
446 if (priv->family_id == RTL9300_FAMILY_ID
447 && (port == 24 || port == 26)) /* Internal serdes */
448 state->speed = SPEED_2500;
449 else
450 state->speed = SPEED_100; /* Is in fact 500Mbit */
451 }
452
453 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
454 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
455 state->pause |= MLO_PAUSE_RX;
456 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
457 state->pause |= MLO_PAUSE_TX;
458 return 1;
459 }
460
461 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
462 struct phylink_link_state *state)
463 {
464 struct rtl838x_switch_priv *priv = ds->priv;
465 u64 speed;
466 u64 link;
467
468 if (port < 0 || port > priv->cpu_port)
469 return -EINVAL;
470
471 /*
472 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
473 * state needs to be read twice in order to read a correct result.
474 * This would not be necessary for ports connected e.g. to RTL8218D
475 * PHYs.
476 */
477 state->link = 0;
478 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
479 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
480 if (link & BIT_ULL(port))
481 state->link = 1;
482 pr_debug("%s: link state port %d: %llx, media %08x\n", __func__, port,
483 link & BIT_ULL(port), sw_r32(RTL930X_MAC_LINK_MEDIA_STS));
484
485 state->duplex = 0;
486 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
487 state->duplex = 1;
488
489 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
490 speed >>= (port % 8) << 2;
491 switch (speed & 0xf) {
492 case 0:
493 state->speed = SPEED_10;
494 break;
495 case 1:
496 state->speed = SPEED_100;
497 break;
498 case 2:
499 case 7:
500 state->speed = SPEED_1000;
501 break;
502 case 4:
503 state->speed = SPEED_10000;
504 break;
505 case 5:
506 case 8:
507 state->speed = SPEED_2500;
508 break;
509 case 6:
510 state->speed = SPEED_5000;
511 break;
512 default:
513 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
514 }
515
516 if (priv->family_id == RTL9310_FAMILY_ID
517 && (port >= 52 || port <= 55)) { /* Internal serdes */
518 state->speed = SPEED_10000;
519 state->link = 1;
520 state->duplex = 1;
521 }
522
523 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
524 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
525 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
526 state->pause |= MLO_PAUSE_RX;
527 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
528 state->pause |= MLO_PAUSE_TX;
529 return 1;
530 }
531
532 static void rtl83xx_config_interface(int port, phy_interface_t interface)
533 {
534 u32 old, int_shift, sds_shift;
535
536 switch (port) {
537 case 24:
538 int_shift = 0;
539 sds_shift = 5;
540 break;
541 case 26:
542 int_shift = 3;
543 sds_shift = 0;
544 break;
545 default:
546 return;
547 }
548
549 old = sw_r32(RTL838X_SDS_MODE_SEL);
550 switch (interface) {
551 case PHY_INTERFACE_MODE_1000BASEX:
552 if ((old >> sds_shift & 0x1f) == 4)
553 return;
554 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
555 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
556 break;
557 case PHY_INTERFACE_MODE_SGMII:
558 if ((old >> sds_shift & 0x1f) == 2)
559 return;
560 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
561 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
562 break;
563 default:
564 return;
565 }
566 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
567 }
568
569 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
570 unsigned int mode,
571 const struct phylink_link_state *state)
572 {
573 struct rtl838x_switch_priv *priv = ds->priv;
574 u32 reg;
575 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
576
577 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
578
579 if (port == priv->cpu_port) {
580 /* Set Speed, duplex, flow control
581 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
582 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
583 * | MEDIA_SEL
584 */
585 if (priv->family_id == RTL8380_FAMILY_ID) {
586 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
587 /* allow CRC errors on CPU-port */
588 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
589 } else {
590 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
591 }
592 return;
593 }
594
595 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
596 /* Auto-Negotiation does not work for MAC in RTL8390 */
597 if (priv->family_id == RTL8380_FAMILY_ID) {
598 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
599 pr_debug("PHY autonegotiates\n");
600 reg |= RTL838X_NWAY_EN;
601 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
602 rtl83xx_config_interface(port, state->interface);
603 return;
604 }
605 }
606
607 if (mode != MLO_AN_FIXED)
608 pr_debug("Fixed state.\n");
609
610 /* Clear id_mode_dis bit, and the existing port mode, let
611 * RGMII_MODE_EN bet set by mac_link_{up,down} */
612 if (priv->family_id == RTL8380_FAMILY_ID) {
613 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
614 if (state->pause & MLO_PAUSE_TXRX_MASK) {
615 if (state->pause & MLO_PAUSE_TX)
616 reg |= RTL838X_TX_PAUSE_EN;
617 reg |= RTL838X_RX_PAUSE_EN;
618 }
619 } else if (priv->family_id == RTL8390_FAMILY_ID) {
620 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
621 if (state->pause & MLO_PAUSE_TXRX_MASK) {
622 if (state->pause & MLO_PAUSE_TX)
623 reg |= RTL839X_TX_PAUSE_EN;
624 reg |= RTL839X_RX_PAUSE_EN;
625 }
626 }
627
628
629 reg &= ~(3 << speed_bit);
630 switch (state->speed) {
631 case SPEED_1000:
632 reg |= 2 << speed_bit;
633 break;
634 case SPEED_100:
635 reg |= 1 << speed_bit;
636 break;
637 default:
638 break; // Ignore, including 10MBit which has a speed value of 0
639 }
640
641 if (priv->family_id == RTL8380_FAMILY_ID) {
642 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
643 if (state->link)
644 reg |= RTL838X_FORCE_LINK_EN;
645 if (state->duplex == RTL838X_DUPLEX_MODE)
646 reg |= RTL838X_DUPLEX_MODE;
647 } else if (priv->family_id == RTL8390_FAMILY_ID) {
648 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
649 if (state->link)
650 reg |= RTL839X_FORCE_LINK_EN;
651 if (state->duplex == RTL839X_DUPLEX_MODE)
652 reg |= RTL839X_DUPLEX_MODE;
653 }
654
655 // LAG members must use DUPLEX and we need to enable the link
656 if (priv->lagmembers & BIT_ULL(port)) {
657 switch(priv->family_id) {
658 case RTL8380_FAMILY_ID:
659 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
660 break;
661 case RTL8390_FAMILY_ID:
662 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
663 break;
664 }
665 }
666
667 // Disable AN
668 if (priv->family_id == RTL8380_FAMILY_ID)
669 reg &= ~RTL838X_NWAY_EN;
670 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
671 }
672
673 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
674 unsigned int mode,
675 const struct phylink_link_state *state)
676 {
677 struct rtl838x_switch_priv *priv = ds->priv;
678 int sds_num;
679 u32 reg, band;
680
681 sds_num = priv->ports[port].sds_num;
682 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
683
684 switch (state->interface) {
685 case PHY_INTERFACE_MODE_HSGMII:
686 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
687 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
688 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
689 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
690 break;
691 case PHY_INTERFACE_MODE_1000BASEX:
692 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
693 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
694 break;
695 case PHY_INTERFACE_MODE_XGMII:
696 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
697 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
698 break;
699 case PHY_INTERFACE_MODE_10GBASER:
700 case PHY_INTERFACE_MODE_10GKR:
701 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
702 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
703 break;
704 case PHY_INTERFACE_MODE_USXGMII:
705 // Translates to MII_USXGMII_10GSXGMII
706 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
707 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
708 break;
709 case PHY_INTERFACE_MODE_SGMII:
710 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
711 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
712 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
713 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
714 break;
715 case PHY_INTERFACE_MODE_QSGMII:
716 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
717 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
718 break;
719 default:
720 pr_err("%s: unknown serdes mode: %s\n",
721 __func__, phy_modes(state->interface));
722 return;
723 }
724
725 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
726 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
727
728 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
729
730 reg &= ~(0xf << 12);
731 reg |= 0x2 << 12; // Set SMI speed to 0x2
732
733 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
734
735 if (priv->lagmembers & BIT_ULL(port))
736 reg |= RTL931X_DUPLEX_MODE;
737
738 if (state->duplex == DUPLEX_FULL)
739 reg |= RTL931X_DUPLEX_MODE;
740
741 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
742
743 }
744
745 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
746 unsigned int mode,
747 const struct phylink_link_state *state)
748 {
749 struct rtl838x_switch_priv *priv = ds->priv;
750 int sds_num, sds_mode;
751 u32 reg;
752
753 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
754 port, mode, phy_modes(state->interface), state->speed, state->link);
755
756 // Nothing to be done for the CPU-port
757 if (port == priv->cpu_port)
758 return;
759
760 if (priv->family_id == RTL9310_FAMILY_ID)
761 return rtl931x_phylink_mac_config(ds, port, mode, state);
762
763 sds_num = priv->ports[port].sds_num;
764 pr_info("%s SDS is %d\n", __func__, sds_num);
765 if (sds_num >= 0) {
766 switch (state->interface) {
767 case PHY_INTERFACE_MODE_HSGMII:
768 sds_mode = 0x12;
769 break;
770 case PHY_INTERFACE_MODE_1000BASEX:
771 sds_mode = 0x04;
772 break;
773 case PHY_INTERFACE_MODE_XGMII:
774 sds_mode = 0x10;
775 break;
776 case PHY_INTERFACE_MODE_10GBASER:
777 case PHY_INTERFACE_MODE_10GKR:
778 sds_mode = 0x1b; // 10G 1000X Auto
779 break;
780 case PHY_INTERFACE_MODE_USXGMII:
781 sds_mode = 0x0d;
782 break;
783 default:
784 pr_err("%s: unknown serdes mode: %s\n",
785 __func__, phy_modes(state->interface));
786 return;
787 }
788 rtl9300_sds_rst(sds_num, sds_mode);
789 }
790
791 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
792 reg &= ~(0xf << 3);
793
794 switch (state->speed) {
795 case SPEED_10000:
796 reg |= 4 << 3;
797 break;
798 case SPEED_5000:
799 reg |= 6 << 3;
800 break;
801 case SPEED_2500:
802 reg |= 5 << 3;
803 break;
804 case SPEED_1000:
805 reg |= 2 << 3;
806 break;
807 default:
808 reg |= 2 << 3;
809 break;
810 }
811
812 if (state->link)
813 reg |= RTL930X_FORCE_LINK_EN;
814
815 if (priv->lagmembers & BIT_ULL(port))
816 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
817
818 if (state->duplex == DUPLEX_FULL)
819 reg |= RTL930X_DUPLEX_MODE;
820
821 if (priv->ports[port].phy_is_integrated)
822 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
823 else
824 reg |= RTL930X_FORCE_EN;
825
826 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
827 }
828
829 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
830 unsigned int mode,
831 phy_interface_t interface)
832 {
833 struct rtl838x_switch_priv *priv = ds->priv;
834 u32 v;
835
836 /* Stop TX/RX to port */
837 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
838
839 // No longer force link
840 if (priv->family_id == RTL9300_FAMILY_ID)
841 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
842 else if (priv->family_id == RTL9310_FAMILY_ID)
843 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
844 sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));
845 }
846
847 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
848 unsigned int mode,
849 phy_interface_t interface)
850 {
851 struct rtl838x_switch_priv *priv = ds->priv;
852 /* Stop TX/RX to port */
853 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
854
855 // No longer force link
856 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
857 }
858
859 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
860 unsigned int mode,
861 phy_interface_t interface,
862 struct phy_device *phydev,
863 int speed, int duplex,
864 bool tx_pause, bool rx_pause)
865 {
866 struct rtl838x_switch_priv *priv = ds->priv;
867 /* Restart TX/RX to port */
868 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
869 // TODO: Set speed/duplex/pauses
870 }
871
872 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
873 unsigned int mode,
874 phy_interface_t interface,
875 struct phy_device *phydev,
876 int speed, int duplex,
877 bool tx_pause, bool rx_pause)
878 {
879 struct rtl838x_switch_priv *priv = ds->priv;
880
881 /* Restart TX/RX to port */
882 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
883 // TODO: Set speed/duplex/pauses
884 }
885
886 static void rtl83xx_get_strings(struct dsa_switch *ds,
887 int port, u32 stringset, u8 *data)
888 {
889 int i;
890
891 if (stringset != ETH_SS_STATS)
892 return;
893
894 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
895 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
896 ETH_GSTRING_LEN);
897 }
898
899 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
900 uint64_t *data)
901 {
902 struct rtl838x_switch_priv *priv = ds->priv;
903 const struct rtl83xx_mib_desc *mib;
904 int i;
905 u64 h;
906
907 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
908 mib = &rtl83xx_mib[i];
909
910 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
911 if (mib->size == 2) {
912 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
913 data[i] |= h << 32;
914 }
915 }
916 }
917
918 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
919 {
920 if (sset != ETH_SS_STATS)
921 return 0;
922
923 return ARRAY_SIZE(rtl83xx_mib);
924 }
925
926 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
927 struct phy_device *phydev)
928 {
929 struct rtl838x_switch_priv *priv = ds->priv;
930 u64 v;
931
932 pr_debug("%s: %x %d", __func__, (u32) priv, port);
933 priv->ports[port].enable = true;
934
935 /* enable inner tagging on egress, do not keep any tags */
936 if (priv->family_id == RTL9310_FAMILY_ID)
937 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
938 else
939 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
940
941 if (dsa_is_cpu_port(ds, port))
942 return 0;
943
944 /* add port to switch mask of CPU_PORT */
945 priv->r->traffic_enable(priv->cpu_port, port);
946
947 if (priv->is_lagmember[port]) {
948 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
949 return 0;
950 }
951
952 /* add all other ports in the same bridge to switch mask of port */
953 v = priv->r->traffic_get(port);
954 v |= priv->ports[port].pm;
955 priv->r->traffic_set(port, v);
956
957 // TODO: Figure out if this is necessary
958 if (priv->family_id == RTL9300_FAMILY_ID) {
959 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
960 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
961 }
962
963 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
964
965 return 0;
966 }
967
968 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
969 {
970 struct rtl838x_switch_priv *priv = ds->priv;
971 u64 v;
972
973 pr_debug("%s %x: %d", __func__, (u32)priv, port);
974 /* you can only disable user ports */
975 if (!dsa_is_user_port(ds, port))
976 return;
977
978 // BUG: This does not work on RTL931X
979 /* remove port from switch mask of CPU_PORT */
980 priv->r->traffic_disable(priv->cpu_port, port);
981
982 /* remove all other ports in the same bridge from switch mask of port */
983 v = priv->r->traffic_get(port);
984 v &= ~priv->ports[port].pm;
985 priv->r->traffic_set(port, v);
986
987 priv->ports[port].enable = false;
988 }
989
990 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
991 struct ethtool_eee *e)
992 {
993 struct rtl838x_switch_priv *priv = ds->priv;
994
995 if (e->eee_enabled && !priv->eee_enabled) {
996 pr_info("Globally enabling EEE\n");
997 priv->r->init_eee(priv, true);
998 }
999
1000 priv->r->port_eee_set(priv, port, e->eee_enabled);
1001
1002 if (e->eee_enabled)
1003 pr_info("Enabled EEE for port %d\n", port);
1004 else
1005 pr_info("Disabled EEE for port %d\n", port);
1006 return 0;
1007 }
1008
1009 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1010 struct ethtool_eee *e)
1011 {
1012 struct rtl838x_switch_priv *priv = ds->priv;
1013
1014 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1015
1016 priv->r->eee_port_ability(priv, e, port);
1017
1018 e->eee_enabled = priv->ports[port].eee_enabled;
1019
1020 e->eee_active = !!(e->advertised & e->lp_advertised);
1021
1022 return 0;
1023 }
1024
1025 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1026 struct ethtool_eee *e)
1027 {
1028 struct rtl838x_switch_priv *priv = ds->priv;
1029
1030 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1031 | SUPPORTED_2500baseX_Full;
1032
1033 priv->r->eee_port_ability(priv, e, port);
1034
1035 e->eee_enabled = priv->ports[port].eee_enabled;
1036
1037 e->eee_active = !!(e->advertised & e->lp_advertised);
1038
1039 return 0;
1040 }
1041
1042 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1043 {
1044 struct rtl838x_switch_priv *priv = ds->priv;
1045
1046 priv->r->set_ageing_time(msec);
1047 return 0;
1048 }
1049
1050 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1051 struct net_device *bridge)
1052 {
1053 struct rtl838x_switch_priv *priv = ds->priv;
1054 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1055 int i;
1056
1057 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1058
1059 if (priv->is_lagmember[port]) {
1060 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1061 return 0;
1062 }
1063
1064 mutex_lock(&priv->reg_mutex);
1065 for (i = 0; i < ds->num_ports; i++) {
1066 /* Add this port to the port matrix of the other ports in the
1067 * same bridge. If the port is disabled, port matrix is kept
1068 * and not being setup until the port becomes enabled.
1069 */
1070 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1071 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1072 continue;
1073 if (priv->ports[i].enable)
1074 priv->r->traffic_enable(i, port);
1075
1076 priv->ports[i].pm |= BIT_ULL(port);
1077 port_bitmap |= BIT_ULL(i);
1078 }
1079 }
1080
1081 /* Add all other ports to this port matrix. */
1082 if (priv->ports[port].enable) {
1083 priv->r->traffic_enable(priv->cpu_port, port);
1084 v = priv->r->traffic_get(port);
1085 v |= port_bitmap;
1086 priv->r->traffic_set(port, v);
1087 }
1088 priv->ports[port].pm |= port_bitmap;
1089 mutex_unlock(&priv->reg_mutex);
1090
1091 return 0;
1092 }
1093
1094 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1095 struct net_device *bridge)
1096 {
1097 struct rtl838x_switch_priv *priv = ds->priv;
1098 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1099 int i;
1100
1101 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1102 mutex_lock(&priv->reg_mutex);
1103 for (i = 0; i < ds->num_ports; i++) {
1104 /* Remove this port from the port matrix of the other ports
1105 * in the same bridge. If the port is disabled, port matrix
1106 * is kept and not being setup until the port becomes enabled.
1107 * And the other port's port matrix cannot be broken when the
1108 * other port is still a VLAN-aware port.
1109 */
1110 if (dsa_is_user_port(ds, i) && i != port) {
1111 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1112 continue;
1113 if (priv->ports[i].enable)
1114 priv->r->traffic_disable(i, port);
1115
1116 priv->ports[i].pm |= BIT_ULL(port);
1117 port_bitmap &= ~BIT_ULL(i);
1118 }
1119 }
1120
1121 /* Add all other ports to this port matrix. */
1122 if (priv->ports[port].enable) {
1123 v = priv->r->traffic_get(port);
1124 v |= port_bitmap;
1125 priv->r->traffic_set(port, v);
1126 }
1127 priv->ports[port].pm &= ~port_bitmap;
1128
1129 mutex_unlock(&priv->reg_mutex);
1130 }
1131
1132 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1133 {
1134 u32 msti = 0;
1135 u32 port_state[4];
1136 int index, bit;
1137 int pos = port;
1138 struct rtl838x_switch_priv *priv = ds->priv;
1139 int n = priv->port_width << 1;
1140
1141 /* Ports above or equal CPU port can never be configured */
1142 if (port >= priv->cpu_port)
1143 return;
1144
1145 mutex_lock(&priv->reg_mutex);
1146
1147 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1148 * have 64 bit fields, 839x and 931x have 128 bit fields
1149 */
1150 if (priv->family_id == RTL8390_FAMILY_ID)
1151 pos += 12;
1152 if (priv->family_id == RTL9300_FAMILY_ID)
1153 pos += 3;
1154 if (priv->family_id == RTL9310_FAMILY_ID)
1155 pos += 8;
1156
1157 index = n - (pos >> 4) - 1;
1158 bit = (pos << 1) % 32;
1159
1160 priv->r->stp_get(priv, msti, port_state);
1161
1162 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1163 port_state[index] &= ~(3 << bit);
1164
1165 switch (state) {
1166 case BR_STATE_DISABLED: /* 0 */
1167 port_state[index] |= (0 << bit);
1168 break;
1169 case BR_STATE_BLOCKING: /* 4 */
1170 case BR_STATE_LISTENING: /* 1 */
1171 port_state[index] |= (1 << bit);
1172 break;
1173 case BR_STATE_LEARNING: /* 2 */
1174 port_state[index] |= (2 << bit);
1175 break;
1176 case BR_STATE_FORWARDING: /* 3*/
1177 port_state[index] |= (3 << bit);
1178 default:
1179 break;
1180 }
1181
1182 priv->r->stp_set(priv, msti, port_state);
1183
1184 mutex_unlock(&priv->reg_mutex);
1185 }
1186
1187 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1188 {
1189 struct rtl838x_switch_priv *priv = ds->priv;
1190 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1191
1192 pr_debug("FAST AGE port %d\n", port);
1193 mutex_lock(&priv->reg_mutex);
1194 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1195 * port fields:
1196 * 0-4: Replacing port
1197 * 5-9: Flushed/replaced port
1198 * 10-21: FVID
1199 * 22: Entry types: 1: dynamic, 0: also static
1200 * 23: Match flush port
1201 * 24: Match FVID
1202 * 25: Flush (0) or replace (1) L2 entries
1203 * 26: Status of action (1: Start, 0: Done)
1204 */
1205 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1206
1207 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1208
1209 mutex_unlock(&priv->reg_mutex);
1210 }
1211
1212 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1213 {
1214 struct rtl838x_switch_priv *priv = ds->priv;
1215
1216 pr_debug("FAST AGE port %d\n", port);
1217 mutex_lock(&priv->reg_mutex);
1218 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1219
1220 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1221
1222 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1223
1224 mutex_unlock(&priv->reg_mutex);
1225 }
1226
1227 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1228 bool vlan_filtering,
1229 struct switchdev_trans *trans)
1230 {
1231 struct rtl838x_switch_priv *priv = ds->priv;
1232
1233 pr_debug("%s: port %d\n", __func__, port);
1234 mutex_lock(&priv->reg_mutex);
1235
1236 if (vlan_filtering) {
1237 /* Enable ingress and egress filtering
1238 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1239 * the filter action:
1240 * 0: Always Forward
1241 * 1: Drop packet
1242 * 2: Trap packet to CPU port
1243 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1244 */
1245 if (port != priv->cpu_port)
1246 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1247
1248 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1249 } else {
1250 /* Disable ingress and egress filtering */
1251 if (port != priv->cpu_port)
1252 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1253
1254 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1255 }
1256
1257 /* Do we need to do something to the CPU-Port, too? */
1258 mutex_unlock(&priv->reg_mutex);
1259
1260 return 0;
1261 }
1262
1263 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1264 const struct switchdev_obj_port_vlan *vlan)
1265 {
1266 struct rtl838x_vlan_info info;
1267 struct rtl838x_switch_priv *priv = ds->priv;
1268
1269 priv->r->vlan_tables_read(0, &info);
1270
1271 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1272 info.tagged_ports, info.untagged_ports, info.profile_id,
1273 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1274
1275 priv->r->vlan_tables_read(1, &info);
1276 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1277 info.tagged_ports, info.untagged_ports, info.profile_id,
1278 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1279 priv->r->vlan_set_untagged(1, info.untagged_ports);
1280 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1281
1282 priv->r->vlan_set_tagged(1, &info);
1283 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1284
1285 mutex_unlock(&priv->reg_mutex);
1286 return 0;
1287 }
1288
1289 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1290 const struct switchdev_obj_port_vlan *vlan)
1291 {
1292 struct rtl838x_vlan_info info;
1293 struct rtl838x_switch_priv *priv = ds->priv;
1294 int v;
1295
1296 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1297 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1298
1299 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1300 dev_err(priv->dev, "VLAN out of range: %d - %d",
1301 vlan->vid_begin, vlan->vid_end);
1302 return;
1303 }
1304
1305 mutex_lock(&priv->reg_mutex);
1306
1307 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1308 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1309 if (!v)
1310 continue;
1311 /* Set both inner and outer PVID of the port */
1312 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1313 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1314 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1315 PBVLAN_MODE_UNTAG_AND_PRITAG);
1316 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1317 PBVLAN_MODE_UNTAG_AND_PRITAG);
1318
1319 priv->ports[port].pvid = vlan->vid_end;
1320 }
1321 }
1322
1323 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1324 /* Get port memberships of this vlan */
1325 priv->r->vlan_tables_read(v, &info);
1326
1327 /* new VLAN? */
1328 if (!info.tagged_ports) {
1329 info.fid = 0;
1330 info.hash_mc_fid = false;
1331 info.hash_uc_fid = false;
1332 info.profile_id = 0;
1333 }
1334
1335 /* sanitize untagged_ports - must be a subset */
1336 if (info.untagged_ports & ~info.tagged_ports)
1337 info.untagged_ports = 0;
1338
1339 info.tagged_ports |= BIT_ULL(port);
1340 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1341 info.untagged_ports |= BIT_ULL(port);
1342
1343 priv->r->vlan_set_untagged(v, info.untagged_ports);
1344 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1345
1346 priv->r->vlan_set_tagged(v, &info);
1347 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1348 }
1349
1350 mutex_unlock(&priv->reg_mutex);
1351 }
1352
1353 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1354 const struct switchdev_obj_port_vlan *vlan)
1355 {
1356 struct rtl838x_vlan_info info;
1357 struct rtl838x_switch_priv *priv = ds->priv;
1358 int v;
1359 u16 pvid;
1360
1361 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1362 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1363
1364 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1365 dev_err(priv->dev, "VLAN out of range: %d - %d",
1366 vlan->vid_begin, vlan->vid_end);
1367 return -ENOTSUPP;
1368 }
1369
1370 mutex_lock(&priv->reg_mutex);
1371 pvid = priv->ports[port].pvid;
1372
1373 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1374 /* Reset to default if removing the current PVID */
1375 if (v == pvid) {
1376 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1377 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1378 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1379 PBVLAN_MODE_UNTAG_AND_PRITAG);
1380 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1381 PBVLAN_MODE_UNTAG_AND_PRITAG);
1382 }
1383 /* Get port memberships of this vlan */
1384 priv->r->vlan_tables_read(v, &info);
1385
1386 /* remove port from both tables */
1387 info.untagged_ports &= (~BIT_ULL(port));
1388 info.tagged_ports &= (~BIT_ULL(port));
1389
1390 priv->r->vlan_set_untagged(v, info.untagged_ports);
1391 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1392
1393 priv->r->vlan_set_tagged(v, &info);
1394 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1395 }
1396 mutex_unlock(&priv->reg_mutex);
1397
1398 return 0;
1399 }
1400
1401 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1402 {
1403 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1404 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1405 e->vid, e->rvid, e->port, e->valid);
1406
1407 if (e->type != L2_MULTICAST) {
1408 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1409 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1410 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1411 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1412 }
1413 if (e->type == L2_MULTICAST)
1414 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1415 if (e->is_ip_mc || e->is_ipv6_mc)
1416 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1417 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1418 pr_info(" stack_dev: %d\n", e->stack_dev);
1419 if (e->next_hop)
1420 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1421 }
1422
1423 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1424 {
1425 e->is_ip_mc = e->is_ipv6_mc = false;
1426 e->valid = true;
1427 e->age = 3;
1428 e->port = port,
1429 e->vid = vid;
1430 u64_to_ether_addr(mac, e->mac);
1431 }
1432
1433 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1434 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1435 {
1436 e->is_ip_mc = e->is_ipv6_mc = false;
1437 e->valid = true;
1438 e->mc_portmask_index = mc_group;
1439 e->type = L2_MULTICAST;
1440 e->rvid = e->vid = vid;
1441 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1442 u64_to_ether_addr(mac, e->mac);
1443 }
1444
1445 /*
1446 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1447 * over the entries in the bucket until either a matching entry is found or an empty slot
1448 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1449 * when an empty slot was found and must exist is false, the index of the slot is returned
1450 * when no slots are available returns -1
1451 */
1452 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1453 bool must_exist, struct rtl838x_l2_entry *e)
1454 {
1455 int i, idx = -1;
1456 u32 key = priv->r->l2_hash_key(priv, seed);
1457 u64 entry;
1458
1459 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1460 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1461 for (i = 0; i < priv->l2_bucket_size; i++) {
1462 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1463 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1464 if (must_exist && !e->valid)
1465 continue;
1466 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1467 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1468 break;
1469 }
1470 }
1471
1472 return idx;
1473 }
1474
1475 /*
1476 * Uses the seed to identify an entry in the CAM by looping over all its entries
1477 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1478 * when an empty slot was found the index of the slot is returned
1479 * when no slots are available returns -1
1480 */
1481 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1482 bool must_exist, struct rtl838x_l2_entry *e)
1483 {
1484 int i, idx = -1;
1485 u64 entry;
1486
1487 for (i = 0; i < 64; i++) {
1488 entry = priv->r->read_cam(i, e);
1489 if (!must_exist && !e->valid) {
1490 if (idx < 0) /* First empty entry? */
1491 idx = i;
1492 break;
1493 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1494 pr_debug("Found entry in CAM\n");
1495 idx = i;
1496 break;
1497 }
1498 }
1499 return idx;
1500 }
1501
1502 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1503 const unsigned char *addr, u16 vid)
1504 {
1505 struct rtl838x_switch_priv *priv = ds->priv;
1506 u64 mac = ether_addr_to_u64(addr);
1507 struct rtl838x_l2_entry e;
1508 int err = 0, idx;
1509 u64 seed = priv->r->l2_hash_seed(mac, vid);
1510
1511 if (priv->is_lagmember[port]) {
1512 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1513 return 0;
1514 }
1515
1516 mutex_lock(&priv->reg_mutex);
1517
1518 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1519
1520 // Found an existing or empty entry
1521 if (idx >= 0) {
1522 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1523 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1524 goto out;
1525 }
1526
1527 // Hash buckets full, try CAM
1528 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1529
1530 if (idx >= 0) {
1531 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1532 priv->r->write_cam(idx, &e);
1533 goto out;
1534 }
1535
1536 err = -ENOTSUPP;
1537 out:
1538 mutex_unlock(&priv->reg_mutex);
1539 return err;
1540 }
1541
1542 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1543 const unsigned char *addr, u16 vid)
1544 {
1545 struct rtl838x_switch_priv *priv = ds->priv;
1546 u64 mac = ether_addr_to_u64(addr);
1547 struct rtl838x_l2_entry e;
1548 int err = 0, idx;
1549 u64 seed = priv->r->l2_hash_seed(mac, vid);
1550
1551 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1552 mutex_lock(&priv->reg_mutex);
1553
1554 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1555
1556 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1557 if (idx >= 0) {
1558 e.valid = false;
1559 dump_l2_entry(&e);
1560 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1561 goto out;
1562 }
1563
1564 /* Check CAM for spillover from hash buckets */
1565 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1566
1567 if (idx >= 0) {
1568 e.valid = false;
1569 priv->r->write_cam(idx, &e);
1570 goto out;
1571 }
1572 err = -ENOENT;
1573 out:
1574 mutex_unlock(&priv->reg_mutex);
1575 return err;
1576 }
1577
1578 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1579 dsa_fdb_dump_cb_t *cb, void *data)
1580 {
1581 struct rtl838x_l2_entry e;
1582 struct rtl838x_switch_priv *priv = ds->priv;
1583 int i;
1584 u32 fid, pkey;
1585 u64 mac;
1586
1587 mutex_lock(&priv->reg_mutex);
1588
1589 for (i = 0; i < priv->fib_entries; i++) {
1590 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1591
1592 if (!e.valid)
1593 continue;
1594
1595 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1596 u64 seed;
1597 u32 key;
1598
1599 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1600 mac = ether_addr_to_u64(&e.mac[0]);
1601 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1602 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1603 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1604 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1605 dump_l2_entry(&e);
1606 seed = priv->r->l2_hash_seed(mac, e.rvid);
1607 key = priv->r->l2_hash_key(priv, seed);
1608 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1609 cb(e.mac, e.vid, e.is_static, data);
1610 }
1611 if (e.type == L2_MULTICAST) {
1612 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1613
1614 if (portmask & BIT_ULL(port)) {
1615 dump_l2_entry(&e);
1616 pr_info(" PM: %016llx\n", portmask);
1617 }
1618 }
1619 }
1620
1621 for (i = 0; i < 64; i++) {
1622 priv->r->read_cam(i, &e);
1623
1624 if (!e.valid)
1625 continue;
1626
1627 if (e.port == port)
1628 cb(e.mac, e.vid, e.is_static, data);
1629 }
1630
1631 mutex_unlock(&priv->reg_mutex);
1632 return 0;
1633 }
1634
1635 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1636 const struct switchdev_obj_port_mdb *mdb)
1637 {
1638 struct rtl838x_switch_priv *priv = ds->priv;
1639
1640 if (priv->id >= 0x9300)
1641 return -EOPNOTSUPP;
1642
1643 return 0;
1644 }
1645
1646 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1647 {
1648 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1649 u64 portmask;
1650
1651 if (mc_group >= MAX_MC_GROUPS - 1)
1652 return -1;
1653
1654 pr_debug("Using MC group %d\n", mc_group);
1655
1656 if (priv->is_lagmember[port]) {
1657 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1658 return 0;
1659 }
1660
1661 set_bit(mc_group, priv->mc_group_bm);
1662 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1663 portmask = BIT_ULL(port);
1664 priv->r->write_mcast_pmask(mc_group, portmask);
1665
1666 return mc_group;
1667 }
1668
1669 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1670 {
1671 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1672
1673 if (priv->is_lagmember[port]) {
1674 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1675 return portmask;
1676 }
1677
1678 portmask |= BIT_ULL(port);
1679 priv->r->write_mcast_pmask(mc_group, portmask);
1680
1681 return portmask;
1682 }
1683
1684 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1685 {
1686 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1687
1688 if (priv->is_lagmember[port]) {
1689 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1690 return portmask;
1691 }
1692
1693 portmask &= ~BIT_ULL(port);
1694 priv->r->write_mcast_pmask(mc_group, portmask);
1695 if (!portmask)
1696 clear_bit(mc_group, priv->mc_group_bm);
1697
1698 return portmask;
1699 }
1700
1701 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1702 const struct switchdev_obj_port_mdb *mdb)
1703 {
1704 struct rtl838x_switch_priv *priv = ds->priv;
1705 u64 mac = ether_addr_to_u64(mdb->addr);
1706 struct rtl838x_l2_entry e;
1707 int err = 0, idx;
1708 int vid = mdb->vid;
1709 u64 seed = priv->r->l2_hash_seed(mac, vid);
1710 int mc_group;
1711
1712 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1713
1714 if (priv->is_lagmember[port]) {
1715 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1716 return;
1717 }
1718
1719 mutex_lock(&priv->reg_mutex);
1720
1721 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1722
1723 // Found an existing or empty entry
1724 if (idx >= 0) {
1725 if (e.valid) {
1726 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1727 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1728 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1729 } else {
1730 pr_debug("New entry for seed %016llx\n", seed);
1731 mc_group = rtl83xx_mc_group_alloc(priv, port);
1732 if (mc_group < 0) {
1733 err = -ENOTSUPP;
1734 goto out;
1735 }
1736 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1737 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1738 }
1739 goto out;
1740 }
1741
1742 // Hash buckets full, try CAM
1743 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1744
1745 if (idx >= 0) {
1746 if (e.valid) {
1747 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1748 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1749 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1750 } else {
1751 pr_debug("New entry\n");
1752 mc_group = rtl83xx_mc_group_alloc(priv, port);
1753 if (mc_group < 0) {
1754 err = -ENOTSUPP;
1755 goto out;
1756 }
1757 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1758 priv->r->write_cam(idx, &e);
1759 }
1760 goto out;
1761 }
1762
1763 err = -ENOTSUPP;
1764 out:
1765 mutex_unlock(&priv->reg_mutex);
1766 if (err)
1767 dev_err(ds->dev, "failed to add MDB entry\n");
1768 }
1769
1770 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1771 const struct switchdev_obj_port_mdb *mdb)
1772 {
1773 struct rtl838x_switch_priv *priv = ds->priv;
1774 u64 mac = ether_addr_to_u64(mdb->addr);
1775 struct rtl838x_l2_entry e;
1776 int err = 0, idx;
1777 int vid = mdb->vid;
1778 u64 seed = priv->r->l2_hash_seed(mac, vid);
1779 u64 portmask;
1780
1781 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1782
1783 if (priv->is_lagmember[port]) {
1784 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1785 return 0;
1786 }
1787
1788 mutex_lock(&priv->reg_mutex);
1789
1790 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1791
1792 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1793 if (idx >= 0) {
1794 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1795 if (!portmask) {
1796 e.valid = false;
1797 // dump_l2_entry(&e);
1798 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1799 }
1800 goto out;
1801 }
1802
1803 /* Check CAM for spillover from hash buckets */
1804 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1805
1806 if (idx >= 0) {
1807 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1808 if (!portmask) {
1809 e.valid = false;
1810 // dump_l2_entry(&e);
1811 priv->r->write_cam(idx, &e);
1812 }
1813 goto out;
1814 }
1815 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1816 out:
1817 mutex_unlock(&priv->reg_mutex);
1818 return err;
1819 }
1820
1821 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1822 struct dsa_mall_mirror_tc_entry *mirror,
1823 bool ingress)
1824 {
1825 /* We support 4 mirror groups, one destination port per group */
1826 int group;
1827 struct rtl838x_switch_priv *priv = ds->priv;
1828 int ctrl_reg, dpm_reg, spm_reg;
1829
1830 pr_debug("In %s\n", __func__);
1831
1832 for (group = 0; group < 4; group++) {
1833 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1834 break;
1835 }
1836 if (group >= 4) {
1837 for (group = 0; group < 4; group++) {
1838 if (priv->mirror_group_ports[group] < 0)
1839 break;
1840 }
1841 }
1842
1843 if (group >= 4)
1844 return -ENOSPC;
1845
1846 ctrl_reg = priv->r->mir_ctrl + group * 4;
1847 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1848 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1849
1850 pr_debug("Using group %d\n", group);
1851 mutex_lock(&priv->reg_mutex);
1852
1853 if (priv->family_id == RTL8380_FAMILY_ID) {
1854 /* Enable mirroring to port across VLANs (bit 11) */
1855 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1856 } else {
1857 /* Enable mirroring to destination port */
1858 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1859 }
1860
1861 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1862 mutex_unlock(&priv->reg_mutex);
1863 return -EEXIST;
1864 }
1865 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1866 mutex_unlock(&priv->reg_mutex);
1867 return -EEXIST;
1868 }
1869
1870 if (ingress)
1871 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1872 else
1873 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1874
1875 priv->mirror_group_ports[group] = mirror->to_local_port;
1876 mutex_unlock(&priv->reg_mutex);
1877 return 0;
1878 }
1879
1880 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1881 struct dsa_mall_mirror_tc_entry *mirror)
1882 {
1883 int group = 0;
1884 struct rtl838x_switch_priv *priv = ds->priv;
1885 int ctrl_reg, dpm_reg, spm_reg;
1886
1887 pr_debug("In %s\n", __func__);
1888 for (group = 0; group < 4; group++) {
1889 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1890 break;
1891 }
1892 if (group >= 4)
1893 return;
1894
1895 ctrl_reg = priv->r->mir_ctrl + group * 4;
1896 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1897 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1898
1899 mutex_lock(&priv->reg_mutex);
1900 if (mirror->ingress) {
1901 /* Ingress, clear source port matrix */
1902 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1903 } else {
1904 /* Egress, clear destination port matrix */
1905 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1906 }
1907
1908 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1909 priv->mirror_group_ports[group] = -1;
1910 sw_w32(0, ctrl_reg);
1911 }
1912
1913 mutex_unlock(&priv->reg_mutex);
1914 }
1915
1916 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1917 {
1918 struct rtl838x_switch_priv *priv = ds->priv;
1919 unsigned long features = 0;
1920 pr_debug("%s: %d %lX\n", __func__, port, flags);
1921 if (priv->r->enable_learning)
1922 features |= BR_LEARNING;
1923 if (priv->r->enable_flood)
1924 features |= BR_FLOOD;
1925 if (priv->r->enable_mcast_flood)
1926 features |= BR_MCAST_FLOOD;
1927 if (priv->r->enable_bcast_flood)
1928 features |= BR_BCAST_FLOOD;
1929 if (flags & ~(features))
1930 return -EINVAL;
1931
1932 return 0;
1933 }
1934
1935 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1936 {
1937 struct rtl838x_switch_priv *priv = ds->priv;
1938
1939 pr_debug("%s: %d %lX\n", __func__, port, flags);
1940 if (priv->r->enable_learning)
1941 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
1942
1943 if (priv->r->enable_flood)
1944 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
1945
1946 if (priv->r->enable_mcast_flood)
1947 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
1948
1949 if (priv->r->enable_bcast_flood)
1950 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
1951
1952 return 0;
1953 }
1954
1955 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1956 struct net_device *lag,
1957 struct netdev_lag_upper_info *info)
1958 {
1959 int id;
1960
1961 id = dsa_lag_id(ds->dst, lag);
1962 if (id < 0 || id >= ds->num_lag_ids)
1963 return false;
1964
1965 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1966 return false;
1967 }
1968 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1969 return false;
1970
1971 return true;
1972 }
1973
1974 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
1975 {
1976 struct rtl838x_switch_priv *priv = ds->priv;
1977
1978 pr_debug("%s: %d\n", __func__, port);
1979 // Nothing to be done...
1980
1981 return 0;
1982 }
1983
1984 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
1985 struct net_device *lag,
1986 struct netdev_lag_upper_info *info)
1987 {
1988 struct rtl838x_switch_priv *priv = ds->priv;
1989 int i, err = 0;
1990
1991 if (!rtl83xx_lag_can_offload(ds, lag, info))
1992 return -EOPNOTSUPP;
1993
1994 mutex_lock(&priv->reg_mutex);
1995
1996 for (i = 0; i < priv->n_lags; i++) {
1997 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
1998 break;
1999 }
2000 if (port >= priv->cpu_port) {
2001 err = -EINVAL;
2002 goto out;
2003 }
2004 pr_info("port_lag_join: group %d, port %d\n",i, port);
2005 if (!priv->lag_devs[i])
2006 priv->lag_devs[i] = lag;
2007
2008 if (priv->lag_primary[i]==-1) {
2009 priv->lag_primary[i]=port;
2010 } else
2011 priv->is_lagmember[port] = 1;
2012
2013 priv->lagmembers |= (1ULL << port);
2014
2015 pr_debug("lag_members = %llX\n", priv->lagmembers);
2016 err = rtl83xx_lag_add(priv->ds, i, port, info);
2017 if (err) {
2018 err = -EINVAL;
2019 goto out;
2020 }
2021
2022 out:
2023 mutex_unlock(&priv->reg_mutex);
2024 return err;
2025
2026 }
2027
2028 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2029 struct net_device *lag)
2030 {
2031 int i, group = -1, err;
2032 struct rtl838x_switch_priv *priv = ds->priv;
2033
2034 mutex_lock(&priv->reg_mutex);
2035 for (i=0;i<priv->n_lags;i++) {
2036 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2037 group = i;
2038 break;
2039 }
2040 }
2041
2042 if (group == -1) {
2043 pr_info("port_lag_leave: port %d is not a member\n", port);
2044 err = -EINVAL;
2045 goto out;
2046 }
2047
2048 if (port >= priv->cpu_port) {
2049 err = -EINVAL;
2050 goto out;
2051 }
2052 pr_info("port_lag_del: group %d, port %d\n",group, port);
2053 priv->lagmembers &=~ (1ULL << port);
2054 priv->lag_primary[i] = -1;
2055 priv->is_lagmember[port] = 0;
2056 pr_debug("lag_members = %llX\n", priv->lagmembers);
2057 err = rtl83xx_lag_del(priv->ds, group, port);
2058 if (err) {
2059 err = -EINVAL;
2060 goto out;
2061 }
2062 if (!priv->lags_port_members[i])
2063 priv->lag_devs[i] = NULL;
2064
2065 out:
2066 mutex_unlock(&priv->reg_mutex);
2067 return 0;
2068 }
2069
2070 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2071 {
2072 u32 val;
2073 u32 offset = 0;
2074 struct rtl838x_switch_priv *priv = ds->priv;
2075
2076 if (phy_addr >= 24 && phy_addr <= 27
2077 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2078 if (phy_addr == 26)
2079 offset = 0x100;
2080 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2081 return val;
2082 }
2083
2084 read_phy(phy_addr, 0, phy_reg, &val);
2085 return val;
2086 }
2087
2088 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2089 {
2090 u32 offset = 0;
2091 struct rtl838x_switch_priv *priv = ds->priv;
2092
2093 if (phy_addr >= 24 && phy_addr <= 27
2094 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2095 if (phy_addr == 26)
2096 offset = 0x100;
2097 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2098 return 0;
2099 }
2100 return write_phy(phy_addr, 0, phy_reg, val);
2101 }
2102
2103 const struct dsa_switch_ops rtl83xx_switch_ops = {
2104 .get_tag_protocol = rtl83xx_get_tag_protocol,
2105 .setup = rtl83xx_setup,
2106
2107 .phy_read = dsa_phy_read,
2108 .phy_write = dsa_phy_write,
2109
2110 .phylink_validate = rtl83xx_phylink_validate,
2111 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2112 .phylink_mac_config = rtl83xx_phylink_mac_config,
2113 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2114 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2115
2116 .get_strings = rtl83xx_get_strings,
2117 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2118 .get_sset_count = rtl83xx_get_sset_count,
2119
2120 .port_enable = rtl83xx_port_enable,
2121 .port_disable = rtl83xx_port_disable,
2122
2123 .get_mac_eee = rtl83xx_get_mac_eee,
2124 .set_mac_eee = rtl83xx_set_mac_eee,
2125
2126 .set_ageing_time = rtl83xx_set_ageing_time,
2127 .port_bridge_join = rtl83xx_port_bridge_join,
2128 .port_bridge_leave = rtl83xx_port_bridge_leave,
2129 .port_stp_state_set = rtl83xx_port_stp_state_set,
2130 .port_fast_age = rtl83xx_fast_age,
2131
2132 .port_vlan_filtering = rtl83xx_vlan_filtering,
2133 .port_vlan_prepare = rtl83xx_vlan_prepare,
2134 .port_vlan_add = rtl83xx_vlan_add,
2135 .port_vlan_del = rtl83xx_vlan_del,
2136
2137 .port_fdb_add = rtl83xx_port_fdb_add,
2138 .port_fdb_del = rtl83xx_port_fdb_del,
2139 .port_fdb_dump = rtl83xx_port_fdb_dump,
2140
2141 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2142 .port_mdb_add = rtl83xx_port_mdb_add,
2143 .port_mdb_del = rtl83xx_port_mdb_del,
2144
2145 .port_mirror_add = rtl83xx_port_mirror_add,
2146 .port_mirror_del = rtl83xx_port_mirror_del,
2147
2148 .port_lag_change = rtl83xx_port_lag_change,
2149 .port_lag_join = rtl83xx_port_lag_join,
2150 .port_lag_leave = rtl83xx_port_lag_leave,
2151
2152 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2153 .port_bridge_flags = rtl83xx_port_bridge_flags,
2154 };
2155
2156 const struct dsa_switch_ops rtl930x_switch_ops = {
2157 .get_tag_protocol = rtl83xx_get_tag_protocol,
2158 .setup = rtl93xx_setup,
2159
2160 .phy_read = dsa_phy_read,
2161 .phy_write = dsa_phy_write,
2162
2163 .phylink_validate = rtl93xx_phylink_validate,
2164 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2165 .phylink_mac_config = rtl93xx_phylink_mac_config,
2166 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2167 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2168
2169 .get_strings = rtl83xx_get_strings,
2170 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2171 .get_sset_count = rtl83xx_get_sset_count,
2172
2173 .port_enable = rtl83xx_port_enable,
2174 .port_disable = rtl83xx_port_disable,
2175
2176 .get_mac_eee = rtl93xx_get_mac_eee,
2177 .set_mac_eee = rtl83xx_set_mac_eee,
2178
2179 .set_ageing_time = rtl83xx_set_ageing_time,
2180 .port_bridge_join = rtl83xx_port_bridge_join,
2181 .port_bridge_leave = rtl83xx_port_bridge_leave,
2182 .port_stp_state_set = rtl83xx_port_stp_state_set,
2183 .port_fast_age = rtl930x_fast_age,
2184
2185 .port_vlan_filtering = rtl83xx_vlan_filtering,
2186 .port_vlan_prepare = rtl83xx_vlan_prepare,
2187 .port_vlan_add = rtl83xx_vlan_add,
2188 .port_vlan_del = rtl83xx_vlan_del,
2189
2190 .port_fdb_add = rtl83xx_port_fdb_add,
2191 .port_fdb_del = rtl83xx_port_fdb_del,
2192 .port_fdb_dump = rtl83xx_port_fdb_dump,
2193
2194 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2195 .port_mdb_add = rtl83xx_port_mdb_add,
2196 .port_mdb_del = rtl83xx_port_mdb_del,
2197
2198 .port_lag_change = rtl83xx_port_lag_change,
2199 .port_lag_join = rtl83xx_port_lag_join,
2200 .port_lag_leave = rtl83xx_port_lag_leave,
2201
2202 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2203 .port_bridge_flags = rtl83xx_port_bridge_flags,
2204 };
Staging tree of Jo-Philipp Wich