1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/iopoll.h>
5 #include <net/nexthop.h>
9 extern struct mutex smi_lock
;
11 // see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
12 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
13 enum template_field_id
{
14 TEMPLATE_FIELD_SPMMASK
= 0,
15 TEMPLATE_FIELD_SPM0
= 1, // Source portmask ports 0-15
16 TEMPLATE_FIELD_SPM1
= 2, // Source portmask ports 16-28
17 TEMPLATE_FIELD_RANGE_CHK
= 3,
18 TEMPLATE_FIELD_DMAC0
= 4, // Destination MAC [15:0]
19 TEMPLATE_FIELD_DMAC1
= 5, // Destination MAC [31:16]
20 TEMPLATE_FIELD_DMAC2
= 6, // Destination MAC [47:32]
21 TEMPLATE_FIELD_SMAC0
= 7, // Source MAC [15:0]
22 TEMPLATE_FIELD_SMAC1
= 8, // Source MAC [31:16]
23 TEMPLATE_FIELD_SMAC2
= 9, // Source MAC [47:32]
24 TEMPLATE_FIELD_ETHERTYPE
= 10, // Ethernet typ
25 TEMPLATE_FIELD_OTAG
= 11, // Outer VLAN tag
26 TEMPLATE_FIELD_ITAG
= 12, // Inner VLAN tag
27 TEMPLATE_FIELD_SIP0
= 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
28 // source protocol address in header
29 TEMPLATE_FIELD_SIP1
= 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
30 TEMPLATE_FIELD_DIP0
= 15, // IPv4 or IPv6 destination IP[15:0]
31 TEMPLATE_FIELD_DIP1
= 16, // IPv4 or IPv6 destination IP[31:16]
32 TEMPLATE_FIELD_IP_TOS_PROTO
= 17, // IPv4 TOS/IPv6 traffic class and
33 // IPv4 proto/IPv6 next header fields
34 TEMPLATE_FIELD_L34_HEADER
= 18, // packet with extra tag and IPv6 with auth, dest,
35 // frag, route, hop-by-hop option header,
36 // IGMP type, TCP flag
37 TEMPLATE_FIELD_L4_SPORT
= 19, // TCP/UDP source port
38 TEMPLATE_FIELD_L4_DPORT
= 20, // TCP/UDP destination port
39 TEMPLATE_FIELD_ICMP_IGMP
= 21,
40 TEMPLATE_FIELD_IP_RANGE
= 22,
41 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 23, // Field selector mask
42 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 24,
43 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 25,
44 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 26,
45 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 27,
46 TEMPLATE_FIELD_SIP2
= 28, // IPv6 source IP[47:32]
47 TEMPLATE_FIELD_SIP3
= 29, // IPv6 source IP[63:48]
48 TEMPLATE_FIELD_SIP4
= 30, // IPv6 source IP[79:64]
49 TEMPLATE_FIELD_SIP5
= 31, // IPv6 source IP[95:80]
50 TEMPLATE_FIELD_SIP6
= 32, // IPv6 source IP[111:96]
51 TEMPLATE_FIELD_SIP7
= 33, // IPv6 source IP[127:112]
52 TEMPLATE_FIELD_DIP2
= 34, // IPv6 destination IP[47:32]
53 TEMPLATE_FIELD_DIP3
= 35, // IPv6 destination IP[63:48]
54 TEMPLATE_FIELD_DIP4
= 36, // IPv6 destination IP[79:64]
55 TEMPLATE_FIELD_DIP5
= 37, // IPv6 destination IP[95:80]
56 TEMPLATE_FIELD_DIP6
= 38, // IPv6 destination IP[111:96]
57 TEMPLATE_FIELD_DIP7
= 39, // IPv6 destination IP[127:112]
58 TEMPLATE_FIELD_FWD_VID
= 40, // Forwarding VLAN-ID
59 TEMPLATE_FIELD_FLOW_LABEL
= 41,
63 * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
64 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
65 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
66 * templates. Additionally, 3 user-definable templates can be set up via the definitions
67 * in RTL838X_ACL_TMPLTE_CTRL control registers.
68 * TODO: See all src/app/diag_v2/src/diag_pie.c
70 #define N_FIXED_TEMPLATES 5
71 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
74 TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_OTAG
,
75 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
76 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
77 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_RANGE_CHK
79 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
80 TEMPLATE_FIELD_DIP1
,TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_L4_SPORT
,
81 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_ITAG
,
82 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
84 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
85 TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
86 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_SIP0
,
87 TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
89 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
90 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
91 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_L4_DPORT
,
92 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_IP_TOS_PROTO
94 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
95 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
96 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_ITAG
,
97 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
101 void rtl838x_print_matrix(void)
103 unsigned volatile int *ptr8
;
106 ptr8
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
107 for (i
= 0; i
< 28; i
+= 8)
108 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
109 ptr8
[i
+ 0], ptr8
[i
+ 1], ptr8
[i
+ 2], ptr8
[i
+ 3],
110 ptr8
[i
+ 4], ptr8
[i
+ 5], ptr8
[i
+ 6], ptr8
[i
+ 7]);
111 pr_debug("CPU_PORT> %8x\n", ptr8
[28]);
114 static inline int rtl838x_port_iso_ctrl(int p
)
116 return RTL838X_PORT_ISO_CTRL(p
);
119 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
121 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
122 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & BIT(15));
125 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
127 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
128 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & BIT(15));
131 static inline int rtl838x_tbl_access_data_0(int i
)
133 return RTL838X_TBL_ACCESS_DATA_0(i
);
136 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
139 // Read VLAN table (0) via register 0
140 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
142 rtl_table_read(r
, vlan
);
143 info
->tagged_ports
= sw_r32(rtl_table_data(r
, 0));
144 v
= sw_r32(rtl_table_data(r
, 1));
145 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan
, info
->tagged_ports
, v
);
146 rtl_table_release(r
);
148 info
->profile_id
= v
& 0x7;
149 info
->hash_mc_fid
= !!(v
& 0x8);
150 info
->hash_uc_fid
= !!(v
& 0x10);
151 info
->fid
= (v
>> 5) & 0x3f;
153 // Read UNTAG table (0) via table register 1
154 r
= rtl_table_get(RTL8380_TBL_1
, 0);
155 rtl_table_read(r
, vlan
);
156 info
->untagged_ports
= sw_r32(rtl_table_data(r
, 0));
157 rtl_table_release(r
);
160 static void rtl838x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
163 // Access VLAN table (0) via register 0
164 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
166 sw_w32(info
->tagged_ports
, rtl_table_data(r
, 0));
168 v
= info
->profile_id
;
169 v
|= info
->hash_mc_fid
? 0x8 : 0;
170 v
|= info
->hash_uc_fid
? 0x10 : 0;
171 v
|= ((u32
)info
->fid
) << 5;
172 sw_w32(v
, rtl_table_data(r
, 1));
174 rtl_table_write(r
, vlan
);
175 rtl_table_release(r
);
178 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
180 // Access UNTAG table (0) via register 1
181 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 0);
183 sw_w32(portmask
& 0x1fffffff, rtl_table_data(r
, 0));
184 rtl_table_write(r
, vlan
);
185 rtl_table_release(r
);
188 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
190 static void rtl838x_vlan_fwd_on_inner(int port
, bool is_set
)
193 sw_w32_mask(BIT(port
), 0, RTL838X_VLAN_PORT_FWD
);
195 sw_w32_mask(0, BIT(port
), RTL838X_VLAN_PORT_FWD
);
198 static u64
rtl838x_l2_hash_seed(u64 mac
, u32 vid
)
200 return mac
<< 12 | vid
;
204 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
205 * and returns a key into the L2 hash table
207 static u32
rtl838x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
211 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
212 h1
= (seed
>> 11) & 0x7ff;
213 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
215 h2
= (seed
>> 33) & 0x7ff;
216 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
218 h3
= (seed
>> 44) & 0x7ff;
219 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
221 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
222 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
224 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
225 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
226 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
232 static inline int rtl838x_mac_force_mode_ctrl(int p
)
234 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
237 static inline int rtl838x_mac_port_ctrl(int p
)
239 return RTL838X_MAC_PORT_CTRL(p
);
242 static inline int rtl838x_l2_port_new_salrn(int p
)
244 return RTL838X_L2_PORT_NEW_SALRN(p
);
247 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
249 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
252 static inline int rtl838x_mac_link_spd_sts(int p
)
254 return RTL838X_MAC_LINK_SPD_STS(p
);
257 inline static int rtl838x_trk_mbr_ctr(int group
)
259 return RTL838X_TRK_MBR_CTR
+ (group
<< 2);
263 * Fills an L2 entry structure from the SoC registers
265 static void rtl838x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
267 /* Table contains different entry types, we need to identify the right one:
268 * Check for MC entries, first
269 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
270 * identify valid entries
272 e
->is_ip_mc
= !!(r
[0] & BIT(22));
273 e
->is_ipv6_mc
= !!(r
[0] & BIT(21));
274 e
->type
= L2_INVALID
;
276 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
277 e
->mac
[0] = (r
[1] >> 20);
278 e
->mac
[1] = (r
[1] >> 12);
279 e
->mac
[2] = (r
[1] >> 4);
280 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
281 e
->mac
[4] = (r
[2] >> 20);
282 e
->mac
[5] = (r
[2] >> 12);
284 e
->rvid
= r
[2] & 0xfff;
285 e
->vid
= r
[0] & 0xfff;
287 /* Is it a unicast entry? check multicast bit */
288 if (!(e
->mac
[0] & 1)) {
289 e
->is_static
= !!((r
[0] >> 19) & 1);
290 e
->port
= (r
[0] >> 12) & 0x1f;
291 e
->block_da
= !!(r
[1] & BIT(30));
292 e
->block_sa
= !!(r
[1] & BIT(31));
293 e
->suspended
= !!(r
[1] & BIT(29));
294 e
->next_hop
= !!(r
[1] & BIT(28));
296 pr_debug("Found next hop entry, need to read extra data\n");
297 e
->nh_vlan_target
= !!(r
[0] & BIT(9));
298 e
->nh_route_id
= r
[0] & 0x1ff;
301 e
->age
= (r
[0] >> 17) & 0x3;
304 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
305 * next-hop or static entry bit set */
306 if (!(r
[0] & 0x007c0000) && !(r
[1] & 0xd0000000))
309 e
->type
= L2_UNICAST
;
310 } else { // L2 multicast
311 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
313 e
->type
= L2_MULTICAST
;
314 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
316 } else { // IPv4 and IPv6 multicast
318 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
319 e
->mc_gip
= (r
[1] << 20) | (r
[2] >> 12);
320 e
->rvid
= r
[2] & 0xfff;
323 e
->type
= IP4_MULTICAST
;
325 e
->type
= IP6_MULTICAST
;
329 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
331 static void rtl838x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
333 u64 mac
= ether_addr_to_u64(e
->mac
);
336 r
[0] = r
[1] = r
[2] = 0;
340 r
[0] = e
->is_ip_mc
? BIT(22) : 0;
341 r
[0] |= e
->is_ipv6_mc
? BIT(21) : 0;
343 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
345 r
[2] = (mac
& 0xfffff) << 12;
347 /* Is it a unicast entry? check multicast bit */
348 if (!(e
->mac
[0] & 1)) {
349 r
[0] |= e
->is_static
? BIT(19) : 0;
350 r
[0] |= (e
->port
& 0x3f) << 12;
352 r
[1] |= e
->block_da
? BIT(30) : 0;
353 r
[1] |= e
->block_sa
? BIT(31) : 0;
354 r
[1] |= e
->suspended
? BIT(29) : 0;
355 r
[2] |= e
->rvid
& 0xfff;
358 r
[0] |= e
->nh_vlan_target
? BIT(9) : 0;
359 r
[0] |= e
->nh_route_id
& 0x1ff;
361 r
[0] |= (e
->age
& 0x3) << 17;
362 } else { // L2 Multicast
363 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
364 r
[2] |= e
->rvid
& 0xfff;
365 r
[0] |= e
->vid
& 0xfff;
366 pr_debug("FILL MC: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
368 } else { // IPv4 and IPv6 multicast
369 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
370 r
[1] = e
->mc_gip
>> 20;
371 r
[2] = e
->mc_gip
<< 12;
377 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
378 * hash is the id of the bucket and pos is the position of the entry in that bucket
379 * The data read from the SoC is filled into rtl838x_l2_entry
381 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
385 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0); // Access L2 Table 0
386 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
389 rtl_table_read(q
, idx
);
390 for (i
= 0; i
< 3; i
++)
391 r
[i
] = sw_r32(rtl_table_data(q
, i
));
393 rtl_table_release(q
);
395 rtl838x_fill_l2_entry(r
, e
);
399 entry
= (((u64
) r
[1]) << 32) | (r
[2]); // mac and vid concatenated as hash seed
403 static void rtl838x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
406 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0);
409 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
411 rtl838x_fill_l2_row(r
, e
);
413 for (i
= 0; i
< 3; i
++)
414 sw_w32(r
[i
], rtl_table_data(q
, i
));
416 rtl_table_write(q
, idx
);
417 rtl_table_release(q
);
420 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
424 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
427 rtl_table_read(q
, idx
);
428 for (i
= 0; i
< 3; i
++)
429 r
[i
] = sw_r32(rtl_table_data(q
, i
));
431 rtl_table_release(q
);
433 rtl838x_fill_l2_entry(r
, e
);
437 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
439 // Return MAC with concatenated VID ac concatenated ID
440 entry
= (((u64
) r
[1]) << 32) | r
[2];
444 static void rtl838x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
447 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
450 rtl838x_fill_l2_row(r
, e
);
452 for (i
= 0; i
< 3; i
++)
453 sw_w32(r
[i
], rtl_table_data(q
, i
));
455 rtl_table_write(q
, idx
);
456 rtl_table_release(q
);
459 static u64
rtl838x_read_mcast_pmask(int idx
)
462 // Read MC_PMSK (2) via register RTL8380_TBL_L2
463 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
465 rtl_table_read(q
, idx
);
466 portmask
= sw_r32(rtl_table_data(q
, 0));
467 rtl_table_release(q
);
472 static void rtl838x_write_mcast_pmask(int idx
, u64 portmask
)
474 // Access MC_PMSK (2) via register RTL8380_TBL_L2
475 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
477 sw_w32(((u32
)portmask
) & 0x1fffffff, rtl_table_data(q
, 0));
478 rtl_table_write(q
, idx
);
479 rtl_table_release(q
);
482 static void rtl838x_vlan_profile_setup(int profile
)
484 u32 pmask_id
= UNKNOWN_MC_PMASK
;
485 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
486 u32 p
= 1 | pmask_id
<< 1 | pmask_id
<< 10 | pmask_id
<< 19;
488 sw_w32(p
, RTL838X_VLAN_PROFILE(profile
));
490 /* RTL8380 and RTL8390 use an index into the portmask table to set the
491 * unknown multicast portmask, setup a default at a safe location
492 * On RTL93XX, the portmask is directly set in the profile,
493 * see e.g. rtl9300_vlan_profile_setup
495 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x1fffffff);
498 static void rtl838x_l2_learning_setup(void)
500 /* Set portmask for broadcast traffic and unknown unicast address flooding
501 * to the reserved entry in the portmask table used also for
502 * multicast flooding */
503 sw_w32(UNKNOWN_MC_PMASK
<< 12 | UNKNOWN_MC_PMASK
, RTL838X_L2_FLD_PMSK
);
505 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
506 * and per vlan (bit 2) */
507 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN
);
509 // Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
510 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT
);
512 // Do not trap ARP packets to CPU_PORT
513 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL
);
516 static void rtl838x_enable_learning(int port
, bool enable
)
518 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
521 // flood after 32k entries
522 sw_w32((0x3fff << 2) | 0, RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
525 sw_w32(0, RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
529 static void rtl838x_enable_flood(int port
, bool enable
)
531 u32 flood_mask
= sw_r32(RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
537 sw_w32(flood_mask
, RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
542 sw_w32(flood_mask
, RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
546 static void rtl838x_enable_mcast_flood(int port
, bool enable
)
551 static void rtl838x_enable_bcast_flood(int port
, bool enable
)
556 static void rtl838x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
559 u32 cmd
= 1 << 15 /* Execute cmd */
561 | 2 << 12 /* Table type 0b10 */
563 priv
->r
->exec_tbl0_cmd(cmd
);
565 for (i
= 0; i
< 2; i
++)
566 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
569 static void rtl838x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
572 u32 cmd
= 1 << 15 /* Execute cmd */
573 | 0 << 14 /* Write */
574 | 2 << 12 /* Table type 0b10 */
577 for (i
= 0; i
< 2; i
++)
578 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
579 priv
->r
->exec_tbl0_cmd(cmd
);
582 u64
rtl838x_traffic_get(int source
)
584 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source
));
587 void rtl838x_traffic_set(int source
, u64 dest_matrix
)
589 rtl838x_set_port_reg(dest_matrix
, rtl838x_port_iso_ctrl(source
));
592 void rtl838x_traffic_enable(int source
, int dest
)
594 rtl838x_mask_port_reg(0, BIT(dest
), rtl838x_port_iso_ctrl(source
));
597 void rtl838x_traffic_disable(int source
, int dest
)
599 rtl838x_mask_port_reg(BIT(dest
), 0, rtl838x_port_iso_ctrl(source
));
603 * Enables or disables the EEE/EEEP capability of a port
605 static void rtl838x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
609 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
613 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
614 v
= enable
? 0x3 : 0x0;
616 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
617 sw_w32_mask(0x3 << 9, v
<< 9, priv
->r
->mac_force_mode_ctrl(port
));
619 // Set TX/RX EEE state
621 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_TX_EN
);
622 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_RX_EN
);
624 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_TX_EN
);
625 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_RX_EN
);
627 priv
->ports
[port
].eee_enabled
= enable
;
632 * Get EEE own capabilities and negotiation result
634 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv
*priv
,
635 struct ethtool_eee
*e
, int port
)
642 link
= rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS
);
643 if (!(link
& BIT(port
)))
646 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(9))
647 e
->advertised
|= ADVERTISED_100baseT_Full
;
649 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(10))
650 e
->advertised
|= ADVERTISED_1000baseT_Full
;
652 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & BIT(port
)) {
653 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
654 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
661 static void rtl838x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
665 pr_info("Setting up EEE, state: %d\n", enable
);
666 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
668 /* Set timers for EEE */
669 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
670 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
672 // Enable EEE MAC support on ports
673 for (i
= 0; i
< priv
->cpu_port
; i
++) {
674 if (priv
->ports
[i
].phy
)
675 rtl838x_port_eee_set(priv
, i
, enable
);
677 priv
->eee_enabled
= enable
;
680 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
682 int block
= index
/ PIE_BLOCK_SIZE
;
683 u32 block_state
= sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL
);
685 // Make sure rule-lookup is enabled in the block
686 if (!(block_state
& BIT(block
)))
687 sw_w32(block_state
| BIT(block
), RTL838X_ACL_BLK_LOOKUP_CTRL
);
690 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
692 int block_from
= index_from
/ PIE_BLOCK_SIZE
;
693 int block_to
= index_to
/ PIE_BLOCK_SIZE
;
694 u32 v
= (index_from
<< 1)| (index_to
<< 12 ) | BIT(0);
698 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
699 mutex_lock(&priv
->reg_mutex
);
701 // Remember currently active blocks
702 block_state
= sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL
);
704 // Make sure rule-lookup is disabled in the relevant blocks
705 for (block
= block_from
; block
<= block_to
; block
++) {
706 if (block_state
& BIT(block
))
707 sw_w32(block_state
& (~BIT(block
)), RTL838X_ACL_BLK_LOOKUP_CTRL
);
710 // Write from-to and execute bit into control register
711 sw_w32(v
, RTL838X_ACL_CLR_CTRL
);
713 // Wait until command has completed
715 } while (sw_r32(RTL838X_ACL_CLR_CTRL
) & BIT(0));
717 // Re-enable rule lookup
718 for (block
= block_from
; block
<= block_to
; block
++) {
719 if (!(block_state
& BIT(block
)))
720 sw_w32(block_state
| BIT(block
), RTL838X_ACL_BLK_LOOKUP_CTRL
);
723 mutex_unlock(&priv
->reg_mutex
);
727 * Reads the intermediate representation of the templated match-fields of the
728 * PIE rule in the pie_rule structure and fills in the raw data fields in the
729 * raw register space r[].
730 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
731 * however the RTL9310 has 2 more registers / fields and the physical field-ids
732 * are specific to every platform.
734 static void rtl838x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
737 enum template_field_id field_type
;
740 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
744 switch (field_type
) {
745 case TEMPLATE_FIELD_SPM0
:
749 case TEMPLATE_FIELD_SPM1
:
750 data
= pr
->spm
>> 16;
751 data_m
= pr
->spm_m
>> 16;
753 case TEMPLATE_FIELD_OTAG
:
757 case TEMPLATE_FIELD_SMAC0
:
759 data
= (data
<< 8) | pr
->smac
[5];
760 data_m
= pr
->smac_m
[4];
761 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
763 case TEMPLATE_FIELD_SMAC1
:
765 data
= (data
<< 8) | pr
->smac
[3];
766 data_m
= pr
->smac_m
[2];
767 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
769 case TEMPLATE_FIELD_SMAC2
:
771 data
= (data
<< 8) | pr
->smac
[1];
772 data_m
= pr
->smac_m
[0];
773 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
775 case TEMPLATE_FIELD_DMAC0
:
777 data
= (data
<< 8) | pr
->dmac
[5];
778 data_m
= pr
->dmac_m
[4];
779 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
781 case TEMPLATE_FIELD_DMAC1
:
783 data
= (data
<< 8) | pr
->dmac
[3];
784 data_m
= pr
->dmac_m
[2];
785 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
787 case TEMPLATE_FIELD_DMAC2
:
789 data
= (data
<< 8) | pr
->dmac
[1];
790 data_m
= pr
->dmac_m
[0];
791 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
793 case TEMPLATE_FIELD_ETHERTYPE
:
794 data
= pr
->ethertype
;
795 data_m
= pr
->ethertype_m
;
797 case TEMPLATE_FIELD_ITAG
:
801 case TEMPLATE_FIELD_RANGE_CHK
:
802 data
= pr
->field_range_check
;
803 data_m
= pr
->field_range_check_m
;
805 case TEMPLATE_FIELD_SIP0
:
807 data
= pr
->sip6
.s6_addr16
[7];
808 data_m
= pr
->sip6_m
.s6_addr16
[7];
814 case TEMPLATE_FIELD_SIP1
:
816 data
= pr
->sip6
.s6_addr16
[6];
817 data_m
= pr
->sip6_m
.s6_addr16
[6];
819 data
= pr
->sip
>> 16;
820 data_m
= pr
->sip_m
>> 16;
824 case TEMPLATE_FIELD_SIP2
:
825 case TEMPLATE_FIELD_SIP3
:
826 case TEMPLATE_FIELD_SIP4
:
827 case TEMPLATE_FIELD_SIP5
:
828 case TEMPLATE_FIELD_SIP6
:
829 case TEMPLATE_FIELD_SIP7
:
830 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
831 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
834 case TEMPLATE_FIELD_DIP0
:
836 data
= pr
->dip6
.s6_addr16
[7];
837 data_m
= pr
->dip6_m
.s6_addr16
[7];
844 case TEMPLATE_FIELD_DIP1
:
846 data
= pr
->dip6
.s6_addr16
[6];
847 data_m
= pr
->dip6_m
.s6_addr16
[6];
849 data
= pr
->dip
>> 16;
850 data_m
= pr
->dip_m
>> 16;
854 case TEMPLATE_FIELD_DIP2
:
855 case TEMPLATE_FIELD_DIP3
:
856 case TEMPLATE_FIELD_DIP4
:
857 case TEMPLATE_FIELD_DIP5
:
858 case TEMPLATE_FIELD_DIP6
:
859 case TEMPLATE_FIELD_DIP7
:
860 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
861 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
864 case TEMPLATE_FIELD_IP_TOS_PROTO
:
865 data
= pr
->tos_proto
;
866 data_m
= pr
->tos_proto_m
;
868 case TEMPLATE_FIELD_L4_SPORT
:
870 data_m
= pr
->sport_m
;
872 case TEMPLATE_FIELD_L4_DPORT
:
874 data_m
= pr
->dport_m
;
876 case TEMPLATE_FIELD_ICMP_IGMP
:
877 data
= pr
->icmp_igmp
;
878 data_m
= pr
->icmp_igmp_m
;
881 pr_info("%s: unknown field %d\n", __func__
, field_type
);
886 r
[12 - i
/ 2] = data_m
;
888 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
889 r
[12 - i
/ 2] |= ((u32
)data_m
) << 16;
895 * Creates the intermediate representation of the templated match-fields of the
896 * PIE rule in the pie_rule structure by reading the raw data fields in the
897 * raw register space r[].
898 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
899 * however the RTL9310 has 2 more registers / fields and the physical field-ids
901 static void rtl838x_read_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
904 enum template_field_id field_type
;
907 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
911 data_m
= r
[12 - i
/ 2];
913 data
= r
[5 - i
/ 2] >> 16;
914 data_m
= r
[12 - i
/ 2] >> 16;
917 switch (field_type
) {
918 case TEMPLATE_FIELD_SPM0
:
919 pr
->spm
= (pr
->spn
<< 16) | data
;
920 pr
->spm_m
= (pr
->spn
<< 16) | data_m
;
922 case TEMPLATE_FIELD_SPM1
:
926 case TEMPLATE_FIELD_OTAG
:
930 case TEMPLATE_FIELD_SMAC0
:
931 pr
->smac
[4] = data
>> 8;
933 pr
->smac_m
[4] = data
>> 8;
934 pr
->smac_m
[5] = data
;
936 case TEMPLATE_FIELD_SMAC1
:
937 pr
->smac
[2] = data
>> 8;
939 pr
->smac_m
[2] = data
>> 8;
940 pr
->smac_m
[3] = data
;
942 case TEMPLATE_FIELD_SMAC2
:
943 pr
->smac
[0] = data
>> 8;
945 pr
->smac_m
[0] = data
>> 8;
946 pr
->smac_m
[1] = data
;
948 case TEMPLATE_FIELD_DMAC0
:
949 pr
->dmac
[4] = data
>> 8;
951 pr
->dmac_m
[4] = data
>> 8;
952 pr
->dmac_m
[5] = data
;
954 case TEMPLATE_FIELD_DMAC1
:
955 pr
->dmac
[2] = data
>> 8;
957 pr
->dmac_m
[2] = data
>> 8;
958 pr
->dmac_m
[3] = data
;
960 case TEMPLATE_FIELD_DMAC2
:
961 pr
->dmac
[0] = data
>> 8;
963 pr
->dmac_m
[0] = data
>> 8;
964 pr
->dmac_m
[1] = data
;
966 case TEMPLATE_FIELD_ETHERTYPE
:
967 pr
->ethertype
= data
;
968 pr
->ethertype_m
= data_m
;
970 case TEMPLATE_FIELD_ITAG
:
974 case TEMPLATE_FIELD_RANGE_CHK
:
975 pr
->field_range_check
= data
;
976 pr
->field_range_check_m
= data_m
;
978 case TEMPLATE_FIELD_SIP0
:
982 case TEMPLATE_FIELD_SIP1
:
983 pr
->sip
= (pr
->sip
<< 16) | data
;
984 pr
->sip_m
= (pr
->sip
<< 16) | data_m
;
986 case TEMPLATE_FIELD_SIP2
:
988 // Make use of limitiations on the position of the match values
989 ipv6_addr_set(&pr
->sip6
, pr
->sip
, r
[5 - i
/ 2],
990 r
[4 - i
/ 2], r
[3 - i
/ 2]);
991 ipv6_addr_set(&pr
->sip6_m
, pr
->sip_m
, r
[5 - i
/ 2],
992 r
[4 - i
/ 2], r
[3 - i
/ 2]);
993 case TEMPLATE_FIELD_SIP3
:
994 case TEMPLATE_FIELD_SIP4
:
995 case TEMPLATE_FIELD_SIP5
:
996 case TEMPLATE_FIELD_SIP6
:
997 case TEMPLATE_FIELD_SIP7
:
1000 case TEMPLATE_FIELD_DIP0
:
1004 case TEMPLATE_FIELD_DIP1
:
1005 pr
->dip
= (pr
->dip
<< 16) | data
;
1006 pr
->dip_m
= (pr
->dip
<< 16) | data_m
;
1008 case TEMPLATE_FIELD_DIP2
:
1010 ipv6_addr_set(&pr
->dip6
, pr
->dip
, r
[5 - i
/ 2],
1011 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1012 ipv6_addr_set(&pr
->dip6_m
, pr
->dip_m
, r
[5 - i
/ 2],
1013 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1014 case TEMPLATE_FIELD_DIP3
:
1015 case TEMPLATE_FIELD_DIP4
:
1016 case TEMPLATE_FIELD_DIP5
:
1017 case TEMPLATE_FIELD_DIP6
:
1018 case TEMPLATE_FIELD_DIP7
:
1020 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1021 pr
->tos_proto
= data
;
1022 pr
->tos_proto_m
= data_m
;
1024 case TEMPLATE_FIELD_L4_SPORT
:
1026 pr
->sport_m
= data_m
;
1028 case TEMPLATE_FIELD_L4_DPORT
:
1030 pr
->dport_m
= data_m
;
1032 case TEMPLATE_FIELD_ICMP_IGMP
:
1033 pr
->icmp_igmp
= data
;
1034 pr
->icmp_igmp_m
= data_m
;
1037 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1042 static void rtl838x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1044 pr
->spmmask_fix
= (r
[6] >> 22) & 0x3;
1045 pr
->spn
= (r
[6] >> 16) & 0x3f;
1046 pr
->mgnt_vlan
= (r
[6] >> 15) & 1;
1047 pr
->dmac_hit_sw
= (r
[6] >> 14) & 1;
1048 pr
->not_first_frag
= (r
[6] >> 13) & 1;
1049 pr
->frame_type_l4
= (r
[6] >> 10) & 7;
1050 pr
->frame_type
= (r
[6] >> 8) & 3;
1051 pr
->otag_fmt
= (r
[6] >> 7) & 1;
1052 pr
->itag_fmt
= (r
[6] >> 6) & 1;
1053 pr
->otag_exist
= (r
[6] >> 5) & 1;
1054 pr
->itag_exist
= (r
[6] >> 4) & 1;
1055 pr
->frame_type_l2
= (r
[6] >> 2) & 3;
1058 pr
->spmmask_fix_m
= (r
[13] >> 22) & 0x3;
1059 pr
->spn_m
= (r
[13] >> 16) & 0x3f;
1060 pr
->mgnt_vlan_m
= (r
[13] >> 15) & 1;
1061 pr
->dmac_hit_sw_m
= (r
[13] >> 14) & 1;
1062 pr
->not_first_frag_m
= (r
[13] >> 13) & 1;
1063 pr
->frame_type_l4_m
= (r
[13] >> 10) & 7;
1064 pr
->frame_type_m
= (r
[13] >> 8) & 3;
1065 pr
->otag_fmt_m
= (r
[13] >> 7) & 1;
1066 pr
->itag_fmt_m
= (r
[13] >> 6) & 1;
1067 pr
->otag_exist_m
= (r
[13] >> 5) & 1;
1068 pr
->itag_exist_m
= (r
[13] >> 4) & 1;
1069 pr
->frame_type_l2_m
= (r
[13] >> 2) & 3;
1070 pr
->tid_m
= r
[13] & 3;
1072 pr
->valid
= r
[14] & BIT(31);
1073 pr
->cond_not
= r
[14] & BIT(30);
1074 pr
->cond_and1
= r
[14] & BIT(29);
1075 pr
->cond_and2
= r
[14] & BIT(28);
1076 pr
->ivalid
= r
[14] & BIT(27);
1078 pr
->drop
= (r
[17] >> 14) & 3;
1079 pr
->fwd_sel
= r
[17] & BIT(13);
1080 pr
->ovid_sel
= r
[17] & BIT(12);
1081 pr
->ivid_sel
= r
[17] & BIT(11);
1082 pr
->flt_sel
= r
[17] & BIT(10);
1083 pr
->log_sel
= r
[17] & BIT(9);
1084 pr
->rmk_sel
= r
[17] & BIT(8);
1085 pr
->meter_sel
= r
[17] & BIT(7);
1086 pr
->tagst_sel
= r
[17] & BIT(6);
1087 pr
->mir_sel
= r
[17] & BIT(5);
1088 pr
->nopri_sel
= r
[17] & BIT(4);
1089 pr
->cpupri_sel
= r
[17] & BIT(3);
1090 pr
->otpid_sel
= r
[17] & BIT(2);
1091 pr
->itpid_sel
= r
[17] & BIT(1);
1092 pr
->shaper_sel
= r
[17] & BIT(0);
1095 static void rtl838x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1097 r
[6] = ((u32
) (pr
->spmmask_fix
& 0x3)) << 22;
1098 r
[6] |= ((u32
) (pr
->spn
& 0x3f)) << 16;
1099 r
[6] |= pr
->mgnt_vlan
? BIT(15) : 0;
1100 r
[6] |= pr
->dmac_hit_sw
? BIT(14) : 0;
1101 r
[6] |= pr
->not_first_frag
? BIT(13) : 0;
1102 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 10;
1103 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 8;
1104 r
[6] |= pr
->otag_fmt
? BIT(7) : 0;
1105 r
[6] |= pr
->itag_fmt
? BIT(6) : 0;
1106 r
[6] |= pr
->otag_exist
? BIT(5) : 0;
1107 r
[6] |= pr
->itag_exist
? BIT(4) : 0;
1108 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 2;
1109 r
[6] |= ((u32
) (pr
->tid
& 0x3));
1111 r
[13] = ((u32
) (pr
->spmmask_fix_m
& 0x3)) << 22;
1112 r
[13] |= ((u32
) (pr
->spn_m
& 0x3f)) << 16;
1113 r
[13] |= pr
->mgnt_vlan_m
? BIT(15) : 0;
1114 r
[13] |= pr
->dmac_hit_sw_m
? BIT(14) : 0;
1115 r
[13] |= pr
->not_first_frag_m
? BIT(13) : 0;
1116 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 10;
1117 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 8;
1118 r
[13] |= pr
->otag_fmt_m
? BIT(7) : 0;
1119 r
[13] |= pr
->itag_fmt_m
? BIT(6) : 0;
1120 r
[13] |= pr
->otag_exist_m
? BIT(5) : 0;
1121 r
[13] |= pr
->itag_exist_m
? BIT(4) : 0;
1122 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 2;
1123 r
[13] |= ((u32
) (pr
->tid_m
& 0x3));
1125 r
[14] = pr
->valid
? BIT(31) : 0;
1126 r
[14] |= pr
->cond_not
? BIT(30) : 0;
1127 r
[14] |= pr
->cond_and1
? BIT(29) : 0;
1128 r
[14] |= pr
->cond_and2
? BIT(28) : 0;
1129 r
[14] |= pr
->ivalid
? BIT(27) : 0;
1132 r
[17] = 0x1 << 14; // Standard drop action
1135 r
[17] |= pr
->fwd_sel
? BIT(13) : 0;
1136 r
[17] |= pr
->ovid_sel
? BIT(12) : 0;
1137 r
[17] |= pr
->ivid_sel
? BIT(11) : 0;
1138 r
[17] |= pr
->flt_sel
? BIT(10) : 0;
1139 r
[17] |= pr
->log_sel
? BIT(9) : 0;
1140 r
[17] |= pr
->rmk_sel
? BIT(8) : 0;
1141 r
[17] |= pr
->meter_sel
? BIT(7) : 0;
1142 r
[17] |= pr
->tagst_sel
? BIT(6) : 0;
1143 r
[17] |= pr
->mir_sel
? BIT(5) : 0;
1144 r
[17] |= pr
->nopri_sel
? BIT(4) : 0;
1145 r
[17] |= pr
->cpupri_sel
? BIT(3) : 0;
1146 r
[17] |= pr
->otpid_sel
? BIT(2) : 0;
1147 r
[17] |= pr
->itpid_sel
? BIT(1) : 0;
1148 r
[17] |= pr
->shaper_sel
? BIT(0) : 0;
1151 static int rtl838x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1153 u16
*aif
= (u16
*)&r
[17];
1155 int fields_used
= 0;
1159 pr_debug("%s, at %08x\n", __func__
, (u32
)aif
);
1160 /* Multiple actions can be linked to a match of a PIE rule,
1161 * they have different precedence depending on their type and this precedence
1162 * defines which Action Information Field (0-4) in the IACL table stores
1163 * the additional data of the action (like e.g. the port number a packet is
1165 // TODO: count bits in selectors to limit to a maximum number of actions
1166 if (pr
->fwd_sel
) { // Forwarding action
1167 data
= pr
->fwd_act
<< 13;
1168 data
|= pr
->fwd_data
;
1169 data
|= pr
->bypass_all
? BIT(12) : 0;
1170 data
|= pr
->bypass_ibc_sc
? BIT(11) : 0;
1171 data
|= pr
->bypass_igr_stp
? BIT(10) : 0;
1176 if (pr
->ovid_sel
) { // Outer VID action
1177 data
= (pr
->ovid_act
& 0x3) << 12;
1178 data
|= pr
->ovid_data
;
1183 if (pr
->ivid_sel
) { // Inner VID action
1184 data
= (pr
->ivid_act
& 0x3) << 12;
1185 data
|= pr
->ivid_data
;
1190 if (pr
->flt_sel
) { // Filter action
1191 *aif
-- = pr
->flt_data
;
1195 if (pr
->log_sel
) { // Log action
1196 if (fields_used
>= 4)
1198 *aif
-- = pr
->log_data
;
1202 if (pr
->rmk_sel
) { // Remark action
1203 if (fields_used
>= 4)
1205 *aif
-- = pr
->rmk_data
;
1209 if (pr
->meter_sel
) { // Meter action
1210 if (fields_used
>= 4)
1212 *aif
-- = pr
->meter_data
;
1216 if (pr
->tagst_sel
) { // Egress Tag Status action
1217 if (fields_used
>= 4)
1219 *aif
-- = pr
->tagst_data
;
1223 if (pr
->mir_sel
) { // Mirror action
1224 if (fields_used
>= 4)
1226 *aif
-- = pr
->mir_data
;
1230 if (pr
->nopri_sel
) { // Normal Priority action
1231 if (fields_used
>= 4)
1233 *aif
-- = pr
->nopri_data
;
1237 if (pr
->cpupri_sel
) { // CPU Priority action
1238 if (fields_used
>= 4)
1240 *aif
-- = pr
->nopri_data
;
1244 if (pr
->otpid_sel
) { // OTPID action
1245 if (fields_used
>= 4)
1247 *aif
-- = pr
->otpid_data
;
1251 if (pr
->itpid_sel
) { // ITPID action
1252 if (fields_used
>= 4)
1254 *aif
-- = pr
->itpid_data
;
1258 if (pr
->shaper_sel
) { // Traffic shaper action
1259 if (fields_used
>= 4)
1261 *aif
-- = pr
->shaper_data
;
1268 static void rtl838x_read_pie_action(u32 r
[], struct pie_rule
*pr
)
1270 u16
*aif
= (u16
*)&r
[17];
1274 pr_debug("%s, at %08x\n", __func__
, (u32
)aif
);
1276 pr_debug("%s: Action Drop: %d", __func__
, pr
->drop
);
1278 if (pr
->fwd_sel
){ // Forwarding action
1279 pr
->fwd_act
= *aif
>> 13;
1280 pr
->fwd_data
= *aif
--;
1281 pr
->bypass_all
= pr
->fwd_data
& BIT(12);
1282 pr
->bypass_ibc_sc
= pr
->fwd_data
& BIT(11);
1283 pr
->bypass_igr_stp
= pr
->fwd_data
& BIT(10);
1284 if (pr
->bypass_all
|| pr
->bypass_ibc_sc
|| pr
->bypass_igr_stp
)
1285 pr
->bypass_sel
= true;
1287 if (pr
->ovid_sel
) // Outer VID action
1288 pr
->ovid_data
= *aif
--;
1289 if (pr
->ivid_sel
) // Inner VID action
1290 pr
->ivid_data
= *aif
--;
1291 if (pr
->flt_sel
) // Filter action
1292 pr
->flt_data
= *aif
--;
1293 if (pr
->log_sel
) // Log action
1294 pr
->log_data
= *aif
--;
1295 if (pr
->rmk_sel
) // Remark action
1296 pr
->rmk_data
= *aif
--;
1297 if (pr
->meter_sel
) // Meter action
1298 pr
->meter_data
= *aif
--;
1299 if (pr
->tagst_sel
) // Egress Tag Status action
1300 pr
->tagst_data
= *aif
--;
1301 if (pr
->mir_sel
) // Mirror action
1302 pr
->mir_data
= *aif
--;
1303 if (pr
->nopri_sel
) // Normal Priority action
1304 pr
->nopri_data
= *aif
--;
1305 if (pr
->cpupri_sel
) // CPU Priority action
1306 pr
->nopri_data
= *aif
--;
1307 if (pr
->otpid_sel
) // OTPID action
1308 pr
->otpid_data
= *aif
--;
1309 if (pr
->itpid_sel
) // ITPID action
1310 pr
->itpid_data
= *aif
--;
1311 if (pr
->shaper_sel
) // Traffic shaper action
1312 pr
->shaper_data
= *aif
--;
1315 static void rtl838x_pie_rule_dump_raw(u32 r
[])
1317 pr_info("Raw IACL table entry:\n");
1318 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1319 pr_info("Fixed : %08x\n", r
[6]);
1320 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r
[7], r
[8], r
[9], r
[10], r
[11], r
[12]);
1321 pr_info("Fixed M: %08x\n", r
[13]);
1322 pr_info("AIF : %08x %08x %08x\n", r
[14], r
[15], r
[16]);
1323 pr_info("Sel : %08x\n", r
[17]);
1326 static void rtl838x_pie_rule_dump(struct pie_rule
*pr
)
1328 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1329 pr
->drop
, pr
->fwd_sel
, pr
->ovid_sel
, pr
->ivid_sel
, pr
->flt_sel
, pr
->log_sel
, pr
->rmk_sel
, pr
->log_sel
, pr
->tagst_sel
, pr
->mir_sel
, pr
->nopri_sel
,
1330 pr
->cpupri_sel
, pr
->otpid_sel
, pr
->itpid_sel
, pr
->shaper_sel
);
1332 pr_info("FWD: %08x\n", pr
->fwd_data
);
1333 pr_info("TID: %x, %x\n", pr
->tid
, pr
->tid_m
);
1336 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1338 // Read IACL table (1) via register 0
1339 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 1);
1342 int block
= idx
/ PIE_BLOCK_SIZE
;
1343 u32 t_select
= sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
));
1345 memset(pr
, 0, sizeof(*pr
));
1346 rtl_table_read(q
, idx
);
1347 for (i
= 0; i
< 18; i
++)
1348 r
[i
] = sw_r32(rtl_table_data(q
, i
));
1350 rtl_table_release(q
);
1352 rtl838x_read_pie_fixed_fields(r
, pr
);
1356 pr_info("%s: template_selectors %08x, tid: %d\n", __func__
, t_select
, pr
->tid
);
1357 rtl838x_pie_rule_dump_raw(r
);
1359 rtl838x_read_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1361 rtl838x_read_pie_action(r
, pr
);
1366 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1368 // Access IACL table (1) via register 0
1369 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 1);
1372 int block
= idx
/ PIE_BLOCK_SIZE
;
1373 u32 t_select
= sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
));
1375 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1377 for (i
= 0; i
< 18; i
++)
1383 rtl838x_write_pie_fixed_fields(r
, pr
);
1385 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 3)) & 0x7);
1386 rtl838x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1388 if (rtl838x_write_pie_action(r
, pr
)) {
1389 pr_err("Rule actions too complex\n");
1393 // rtl838x_pie_rule_dump_raw(r);
1395 for (i
= 0; i
< 18; i
++)
1396 sw_w32(r
[i
], rtl_table_data(q
, i
));
1399 rtl_table_write(q
, idx
);
1400 rtl_table_release(q
);
1405 static bool rtl838x_pie_templ_has(int t
, enum template_field_id field_type
)
1408 enum template_field_id ft
;
1410 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1411 ft
= fixed_templates
[t
][i
];
1412 if (field_type
== ft
)
1419 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1420 struct pie_rule
*pr
, int t
, int block
)
1424 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1427 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1431 if ((pr
->sip6_m
.s6_addr32
[0] || pr
->sip6_m
.s6_addr32
[1]
1432 || pr
->sip6_m
.s6_addr32
[2] || pr
->sip6_m
.s6_addr32
[3])
1433 && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1435 if ((pr
->dip6_m
.s6_addr32
[0] || pr
->dip6_m
.s6_addr32
[1]
1436 || pr
->dip6_m
.s6_addr32
[2] || pr
->dip6_m
.s6_addr32
[3])
1437 && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1441 if (ether_addr_to_u64(pr
->smac
) && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1444 if (ether_addr_to_u64(pr
->dmac
) && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1449 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1451 if (i
>= PIE_BLOCK_SIZE
)
1454 return i
+ PIE_BLOCK_SIZE
* block
;
1457 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1459 int idx
, block
, j
, t
;
1461 pr_debug("In %s\n", __func__
);
1463 mutex_lock(&priv
->pie_mutex
);
1465 for (block
= 0; block
< priv
->n_pie_blocks
; block
++) {
1466 for (j
= 0; j
< 3; j
++) {
1467 t
= (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
)) >> (j
* 3)) & 0x7;
1468 pr_debug("Testing block %d, template %d, template id %d\n", block
, j
, t
);
1469 idx
= rtl838x_pie_verify_template(priv
, pr
, t
, block
);
1477 if (block
>= priv
->n_pie_blocks
) {
1478 mutex_unlock(&priv
->pie_mutex
);
1482 pr_debug("Using block: %d, index %d, template-id %d\n", block
, idx
, j
);
1483 set_bit(idx
, priv
->pie_use_bm
);
1486 pr
->tid
= j
; // Mapped to template number
1490 rtl838x_pie_lookup_enable(priv
, idx
);
1491 rtl838x_pie_rule_write(priv
, idx
, pr
);
1493 mutex_unlock(&priv
->pie_mutex
);
1497 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1501 rtl838x_pie_rule_del(priv
, idx
, idx
);
1502 clear_bit(idx
, priv
->pie_use_bm
);
1506 * Initializes the Packet Inspection Engine:
1507 * powers it up, enables default matching templates for all blocks
1508 * and clears all rules possibly installed by u-boot
1510 static void rtl838x_pie_init(struct rtl838x_switch_priv
*priv
)
1513 u32 template_selectors
;
1515 mutex_init(&priv
->pie_mutex
);
1517 // Enable ACL lookup on all ports, including CPU_PORT
1518 for (i
= 0; i
<= priv
->cpu_port
; i
++)
1519 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i
));
1521 // Power on all PIE blocks
1522 for (i
= 0; i
< priv
->n_pie_blocks
; i
++)
1523 sw_w32_mask(0, BIT(i
), RTL838X_ACL_BLK_PWR_CTRL
);
1525 // Include IPG in metering
1526 sw_w32(1, RTL838X_METER_GLB_CTRL
);
1528 // Delete all present rules
1529 rtl838x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* PIE_BLOCK_SIZE
- 1);
1531 // Routing bypasses source port filter: disable write-protection, first
1532 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL
);
1533 sw_w32_mask(0, 1, RTL838X_DMY_REG27
);
1534 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL
);
1536 // Enable predefined templates 0, 1 and 2 for even blocks
1537 template_selectors
= 0 | (1 << 3) | (2 << 6);
1538 for (i
= 0; i
< 6; i
+= 2)
1539 sw_w32(template_selectors
, RTL838X_ACL_BLK_TMPLTE_CTRL(i
));
1541 // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
1542 template_selectors
= 0 | (3 << 3) | (4 << 6);
1543 for (i
= 1; i
< priv
->n_pie_blocks
; i
+= 2)
1544 sw_w32(template_selectors
, RTL838X_ACL_BLK_TMPLTE_CTRL(i
));
1546 // Group each pair of physical blocks together to a logical block
1547 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL
);
1550 static u32
rtl838x_packet_cntr_read(int counter
)
1554 // Read LOG table (3) via register RTL8380_TBL_0
1555 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 3);
1557 pr_debug("In %s, id %d\n", __func__
, counter
);
1558 rtl_table_read(r
, counter
/ 2);
1560 pr_debug("Registers: %08x %08x\n",
1561 sw_r32(rtl_table_data(r
, 0)), sw_r32(rtl_table_data(r
, 1)));
1562 // The table has a size of 2 registers
1564 v
= sw_r32(rtl_table_data(r
, 0));
1566 v
= sw_r32(rtl_table_data(r
, 1));
1568 rtl_table_release(r
);
1573 static void rtl838x_packet_cntr_clear(int counter
)
1575 // Access LOG table (3) via register RTL8380_TBL_0
1576 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 3);
1578 pr_debug("In %s, id %d\n", __func__
, counter
);
1579 // The table has a size of 2 registers
1581 sw_w32(0, rtl_table_data(r
, 0));
1583 sw_w32(0, rtl_table_data(r
, 1));
1585 rtl_table_write(r
, counter
/ 2);
1587 rtl_table_release(r
);
1590 static void rtl838x_route_read(int idx
, struct rtl83xx_route
*rt
)
1592 // Read ROUTING table (2) via register RTL8380_TBL_1
1593 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 2);
1595 pr_debug("In %s, id %d\n", __func__
, idx
);
1596 rtl_table_read(r
, idx
);
1598 // The table has a size of 2 registers
1599 rt
->nh
.gw
= sw_r32(rtl_table_data(r
, 0));
1601 rt
->nh
.gw
|= sw_r32(rtl_table_data(r
, 1));
1603 rtl_table_release(r
);
1606 static void rtl838x_route_write(int idx
, struct rtl83xx_route
*rt
)
1608 // Access ROUTING table (2) via register RTL8380_TBL_1
1609 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 2);
1611 pr_debug("In %s, id %d, gw: %016llx\n", __func__
, idx
, rt
->nh
.gw
);
1612 sw_w32(rt
->nh
.gw
>> 32, rtl_table_data(r
, 0));
1613 sw_w32(rt
->nh
.gw
, rtl_table_data(r
, 1));
1614 rtl_table_write(r
, idx
);
1616 rtl_table_release(r
);
1619 static int rtl838x_l3_setup(struct rtl838x_switch_priv
*priv
)
1621 // Nothing to be done
1625 void rtl838x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
1627 if (type
== PBVLAN_TYPE_INNER
)
1628 sw_w32_mask(0x3, mode
, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1630 sw_w32_mask(0x3 << 14, mode
<< 14, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1633 void rtl838x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
1635 if (type
== PBVLAN_TYPE_INNER
)
1636 sw_w32_mask(0xfff << 2, pvid
<< 2, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1638 sw_w32_mask(0xfff << 16, pvid
<< 16, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1641 static int rtl838x_set_ageing_time(unsigned long msec
)
1643 int t
= sw_r32(RTL838X_L2_CTRL_1
);
1646 t
= t
* 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1647 pr_debug("L2 AGING time: %d sec\n", t
);
1649 t
= (msec
* 625 + 127000) / 128000;
1650 t
= t
> 0x7FFFFF ? 0x7FFFFF : t
;
1651 sw_w32_mask(0x7FFFFF, t
, RTL838X_L2_CTRL_1
);
1652 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT
));
1657 static void rtl838x_set_igr_filter(int port
, enum igr_filter state
)
1659 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
1660 RTL838X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
1663 static void rtl838x_set_egr_filter(int port
, enum egr_filter state
)
1665 sw_w32_mask(0x1 << (port
% 0x1d), state
<< (port
% 0x1d),
1666 RTL838X_VLAN_PORT_EGR_FLTR
+ (((port
/ 29) << 2)));
1669 void rtl838x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
1671 algoidx
&= 1; // RTL838X only supports 2 concurrent algorithms
1672 sw_w32_mask(1 << (group
% 8), algoidx
<< (group
% 8),
1673 RTL838X_TRK_HASH_IDX_CTRL
+ ((group
>> 3) << 2));
1674 sw_w32(algomsk
, RTL838X_TRK_HASH_CTRL
+ (algoidx
<< 2));
1677 void rtl838x_set_receive_management_action(int port
, rma_ctrl_t type
, action_type_t action
)
1681 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1682 RTL838X_RMA_BPDU_CTRL
+ ((port
>> 4) << 2));
1685 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1686 RTL838X_RMA_PTP_CTRL
+ ((port
>> 4) << 2));
1689 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1690 RTL838X_RMA_LLTP_CTRL
+ ((port
>> 4) << 2));
1697 const struct rtl838x_reg rtl838x_reg
= {
1698 .mask_port_reg_be
= rtl838x_mask_port_reg
,
1699 .set_port_reg_be
= rtl838x_set_port_reg
,
1700 .get_port_reg_be
= rtl838x_get_port_reg
,
1701 .mask_port_reg_le
= rtl838x_mask_port_reg
,
1702 .set_port_reg_le
= rtl838x_set_port_reg
,
1703 .get_port_reg_le
= rtl838x_get_port_reg
,
1704 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
1705 .stat_rst
= RTL838X_STAT_RST
,
1706 .stat_port_std_mib
= RTL838X_STAT_PORT_STD_MIB
,
1707 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
1708 .traffic_enable
= rtl838x_traffic_enable
,
1709 .traffic_disable
= rtl838x_traffic_disable
,
1710 .traffic_get
= rtl838x_traffic_get
,
1711 .traffic_set
= rtl838x_traffic_set
,
1712 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
1713 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
1714 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
1715 .set_ageing_time
= rtl838x_set_ageing_time
,
1716 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
1717 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
1718 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
1719 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
1720 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
1721 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
1722 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
1723 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
1724 .imr_glb
= RTL838X_IMR_GLB
,
1725 .vlan_tables_read
= rtl838x_vlan_tables_read
,
1726 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
1727 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
1728 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
1729 .vlan_profile_dump
= rtl838x_vlan_profile_dump
,
1730 .vlan_profile_setup
= rtl838x_vlan_profile_setup
,
1731 .vlan_fwd_on_inner
= rtl838x_vlan_fwd_on_inner
,
1732 .set_vlan_igr_filter
= rtl838x_set_igr_filter
,
1733 .set_vlan_egr_filter
= rtl838x_set_egr_filter
,
1734 .enable_learning
= rtl838x_enable_learning
,
1735 .enable_flood
= rtl838x_enable_flood
,
1736 .enable_mcast_flood
= rtl838x_enable_mcast_flood
,
1737 .enable_bcast_flood
= rtl838x_enable_bcast_flood
,
1738 .stp_get
= rtl838x_stp_get
,
1739 .stp_set
= rtl838x_stp_set
,
1740 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
1741 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
1742 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
1743 .mir_ctrl
= RTL838X_MIR_CTRL
,
1744 .mir_dpm
= RTL838X_MIR_DPM_CTRL
,
1745 .mir_spm
= RTL838X_MIR_SPM_CTRL
,
1746 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
1747 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
1748 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
1749 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
1750 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
1751 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
1752 .write_l2_entry_using_hash
= rtl838x_write_l2_entry_using_hash
,
1753 .read_cam
= rtl838x_read_cam
,
1754 .write_cam
= rtl838x_write_cam
,
1755 .vlan_port_tag_sts_ctrl
= RTL838X_VLAN_PORT_TAG_STS_CTRL
,
1756 .vlan_port_pvidmode_set
= rtl838x_vlan_port_pvidmode_set
,
1757 .vlan_port_pvid_set
= rtl838x_vlan_port_pvid_set
,
1758 .trk_mbr_ctr
= rtl838x_trk_mbr_ctr
,
1759 .rma_bpdu_fld_pmask
= RTL838X_RMA_BPDU_FLD_PMSK
,
1760 .spcl_trap_eapol_ctrl
= RTL838X_SPCL_TRAP_EAPOL_CTRL
,
1761 .init_eee
= rtl838x_init_eee
,
1762 .port_eee_set
= rtl838x_port_eee_set
,
1763 .eee_port_ability
= rtl838x_eee_port_ability
,
1764 .l2_hash_seed
= rtl838x_l2_hash_seed
,
1765 .l2_hash_key
= rtl838x_l2_hash_key
,
1766 .read_mcast_pmask
= rtl838x_read_mcast_pmask
,
1767 .write_mcast_pmask
= rtl838x_write_mcast_pmask
,
1768 .pie_init
= rtl838x_pie_init
,
1769 .pie_rule_read
= rtl838x_pie_rule_read
,
1770 .pie_rule_write
= rtl838x_pie_rule_write
,
1771 .pie_rule_add
= rtl838x_pie_rule_add
,
1772 .pie_rule_rm
= rtl838x_pie_rule_rm
,
1773 .l2_learning_setup
= rtl838x_l2_learning_setup
,
1774 .packet_cntr_read
= rtl838x_packet_cntr_read
,
1775 .packet_cntr_clear
= rtl838x_packet_cntr_clear
,
1776 .route_read
= rtl838x_route_read
,
1777 .route_write
= rtl838x_route_write
,
1778 .l3_setup
= rtl838x_l3_setup
,
1779 .set_distribution_algorithm
= rtl838x_set_distribution_algorithm
,
1780 .set_receive_management_action
= rtl838x_set_receive_management_action
,
1783 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
1785 struct dsa_switch
*ds
= dev_id
;
1786 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
1787 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
1792 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
1793 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
1795 for (i
= 0; i
< 28; i
++) {
1796 if (ports
& BIT(i
)) {
1797 link
= sw_r32(RTL838X_MAC_LINK_STS
);
1799 dsa_port_phylink_mac_change(ds
, i
, true);
1801 dsa_port_phylink_mac_change(ds
, i
, false);
1807 int rtl838x_smi_wait_op(int timeout
)
1812 ret
= readx_poll_timeout(sw_r32
, RTL838X_SMI_ACCESS_PHY_CTRL_1
,
1813 val
, !(val
& 0x1), 20, timeout
);
1815 pr_err("%s: timeout\n", __func__
);
1821 * Reads a register in a page from the PHY
1823 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
1833 if (page
> 4095 || reg
> 31)
1836 mutex_lock(&smi_lock
);
1838 if (rtl838x_smi_wait_op(100000))
1841 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1843 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
1844 v
= reg
<< 20 | page
<< 3;
1845 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1846 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1848 if (rtl838x_smi_wait_op(100000))
1851 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1853 mutex_unlock(&smi_lock
);
1857 mutex_unlock(&smi_lock
);
1862 * Write to a register in a page of the PHY
1864 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
1870 if (port
> 31 || page
> 4095 || reg
> 31)
1873 mutex_lock(&smi_lock
);
1874 if (rtl838x_smi_wait_op(100000))
1877 sw_w32(BIT(port
), RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1880 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1882 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
1883 v
= reg
<< 20 | page
<< 3 | 0x4;
1884 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1885 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1887 if (rtl838x_smi_wait_op(100000))
1890 mutex_unlock(&smi_lock
);
1894 mutex_unlock(&smi_lock
);
1899 * Read an mmd register of a PHY
1901 int rtl838x_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
1905 mutex_lock(&smi_lock
);
1907 if (rtl838x_smi_wait_op(100000))
1910 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1913 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1915 v
= addr
<< 16 | reg
;
1916 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1918 /* mmd-access | read | cmd-start */
1919 v
= 1 << 1 | 0 << 2 | 1;
1920 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1922 if (rtl838x_smi_wait_op(100000))
1925 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1927 mutex_unlock(&smi_lock
);
1931 mutex_unlock(&smi_lock
);
1936 * Write to an mmd register of a PHY
1938 int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
1942 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
1944 mutex_lock(&smi_lock
);
1946 if (rtl838x_smi_wait_op(100000))
1949 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1952 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1954 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1955 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1956 /* mmd-access | write | cmd-start */
1957 v
= 1 << 1 | 1 << 2 | 1;
1958 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1960 if (rtl838x_smi_wait_op(100000))
1963 mutex_unlock(&smi_lock
);
1967 mutex_unlock(&smi_lock
);
1971 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
1973 u32 rw_save
, info_save
;
1976 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
1977 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
1979 info_save
= sw_r32(RTL838X_CHIP_INFO
);
1980 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
1982 info
= sw_r32(RTL838X_CHIP_INFO
);
1983 sw_w32(info_save
, RTL838X_CHIP_INFO
);
1984 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
1986 if ((info
& 0xFFFF) == 0x6275) {
1987 if (((info
>> 16) & 0x1F) == 0x1)
1988 priv
->version
= RTL8380_VERSION_A
;
1989 else if (((info
>> 16) & 0x1F) == 0x2)
1990 priv
->version
= RTL8380_VERSION_B
;
1992 priv
->version
= RTL8380_VERSION_B
;
1994 priv
->version
= '-';
1998 void rtl838x_vlan_profile_dump(int profile
)
2002 if (profile
< 0 || profile
> 7)
2005 p
= sw_r32(RTL838X_VLAN_PROFILE(profile
));
2007 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
2008 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
2009 profile
, p
& 1, (p
>> 1) & 0x1ff, (p
>> 10) & 0x1ff, (p
>> 19) & 0x1ff);
2012 void rtl8380_sds_rst(int mac
)
2014 u32 offset
= (mac
== 24) ? 0 : 0x100;
2016 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0
+ offset
);
2017 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28
+ offset
);
2018 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28
+ offset
);
2019 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0
+ offset
);
2020 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0
+ offset
);
2021 pr_debug("SERDES reset: %d\n", mac
);
2024 int rtl8380_sds_power(int mac
, int val
)
2026 u32 mode
= (val
== 1) ? 0x4 : 0x9;
2027 u32 offset
= (mac
== 24) ? 5 : 0;
2029 if ((mac
!= 24) && (mac
!= 26)) {
2030 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
2034 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
2036 rtl8380_sds_rst(mac
);