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[openwrt/staging/hauke.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl838x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/iopoll.h>
5 #include <net/nexthop.h>
6
7 #include "rtl83xx.h"
8
9 extern struct mutex smi_lock;
10
11 // see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
12 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
13 enum template_field_id {
14 TEMPLATE_FIELD_SPMMASK = 0,
15 TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
16 TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-28
17 TEMPLATE_FIELD_RANGE_CHK = 3,
18 TEMPLATE_FIELD_DMAC0 = 4, // Destination MAC [15:0]
19 TEMPLATE_FIELD_DMAC1 = 5, // Destination MAC [31:16]
20 TEMPLATE_FIELD_DMAC2 = 6, // Destination MAC [47:32]
21 TEMPLATE_FIELD_SMAC0 = 7, // Source MAC [15:0]
22 TEMPLATE_FIELD_SMAC1 = 8, // Source MAC [31:16]
23 TEMPLATE_FIELD_SMAC2 = 9, // Source MAC [47:32]
24 TEMPLATE_FIELD_ETHERTYPE = 10, // Ethernet typ
25 TEMPLATE_FIELD_OTAG = 11, // Outer VLAN tag
26 TEMPLATE_FIELD_ITAG = 12, // Inner VLAN tag
27 TEMPLATE_FIELD_SIP0 = 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
28 // source protocol address in header
29 TEMPLATE_FIELD_SIP1 = 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
30 TEMPLATE_FIELD_DIP0 = 15, // IPv4 or IPv6 destination IP[15:0]
31 TEMPLATE_FIELD_DIP1 = 16, // IPv4 or IPv6 destination IP[31:16]
32 TEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and
33 // IPv4 proto/IPv6 next header fields
34 TEMPLATE_FIELD_L34_HEADER = 18, // packet with extra tag and IPv6 with auth, dest,
35 // frag, route, hop-by-hop option header,
36 // IGMP type, TCP flag
37 TEMPLATE_FIELD_L4_SPORT = 19, // TCP/UDP source port
38 TEMPLATE_FIELD_L4_DPORT = 20, // TCP/UDP destination port
39 TEMPLATE_FIELD_ICMP_IGMP = 21,
40 TEMPLATE_FIELD_IP_RANGE = 22,
41 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask
42 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
43 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
44 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
45 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
46 TEMPLATE_FIELD_SIP2 = 28, // IPv6 source IP[47:32]
47 TEMPLATE_FIELD_SIP3 = 29, // IPv6 source IP[63:48]
48 TEMPLATE_FIELD_SIP4 = 30, // IPv6 source IP[79:64]
49 TEMPLATE_FIELD_SIP5 = 31, // IPv6 source IP[95:80]
50 TEMPLATE_FIELD_SIP6 = 32, // IPv6 source IP[111:96]
51 TEMPLATE_FIELD_SIP7 = 33, // IPv6 source IP[127:112]
52 TEMPLATE_FIELD_DIP2 = 34, // IPv6 destination IP[47:32]
53 TEMPLATE_FIELD_DIP3 = 35, // IPv6 destination IP[63:48]
54 TEMPLATE_FIELD_DIP4 = 36, // IPv6 destination IP[79:64]
55 TEMPLATE_FIELD_DIP5 = 37, // IPv6 destination IP[95:80]
56 TEMPLATE_FIELD_DIP6 = 38, // IPv6 destination IP[111:96]
57 TEMPLATE_FIELD_DIP7 = 39, // IPv6 destination IP[127:112]
58 TEMPLATE_FIELD_FWD_VID = 40, // Forwarding VLAN-ID
59 TEMPLATE_FIELD_FLOW_LABEL = 41,
60 };
61
62 /*
63 * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
64 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
65 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
66 * templates. Additionally, 3 user-definable templates can be set up via the definitions
67 * in RTL838X_ACL_TMPLTE_CTRL control registers.
68 * TODO: See all src/app/diag_v2/src/diag_pie.c
69 */
70 #define N_FIXED_TEMPLATES 5
71 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
72 {
73 {
74 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
75 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
76 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
77 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
78 }, {
79 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
80 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
81 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
82 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
83 }, {
84 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
85 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
86 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
87 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
88 }, {
89 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
90 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
91 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
92 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
93 }, {
94 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
95 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
96 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,
97 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
98 },
99 };
100
101 void rtl838x_print_matrix(void)
102 {
103 unsigned volatile int *ptr8;
104 int i;
105
106 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
107 for (i = 0; i < 28; i += 8)
108 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
109 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
110 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
111 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
112 }
113
114 static inline int rtl838x_port_iso_ctrl(int p)
115 {
116 return RTL838X_PORT_ISO_CTRL(p);
117 }
118
119 static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
120 {
121 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
122 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
123 }
124
125 static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
126 {
127 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
128 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
129 }
130
131 static inline int rtl838x_tbl_access_data_0(int i)
132 {
133 return RTL838X_TBL_ACCESS_DATA_0(i);
134 }
135
136 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
137 {
138 u32 v;
139 // Read VLAN table (0) via register 0
140 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
141
142 rtl_table_read(r, vlan);
143 info->tagged_ports = sw_r32(rtl_table_data(r, 0));
144 v = sw_r32(rtl_table_data(r, 1));
145 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
146 rtl_table_release(r);
147
148 info->profile_id = v & 0x7;
149 info->hash_mc_fid = !!(v & 0x8);
150 info->hash_uc_fid = !!(v & 0x10);
151 info->fid = (v >> 5) & 0x3f;
152
153 // Read UNTAG table (0) via table register 1
154 r = rtl_table_get(RTL8380_TBL_1, 0);
155 rtl_table_read(r, vlan);
156 info->untagged_ports = sw_r32(rtl_table_data(r, 0));
157 rtl_table_release(r);
158 }
159
160 static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
161 {
162 u32 v;
163 // Access VLAN table (0) via register 0
164 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
165
166 sw_w32(info->tagged_ports, rtl_table_data(r, 0));
167
168 v = info->profile_id;
169 v |= info->hash_mc_fid ? 0x8 : 0;
170 v |= info->hash_uc_fid ? 0x10 : 0;
171 v |= ((u32)info->fid) << 5;
172 sw_w32(v, rtl_table_data(r, 1));
173
174 rtl_table_write(r, vlan);
175 rtl_table_release(r);
176 }
177
178 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
179 {
180 // Access UNTAG table (0) via register 1
181 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
182
183 sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
184 rtl_table_write(r, vlan);
185 rtl_table_release(r);
186 }
187
188 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
189 */
190 static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
191 {
192 if (is_set)
193 sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
194 else
195 sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
196 }
197
198 static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
199 {
200 return mac << 12 | vid;
201 }
202
203 /*
204 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
205 * and returns a key into the L2 hash table
206 */
207 static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
208 {
209 u32 h1, h2, h3, h;
210
211 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
212 h1 = (seed >> 11) & 0x7ff;
213 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
214
215 h2 = (seed >> 33) & 0x7ff;
216 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
217
218 h3 = (seed >> 44) & 0x7ff;
219 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
220
221 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
222 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
223 } else {
224 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
225 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
226 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
227 }
228
229 return h;
230 }
231
232 static inline int rtl838x_mac_force_mode_ctrl(int p)
233 {
234 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
235 }
236
237 static inline int rtl838x_mac_port_ctrl(int p)
238 {
239 return RTL838X_MAC_PORT_CTRL(p);
240 }
241
242 static inline int rtl838x_l2_port_new_salrn(int p)
243 {
244 return RTL838X_L2_PORT_NEW_SALRN(p);
245 }
246
247 static inline int rtl838x_l2_port_new_sa_fwd(int p)
248 {
249 return RTL838X_L2_PORT_NEW_SA_FWD(p);
250 }
251
252 static inline int rtl838x_mac_link_spd_sts(int p)
253 {
254 return RTL838X_MAC_LINK_SPD_STS(p);
255 }
256
257 inline static int rtl838x_trk_mbr_ctr(int group)
258 {
259 return RTL838X_TRK_MBR_CTR + (group << 2);
260 }
261
262 /*
263 * Fills an L2 entry structure from the SoC registers
264 */
265 static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
266 {
267 /* Table contains different entry types, we need to identify the right one:
268 * Check for MC entries, first
269 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
270 * identify valid entries
271 */
272 e->is_ip_mc = !!(r[0] & BIT(22));
273 e->is_ipv6_mc = !!(r[0] & BIT(21));
274 e->type = L2_INVALID;
275
276 if (!e->is_ip_mc && !e->is_ipv6_mc) {
277 e->mac[0] = (r[1] >> 20);
278 e->mac[1] = (r[1] >> 12);
279 e->mac[2] = (r[1] >> 4);
280 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
281 e->mac[4] = (r[2] >> 20);
282 e->mac[5] = (r[2] >> 12);
283
284 e->rvid = r[2] & 0xfff;
285 e->vid = r[0] & 0xfff;
286
287 /* Is it a unicast entry? check multicast bit */
288 if (!(e->mac[0] & 1)) {
289 e->is_static = !!((r[0] >> 19) & 1);
290 e->port = (r[0] >> 12) & 0x1f;
291 e->block_da = !!(r[1] & BIT(30));
292 e->block_sa = !!(r[1] & BIT(31));
293 e->suspended = !!(r[1] & BIT(29));
294 e->next_hop = !!(r[1] & BIT(28));
295 if (e->next_hop) {
296 pr_debug("Found next hop entry, need to read extra data\n");
297 e->nh_vlan_target = !!(r[0] & BIT(9));
298 e->nh_route_id = r[0] & 0x1ff;
299 e->vid = e->rvid;
300 }
301 e->age = (r[0] >> 17) & 0x3;
302 e->valid = true;
303
304 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
305 * next-hop or static entry bit set */
306 if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
307 e->valid = false;
308 else
309 e->type = L2_UNICAST;
310 } else { // L2 multicast
311 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
312 e->valid = true;
313 e->type = L2_MULTICAST;
314 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
315 }
316 } else { // IPv4 and IPv6 multicast
317 e->valid = true;
318 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
319 e->mc_gip = (r[1] << 20) | (r[2] >> 12);
320 e->rvid = r[2] & 0xfff;
321 }
322 if (e->is_ip_mc)
323 e->type = IP4_MULTICAST;
324 if (e->is_ipv6_mc)
325 e->type = IP6_MULTICAST;
326 }
327
328 /*
329 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
330 */
331 static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
332 {
333 u64 mac = ether_addr_to_u64(e->mac);
334
335 if (!e->valid) {
336 r[0] = r[1] = r[2] = 0;
337 return;
338 }
339
340 r[0] = e->is_ip_mc ? BIT(22) : 0;
341 r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
342
343 if (!e->is_ip_mc && !e->is_ipv6_mc) {
344 r[1] = mac >> 20;
345 r[2] = (mac & 0xfffff) << 12;
346
347 /* Is it a unicast entry? check multicast bit */
348 if (!(e->mac[0] & 1)) {
349 r[0] |= e->is_static ? BIT(19) : 0;
350 r[0] |= (e->port & 0x3f) << 12;
351 r[0] |= e->vid;
352 r[1] |= e->block_da ? BIT(30) : 0;
353 r[1] |= e->block_sa ? BIT(31) : 0;
354 r[1] |= e->suspended ? BIT(29) : 0;
355 r[2] |= e->rvid & 0xfff;
356 if (e->next_hop) {
357 r[1] |= BIT(28);
358 r[0] |= e->nh_vlan_target ? BIT(9) : 0;
359 r[0] |= e->nh_route_id & 0x1ff;
360 }
361 r[0] |= (e->age & 0x3) << 17;
362 } else { // L2 Multicast
363 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
364 r[2] |= e->rvid & 0xfff;
365 r[0] |= e->vid & 0xfff;
366 pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
367 }
368 } else { // IPv4 and IPv6 multicast
369 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
370 r[1] = e->mc_gip >> 20;
371 r[2] = e->mc_gip << 12;
372 r[2] |= e->rvid;
373 }
374 }
375
376 /*
377 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
378 * hash is the id of the bucket and pos is the position of the entry in that bucket
379 * The data read from the SoC is filled into rtl838x_l2_entry
380 */
381 static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
382 {
383 u64 entry;
384 u32 r[3];
385 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0
386 u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
387 int i;
388
389 rtl_table_read(q, idx);
390 for (i= 0; i < 3; i++)
391 r[i] = sw_r32(rtl_table_data(q, i));
392
393 rtl_table_release(q);
394
395 rtl838x_fill_l2_entry(r, e);
396 if (!e->valid)
397 return 0;
398
399 entry = (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed
400 return entry;
401 }
402
403 static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
404 {
405 u32 r[3];
406 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
407 int i;
408
409 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
410
411 rtl838x_fill_l2_row(r, e);
412
413 for (i= 0; i < 3; i++)
414 sw_w32(r[i], rtl_table_data(q, i));
415
416 rtl_table_write(q, idx);
417 rtl_table_release(q);
418 }
419
420 static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
421 {
422 u64 entry;
423 u32 r[3];
424 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
425 int i;
426
427 rtl_table_read(q, idx);
428 for (i= 0; i < 3; i++)
429 r[i] = sw_r32(rtl_table_data(q, i));
430
431 rtl_table_release(q);
432
433 rtl838x_fill_l2_entry(r, e);
434 if (!e->valid)
435 return 0;
436
437 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
438
439 // Return MAC with concatenated VID ac concatenated ID
440 entry = (((u64) r[1]) << 32) | r[2];
441 return entry;
442 }
443
444 static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
445 {
446 u32 r[3];
447 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
448 int i;
449
450 rtl838x_fill_l2_row(r, e);
451
452 for (i= 0; i < 3; i++)
453 sw_w32(r[i], rtl_table_data(q, i));
454
455 rtl_table_write(q, idx);
456 rtl_table_release(q);
457 }
458
459 static u64 rtl838x_read_mcast_pmask(int idx)
460 {
461 u32 portmask;
462 // Read MC_PMSK (2) via register RTL8380_TBL_L2
463 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
464
465 rtl_table_read(q, idx);
466 portmask = sw_r32(rtl_table_data(q, 0));
467 rtl_table_release(q);
468
469 return portmask;
470 }
471
472 static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
473 {
474 // Access MC_PMSK (2) via register RTL8380_TBL_L2
475 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
476
477 sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
478 rtl_table_write(q, idx);
479 rtl_table_release(q);
480 }
481
482 static void rtl838x_vlan_profile_setup(int profile)
483 {
484 u32 pmask_id = UNKNOWN_MC_PMASK;
485 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
486 u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
487
488 sw_w32(p, RTL838X_VLAN_PROFILE(profile));
489
490 /* RTL8380 and RTL8390 use an index into the portmask table to set the
491 * unknown multicast portmask, setup a default at a safe location
492 * On RTL93XX, the portmask is directly set in the profile,
493 * see e.g. rtl9300_vlan_profile_setup
494 */
495 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
496 }
497
498 static void rtl838x_l2_learning_setup(void)
499 {
500 /* Set portmask for broadcast traffic and unknown unicast address flooding
501 * to the reserved entry in the portmask table used also for
502 * multicast flooding */
503 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
504
505 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
506 * and per vlan (bit 2) */
507 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
508
509 // Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
510 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
511
512 // Do not trap ARP packets to CPU_PORT
513 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
514 }
515
516 static void rtl838x_enable_learning(int port, bool enable)
517 {
518 // Limit learning to maximum: 16k entries
519
520 sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0,
521 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
522 }
523
524 static void rtl838x_enable_flood(int port, bool enable)
525 {
526 /*
527 * 0: Forward
528 * 1: Disable
529 * 2: to CPU
530 * 3: Copy to CPU
531 */
532 sw_w32_mask(0x3, enable ? 0 : 1,
533 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
534 }
535
536 static void rtl838x_enable_mcast_flood(int port, bool enable)
537 {
538
539 }
540
541 static void rtl838x_enable_bcast_flood(int port, bool enable)
542 {
543
544 }
545
546 static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
547 {
548 int i;
549 u32 cmd = 1 << 15 /* Execute cmd */
550 | 1 << 14 /* Read */
551 | 2 << 12 /* Table type 0b10 */
552 | (msti & 0xfff);
553 priv->r->exec_tbl0_cmd(cmd);
554
555 for (i = 0; i < 2; i++)
556 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
557 }
558
559 static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
560 {
561 int i;
562 u32 cmd = 1 << 15 /* Execute cmd */
563 | 0 << 14 /* Write */
564 | 2 << 12 /* Table type 0b10 */
565 | (msti & 0xfff);
566
567 for (i = 0; i < 2; i++)
568 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
569 priv->r->exec_tbl0_cmd(cmd);
570 }
571
572 u64 rtl838x_traffic_get(int source)
573 {
574 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
575 }
576
577 void rtl838x_traffic_set(int source, u64 dest_matrix)
578 {
579 rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
580 }
581
582 void rtl838x_traffic_enable(int source, int dest)
583 {
584 rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
585 }
586
587 void rtl838x_traffic_disable(int source, int dest)
588 {
589 rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
590 }
591
592 /*
593 * Enables or disables the EEE/EEEP capability of a port
594 */
595 static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
596 {
597 u32 v;
598
599 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
600 if (port >= 24)
601 return;
602
603 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
604 v = enable ? 0x3 : 0x0;
605
606 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
607 sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
608
609 // Set TX/RX EEE state
610 if (enable) {
611 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
612 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
613 } else {
614 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
615 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
616 }
617 priv->ports[port].eee_enabled = enable;
618 }
619
620
621 /*
622 * Get EEE own capabilities and negotiation result
623 */
624 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
625 struct ethtool_eee *e, int port)
626 {
627 u64 link;
628
629 if (port >= 24)
630 return 0;
631
632 link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
633 if (!(link & BIT(port)))
634 return 0;
635
636 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
637 e->advertised |= ADVERTISED_100baseT_Full;
638
639 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
640 e->advertised |= ADVERTISED_1000baseT_Full;
641
642 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
643 e->lp_advertised = ADVERTISED_100baseT_Full;
644 e->lp_advertised |= ADVERTISED_1000baseT_Full;
645 return 1;
646 }
647
648 return 0;
649 }
650
651 static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
652 {
653 int i;
654
655 pr_info("Setting up EEE, state: %d\n", enable);
656 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
657
658 /* Set timers for EEE */
659 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
660 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
661
662 // Enable EEE MAC support on ports
663 for (i = 0; i < priv->cpu_port; i++) {
664 if (priv->ports[i].phy)
665 rtl838x_port_eee_set(priv, i, enable);
666 }
667 priv->eee_enabled = enable;
668 }
669
670 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
671 {
672 int block = index / PIE_BLOCK_SIZE;
673 u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
674
675 // Make sure rule-lookup is enabled in the block
676 if (!(block_state & BIT(block)))
677 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
678 }
679
680 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
681 {
682 int block_from = index_from / PIE_BLOCK_SIZE;
683 int block_to = index_to / PIE_BLOCK_SIZE;
684 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
685 int block;
686 u32 block_state;
687
688 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
689 mutex_lock(&priv->reg_mutex);
690
691 // Remember currently active blocks
692 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
693
694 // Make sure rule-lookup is disabled in the relevant blocks
695 for (block = block_from; block <= block_to; block++) {
696 if (block_state & BIT(block))
697 sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
698 }
699
700 // Write from-to and execute bit into control register
701 sw_w32(v, RTL838X_ACL_CLR_CTRL);
702
703 // Wait until command has completed
704 do {
705 } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
706
707 // Re-enable rule lookup
708 for (block = block_from; block <= block_to; block++) {
709 if (!(block_state & BIT(block)))
710 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
711 }
712
713 mutex_unlock(&priv->reg_mutex);
714 }
715
716 /*
717 * Reads the intermediate representation of the templated match-fields of the
718 * PIE rule in the pie_rule structure and fills in the raw data fields in the
719 * raw register space r[].
720 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
721 * however the RTL9310 has 2 more registers / fields and the physical field-ids
722 * are specific to every platform.
723 */
724 static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
725 {
726 int i;
727 enum template_field_id field_type;
728 u16 data, data_m;
729
730 for (i = 0; i < N_FIXED_FIELDS; i++) {
731 field_type = t[i];
732 data = data_m = 0;
733
734 switch (field_type) {
735 case TEMPLATE_FIELD_SPM0:
736 data = pr->spm;
737 data_m = pr->spm_m;
738 break;
739 case TEMPLATE_FIELD_SPM1:
740 data = pr->spm >> 16;
741 data_m = pr->spm_m >> 16;
742 break;
743 case TEMPLATE_FIELD_OTAG:
744 data = pr->otag;
745 data_m = pr->otag_m;
746 break;
747 case TEMPLATE_FIELD_SMAC0:
748 data = pr->smac[4];
749 data = (data << 8) | pr->smac[5];
750 data_m = pr->smac_m[4];
751 data_m = (data_m << 8) | pr->smac_m[5];
752 break;
753 case TEMPLATE_FIELD_SMAC1:
754 data = pr->smac[2];
755 data = (data << 8) | pr->smac[3];
756 data_m = pr->smac_m[2];
757 data_m = (data_m << 8) | pr->smac_m[3];
758 break;
759 case TEMPLATE_FIELD_SMAC2:
760 data = pr->smac[0];
761 data = (data << 8) | pr->smac[1];
762 data_m = pr->smac_m[0];
763 data_m = (data_m << 8) | pr->smac_m[1];
764 break;
765 case TEMPLATE_FIELD_DMAC0:
766 data = pr->dmac[4];
767 data = (data << 8) | pr->dmac[5];
768 data_m = pr->dmac_m[4];
769 data_m = (data_m << 8) | pr->dmac_m[5];
770 break;
771 case TEMPLATE_FIELD_DMAC1:
772 data = pr->dmac[2];
773 data = (data << 8) | pr->dmac[3];
774 data_m = pr->dmac_m[2];
775 data_m = (data_m << 8) | pr->dmac_m[3];
776 break;
777 case TEMPLATE_FIELD_DMAC2:
778 data = pr->dmac[0];
779 data = (data << 8) | pr->dmac[1];
780 data_m = pr->dmac_m[0];
781 data_m = (data_m << 8) | pr->dmac_m[1];
782 break;
783 case TEMPLATE_FIELD_ETHERTYPE:
784 data = pr->ethertype;
785 data_m = pr->ethertype_m;
786 break;
787 case TEMPLATE_FIELD_ITAG:
788 data = pr->itag;
789 data_m = pr->itag_m;
790 break;
791 case TEMPLATE_FIELD_RANGE_CHK:
792 data = pr->field_range_check;
793 data_m = pr->field_range_check_m;
794 break;
795 case TEMPLATE_FIELD_SIP0:
796 if (pr->is_ipv6) {
797 data = pr->sip6.s6_addr16[7];
798 data_m = pr->sip6_m.s6_addr16[7];
799 } else {
800 data = pr->sip;
801 data_m = pr->sip_m;
802 }
803 break;
804 case TEMPLATE_FIELD_SIP1:
805 if (pr->is_ipv6) {
806 data = pr->sip6.s6_addr16[6];
807 data_m = pr->sip6_m.s6_addr16[6];
808 } else {
809 data = pr->sip >> 16;
810 data_m = pr->sip_m >> 16;
811 }
812 break;
813
814 case TEMPLATE_FIELD_SIP2:
815 case TEMPLATE_FIELD_SIP3:
816 case TEMPLATE_FIELD_SIP4:
817 case TEMPLATE_FIELD_SIP5:
818 case TEMPLATE_FIELD_SIP6:
819 case TEMPLATE_FIELD_SIP7:
820 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
821 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
822 break;
823
824 case TEMPLATE_FIELD_DIP0:
825 if (pr->is_ipv6) {
826 data = pr->dip6.s6_addr16[7];
827 data_m = pr->dip6_m.s6_addr16[7];
828 } else {
829 data = pr->dip;
830 data_m = pr->dip_m;
831 }
832 break;
833
834 case TEMPLATE_FIELD_DIP1:
835 if (pr->is_ipv6) {
836 data = pr->dip6.s6_addr16[6];
837 data_m = pr->dip6_m.s6_addr16[6];
838 } else {
839 data = pr->dip >> 16;
840 data_m = pr->dip_m >> 16;
841 }
842 break;
843
844 case TEMPLATE_FIELD_DIP2:
845 case TEMPLATE_FIELD_DIP3:
846 case TEMPLATE_FIELD_DIP4:
847 case TEMPLATE_FIELD_DIP5:
848 case TEMPLATE_FIELD_DIP6:
849 case TEMPLATE_FIELD_DIP7:
850 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
851 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
852 break;
853
854 case TEMPLATE_FIELD_IP_TOS_PROTO:
855 data = pr->tos_proto;
856 data_m = pr->tos_proto_m;
857 break;
858 case TEMPLATE_FIELD_L4_SPORT:
859 data = pr->sport;
860 data_m = pr->sport_m;
861 break;
862 case TEMPLATE_FIELD_L4_DPORT:
863 data = pr->dport;
864 data_m = pr->dport_m;
865 break;
866 case TEMPLATE_FIELD_ICMP_IGMP:
867 data = pr->icmp_igmp;
868 data_m = pr->icmp_igmp_m;
869 break;
870 default:
871 pr_info("%s: unknown field %d\n", __func__, field_type);
872 continue;
873 }
874 if (!(i % 2)) {
875 r[5 - i / 2] = data;
876 r[12 - i / 2] = data_m;
877 } else {
878 r[5 - i / 2] |= ((u32)data) << 16;
879 r[12 - i / 2] |= ((u32)data_m) << 16;
880 }
881 }
882 }
883
884 /*
885 * Creates the intermediate representation of the templated match-fields of the
886 * PIE rule in the pie_rule structure by reading the raw data fields in the
887 * raw register space r[].
888 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
889 * however the RTL9310 has 2 more registers / fields and the physical field-ids
890 */
891 static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
892 {
893 int i;
894 enum template_field_id field_type;
895 u16 data, data_m;
896
897 for (i = 0; i < N_FIXED_FIELDS; i++) {
898 field_type = t[i];
899 if (!(i % 2)) {
900 data = r[5 - i / 2];
901 data_m = r[12 - i / 2];
902 } else {
903 data = r[5 - i / 2] >> 16;
904 data_m = r[12 - i / 2] >> 16;
905 }
906
907 switch (field_type) {
908 case TEMPLATE_FIELD_SPM0:
909 pr->spm = (pr->spn << 16) | data;
910 pr->spm_m = (pr->spn << 16) | data_m;
911 break;
912 case TEMPLATE_FIELD_SPM1:
913 pr->spm = data;
914 pr->spm_m = data_m;
915 break;
916 case TEMPLATE_FIELD_OTAG:
917 pr->otag = data;
918 pr->otag_m = data_m;
919 break;
920 case TEMPLATE_FIELD_SMAC0:
921 pr->smac[4] = data >> 8;
922 pr->smac[5] = data;
923 pr->smac_m[4] = data >> 8;
924 pr->smac_m[5] = data;
925 break;
926 case TEMPLATE_FIELD_SMAC1:
927 pr->smac[2] = data >> 8;
928 pr->smac[3] = data;
929 pr->smac_m[2] = data >> 8;
930 pr->smac_m[3] = data;
931 break;
932 case TEMPLATE_FIELD_SMAC2:
933 pr->smac[0] = data >> 8;
934 pr->smac[1] = data;
935 pr->smac_m[0] = data >> 8;
936 pr->smac_m[1] = data;
937 break;
938 case TEMPLATE_FIELD_DMAC0:
939 pr->dmac[4] = data >> 8;
940 pr->dmac[5] = data;
941 pr->dmac_m[4] = data >> 8;
942 pr->dmac_m[5] = data;
943 break;
944 case TEMPLATE_FIELD_DMAC1:
945 pr->dmac[2] = data >> 8;
946 pr->dmac[3] = data;
947 pr->dmac_m[2] = data >> 8;
948 pr->dmac_m[3] = data;
949 break;
950 case TEMPLATE_FIELD_DMAC2:
951 pr->dmac[0] = data >> 8;
952 pr->dmac[1] = data;
953 pr->dmac_m[0] = data >> 8;
954 pr->dmac_m[1] = data;
955 break;
956 case TEMPLATE_FIELD_ETHERTYPE:
957 pr->ethertype = data;
958 pr->ethertype_m = data_m;
959 break;
960 case TEMPLATE_FIELD_ITAG:
961 pr->itag = data;
962 pr->itag_m = data_m;
963 break;
964 case TEMPLATE_FIELD_RANGE_CHK:
965 pr->field_range_check = data;
966 pr->field_range_check_m = data_m;
967 break;
968 case TEMPLATE_FIELD_SIP0:
969 pr->sip = data;
970 pr->sip_m = data_m;
971 break;
972 case TEMPLATE_FIELD_SIP1:
973 pr->sip = (pr->sip << 16) | data;
974 pr->sip_m = (pr->sip << 16) | data_m;
975 break;
976 case TEMPLATE_FIELD_SIP2:
977 pr->is_ipv6 = true;
978 // Make use of limitiations on the position of the match values
979 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
980 r[4 - i / 2], r[3 - i / 2]);
981 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
982 r[4 - i / 2], r[3 - i / 2]);
983 case TEMPLATE_FIELD_SIP3:
984 case TEMPLATE_FIELD_SIP4:
985 case TEMPLATE_FIELD_SIP5:
986 case TEMPLATE_FIELD_SIP6:
987 case TEMPLATE_FIELD_SIP7:
988 break;
989
990 case TEMPLATE_FIELD_DIP0:
991 pr->dip = data;
992 pr->dip_m = data_m;
993 break;
994 case TEMPLATE_FIELD_DIP1:
995 pr->dip = (pr->dip << 16) | data;
996 pr->dip_m = (pr->dip << 16) | data_m;
997 break;
998 case TEMPLATE_FIELD_DIP2:
999 pr->is_ipv6 = true;
1000 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1001 r[4 - i / 2], r[3 - i / 2]);
1002 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1003 r[4 - i / 2], r[3 - i / 2]);
1004 case TEMPLATE_FIELD_DIP3:
1005 case TEMPLATE_FIELD_DIP4:
1006 case TEMPLATE_FIELD_DIP5:
1007 case TEMPLATE_FIELD_DIP6:
1008 case TEMPLATE_FIELD_DIP7:
1009 break;
1010 case TEMPLATE_FIELD_IP_TOS_PROTO:
1011 pr->tos_proto = data;
1012 pr->tos_proto_m = data_m;
1013 break;
1014 case TEMPLATE_FIELD_L4_SPORT:
1015 pr->sport = data;
1016 pr->sport_m = data_m;
1017 break;
1018 case TEMPLATE_FIELD_L4_DPORT:
1019 pr->dport = data;
1020 pr->dport_m = data_m;
1021 break;
1022 case TEMPLATE_FIELD_ICMP_IGMP:
1023 pr->icmp_igmp = data;
1024 pr->icmp_igmp_m = data_m;
1025 break;
1026 default:
1027 pr_info("%s: unknown field %d\n", __func__, field_type);
1028 }
1029 }
1030 }
1031
1032 static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1033 {
1034 pr->spmmask_fix = (r[6] >> 22) & 0x3;
1035 pr->spn = (r[6] >> 16) & 0x3f;
1036 pr->mgnt_vlan = (r[6] >> 15) & 1;
1037 pr->dmac_hit_sw = (r[6] >> 14) & 1;
1038 pr->not_first_frag = (r[6] >> 13) & 1;
1039 pr->frame_type_l4 = (r[6] >> 10) & 7;
1040 pr->frame_type = (r[6] >> 8) & 3;
1041 pr->otag_fmt = (r[6] >> 7) & 1;
1042 pr->itag_fmt = (r[6] >> 6) & 1;
1043 pr->otag_exist = (r[6] >> 5) & 1;
1044 pr->itag_exist = (r[6] >> 4) & 1;
1045 pr->frame_type_l2 = (r[6] >> 2) & 3;
1046 pr->tid = r[6] & 3;
1047
1048 pr->spmmask_fix_m = (r[13] >> 22) & 0x3;
1049 pr->spn_m = (r[13] >> 16) & 0x3f;
1050 pr->mgnt_vlan_m = (r[13] >> 15) & 1;
1051 pr->dmac_hit_sw_m = (r[13] >> 14) & 1;
1052 pr->not_first_frag_m = (r[13] >> 13) & 1;
1053 pr->frame_type_l4_m = (r[13] >> 10) & 7;
1054 pr->frame_type_m = (r[13] >> 8) & 3;
1055 pr->otag_fmt_m = (r[13] >> 7) & 1;
1056 pr->itag_fmt_m = (r[13] >> 6) & 1;
1057 pr->otag_exist_m = (r[13] >> 5) & 1;
1058 pr->itag_exist_m = (r[13] >> 4) & 1;
1059 pr->frame_type_l2_m = (r[13] >> 2) & 3;
1060 pr->tid_m = r[13] & 3;
1061
1062 pr->valid = r[14] & BIT(31);
1063 pr->cond_not = r[14] & BIT(30);
1064 pr->cond_and1 = r[14] & BIT(29);
1065 pr->cond_and2 = r[14] & BIT(28);
1066 pr->ivalid = r[14] & BIT(27);
1067
1068 pr->drop = (r[17] >> 14) & 3;
1069 pr->fwd_sel = r[17] & BIT(13);
1070 pr->ovid_sel = r[17] & BIT(12);
1071 pr->ivid_sel = r[17] & BIT(11);
1072 pr->flt_sel = r[17] & BIT(10);
1073 pr->log_sel = r[17] & BIT(9);
1074 pr->rmk_sel = r[17] & BIT(8);
1075 pr->meter_sel = r[17] & BIT(7);
1076 pr->tagst_sel = r[17] & BIT(6);
1077 pr->mir_sel = r[17] & BIT(5);
1078 pr->nopri_sel = r[17] & BIT(4);
1079 pr->cpupri_sel = r[17] & BIT(3);
1080 pr->otpid_sel = r[17] & BIT(2);
1081 pr->itpid_sel = r[17] & BIT(1);
1082 pr->shaper_sel = r[17] & BIT(0);
1083 }
1084
1085 static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1086 {
1087 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;
1088 r[6] |= ((u32) (pr->spn & 0x3f)) << 16;
1089 r[6] |= pr->mgnt_vlan ? BIT(15) : 0;
1090 r[6] |= pr->dmac_hit_sw ? BIT(14) : 0;
1091 r[6] |= pr->not_first_frag ? BIT(13) : 0;
1092 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;
1093 r[6] |= ((u32) (pr->frame_type & 0x3)) << 8;
1094 r[6] |= pr->otag_fmt ? BIT(7) : 0;
1095 r[6] |= pr->itag_fmt ? BIT(6) : 0;
1096 r[6] |= pr->otag_exist ? BIT(5) : 0;
1097 r[6] |= pr->itag_exist ? BIT(4) : 0;
1098 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;
1099 r[6] |= ((u32) (pr->tid & 0x3));
1100
1101 r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;
1102 r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;
1103 r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1104 r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1105 r[13] |= pr->not_first_frag_m ? BIT(13) : 0;
1106 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1107 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1108 r[13] |= pr->otag_fmt_m ? BIT(7) : 0;
1109 r[13] |= pr->itag_fmt_m ? BIT(6) : 0;
1110 r[13] |= pr->otag_exist_m ? BIT(5) : 0;
1111 r[13] |= pr->itag_exist_m ? BIT(4) : 0;
1112 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1113 r[13] |= ((u32) (pr->tid_m & 0x3));
1114
1115 r[14] = pr->valid ? BIT(31) : 0;
1116 r[14] |= pr->cond_not ? BIT(30) : 0;
1117 r[14] |= pr->cond_and1 ? BIT(29) : 0;
1118 r[14] |= pr->cond_and2 ? BIT(28) : 0;
1119 r[14] |= pr->ivalid ? BIT(27) : 0;
1120
1121 if (pr->drop)
1122 r[17] = 0x1 << 14; // Standard drop action
1123 else
1124 r[17] = 0;
1125 r[17] |= pr->fwd_sel ? BIT(13) : 0;
1126 r[17] |= pr->ovid_sel ? BIT(12) : 0;
1127 r[17] |= pr->ivid_sel ? BIT(11) : 0;
1128 r[17] |= pr->flt_sel ? BIT(10) : 0;
1129 r[17] |= pr->log_sel ? BIT(9) : 0;
1130 r[17] |= pr->rmk_sel ? BIT(8) : 0;
1131 r[17] |= pr->meter_sel ? BIT(7) : 0;
1132 r[17] |= pr->tagst_sel ? BIT(6) : 0;
1133 r[17] |= pr->mir_sel ? BIT(5) : 0;
1134 r[17] |= pr->nopri_sel ? BIT(4) : 0;
1135 r[17] |= pr->cpupri_sel ? BIT(3) : 0;
1136 r[17] |= pr->otpid_sel ? BIT(2) : 0;
1137 r[17] |= pr->itpid_sel ? BIT(1) : 0;
1138 r[17] |= pr->shaper_sel ? BIT(0) : 0;
1139 }
1140
1141 static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr)
1142 {
1143 u16 *aif = (u16 *)&r[17];
1144 u16 data;
1145 int fields_used = 0;
1146
1147 aif--;
1148
1149 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1150 /* Multiple actions can be linked to a match of a PIE rule,
1151 * they have different precedence depending on their type and this precedence
1152 * defines which Action Information Field (0-4) in the IACL table stores
1153 * the additional data of the action (like e.g. the port number a packet is
1154 * forwarded to) */
1155 // TODO: count bits in selectors to limit to a maximum number of actions
1156 if (pr->fwd_sel) { // Forwarding action
1157 data = pr->fwd_act << 13;
1158 data |= pr->fwd_data;
1159 data |= pr->bypass_all ? BIT(12) : 0;
1160 data |= pr->bypass_ibc_sc ? BIT(11) : 0;
1161 data |= pr->bypass_igr_stp ? BIT(10) : 0;
1162 *aif-- = data;
1163 fields_used++;
1164 }
1165
1166 if (pr->ovid_sel) { // Outer VID action
1167 data = (pr->ovid_act & 0x3) << 12;
1168 data |= pr->ovid_data;
1169 *aif-- = data;
1170 fields_used++;
1171 }
1172
1173 if (pr->ivid_sel) { // Inner VID action
1174 data = (pr->ivid_act & 0x3) << 12;
1175 data |= pr->ivid_data;
1176 *aif-- = data;
1177 fields_used++;
1178 }
1179
1180 if (pr->flt_sel) { // Filter action
1181 *aif-- = pr->flt_data;
1182 fields_used++;
1183 }
1184
1185 if (pr->log_sel) { // Log action
1186 if (fields_used >= 4)
1187 return -1;
1188 *aif-- = pr->log_data;
1189 fields_used++;
1190 }
1191
1192 if (pr->rmk_sel) { // Remark action
1193 if (fields_used >= 4)
1194 return -1;
1195 *aif-- = pr->rmk_data;
1196 fields_used++;
1197 }
1198
1199 if (pr->meter_sel) { // Meter action
1200 if (fields_used >= 4)
1201 return -1;
1202 *aif-- = pr->meter_data;
1203 fields_used++;
1204 }
1205
1206 if (pr->tagst_sel) { // Egress Tag Status action
1207 if (fields_used >= 4)
1208 return -1;
1209 *aif-- = pr->tagst_data;
1210 fields_used++;
1211 }
1212
1213 if (pr->mir_sel) { // Mirror action
1214 if (fields_used >= 4)
1215 return -1;
1216 *aif-- = pr->mir_data;
1217 fields_used++;
1218 }
1219
1220 if (pr->nopri_sel) { // Normal Priority action
1221 if (fields_used >= 4)
1222 return -1;
1223 *aif-- = pr->nopri_data;
1224 fields_used++;
1225 }
1226
1227 if (pr->cpupri_sel) { // CPU Priority action
1228 if (fields_used >= 4)
1229 return -1;
1230 *aif-- = pr->nopri_data;
1231 fields_used++;
1232 }
1233
1234 if (pr->otpid_sel) { // OTPID action
1235 if (fields_used >= 4)
1236 return -1;
1237 *aif-- = pr->otpid_data;
1238 fields_used++;
1239 }
1240
1241 if (pr->itpid_sel) { // ITPID action
1242 if (fields_used >= 4)
1243 return -1;
1244 *aif-- = pr->itpid_data;
1245 fields_used++;
1246 }
1247
1248 if (pr->shaper_sel) { // Traffic shaper action
1249 if (fields_used >= 4)
1250 return -1;
1251 *aif-- = pr->shaper_data;
1252 fields_used++;
1253 }
1254
1255 return 0;
1256 }
1257
1258 static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr)
1259 {
1260 u16 *aif = (u16 *)&r[17];
1261
1262 aif--;
1263
1264 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1265 if (pr->drop)
1266 pr_debug("%s: Action Drop: %d", __func__, pr->drop);
1267
1268 if (pr->fwd_sel){ // Forwarding action
1269 pr->fwd_act = *aif >> 13;
1270 pr->fwd_data = *aif--;
1271 pr->bypass_all = pr->fwd_data & BIT(12);
1272 pr->bypass_ibc_sc = pr->fwd_data & BIT(11);
1273 pr->bypass_igr_stp = pr->fwd_data & BIT(10);
1274 if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)
1275 pr->bypass_sel = true;
1276 }
1277 if (pr->ovid_sel) // Outer VID action
1278 pr->ovid_data = *aif--;
1279 if (pr->ivid_sel) // Inner VID action
1280 pr->ivid_data = *aif--;
1281 if (pr->flt_sel) // Filter action
1282 pr->flt_data = *aif--;
1283 if (pr->log_sel) // Log action
1284 pr->log_data = *aif--;
1285 if (pr->rmk_sel) // Remark action
1286 pr->rmk_data = *aif--;
1287 if (pr->meter_sel) // Meter action
1288 pr->meter_data = *aif--;
1289 if (pr->tagst_sel) // Egress Tag Status action
1290 pr->tagst_data = *aif--;
1291 if (pr->mir_sel) // Mirror action
1292 pr->mir_data = *aif--;
1293 if (pr->nopri_sel) // Normal Priority action
1294 pr->nopri_data = *aif--;
1295 if (pr->cpupri_sel) // CPU Priority action
1296 pr->nopri_data = *aif--;
1297 if (pr->otpid_sel) // OTPID action
1298 pr->otpid_data = *aif--;
1299 if (pr->itpid_sel) // ITPID action
1300 pr->itpid_data = *aif--;
1301 if (pr->shaper_sel) // Traffic shaper action
1302 pr->shaper_data = *aif--;
1303 }
1304
1305 static void rtl838x_pie_rule_dump_raw(u32 r[])
1306 {
1307 pr_info("Raw IACL table entry:\n");
1308 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1309 pr_info("Fixed : %08x\n", r[6]);
1310 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
1311 pr_info("Fixed M: %08x\n", r[13]);
1312 pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
1313 pr_info("Sel : %08x\n", r[17]);
1314 }
1315
1316 static void rtl838x_pie_rule_dump(struct pie_rule *pr)
1317 {
1318 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1319 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1320 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1321 if (pr->fwd_sel)
1322 pr_info("FWD: %08x\n", pr->fwd_data);
1323 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1324 }
1325
1326 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1327 {
1328 // Read IACL table (1) via register 0
1329 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1330 u32 r[18];
1331 int i;
1332 int block = idx / PIE_BLOCK_SIZE;
1333 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1334
1335 memset(pr, 0, sizeof(*pr));
1336 rtl_table_read(q, idx);
1337 for (i = 0; i < 18; i++)
1338 r[i] = sw_r32(rtl_table_data(q, i));
1339
1340 rtl_table_release(q);
1341
1342 rtl838x_read_pie_fixed_fields(r, pr);
1343 if (!pr->valid)
1344 return 0;
1345
1346 pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1347 rtl838x_pie_rule_dump_raw(r);
1348
1349 rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1350
1351 rtl838x_read_pie_action(r, pr);
1352
1353 return 0;
1354 }
1355
1356 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1357 {
1358 // Access IACL table (1) via register 0
1359 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1360 u32 r[18];
1361 int i, err = 0;
1362 int block = idx / PIE_BLOCK_SIZE;
1363 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1364
1365 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1366
1367 for (i = 0; i < 18; i++)
1368 r[i] = 0;
1369
1370 if (!pr->valid)
1371 goto err_out;
1372
1373 rtl838x_write_pie_fixed_fields(r, pr);
1374
1375 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1376 rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1377
1378 if (rtl838x_write_pie_action(r, pr)) {
1379 pr_err("Rule actions too complex\n");
1380 goto err_out;
1381 }
1382
1383 // rtl838x_pie_rule_dump_raw(r);
1384
1385 for (i = 0; i < 18; i++)
1386 sw_w32(r[i], rtl_table_data(q, i));
1387
1388 err_out:
1389 rtl_table_write(q, idx);
1390 rtl_table_release(q);
1391
1392 return err;
1393 }
1394
1395 static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type)
1396 {
1397 int i;
1398 enum template_field_id ft;
1399
1400 for (i = 0; i < N_FIXED_FIELDS; i++) {
1401 ft = fixed_templates[t][i];
1402 if (field_type == ft)
1403 return true;
1404 }
1405
1406 return false;
1407 }
1408
1409 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv,
1410 struct pie_rule *pr, int t, int block)
1411 {
1412 int i;
1413
1414 if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1415 return -1;
1416
1417 if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1418 return -1;
1419
1420 if (pr->is_ipv6) {
1421 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1422 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1423 && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1424 return -1;
1425 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1426 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1427 && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1428 return -1;
1429 }
1430
1431 if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1432 return -1;
1433
1434 if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1435 return -1;
1436
1437 // TODO: Check more
1438
1439 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1440
1441 if (i >= PIE_BLOCK_SIZE)
1442 return -1;
1443
1444 return i + PIE_BLOCK_SIZE * block;
1445 }
1446
1447 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1448 {
1449 int idx, block, j, t;
1450
1451 pr_debug("In %s\n", __func__);
1452
1453 mutex_lock(&priv->pie_mutex);
1454
1455 for (block = 0; block < priv->n_pie_blocks; block++) {
1456 for (j = 0; j < 3; j++) {
1457 t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1458 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1459 idx = rtl838x_pie_verify_template(priv, pr, t, block);
1460 if (idx >= 0)
1461 break;
1462 }
1463 if (j < 3)
1464 break;
1465 }
1466
1467 if (block >= priv->n_pie_blocks) {
1468 mutex_unlock(&priv->pie_mutex);
1469 return -EOPNOTSUPP;
1470 }
1471
1472 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1473 set_bit(idx, priv->pie_use_bm);
1474
1475 pr->valid = true;
1476 pr->tid = j; // Mapped to template number
1477 pr->tid_m = 0x3;
1478 pr->id = idx;
1479
1480 rtl838x_pie_lookup_enable(priv, idx);
1481 rtl838x_pie_rule_write(priv, idx, pr);
1482
1483 mutex_unlock(&priv->pie_mutex);
1484 return 0;
1485 }
1486
1487 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1488 {
1489 int idx = pr->id;
1490
1491 rtl838x_pie_rule_del(priv, idx, idx);
1492 clear_bit(idx, priv->pie_use_bm);
1493 }
1494
1495 /*
1496 * Initializes the Packet Inspection Engine:
1497 * powers it up, enables default matching templates for all blocks
1498 * and clears all rules possibly installed by u-boot
1499 */
1500 static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
1501 {
1502 int i;
1503 u32 template_selectors;
1504
1505 mutex_init(&priv->pie_mutex);
1506
1507 // Enable ACL lookup on all ports, including CPU_PORT
1508 for (i = 0; i <= priv->cpu_port; i++)
1509 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
1510
1511 // Power on all PIE blocks
1512 for (i = 0; i < priv->n_pie_blocks; i++)
1513 sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
1514
1515 // Include IPG in metering
1516 sw_w32(1, RTL838X_METER_GLB_CTRL);
1517
1518 // Delete all present rules
1519 rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1520
1521 // Routing bypasses source port filter: disable write-protection, first
1522 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
1523 sw_w32_mask(0, 1, RTL838X_DMY_REG27);
1524 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
1525
1526 // Enable predefined templates 0, 1 and 2 for even blocks
1527 template_selectors = 0 | (1 << 3) | (2 << 6);
1528 for (i = 0; i < 6; i += 2)
1529 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1530
1531 // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
1532 template_selectors = 0 | (3 << 3) | (4 << 6);
1533 for (i = 1; i < priv->n_pie_blocks; i += 2)
1534 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1535
1536 // Group each pair of physical blocks together to a logical block
1537 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
1538 }
1539
1540 static u32 rtl838x_packet_cntr_read(int counter)
1541 {
1542 u32 v;
1543
1544 // Read LOG table (3) via register RTL8380_TBL_0
1545 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1546
1547 pr_debug("In %s, id %d\n", __func__, counter);
1548 rtl_table_read(r, counter / 2);
1549
1550 pr_debug("Registers: %08x %08x\n",
1551 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
1552 // The table has a size of 2 registers
1553 if (counter % 2)
1554 v = sw_r32(rtl_table_data(r, 0));
1555 else
1556 v = sw_r32(rtl_table_data(r, 1));
1557
1558 rtl_table_release(r);
1559
1560 return v;
1561 }
1562
1563 static void rtl838x_packet_cntr_clear(int counter)
1564 {
1565 // Access LOG table (3) via register RTL8380_TBL_0
1566 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1567
1568 pr_debug("In %s, id %d\n", __func__, counter);
1569 // The table has a size of 2 registers
1570 if (counter % 2)
1571 sw_w32(0, rtl_table_data(r, 0));
1572 else
1573 sw_w32(0, rtl_table_data(r, 1));
1574
1575 rtl_table_write(r, counter / 2);
1576
1577 rtl_table_release(r);
1578 }
1579
1580 static void rtl838x_route_read(int idx, struct rtl83xx_route *rt)
1581 {
1582 // Read ROUTING table (2) via register RTL8380_TBL_1
1583 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1584
1585 pr_debug("In %s, id %d\n", __func__, idx);
1586 rtl_table_read(r, idx);
1587
1588 // The table has a size of 2 registers
1589 rt->nh.gw = sw_r32(rtl_table_data(r, 0));
1590 rt->nh.gw <<= 32;
1591 rt->nh.gw |= sw_r32(rtl_table_data(r, 1));
1592
1593 rtl_table_release(r);
1594 }
1595
1596 static void rtl838x_route_write(int idx, struct rtl83xx_route *rt)
1597 {
1598 // Access ROUTING table (2) via register RTL8380_TBL_1
1599 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1600
1601 pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw);
1602 sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0));
1603 sw_w32(rt->nh.gw, rtl_table_data(r, 1));
1604 rtl_table_write(r, idx);
1605
1606 rtl_table_release(r);
1607 }
1608
1609 static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)
1610 {
1611 // Nothing to be done
1612 return 0;
1613 }
1614
1615 void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1616 {
1617 if (type == PBVLAN_TYPE_INNER)
1618 sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1619 else
1620 sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1621 }
1622
1623 void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1624 {
1625 if (type == PBVLAN_TYPE_INNER)
1626 sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1627 else
1628 sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1629 }
1630
1631 static int rtl838x_set_ageing_time(unsigned long msec)
1632 {
1633 int t = sw_r32(RTL838X_L2_CTRL_1);
1634
1635 t &= 0x7FFFFF;
1636 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1637 pr_debug("L2 AGING time: %d sec\n", t);
1638
1639 t = (msec * 625 + 127000) / 128000;
1640 t = t > 0x7FFFFF ? 0x7FFFFF : t;
1641 sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1);
1642 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT));
1643
1644 return 0;
1645 }
1646
1647 static void rtl838x_set_igr_filter(int port, enum igr_filter state)
1648 {
1649 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1650 RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1651 }
1652
1653 static void rtl838x_set_egr_filter(int port, enum egr_filter state)
1654 {
1655 sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d),
1656 RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
1657 }
1658
1659 void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1660 {
1661 algoidx &= 1; // RTL838X only supports 2 concurrent algorithms
1662 sw_w32_mask(1 << (group % 8), algoidx << (group % 8),
1663 RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));
1664 sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
1665 }
1666
1667 void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1668 {
1669 switch(type) {
1670 case BPDU:
1671 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1672 RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1673 break;
1674 case PTP:
1675 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1676 RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
1677 break;
1678 case LLTP:
1679 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1680 RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1681 break;
1682 default:
1683 break;
1684 }
1685 }
1686
1687 const struct rtl838x_reg rtl838x_reg = {
1688 .mask_port_reg_be = rtl838x_mask_port_reg,
1689 .set_port_reg_be = rtl838x_set_port_reg,
1690 .get_port_reg_be = rtl838x_get_port_reg,
1691 .mask_port_reg_le = rtl838x_mask_port_reg,
1692 .set_port_reg_le = rtl838x_set_port_reg,
1693 .get_port_reg_le = rtl838x_get_port_reg,
1694 .stat_port_rst = RTL838X_STAT_PORT_RST,
1695 .stat_rst = RTL838X_STAT_RST,
1696 .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,
1697 .port_iso_ctrl = rtl838x_port_iso_ctrl,
1698 .traffic_enable = rtl838x_traffic_enable,
1699 .traffic_disable = rtl838x_traffic_disable,
1700 .traffic_get = rtl838x_traffic_get,
1701 .traffic_set = rtl838x_traffic_set,
1702 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
1703 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
1704 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
1705 .set_ageing_time = rtl838x_set_ageing_time,
1706 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
1707 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
1708 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
1709 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
1710 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
1711 .isr_glb_src = RTL838X_ISR_GLB_SRC,
1712 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
1713 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
1714 .imr_glb = RTL838X_IMR_GLB,
1715 .vlan_tables_read = rtl838x_vlan_tables_read,
1716 .vlan_set_tagged = rtl838x_vlan_set_tagged,
1717 .vlan_set_untagged = rtl838x_vlan_set_untagged,
1718 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
1719 .vlan_profile_dump = rtl838x_vlan_profile_dump,
1720 .vlan_profile_setup = rtl838x_vlan_profile_setup,
1721 .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,
1722 .set_vlan_igr_filter = rtl838x_set_igr_filter,
1723 .set_vlan_egr_filter = rtl838x_set_egr_filter,
1724 .enable_learning = rtl838x_enable_learning,
1725 .enable_flood = rtl838x_enable_flood,
1726 .enable_mcast_flood = rtl838x_enable_mcast_flood,
1727 .enable_bcast_flood = rtl838x_enable_bcast_flood,
1728 .stp_get = rtl838x_stp_get,
1729 .stp_set = rtl838x_stp_set,
1730 .mac_port_ctrl = rtl838x_mac_port_ctrl,
1731 .l2_port_new_salrn = rtl838x_l2_port_new_salrn,
1732 .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
1733 .mir_ctrl = RTL838X_MIR_CTRL,
1734 .mir_dpm = RTL838X_MIR_DPM_CTRL,
1735 .mir_spm = RTL838X_MIR_SPM_CTRL,
1736 .mac_link_sts = RTL838X_MAC_LINK_STS,
1737 .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
1738 .mac_link_spd_sts = rtl838x_mac_link_spd_sts,
1739 .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
1740 .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
1741 .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
1742 .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,
1743 .read_cam = rtl838x_read_cam,
1744 .write_cam = rtl838x_write_cam,
1745 .vlan_port_tag_sts_ctrl = RTL838X_VLAN_PORT_TAG_STS_CTRL,
1746 .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set,
1747 .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set,
1748 .trk_mbr_ctr = rtl838x_trk_mbr_ctr,
1749 .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,
1750 .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,
1751 .init_eee = rtl838x_init_eee,
1752 .port_eee_set = rtl838x_port_eee_set,
1753 .eee_port_ability = rtl838x_eee_port_ability,
1754 .l2_hash_seed = rtl838x_l2_hash_seed,
1755 .l2_hash_key = rtl838x_l2_hash_key,
1756 .read_mcast_pmask = rtl838x_read_mcast_pmask,
1757 .write_mcast_pmask = rtl838x_write_mcast_pmask,
1758 .pie_init = rtl838x_pie_init,
1759 .pie_rule_read = rtl838x_pie_rule_read,
1760 .pie_rule_write = rtl838x_pie_rule_write,
1761 .pie_rule_add = rtl838x_pie_rule_add,
1762 .pie_rule_rm = rtl838x_pie_rule_rm,
1763 .l2_learning_setup = rtl838x_l2_learning_setup,
1764 .packet_cntr_read = rtl838x_packet_cntr_read,
1765 .packet_cntr_clear = rtl838x_packet_cntr_clear,
1766 .route_read = rtl838x_route_read,
1767 .route_write = rtl838x_route_write,
1768 .l3_setup = rtl838x_l3_setup,
1769 .set_distribution_algorithm = rtl838x_set_distribution_algorithm,
1770 .set_receive_management_action = rtl838x_set_receive_management_action,
1771 };
1772
1773 irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
1774 {
1775 struct dsa_switch *ds = dev_id;
1776 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
1777 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
1778 u32 link;
1779 int i;
1780
1781 /* Clear status */
1782 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
1783 pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
1784
1785 for (i = 0; i < 28; i++) {
1786 if (ports & BIT(i)) {
1787 link = sw_r32(RTL838X_MAC_LINK_STS);
1788 if (link & BIT(i))
1789 dsa_port_phylink_mac_change(ds, i, true);
1790 else
1791 dsa_port_phylink_mac_change(ds, i, false);
1792 }
1793 }
1794 return IRQ_HANDLED;
1795 }
1796
1797 int rtl838x_smi_wait_op(int timeout)
1798 {
1799 int ret = 0;
1800 u32 val;
1801
1802 ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1,
1803 val, !(val & 0x1), 20, timeout);
1804 if (ret)
1805 pr_err("%s: timeout\n", __func__);
1806
1807 return ret;
1808 }
1809
1810 /*
1811 * Reads a register in a page from the PHY
1812 */
1813 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
1814 {
1815 u32 v;
1816 u32 park_page;
1817
1818 if (port > 31) {
1819 *val = 0xffff;
1820 return 0;
1821 }
1822
1823 if (page > 4095 || reg > 31)
1824 return -ENOTSUPP;
1825
1826 mutex_lock(&smi_lock);
1827
1828 if (rtl838x_smi_wait_op(100000))
1829 goto timeout;
1830
1831 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1832
1833 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1834 v = reg << 20 | page << 3;
1835 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1836 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1837
1838 if (rtl838x_smi_wait_op(100000))
1839 goto timeout;
1840
1841 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1842
1843 mutex_unlock(&smi_lock);
1844 return 0;
1845
1846 timeout:
1847 mutex_unlock(&smi_lock);
1848 return -ETIMEDOUT;
1849 }
1850
1851 /*
1852 * Write to a register in a page of the PHY
1853 */
1854 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
1855 {
1856 u32 v;
1857 u32 park_page;
1858
1859 val &= 0xffff;
1860 if (port > 31 || page > 4095 || reg > 31)
1861 return -ENOTSUPP;
1862
1863 mutex_lock(&smi_lock);
1864 if (rtl838x_smi_wait_op(100000))
1865 goto timeout;
1866
1867 sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
1868 mdelay(10);
1869
1870 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1871
1872 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1873 v = reg << 20 | page << 3 | 0x4;
1874 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1875 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1876
1877 if (rtl838x_smi_wait_op(100000))
1878 goto timeout;
1879
1880 mutex_unlock(&smi_lock);
1881 return 0;
1882
1883 timeout:
1884 mutex_unlock(&smi_lock);
1885 return -ETIMEDOUT;
1886 }
1887
1888 /*
1889 * Read an mmd register of a PHY
1890 */
1891 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
1892 {
1893 u32 v;
1894
1895 mutex_lock(&smi_lock);
1896
1897 if (rtl838x_smi_wait_op(100000))
1898 goto timeout;
1899
1900 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1901 mdelay(10);
1902
1903 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1904
1905 v = addr << 16 | reg;
1906 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1907
1908 /* mmd-access | read | cmd-start */
1909 v = 1 << 1 | 0 << 2 | 1;
1910 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1911
1912 if (rtl838x_smi_wait_op(100000))
1913 goto timeout;
1914
1915 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1916
1917 mutex_unlock(&smi_lock);
1918 return 0;
1919
1920 timeout:
1921 mutex_unlock(&smi_lock);
1922 return -ETIMEDOUT;
1923 }
1924
1925 /*
1926 * Write to an mmd register of a PHY
1927 */
1928 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
1929 {
1930 u32 v;
1931
1932 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
1933 val &= 0xffff;
1934 mutex_lock(&smi_lock);
1935
1936 if (rtl838x_smi_wait_op(100000))
1937 goto timeout;
1938
1939 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1940 mdelay(10);
1941
1942 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1943
1944 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1945 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1946 /* mmd-access | write | cmd-start */
1947 v = 1 << 1 | 1 << 2 | 1;
1948 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1949
1950 if (rtl838x_smi_wait_op(100000))
1951 goto timeout;
1952
1953 mutex_unlock(&smi_lock);
1954 return 0;
1955
1956 timeout:
1957 mutex_unlock(&smi_lock);
1958 return -ETIMEDOUT;
1959 }
1960
1961 void rtl8380_get_version(struct rtl838x_switch_priv *priv)
1962 {
1963 u32 rw_save, info_save;
1964 u32 info;
1965
1966 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
1967 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
1968
1969 info_save = sw_r32(RTL838X_CHIP_INFO);
1970 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
1971
1972 info = sw_r32(RTL838X_CHIP_INFO);
1973 sw_w32(info_save, RTL838X_CHIP_INFO);
1974 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
1975
1976 if ((info & 0xFFFF) == 0x6275) {
1977 if (((info >> 16) & 0x1F) == 0x1)
1978 priv->version = RTL8380_VERSION_A;
1979 else if (((info >> 16) & 0x1F) == 0x2)
1980 priv->version = RTL8380_VERSION_B;
1981 else
1982 priv->version = RTL8380_VERSION_B;
1983 } else {
1984 priv->version = '-';
1985 }
1986 }
1987
1988 void rtl838x_vlan_profile_dump(int profile)
1989 {
1990 u32 p;
1991
1992 if (profile < 0 || profile > 7)
1993 return;
1994
1995 p = sw_r32(RTL838X_VLAN_PROFILE(profile));
1996
1997 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
1998 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
1999 profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
2000 }
2001
2002 void rtl8380_sds_rst(int mac)
2003 {
2004 u32 offset = (mac == 24) ? 0 : 0x100;
2005
2006 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
2007 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
2008 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
2009 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
2010 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
2011 pr_debug("SERDES reset: %d\n", mac);
2012 }
2013
2014 int rtl8380_sds_power(int mac, int val)
2015 {
2016 u32 mode = (val == 1) ? 0x4 : 0x9;
2017 u32 offset = (mac == 24) ? 5 : 0;
2018
2019 if ((mac != 24) && (mac != 26)) {
2020 pr_err("%s: not a fibre port: %d\n", __func__, mac);
2021 return -1;
2022 }
2023
2024 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
2025
2026 rtl8380_sds_rst(mac);
2027
2028 return 0;
2029 }
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