1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/iopoll.h>
5 #include <net/nexthop.h>
9 #define RTL838X_VLAN_PORT_TAG_STS_UNTAG 0x0
10 #define RTL838X_VLAN_PORT_TAG_STS_TAGGED 0x1
11 #define RTL838X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
13 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE 0xA530
15 #define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \
16 RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
18 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(11,10)
19 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(9,8)
20 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(7,6)
21 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(5,4)
22 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(3,2)
23 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(1,0)
25 extern struct mutex smi_lock
;
27 // see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
28 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
29 enum template_field_id
{
30 TEMPLATE_FIELD_SPMMASK
= 0,
31 TEMPLATE_FIELD_SPM0
= 1, // Source portmask ports 0-15
32 TEMPLATE_FIELD_SPM1
= 2, // Source portmask ports 16-28
33 TEMPLATE_FIELD_RANGE_CHK
= 3,
34 TEMPLATE_FIELD_DMAC0
= 4, // Destination MAC [15:0]
35 TEMPLATE_FIELD_DMAC1
= 5, // Destination MAC [31:16]
36 TEMPLATE_FIELD_DMAC2
= 6, // Destination MAC [47:32]
37 TEMPLATE_FIELD_SMAC0
= 7, // Source MAC [15:0]
38 TEMPLATE_FIELD_SMAC1
= 8, // Source MAC [31:16]
39 TEMPLATE_FIELD_SMAC2
= 9, // Source MAC [47:32]
40 TEMPLATE_FIELD_ETHERTYPE
= 10, // Ethernet typ
41 TEMPLATE_FIELD_OTAG
= 11, // Outer VLAN tag
42 TEMPLATE_FIELD_ITAG
= 12, // Inner VLAN tag
43 TEMPLATE_FIELD_SIP0
= 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
44 // source protocol address in header
45 TEMPLATE_FIELD_SIP1
= 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
46 TEMPLATE_FIELD_DIP0
= 15, // IPv4 or IPv6 destination IP[15:0]
47 TEMPLATE_FIELD_DIP1
= 16, // IPv4 or IPv6 destination IP[31:16]
48 TEMPLATE_FIELD_IP_TOS_PROTO
= 17, // IPv4 TOS/IPv6 traffic class and
49 // IPv4 proto/IPv6 next header fields
50 TEMPLATE_FIELD_L34_HEADER
= 18, // packet with extra tag and IPv6 with auth, dest,
51 // frag, route, hop-by-hop option header,
52 // IGMP type, TCP flag
53 TEMPLATE_FIELD_L4_SPORT
= 19, // TCP/UDP source port
54 TEMPLATE_FIELD_L4_DPORT
= 20, // TCP/UDP destination port
55 TEMPLATE_FIELD_ICMP_IGMP
= 21,
56 TEMPLATE_FIELD_IP_RANGE
= 22,
57 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 23, // Field selector mask
58 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 24,
59 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 25,
60 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 26,
61 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 27,
62 TEMPLATE_FIELD_SIP2
= 28, // IPv6 source IP[47:32]
63 TEMPLATE_FIELD_SIP3
= 29, // IPv6 source IP[63:48]
64 TEMPLATE_FIELD_SIP4
= 30, // IPv6 source IP[79:64]
65 TEMPLATE_FIELD_SIP5
= 31, // IPv6 source IP[95:80]
66 TEMPLATE_FIELD_SIP6
= 32, // IPv6 source IP[111:96]
67 TEMPLATE_FIELD_SIP7
= 33, // IPv6 source IP[127:112]
68 TEMPLATE_FIELD_DIP2
= 34, // IPv6 destination IP[47:32]
69 TEMPLATE_FIELD_DIP3
= 35, // IPv6 destination IP[63:48]
70 TEMPLATE_FIELD_DIP4
= 36, // IPv6 destination IP[79:64]
71 TEMPLATE_FIELD_DIP5
= 37, // IPv6 destination IP[95:80]
72 TEMPLATE_FIELD_DIP6
= 38, // IPv6 destination IP[111:96]
73 TEMPLATE_FIELD_DIP7
= 39, // IPv6 destination IP[127:112]
74 TEMPLATE_FIELD_FWD_VID
= 40, // Forwarding VLAN-ID
75 TEMPLATE_FIELD_FLOW_LABEL
= 41,
79 * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
80 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
81 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
82 * templates. Additionally, 3 user-definable templates can be set up via the definitions
83 * in RTL838X_ACL_TMPLTE_CTRL control registers.
84 * TODO: See all src/app/diag_v2/src/diag_pie.c
86 #define N_FIXED_TEMPLATES 5
87 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
90 TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_OTAG
,
91 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
92 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
93 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_RANGE_CHK
95 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
96 TEMPLATE_FIELD_DIP1
,TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_L4_SPORT
,
97 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_ITAG
,
98 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
100 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
101 TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
102 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_SIP0
,
103 TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
105 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
106 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
107 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_L4_DPORT
,
108 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_IP_TOS_PROTO
110 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
111 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
112 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_ITAG
,
113 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
117 void rtl838x_print_matrix(void)
119 unsigned volatile int *ptr8
;
122 ptr8
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
123 for (i
= 0; i
< 28; i
+= 8)
124 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
125 ptr8
[i
+ 0], ptr8
[i
+ 1], ptr8
[i
+ 2], ptr8
[i
+ 3],
126 ptr8
[i
+ 4], ptr8
[i
+ 5], ptr8
[i
+ 6], ptr8
[i
+ 7]);
127 pr_debug("CPU_PORT> %8x\n", ptr8
[28]);
130 static inline int rtl838x_port_iso_ctrl(int p
)
132 return RTL838X_PORT_ISO_CTRL(p
);
135 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
137 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
138 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & BIT(15));
141 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
143 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
144 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & BIT(15));
147 static inline int rtl838x_tbl_access_data_0(int i
)
149 return RTL838X_TBL_ACCESS_DATA_0(i
);
152 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
155 // Read VLAN table (0) via register 0
156 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
158 rtl_table_read(r
, vlan
);
159 info
->tagged_ports
= sw_r32(rtl_table_data(r
, 0));
160 v
= sw_r32(rtl_table_data(r
, 1));
161 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan
, info
->tagged_ports
, v
);
162 rtl_table_release(r
);
164 info
->profile_id
= v
& 0x7;
165 info
->hash_mc_fid
= !!(v
& 0x8);
166 info
->hash_uc_fid
= !!(v
& 0x10);
167 info
->fid
= (v
>> 5) & 0x3f;
169 // Read UNTAG table (0) via table register 1
170 r
= rtl_table_get(RTL8380_TBL_1
, 0);
171 rtl_table_read(r
, vlan
);
172 info
->untagged_ports
= sw_r32(rtl_table_data(r
, 0));
173 rtl_table_release(r
);
176 static void rtl838x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
179 // Access VLAN table (0) via register 0
180 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
182 sw_w32(info
->tagged_ports
, rtl_table_data(r
, 0));
184 v
= info
->profile_id
;
185 v
|= info
->hash_mc_fid
? 0x8 : 0;
186 v
|= info
->hash_uc_fid
? 0x10 : 0;
187 v
|= ((u32
)info
->fid
) << 5;
188 sw_w32(v
, rtl_table_data(r
, 1));
190 rtl_table_write(r
, vlan
);
191 rtl_table_release(r
);
194 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
196 // Access UNTAG table (0) via register 1
197 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 0);
199 sw_w32(portmask
& 0x1fffffff, rtl_table_data(r
, 0));
200 rtl_table_write(r
, vlan
);
201 rtl_table_release(r
);
204 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
206 static void rtl838x_vlan_fwd_on_inner(int port
, bool is_set
)
209 sw_w32_mask(BIT(port
), 0, RTL838X_VLAN_PORT_FWD
);
211 sw_w32_mask(0, BIT(port
), RTL838X_VLAN_PORT_FWD
);
214 static u64
rtl838x_l2_hash_seed(u64 mac
, u32 vid
)
216 return mac
<< 12 | vid
;
220 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
221 * and returns a key into the L2 hash table
223 static u32
rtl838x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
227 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
228 h1
= (seed
>> 11) & 0x7ff;
229 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
231 h2
= (seed
>> 33) & 0x7ff;
232 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
234 h3
= (seed
>> 44) & 0x7ff;
235 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
237 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
238 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
240 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
241 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
242 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
248 static inline int rtl838x_mac_force_mode_ctrl(int p
)
250 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
253 static inline int rtl838x_mac_port_ctrl(int p
)
255 return RTL838X_MAC_PORT_CTRL(p
);
258 static inline int rtl838x_l2_port_new_salrn(int p
)
260 return RTL838X_L2_PORT_NEW_SALRN(p
);
263 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
265 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
268 static inline int rtl838x_mac_link_spd_sts(int p
)
270 return RTL838X_MAC_LINK_SPD_STS(p
);
273 inline static int rtl838x_trk_mbr_ctr(int group
)
275 return RTL838X_TRK_MBR_CTR
+ (group
<< 2);
279 * Fills an L2 entry structure from the SoC registers
281 static void rtl838x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
283 /* Table contains different entry types, we need to identify the right one:
284 * Check for MC entries, first
285 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
286 * identify valid entries
288 e
->is_ip_mc
= !!(r
[0] & BIT(22));
289 e
->is_ipv6_mc
= !!(r
[0] & BIT(21));
290 e
->type
= L2_INVALID
;
292 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
293 e
->mac
[0] = (r
[1] >> 20);
294 e
->mac
[1] = (r
[1] >> 12);
295 e
->mac
[2] = (r
[1] >> 4);
296 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
297 e
->mac
[4] = (r
[2] >> 20);
298 e
->mac
[5] = (r
[2] >> 12);
300 e
->rvid
= r
[2] & 0xfff;
301 e
->vid
= r
[0] & 0xfff;
303 /* Is it a unicast entry? check multicast bit */
304 if (!(e
->mac
[0] & 1)) {
305 e
->is_static
= !!((r
[0] >> 19) & 1);
306 e
->port
= (r
[0] >> 12) & 0x1f;
307 e
->block_da
= !!(r
[1] & BIT(30));
308 e
->block_sa
= !!(r
[1] & BIT(31));
309 e
->suspended
= !!(r
[1] & BIT(29));
310 e
->next_hop
= !!(r
[1] & BIT(28));
312 pr_debug("Found next hop entry, need to read extra data\n");
313 e
->nh_vlan_target
= !!(r
[0] & BIT(9));
314 e
->nh_route_id
= r
[0] & 0x1ff;
317 e
->age
= (r
[0] >> 17) & 0x3;
320 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
321 * next-hop or static entry bit set */
322 if (!(r
[0] & 0x007c0000) && !(r
[1] & 0xd0000000))
325 e
->type
= L2_UNICAST
;
326 } else { // L2 multicast
327 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
329 e
->type
= L2_MULTICAST
;
330 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
332 } else { // IPv4 and IPv6 multicast
334 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
335 e
->mc_gip
= (r
[1] << 20) | (r
[2] >> 12);
336 e
->rvid
= r
[2] & 0xfff;
339 e
->type
= IP4_MULTICAST
;
341 e
->type
= IP6_MULTICAST
;
345 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
347 static void rtl838x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
349 u64 mac
= ether_addr_to_u64(e
->mac
);
352 r
[0] = r
[1] = r
[2] = 0;
356 r
[0] = e
->is_ip_mc
? BIT(22) : 0;
357 r
[0] |= e
->is_ipv6_mc
? BIT(21) : 0;
359 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
361 r
[2] = (mac
& 0xfffff) << 12;
363 /* Is it a unicast entry? check multicast bit */
364 if (!(e
->mac
[0] & 1)) {
365 r
[0] |= e
->is_static
? BIT(19) : 0;
366 r
[0] |= (e
->port
& 0x3f) << 12;
368 r
[1] |= e
->block_da
? BIT(30) : 0;
369 r
[1] |= e
->block_sa
? BIT(31) : 0;
370 r
[1] |= e
->suspended
? BIT(29) : 0;
371 r
[2] |= e
->rvid
& 0xfff;
374 r
[0] |= e
->nh_vlan_target
? BIT(9) : 0;
375 r
[0] |= e
->nh_route_id
& 0x1ff;
377 r
[0] |= (e
->age
& 0x3) << 17;
378 } else { // L2 Multicast
379 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
380 r
[2] |= e
->rvid
& 0xfff;
381 r
[0] |= e
->vid
& 0xfff;
382 pr_debug("FILL MC: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
384 } else { // IPv4 and IPv6 multicast
385 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
386 r
[1] = e
->mc_gip
>> 20;
387 r
[2] = e
->mc_gip
<< 12;
393 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
394 * hash is the id of the bucket and pos is the position of the entry in that bucket
395 * The data read from the SoC is filled into rtl838x_l2_entry
397 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
401 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0); // Access L2 Table 0
402 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
405 rtl_table_read(q
, idx
);
406 for (i
= 0; i
< 3; i
++)
407 r
[i
] = sw_r32(rtl_table_data(q
, i
));
409 rtl_table_release(q
);
411 rtl838x_fill_l2_entry(r
, e
);
415 entry
= (((u64
) r
[1]) << 32) | (r
[2]); // mac and vid concatenated as hash seed
419 static void rtl838x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
422 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0);
425 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
427 rtl838x_fill_l2_row(r
, e
);
429 for (i
= 0; i
< 3; i
++)
430 sw_w32(r
[i
], rtl_table_data(q
, i
));
432 rtl_table_write(q
, idx
);
433 rtl_table_release(q
);
436 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
440 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
443 rtl_table_read(q
, idx
);
444 for (i
= 0; i
< 3; i
++)
445 r
[i
] = sw_r32(rtl_table_data(q
, i
));
447 rtl_table_release(q
);
449 rtl838x_fill_l2_entry(r
, e
);
453 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
455 // Return MAC with concatenated VID ac concatenated ID
456 entry
= (((u64
) r
[1]) << 32) | r
[2];
460 static void rtl838x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
463 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
466 rtl838x_fill_l2_row(r
, e
);
468 for (i
= 0; i
< 3; i
++)
469 sw_w32(r
[i
], rtl_table_data(q
, i
));
471 rtl_table_write(q
, idx
);
472 rtl_table_release(q
);
475 static u64
rtl838x_read_mcast_pmask(int idx
)
478 // Read MC_PMSK (2) via register RTL8380_TBL_L2
479 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
481 rtl_table_read(q
, idx
);
482 portmask
= sw_r32(rtl_table_data(q
, 0));
483 rtl_table_release(q
);
488 static void rtl838x_write_mcast_pmask(int idx
, u64 portmask
)
490 // Access MC_PMSK (2) via register RTL8380_TBL_L2
491 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
493 sw_w32(((u32
)portmask
) & 0x1fffffff, rtl_table_data(q
, 0));
494 rtl_table_write(q
, idx
);
495 rtl_table_release(q
);
498 static void rtl838x_vlan_profile_setup(int profile
)
500 u32 pmask_id
= UNKNOWN_MC_PMASK
;
501 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
502 u32 p
= 1 | pmask_id
<< 1 | pmask_id
<< 10 | pmask_id
<< 19;
504 sw_w32(p
, RTL838X_VLAN_PROFILE(profile
));
506 /* RTL8380 and RTL8390 use an index into the portmask table to set the
507 * unknown multicast portmask, setup a default at a safe location
508 * On RTL93XX, the portmask is directly set in the profile,
509 * see e.g. rtl9300_vlan_profile_setup
511 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x1fffffff);
514 static void rtl838x_l2_learning_setup(void)
516 /* Set portmask for broadcast traffic and unknown unicast address flooding
517 * to the reserved entry in the portmask table used also for
518 * multicast flooding */
519 sw_w32(UNKNOWN_MC_PMASK
<< 12 | UNKNOWN_MC_PMASK
, RTL838X_L2_FLD_PMSK
);
521 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
522 * and per vlan (bit 2) */
523 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN
);
525 // Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
526 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT
);
528 // Do not trap ARP packets to CPU_PORT
529 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL
);
532 static void rtl838x_enable_learning(int port
, bool enable
)
534 // Limit learning to maximum: 16k entries
536 sw_w32_mask(0x3fff << 2, enable
? (0x3fff << 2) : 0,
537 RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
540 static void rtl838x_enable_flood(int port
, bool enable
)
548 sw_w32_mask(0x3, enable
? 0 : 1,
549 RTL838X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
552 static void rtl838x_enable_mcast_flood(int port
, bool enable
)
557 static void rtl838x_enable_bcast_flood(int port
, bool enable
)
562 static void rtl838x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
565 u32 cmd
= 1 << 15 /* Execute cmd */
567 | 2 << 12 /* Table type 0b10 */
569 priv
->r
->exec_tbl0_cmd(cmd
);
571 for (i
= 0; i
< 2; i
++)
572 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
575 static void rtl838x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
578 u32 cmd
= 1 << 15 /* Execute cmd */
579 | 0 << 14 /* Write */
580 | 2 << 12 /* Table type 0b10 */
583 for (i
= 0; i
< 2; i
++)
584 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
585 priv
->r
->exec_tbl0_cmd(cmd
);
588 u64
rtl838x_traffic_get(int source
)
590 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source
));
593 void rtl838x_traffic_set(int source
, u64 dest_matrix
)
595 rtl838x_set_port_reg(dest_matrix
, rtl838x_port_iso_ctrl(source
));
598 void rtl838x_traffic_enable(int source
, int dest
)
600 rtl838x_mask_port_reg(0, BIT(dest
), rtl838x_port_iso_ctrl(source
));
603 void rtl838x_traffic_disable(int source
, int dest
)
605 rtl838x_mask_port_reg(BIT(dest
), 0, rtl838x_port_iso_ctrl(source
));
609 * Enables or disables the EEE/EEEP capability of a port
611 static void rtl838x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
615 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
619 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
620 v
= enable
? 0x3 : 0x0;
622 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
623 sw_w32_mask(0x3 << 9, v
<< 9, priv
->r
->mac_force_mode_ctrl(port
));
625 // Set TX/RX EEE state
627 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_TX_EN
);
628 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_RX_EN
);
630 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_TX_EN
);
631 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_RX_EN
);
633 priv
->ports
[port
].eee_enabled
= enable
;
638 * Get EEE own capabilities and negotiation result
640 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv
*priv
,
641 struct ethtool_eee
*e
, int port
)
648 link
= rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS
);
649 if (!(link
& BIT(port
)))
652 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(9))
653 e
->advertised
|= ADVERTISED_100baseT_Full
;
655 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(10))
656 e
->advertised
|= ADVERTISED_1000baseT_Full
;
658 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & BIT(port
)) {
659 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
660 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
667 static void rtl838x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
671 pr_info("Setting up EEE, state: %d\n", enable
);
672 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
674 /* Set timers for EEE */
675 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
676 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
678 // Enable EEE MAC support on ports
679 for (i
= 0; i
< priv
->cpu_port
; i
++) {
680 if (priv
->ports
[i
].phy
)
681 rtl838x_port_eee_set(priv
, i
, enable
);
683 priv
->eee_enabled
= enable
;
686 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
688 int block
= index
/ PIE_BLOCK_SIZE
;
689 u32 block_state
= sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL
);
691 // Make sure rule-lookup is enabled in the block
692 if (!(block_state
& BIT(block
)))
693 sw_w32(block_state
| BIT(block
), RTL838X_ACL_BLK_LOOKUP_CTRL
);
696 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
698 int block_from
= index_from
/ PIE_BLOCK_SIZE
;
699 int block_to
= index_to
/ PIE_BLOCK_SIZE
;
700 u32 v
= (index_from
<< 1)| (index_to
<< 12 ) | BIT(0);
704 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
705 mutex_lock(&priv
->reg_mutex
);
707 // Remember currently active blocks
708 block_state
= sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL
);
710 // Make sure rule-lookup is disabled in the relevant blocks
711 for (block
= block_from
; block
<= block_to
; block
++) {
712 if (block_state
& BIT(block
))
713 sw_w32(block_state
& (~BIT(block
)), RTL838X_ACL_BLK_LOOKUP_CTRL
);
716 // Write from-to and execute bit into control register
717 sw_w32(v
, RTL838X_ACL_CLR_CTRL
);
719 // Wait until command has completed
721 } while (sw_r32(RTL838X_ACL_CLR_CTRL
) & BIT(0));
723 // Re-enable rule lookup
724 for (block
= block_from
; block
<= block_to
; block
++) {
725 if (!(block_state
& BIT(block
)))
726 sw_w32(block_state
| BIT(block
), RTL838X_ACL_BLK_LOOKUP_CTRL
);
729 mutex_unlock(&priv
->reg_mutex
);
733 * Reads the intermediate representation of the templated match-fields of the
734 * PIE rule in the pie_rule structure and fills in the raw data fields in the
735 * raw register space r[].
736 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
737 * however the RTL9310 has 2 more registers / fields and the physical field-ids
738 * are specific to every platform.
740 static void rtl838x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
743 enum template_field_id field_type
;
746 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
750 switch (field_type
) {
751 case TEMPLATE_FIELD_SPM0
:
755 case TEMPLATE_FIELD_SPM1
:
756 data
= pr
->spm
>> 16;
757 data_m
= pr
->spm_m
>> 16;
759 case TEMPLATE_FIELD_OTAG
:
763 case TEMPLATE_FIELD_SMAC0
:
765 data
= (data
<< 8) | pr
->smac
[5];
766 data_m
= pr
->smac_m
[4];
767 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
769 case TEMPLATE_FIELD_SMAC1
:
771 data
= (data
<< 8) | pr
->smac
[3];
772 data_m
= pr
->smac_m
[2];
773 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
775 case TEMPLATE_FIELD_SMAC2
:
777 data
= (data
<< 8) | pr
->smac
[1];
778 data_m
= pr
->smac_m
[0];
779 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
781 case TEMPLATE_FIELD_DMAC0
:
783 data
= (data
<< 8) | pr
->dmac
[5];
784 data_m
= pr
->dmac_m
[4];
785 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
787 case TEMPLATE_FIELD_DMAC1
:
789 data
= (data
<< 8) | pr
->dmac
[3];
790 data_m
= pr
->dmac_m
[2];
791 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
793 case TEMPLATE_FIELD_DMAC2
:
795 data
= (data
<< 8) | pr
->dmac
[1];
796 data_m
= pr
->dmac_m
[0];
797 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
799 case TEMPLATE_FIELD_ETHERTYPE
:
800 data
= pr
->ethertype
;
801 data_m
= pr
->ethertype_m
;
803 case TEMPLATE_FIELD_ITAG
:
807 case TEMPLATE_FIELD_RANGE_CHK
:
808 data
= pr
->field_range_check
;
809 data_m
= pr
->field_range_check_m
;
811 case TEMPLATE_FIELD_SIP0
:
813 data
= pr
->sip6
.s6_addr16
[7];
814 data_m
= pr
->sip6_m
.s6_addr16
[7];
820 case TEMPLATE_FIELD_SIP1
:
822 data
= pr
->sip6
.s6_addr16
[6];
823 data_m
= pr
->sip6_m
.s6_addr16
[6];
825 data
= pr
->sip
>> 16;
826 data_m
= pr
->sip_m
>> 16;
830 case TEMPLATE_FIELD_SIP2
:
831 case TEMPLATE_FIELD_SIP3
:
832 case TEMPLATE_FIELD_SIP4
:
833 case TEMPLATE_FIELD_SIP5
:
834 case TEMPLATE_FIELD_SIP6
:
835 case TEMPLATE_FIELD_SIP7
:
836 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
837 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
840 case TEMPLATE_FIELD_DIP0
:
842 data
= pr
->dip6
.s6_addr16
[7];
843 data_m
= pr
->dip6_m
.s6_addr16
[7];
850 case TEMPLATE_FIELD_DIP1
:
852 data
= pr
->dip6
.s6_addr16
[6];
853 data_m
= pr
->dip6_m
.s6_addr16
[6];
855 data
= pr
->dip
>> 16;
856 data_m
= pr
->dip_m
>> 16;
860 case TEMPLATE_FIELD_DIP2
:
861 case TEMPLATE_FIELD_DIP3
:
862 case TEMPLATE_FIELD_DIP4
:
863 case TEMPLATE_FIELD_DIP5
:
864 case TEMPLATE_FIELD_DIP6
:
865 case TEMPLATE_FIELD_DIP7
:
866 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
867 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
870 case TEMPLATE_FIELD_IP_TOS_PROTO
:
871 data
= pr
->tos_proto
;
872 data_m
= pr
->tos_proto_m
;
874 case TEMPLATE_FIELD_L4_SPORT
:
876 data_m
= pr
->sport_m
;
878 case TEMPLATE_FIELD_L4_DPORT
:
880 data_m
= pr
->dport_m
;
882 case TEMPLATE_FIELD_ICMP_IGMP
:
883 data
= pr
->icmp_igmp
;
884 data_m
= pr
->icmp_igmp_m
;
887 pr_info("%s: unknown field %d\n", __func__
, field_type
);
892 r
[12 - i
/ 2] = data_m
;
894 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
895 r
[12 - i
/ 2] |= ((u32
)data_m
) << 16;
901 * Creates the intermediate representation of the templated match-fields of the
902 * PIE rule in the pie_rule structure by reading the raw data fields in the
903 * raw register space r[].
904 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
905 * however the RTL9310 has 2 more registers / fields and the physical field-ids
907 static void rtl838x_read_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
910 enum template_field_id field_type
;
913 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
917 data_m
= r
[12 - i
/ 2];
919 data
= r
[5 - i
/ 2] >> 16;
920 data_m
= r
[12 - i
/ 2] >> 16;
923 switch (field_type
) {
924 case TEMPLATE_FIELD_SPM0
:
925 pr
->spm
= (pr
->spn
<< 16) | data
;
926 pr
->spm_m
= (pr
->spn
<< 16) | data_m
;
928 case TEMPLATE_FIELD_SPM1
:
932 case TEMPLATE_FIELD_OTAG
:
936 case TEMPLATE_FIELD_SMAC0
:
937 pr
->smac
[4] = data
>> 8;
939 pr
->smac_m
[4] = data
>> 8;
940 pr
->smac_m
[5] = data
;
942 case TEMPLATE_FIELD_SMAC1
:
943 pr
->smac
[2] = data
>> 8;
945 pr
->smac_m
[2] = data
>> 8;
946 pr
->smac_m
[3] = data
;
948 case TEMPLATE_FIELD_SMAC2
:
949 pr
->smac
[0] = data
>> 8;
951 pr
->smac_m
[0] = data
>> 8;
952 pr
->smac_m
[1] = data
;
954 case TEMPLATE_FIELD_DMAC0
:
955 pr
->dmac
[4] = data
>> 8;
957 pr
->dmac_m
[4] = data
>> 8;
958 pr
->dmac_m
[5] = data
;
960 case TEMPLATE_FIELD_DMAC1
:
961 pr
->dmac
[2] = data
>> 8;
963 pr
->dmac_m
[2] = data
>> 8;
964 pr
->dmac_m
[3] = data
;
966 case TEMPLATE_FIELD_DMAC2
:
967 pr
->dmac
[0] = data
>> 8;
969 pr
->dmac_m
[0] = data
>> 8;
970 pr
->dmac_m
[1] = data
;
972 case TEMPLATE_FIELD_ETHERTYPE
:
973 pr
->ethertype
= data
;
974 pr
->ethertype_m
= data_m
;
976 case TEMPLATE_FIELD_ITAG
:
980 case TEMPLATE_FIELD_RANGE_CHK
:
981 pr
->field_range_check
= data
;
982 pr
->field_range_check_m
= data_m
;
984 case TEMPLATE_FIELD_SIP0
:
988 case TEMPLATE_FIELD_SIP1
:
989 pr
->sip
= (pr
->sip
<< 16) | data
;
990 pr
->sip_m
= (pr
->sip
<< 16) | data_m
;
992 case TEMPLATE_FIELD_SIP2
:
994 // Make use of limitiations on the position of the match values
995 ipv6_addr_set(&pr
->sip6
, pr
->sip
, r
[5 - i
/ 2],
996 r
[4 - i
/ 2], r
[3 - i
/ 2]);
997 ipv6_addr_set(&pr
->sip6_m
, pr
->sip_m
, r
[5 - i
/ 2],
998 r
[4 - i
/ 2], r
[3 - i
/ 2]);
999 case TEMPLATE_FIELD_SIP3
:
1000 case TEMPLATE_FIELD_SIP4
:
1001 case TEMPLATE_FIELD_SIP5
:
1002 case TEMPLATE_FIELD_SIP6
:
1003 case TEMPLATE_FIELD_SIP7
:
1006 case TEMPLATE_FIELD_DIP0
:
1010 case TEMPLATE_FIELD_DIP1
:
1011 pr
->dip
= (pr
->dip
<< 16) | data
;
1012 pr
->dip_m
= (pr
->dip
<< 16) | data_m
;
1014 case TEMPLATE_FIELD_DIP2
:
1016 ipv6_addr_set(&pr
->dip6
, pr
->dip
, r
[5 - i
/ 2],
1017 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1018 ipv6_addr_set(&pr
->dip6_m
, pr
->dip_m
, r
[5 - i
/ 2],
1019 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1020 case TEMPLATE_FIELD_DIP3
:
1021 case TEMPLATE_FIELD_DIP4
:
1022 case TEMPLATE_FIELD_DIP5
:
1023 case TEMPLATE_FIELD_DIP6
:
1024 case TEMPLATE_FIELD_DIP7
:
1026 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1027 pr
->tos_proto
= data
;
1028 pr
->tos_proto_m
= data_m
;
1030 case TEMPLATE_FIELD_L4_SPORT
:
1032 pr
->sport_m
= data_m
;
1034 case TEMPLATE_FIELD_L4_DPORT
:
1036 pr
->dport_m
= data_m
;
1038 case TEMPLATE_FIELD_ICMP_IGMP
:
1039 pr
->icmp_igmp
= data
;
1040 pr
->icmp_igmp_m
= data_m
;
1043 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1048 static void rtl838x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1050 pr
->spmmask_fix
= (r
[6] >> 22) & 0x3;
1051 pr
->spn
= (r
[6] >> 16) & 0x3f;
1052 pr
->mgnt_vlan
= (r
[6] >> 15) & 1;
1053 pr
->dmac_hit_sw
= (r
[6] >> 14) & 1;
1054 pr
->not_first_frag
= (r
[6] >> 13) & 1;
1055 pr
->frame_type_l4
= (r
[6] >> 10) & 7;
1056 pr
->frame_type
= (r
[6] >> 8) & 3;
1057 pr
->otag_fmt
= (r
[6] >> 7) & 1;
1058 pr
->itag_fmt
= (r
[6] >> 6) & 1;
1059 pr
->otag_exist
= (r
[6] >> 5) & 1;
1060 pr
->itag_exist
= (r
[6] >> 4) & 1;
1061 pr
->frame_type_l2
= (r
[6] >> 2) & 3;
1064 pr
->spmmask_fix_m
= (r
[13] >> 22) & 0x3;
1065 pr
->spn_m
= (r
[13] >> 16) & 0x3f;
1066 pr
->mgnt_vlan_m
= (r
[13] >> 15) & 1;
1067 pr
->dmac_hit_sw_m
= (r
[13] >> 14) & 1;
1068 pr
->not_first_frag_m
= (r
[13] >> 13) & 1;
1069 pr
->frame_type_l4_m
= (r
[13] >> 10) & 7;
1070 pr
->frame_type_m
= (r
[13] >> 8) & 3;
1071 pr
->otag_fmt_m
= (r
[13] >> 7) & 1;
1072 pr
->itag_fmt_m
= (r
[13] >> 6) & 1;
1073 pr
->otag_exist_m
= (r
[13] >> 5) & 1;
1074 pr
->itag_exist_m
= (r
[13] >> 4) & 1;
1075 pr
->frame_type_l2_m
= (r
[13] >> 2) & 3;
1076 pr
->tid_m
= r
[13] & 3;
1078 pr
->valid
= r
[14] & BIT(31);
1079 pr
->cond_not
= r
[14] & BIT(30);
1080 pr
->cond_and1
= r
[14] & BIT(29);
1081 pr
->cond_and2
= r
[14] & BIT(28);
1082 pr
->ivalid
= r
[14] & BIT(27);
1084 pr
->drop
= (r
[17] >> 14) & 3;
1085 pr
->fwd_sel
= r
[17] & BIT(13);
1086 pr
->ovid_sel
= r
[17] & BIT(12);
1087 pr
->ivid_sel
= r
[17] & BIT(11);
1088 pr
->flt_sel
= r
[17] & BIT(10);
1089 pr
->log_sel
= r
[17] & BIT(9);
1090 pr
->rmk_sel
= r
[17] & BIT(8);
1091 pr
->meter_sel
= r
[17] & BIT(7);
1092 pr
->tagst_sel
= r
[17] & BIT(6);
1093 pr
->mir_sel
= r
[17] & BIT(5);
1094 pr
->nopri_sel
= r
[17] & BIT(4);
1095 pr
->cpupri_sel
= r
[17] & BIT(3);
1096 pr
->otpid_sel
= r
[17] & BIT(2);
1097 pr
->itpid_sel
= r
[17] & BIT(1);
1098 pr
->shaper_sel
= r
[17] & BIT(0);
1101 static void rtl838x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1103 r
[6] = ((u32
) (pr
->spmmask_fix
& 0x3)) << 22;
1104 r
[6] |= ((u32
) (pr
->spn
& 0x3f)) << 16;
1105 r
[6] |= pr
->mgnt_vlan
? BIT(15) : 0;
1106 r
[6] |= pr
->dmac_hit_sw
? BIT(14) : 0;
1107 r
[6] |= pr
->not_first_frag
? BIT(13) : 0;
1108 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 10;
1109 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 8;
1110 r
[6] |= pr
->otag_fmt
? BIT(7) : 0;
1111 r
[6] |= pr
->itag_fmt
? BIT(6) : 0;
1112 r
[6] |= pr
->otag_exist
? BIT(5) : 0;
1113 r
[6] |= pr
->itag_exist
? BIT(4) : 0;
1114 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 2;
1115 r
[6] |= ((u32
) (pr
->tid
& 0x3));
1117 r
[13] = ((u32
) (pr
->spmmask_fix_m
& 0x3)) << 22;
1118 r
[13] |= ((u32
) (pr
->spn_m
& 0x3f)) << 16;
1119 r
[13] |= pr
->mgnt_vlan_m
? BIT(15) : 0;
1120 r
[13] |= pr
->dmac_hit_sw_m
? BIT(14) : 0;
1121 r
[13] |= pr
->not_first_frag_m
? BIT(13) : 0;
1122 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 10;
1123 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 8;
1124 r
[13] |= pr
->otag_fmt_m
? BIT(7) : 0;
1125 r
[13] |= pr
->itag_fmt_m
? BIT(6) : 0;
1126 r
[13] |= pr
->otag_exist_m
? BIT(5) : 0;
1127 r
[13] |= pr
->itag_exist_m
? BIT(4) : 0;
1128 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 2;
1129 r
[13] |= ((u32
) (pr
->tid_m
& 0x3));
1131 r
[14] = pr
->valid
? BIT(31) : 0;
1132 r
[14] |= pr
->cond_not
? BIT(30) : 0;
1133 r
[14] |= pr
->cond_and1
? BIT(29) : 0;
1134 r
[14] |= pr
->cond_and2
? BIT(28) : 0;
1135 r
[14] |= pr
->ivalid
? BIT(27) : 0;
1138 r
[17] = 0x1 << 14; // Standard drop action
1141 r
[17] |= pr
->fwd_sel
? BIT(13) : 0;
1142 r
[17] |= pr
->ovid_sel
? BIT(12) : 0;
1143 r
[17] |= pr
->ivid_sel
? BIT(11) : 0;
1144 r
[17] |= pr
->flt_sel
? BIT(10) : 0;
1145 r
[17] |= pr
->log_sel
? BIT(9) : 0;
1146 r
[17] |= pr
->rmk_sel
? BIT(8) : 0;
1147 r
[17] |= pr
->meter_sel
? BIT(7) : 0;
1148 r
[17] |= pr
->tagst_sel
? BIT(6) : 0;
1149 r
[17] |= pr
->mir_sel
? BIT(5) : 0;
1150 r
[17] |= pr
->nopri_sel
? BIT(4) : 0;
1151 r
[17] |= pr
->cpupri_sel
? BIT(3) : 0;
1152 r
[17] |= pr
->otpid_sel
? BIT(2) : 0;
1153 r
[17] |= pr
->itpid_sel
? BIT(1) : 0;
1154 r
[17] |= pr
->shaper_sel
? BIT(0) : 0;
1157 static int rtl838x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1159 u16
*aif
= (u16
*)&r
[17];
1161 int fields_used
= 0;
1165 pr_debug("%s, at %08x\n", __func__
, (u32
)aif
);
1166 /* Multiple actions can be linked to a match of a PIE rule,
1167 * they have different precedence depending on their type and this precedence
1168 * defines which Action Information Field (0-4) in the IACL table stores
1169 * the additional data of the action (like e.g. the port number a packet is
1171 // TODO: count bits in selectors to limit to a maximum number of actions
1172 if (pr
->fwd_sel
) { // Forwarding action
1173 data
= pr
->fwd_act
<< 13;
1174 data
|= pr
->fwd_data
;
1175 data
|= pr
->bypass_all
? BIT(12) : 0;
1176 data
|= pr
->bypass_ibc_sc
? BIT(11) : 0;
1177 data
|= pr
->bypass_igr_stp
? BIT(10) : 0;
1182 if (pr
->ovid_sel
) { // Outer VID action
1183 data
= (pr
->ovid_act
& 0x3) << 12;
1184 data
|= pr
->ovid_data
;
1189 if (pr
->ivid_sel
) { // Inner VID action
1190 data
= (pr
->ivid_act
& 0x3) << 12;
1191 data
|= pr
->ivid_data
;
1196 if (pr
->flt_sel
) { // Filter action
1197 *aif
-- = pr
->flt_data
;
1201 if (pr
->log_sel
) { // Log action
1202 if (fields_used
>= 4)
1204 *aif
-- = pr
->log_data
;
1208 if (pr
->rmk_sel
) { // Remark action
1209 if (fields_used
>= 4)
1211 *aif
-- = pr
->rmk_data
;
1215 if (pr
->meter_sel
) { // Meter action
1216 if (fields_used
>= 4)
1218 *aif
-- = pr
->meter_data
;
1222 if (pr
->tagst_sel
) { // Egress Tag Status action
1223 if (fields_used
>= 4)
1225 *aif
-- = pr
->tagst_data
;
1229 if (pr
->mir_sel
) { // Mirror action
1230 if (fields_used
>= 4)
1232 *aif
-- = pr
->mir_data
;
1236 if (pr
->nopri_sel
) { // Normal Priority action
1237 if (fields_used
>= 4)
1239 *aif
-- = pr
->nopri_data
;
1243 if (pr
->cpupri_sel
) { // CPU Priority action
1244 if (fields_used
>= 4)
1246 *aif
-- = pr
->nopri_data
;
1250 if (pr
->otpid_sel
) { // OTPID action
1251 if (fields_used
>= 4)
1253 *aif
-- = pr
->otpid_data
;
1257 if (pr
->itpid_sel
) { // ITPID action
1258 if (fields_used
>= 4)
1260 *aif
-- = pr
->itpid_data
;
1264 if (pr
->shaper_sel
) { // Traffic shaper action
1265 if (fields_used
>= 4)
1267 *aif
-- = pr
->shaper_data
;
1274 static void rtl838x_read_pie_action(u32 r
[], struct pie_rule
*pr
)
1276 u16
*aif
= (u16
*)&r
[17];
1280 pr_debug("%s, at %08x\n", __func__
, (u32
)aif
);
1282 pr_debug("%s: Action Drop: %d", __func__
, pr
->drop
);
1284 if (pr
->fwd_sel
){ // Forwarding action
1285 pr
->fwd_act
= *aif
>> 13;
1286 pr
->fwd_data
= *aif
--;
1287 pr
->bypass_all
= pr
->fwd_data
& BIT(12);
1288 pr
->bypass_ibc_sc
= pr
->fwd_data
& BIT(11);
1289 pr
->bypass_igr_stp
= pr
->fwd_data
& BIT(10);
1290 if (pr
->bypass_all
|| pr
->bypass_ibc_sc
|| pr
->bypass_igr_stp
)
1291 pr
->bypass_sel
= true;
1293 if (pr
->ovid_sel
) // Outer VID action
1294 pr
->ovid_data
= *aif
--;
1295 if (pr
->ivid_sel
) // Inner VID action
1296 pr
->ivid_data
= *aif
--;
1297 if (pr
->flt_sel
) // Filter action
1298 pr
->flt_data
= *aif
--;
1299 if (pr
->log_sel
) // Log action
1300 pr
->log_data
= *aif
--;
1301 if (pr
->rmk_sel
) // Remark action
1302 pr
->rmk_data
= *aif
--;
1303 if (pr
->meter_sel
) // Meter action
1304 pr
->meter_data
= *aif
--;
1305 if (pr
->tagst_sel
) // Egress Tag Status action
1306 pr
->tagst_data
= *aif
--;
1307 if (pr
->mir_sel
) // Mirror action
1308 pr
->mir_data
= *aif
--;
1309 if (pr
->nopri_sel
) // Normal Priority action
1310 pr
->nopri_data
= *aif
--;
1311 if (pr
->cpupri_sel
) // CPU Priority action
1312 pr
->nopri_data
= *aif
--;
1313 if (pr
->otpid_sel
) // OTPID action
1314 pr
->otpid_data
= *aif
--;
1315 if (pr
->itpid_sel
) // ITPID action
1316 pr
->itpid_data
= *aif
--;
1317 if (pr
->shaper_sel
) // Traffic shaper action
1318 pr
->shaper_data
= *aif
--;
1321 static void rtl838x_pie_rule_dump_raw(u32 r
[])
1323 pr_info("Raw IACL table entry:\n");
1324 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1325 pr_info("Fixed : %08x\n", r
[6]);
1326 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r
[7], r
[8], r
[9], r
[10], r
[11], r
[12]);
1327 pr_info("Fixed M: %08x\n", r
[13]);
1328 pr_info("AIF : %08x %08x %08x\n", r
[14], r
[15], r
[16]);
1329 pr_info("Sel : %08x\n", r
[17]);
1332 static void rtl838x_pie_rule_dump(struct pie_rule
*pr
)
1334 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1335 pr
->drop
, pr
->fwd_sel
, pr
->ovid_sel
, pr
->ivid_sel
, pr
->flt_sel
, pr
->log_sel
, pr
->rmk_sel
, pr
->log_sel
, pr
->tagst_sel
, pr
->mir_sel
, pr
->nopri_sel
,
1336 pr
->cpupri_sel
, pr
->otpid_sel
, pr
->itpid_sel
, pr
->shaper_sel
);
1338 pr_info("FWD: %08x\n", pr
->fwd_data
);
1339 pr_info("TID: %x, %x\n", pr
->tid
, pr
->tid_m
);
1342 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1344 // Read IACL table (1) via register 0
1345 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 1);
1348 int block
= idx
/ PIE_BLOCK_SIZE
;
1349 u32 t_select
= sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
));
1351 memset(pr
, 0, sizeof(*pr
));
1352 rtl_table_read(q
, idx
);
1353 for (i
= 0; i
< 18; i
++)
1354 r
[i
] = sw_r32(rtl_table_data(q
, i
));
1356 rtl_table_release(q
);
1358 rtl838x_read_pie_fixed_fields(r
, pr
);
1362 pr_info("%s: template_selectors %08x, tid: %d\n", __func__
, t_select
, pr
->tid
);
1363 rtl838x_pie_rule_dump_raw(r
);
1365 rtl838x_read_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1367 rtl838x_read_pie_action(r
, pr
);
1372 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1374 // Access IACL table (1) via register 0
1375 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 1);
1378 int block
= idx
/ PIE_BLOCK_SIZE
;
1379 u32 t_select
= sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
));
1381 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1383 for (i
= 0; i
< 18; i
++)
1389 rtl838x_write_pie_fixed_fields(r
, pr
);
1391 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 3)) & 0x7);
1392 rtl838x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1394 if (rtl838x_write_pie_action(r
, pr
)) {
1395 pr_err("Rule actions too complex\n");
1399 // rtl838x_pie_rule_dump_raw(r);
1401 for (i
= 0; i
< 18; i
++)
1402 sw_w32(r
[i
], rtl_table_data(q
, i
));
1405 rtl_table_write(q
, idx
);
1406 rtl_table_release(q
);
1411 static bool rtl838x_pie_templ_has(int t
, enum template_field_id field_type
)
1414 enum template_field_id ft
;
1416 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1417 ft
= fixed_templates
[t
][i
];
1418 if (field_type
== ft
)
1425 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1426 struct pie_rule
*pr
, int t
, int block
)
1430 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1433 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1437 if ((pr
->sip6_m
.s6_addr32
[0] || pr
->sip6_m
.s6_addr32
[1]
1438 || pr
->sip6_m
.s6_addr32
[2] || pr
->sip6_m
.s6_addr32
[3])
1439 && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1441 if ((pr
->dip6_m
.s6_addr32
[0] || pr
->dip6_m
.s6_addr32
[1]
1442 || pr
->dip6_m
.s6_addr32
[2] || pr
->dip6_m
.s6_addr32
[3])
1443 && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1447 if (ether_addr_to_u64(pr
->smac
) && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1450 if (ether_addr_to_u64(pr
->dmac
) && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1455 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1457 if (i
>= PIE_BLOCK_SIZE
)
1460 return i
+ PIE_BLOCK_SIZE
* block
;
1463 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1465 int idx
, block
, j
, t
;
1467 pr_debug("In %s\n", __func__
);
1469 mutex_lock(&priv
->pie_mutex
);
1471 for (block
= 0; block
< priv
->n_pie_blocks
; block
++) {
1472 for (j
= 0; j
< 3; j
++) {
1473 t
= (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
)) >> (j
* 3)) & 0x7;
1474 pr_debug("Testing block %d, template %d, template id %d\n", block
, j
, t
);
1475 idx
= rtl838x_pie_verify_template(priv
, pr
, t
, block
);
1483 if (block
>= priv
->n_pie_blocks
) {
1484 mutex_unlock(&priv
->pie_mutex
);
1488 pr_debug("Using block: %d, index %d, template-id %d\n", block
, idx
, j
);
1489 set_bit(idx
, priv
->pie_use_bm
);
1492 pr
->tid
= j
; // Mapped to template number
1496 rtl838x_pie_lookup_enable(priv
, idx
);
1497 rtl838x_pie_rule_write(priv
, idx
, pr
);
1499 mutex_unlock(&priv
->pie_mutex
);
1503 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1507 rtl838x_pie_rule_del(priv
, idx
, idx
);
1508 clear_bit(idx
, priv
->pie_use_bm
);
1512 * Initializes the Packet Inspection Engine:
1513 * powers it up, enables default matching templates for all blocks
1514 * and clears all rules possibly installed by u-boot
1516 static void rtl838x_pie_init(struct rtl838x_switch_priv
*priv
)
1519 u32 template_selectors
;
1521 mutex_init(&priv
->pie_mutex
);
1523 // Enable ACL lookup on all ports, including CPU_PORT
1524 for (i
= 0; i
<= priv
->cpu_port
; i
++)
1525 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i
));
1527 // Power on all PIE blocks
1528 for (i
= 0; i
< priv
->n_pie_blocks
; i
++)
1529 sw_w32_mask(0, BIT(i
), RTL838X_ACL_BLK_PWR_CTRL
);
1531 // Include IPG in metering
1532 sw_w32(1, RTL838X_METER_GLB_CTRL
);
1534 // Delete all present rules
1535 rtl838x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* PIE_BLOCK_SIZE
- 1);
1537 // Routing bypasses source port filter: disable write-protection, first
1538 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL
);
1539 sw_w32_mask(0, 1, RTL838X_DMY_REG27
);
1540 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL
);
1542 // Enable predefined templates 0, 1 and 2 for even blocks
1543 template_selectors
= 0 | (1 << 3) | (2 << 6);
1544 for (i
= 0; i
< 6; i
+= 2)
1545 sw_w32(template_selectors
, RTL838X_ACL_BLK_TMPLTE_CTRL(i
));
1547 // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
1548 template_selectors
= 0 | (3 << 3) | (4 << 6);
1549 for (i
= 1; i
< priv
->n_pie_blocks
; i
+= 2)
1550 sw_w32(template_selectors
, RTL838X_ACL_BLK_TMPLTE_CTRL(i
));
1552 // Group each pair of physical blocks together to a logical block
1553 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL
);
1556 static u32
rtl838x_packet_cntr_read(int counter
)
1560 // Read LOG table (3) via register RTL8380_TBL_0
1561 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 3);
1563 pr_debug("In %s, id %d\n", __func__
, counter
);
1564 rtl_table_read(r
, counter
/ 2);
1566 pr_debug("Registers: %08x %08x\n",
1567 sw_r32(rtl_table_data(r
, 0)), sw_r32(rtl_table_data(r
, 1)));
1568 // The table has a size of 2 registers
1570 v
= sw_r32(rtl_table_data(r
, 0));
1572 v
= sw_r32(rtl_table_data(r
, 1));
1574 rtl_table_release(r
);
1579 static void rtl838x_packet_cntr_clear(int counter
)
1581 // Access LOG table (3) via register RTL8380_TBL_0
1582 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 3);
1584 pr_debug("In %s, id %d\n", __func__
, counter
);
1585 // The table has a size of 2 registers
1587 sw_w32(0, rtl_table_data(r
, 0));
1589 sw_w32(0, rtl_table_data(r
, 1));
1591 rtl_table_write(r
, counter
/ 2);
1593 rtl_table_release(r
);
1596 static void rtl838x_route_read(int idx
, struct rtl83xx_route
*rt
)
1598 // Read ROUTING table (2) via register RTL8380_TBL_1
1599 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 2);
1601 pr_debug("In %s, id %d\n", __func__
, idx
);
1602 rtl_table_read(r
, idx
);
1604 // The table has a size of 2 registers
1605 rt
->nh
.gw
= sw_r32(rtl_table_data(r
, 0));
1607 rt
->nh
.gw
|= sw_r32(rtl_table_data(r
, 1));
1609 rtl_table_release(r
);
1612 static void rtl838x_route_write(int idx
, struct rtl83xx_route
*rt
)
1614 // Access ROUTING table (2) via register RTL8380_TBL_1
1615 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 2);
1617 pr_debug("In %s, id %d, gw: %016llx\n", __func__
, idx
, rt
->nh
.gw
);
1618 sw_w32(rt
->nh
.gw
>> 32, rtl_table_data(r
, 0));
1619 sw_w32(rt
->nh
.gw
, rtl_table_data(r
, 1));
1620 rtl_table_write(r
, idx
);
1622 rtl_table_release(r
);
1625 static int rtl838x_l3_setup(struct rtl838x_switch_priv
*priv
)
1627 // Nothing to be done
1631 void rtl838x_vlan_port_keep_tag_set(int port
, bool keep_outer
, bool keep_inner
)
1633 sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK
,
1634 keep_outer
? RTL838X_VLAN_PORT_TAG_STS_TAGGED
: RTL838X_VLAN_PORT_TAG_STS_UNTAG
) |
1635 FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK
,
1636 keep_inner
? RTL838X_VLAN_PORT_TAG_STS_TAGGED
: RTL838X_VLAN_PORT_TAG_STS_UNTAG
),
1637 RTL838X_VLAN_PORT_TAG_STS_CTRL(port
));
1640 void rtl838x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
1642 if (type
== PBVLAN_TYPE_INNER
)
1643 sw_w32_mask(0x3, mode
, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1645 sw_w32_mask(0x3 << 14, mode
<< 14, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1648 void rtl838x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
1650 if (type
== PBVLAN_TYPE_INNER
)
1651 sw_w32_mask(0xfff << 2, pvid
<< 2, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1653 sw_w32_mask(0xfff << 16, pvid
<< 16, RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1656 static int rtl838x_set_ageing_time(unsigned long msec
)
1658 int t
= sw_r32(RTL838X_L2_CTRL_1
);
1661 t
= t
* 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1662 pr_debug("L2 AGING time: %d sec\n", t
);
1664 t
= (msec
* 625 + 127000) / 128000;
1665 t
= t
> 0x7FFFFF ? 0x7FFFFF : t
;
1666 sw_w32_mask(0x7FFFFF, t
, RTL838X_L2_CTRL_1
);
1667 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT
));
1672 static void rtl838x_set_igr_filter(int port
, enum igr_filter state
)
1674 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
1675 RTL838X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
1678 static void rtl838x_set_egr_filter(int port
, enum egr_filter state
)
1680 sw_w32_mask(0x1 << (port
% 0x1d), state
<< (port
% 0x1d),
1681 RTL838X_VLAN_PORT_EGR_FLTR
+ (((port
/ 29) << 2)));
1684 void rtl838x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
1686 algoidx
&= 1; // RTL838X only supports 2 concurrent algorithms
1687 sw_w32_mask(1 << (group
% 8), algoidx
<< (group
% 8),
1688 RTL838X_TRK_HASH_IDX_CTRL
+ ((group
>> 3) << 2));
1689 sw_w32(algomsk
, RTL838X_TRK_HASH_CTRL
+ (algoidx
<< 2));
1692 void rtl838x_set_receive_management_action(int port
, rma_ctrl_t type
, action_type_t action
)
1696 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1697 RTL838X_RMA_BPDU_CTRL
+ ((port
>> 4) << 2));
1700 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1701 RTL838X_RMA_PTP_CTRL
+ ((port
>> 4) << 2));
1704 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1705 RTL838X_RMA_LLTP_CTRL
+ ((port
>> 4) << 2));
1712 const struct rtl838x_reg rtl838x_reg
= {
1713 .mask_port_reg_be
= rtl838x_mask_port_reg
,
1714 .set_port_reg_be
= rtl838x_set_port_reg
,
1715 .get_port_reg_be
= rtl838x_get_port_reg
,
1716 .mask_port_reg_le
= rtl838x_mask_port_reg
,
1717 .set_port_reg_le
= rtl838x_set_port_reg
,
1718 .get_port_reg_le
= rtl838x_get_port_reg
,
1719 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
1720 .stat_rst
= RTL838X_STAT_RST
,
1721 .stat_port_std_mib
= RTL838X_STAT_PORT_STD_MIB
,
1722 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
1723 .traffic_enable
= rtl838x_traffic_enable
,
1724 .traffic_disable
= rtl838x_traffic_disable
,
1725 .traffic_get
= rtl838x_traffic_get
,
1726 .traffic_set
= rtl838x_traffic_set
,
1727 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
1728 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
1729 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
1730 .set_ageing_time
= rtl838x_set_ageing_time
,
1731 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
1732 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
1733 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
1734 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
1735 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
1736 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
1737 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
1738 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
1739 .imr_glb
= RTL838X_IMR_GLB
,
1740 .vlan_tables_read
= rtl838x_vlan_tables_read
,
1741 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
1742 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
1743 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
1744 .vlan_profile_dump
= rtl838x_vlan_profile_dump
,
1745 .vlan_profile_setup
= rtl838x_vlan_profile_setup
,
1746 .vlan_fwd_on_inner
= rtl838x_vlan_fwd_on_inner
,
1747 .set_vlan_igr_filter
= rtl838x_set_igr_filter
,
1748 .set_vlan_egr_filter
= rtl838x_set_egr_filter
,
1749 .enable_learning
= rtl838x_enable_learning
,
1750 .enable_flood
= rtl838x_enable_flood
,
1751 .enable_mcast_flood
= rtl838x_enable_mcast_flood
,
1752 .enable_bcast_flood
= rtl838x_enable_bcast_flood
,
1753 .stp_get
= rtl838x_stp_get
,
1754 .stp_set
= rtl838x_stp_set
,
1755 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
1756 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
1757 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
1758 .mir_ctrl
= RTL838X_MIR_CTRL
,
1759 .mir_dpm
= RTL838X_MIR_DPM_CTRL
,
1760 .mir_spm
= RTL838X_MIR_SPM_CTRL
,
1761 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
1762 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
1763 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
1764 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
1765 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
1766 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
1767 .write_l2_entry_using_hash
= rtl838x_write_l2_entry_using_hash
,
1768 .read_cam
= rtl838x_read_cam
,
1769 .write_cam
= rtl838x_write_cam
,
1770 .vlan_port_keep_tag_set
= rtl838x_vlan_port_keep_tag_set
,
1771 .vlan_port_pvidmode_set
= rtl838x_vlan_port_pvidmode_set
,
1772 .vlan_port_pvid_set
= rtl838x_vlan_port_pvid_set
,
1773 .trk_mbr_ctr
= rtl838x_trk_mbr_ctr
,
1774 .rma_bpdu_fld_pmask
= RTL838X_RMA_BPDU_FLD_PMSK
,
1775 .spcl_trap_eapol_ctrl
= RTL838X_SPCL_TRAP_EAPOL_CTRL
,
1776 .init_eee
= rtl838x_init_eee
,
1777 .port_eee_set
= rtl838x_port_eee_set
,
1778 .eee_port_ability
= rtl838x_eee_port_ability
,
1779 .l2_hash_seed
= rtl838x_l2_hash_seed
,
1780 .l2_hash_key
= rtl838x_l2_hash_key
,
1781 .read_mcast_pmask
= rtl838x_read_mcast_pmask
,
1782 .write_mcast_pmask
= rtl838x_write_mcast_pmask
,
1783 .pie_init
= rtl838x_pie_init
,
1784 .pie_rule_read
= rtl838x_pie_rule_read
,
1785 .pie_rule_write
= rtl838x_pie_rule_write
,
1786 .pie_rule_add
= rtl838x_pie_rule_add
,
1787 .pie_rule_rm
= rtl838x_pie_rule_rm
,
1788 .l2_learning_setup
= rtl838x_l2_learning_setup
,
1789 .packet_cntr_read
= rtl838x_packet_cntr_read
,
1790 .packet_cntr_clear
= rtl838x_packet_cntr_clear
,
1791 .route_read
= rtl838x_route_read
,
1792 .route_write
= rtl838x_route_write
,
1793 .l3_setup
= rtl838x_l3_setup
,
1794 .set_distribution_algorithm
= rtl838x_set_distribution_algorithm
,
1795 .set_receive_management_action
= rtl838x_set_receive_management_action
,
1798 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
1800 struct dsa_switch
*ds
= dev_id
;
1801 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
1802 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
1807 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
1808 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
1810 for (i
= 0; i
< 28; i
++) {
1811 if (ports
& BIT(i
)) {
1812 link
= sw_r32(RTL838X_MAC_LINK_STS
);
1814 dsa_port_phylink_mac_change(ds
, i
, true);
1816 dsa_port_phylink_mac_change(ds
, i
, false);
1822 int rtl838x_smi_wait_op(int timeout
)
1827 ret
= readx_poll_timeout(sw_r32
, RTL838X_SMI_ACCESS_PHY_CTRL_1
,
1828 val
, !(val
& 0x1), 20, timeout
);
1830 pr_err("%s: timeout\n", __func__
);
1836 * Reads a register in a page from the PHY
1838 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
1848 if (page
> 4095 || reg
> 31)
1851 mutex_lock(&smi_lock
);
1853 if (rtl838x_smi_wait_op(100000))
1856 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1858 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
1859 v
= reg
<< 20 | page
<< 3;
1860 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1861 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1863 if (rtl838x_smi_wait_op(100000))
1866 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1868 mutex_unlock(&smi_lock
);
1872 mutex_unlock(&smi_lock
);
1877 * Write to a register in a page of the PHY
1879 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
1885 if (port
> 31 || page
> 4095 || reg
> 31)
1888 mutex_lock(&smi_lock
);
1889 if (rtl838x_smi_wait_op(100000))
1892 sw_w32(BIT(port
), RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1895 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1897 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
1898 v
= reg
<< 20 | page
<< 3 | 0x4;
1899 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1900 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1902 if (rtl838x_smi_wait_op(100000))
1905 mutex_unlock(&smi_lock
);
1909 mutex_unlock(&smi_lock
);
1914 * Read an mmd register of a PHY
1916 int rtl838x_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
1920 mutex_lock(&smi_lock
);
1922 if (rtl838x_smi_wait_op(100000))
1925 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1928 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1930 v
= addr
<< 16 | reg
;
1931 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1933 /* mmd-access | read | cmd-start */
1934 v
= 1 << 1 | 0 << 2 | 1;
1935 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1937 if (rtl838x_smi_wait_op(100000))
1940 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1942 mutex_unlock(&smi_lock
);
1946 mutex_unlock(&smi_lock
);
1951 * Write to an mmd register of a PHY
1953 int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
1957 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
1959 mutex_lock(&smi_lock
);
1961 if (rtl838x_smi_wait_op(100000))
1964 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1967 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1969 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1970 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1971 /* mmd-access | write | cmd-start */
1972 v
= 1 << 1 | 1 << 2 | 1;
1973 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1975 if (rtl838x_smi_wait_op(100000))
1978 mutex_unlock(&smi_lock
);
1982 mutex_unlock(&smi_lock
);
1986 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
1988 u32 rw_save
, info_save
;
1991 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
1992 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
1994 info_save
= sw_r32(RTL838X_CHIP_INFO
);
1995 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
1997 info
= sw_r32(RTL838X_CHIP_INFO
);
1998 sw_w32(info_save
, RTL838X_CHIP_INFO
);
1999 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
2001 if ((info
& 0xFFFF) == 0x6275) {
2002 if (((info
>> 16) & 0x1F) == 0x1)
2003 priv
->version
= RTL8380_VERSION_A
;
2004 else if (((info
>> 16) & 0x1F) == 0x2)
2005 priv
->version
= RTL8380_VERSION_B
;
2007 priv
->version
= RTL8380_VERSION_B
;
2009 priv
->version
= '-';
2013 void rtl838x_vlan_profile_dump(int profile
)
2017 if (profile
< 0 || profile
> 7)
2020 p
= sw_r32(RTL838X_VLAN_PROFILE(profile
));
2022 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
2023 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
2024 profile
, p
& 1, (p
>> 1) & 0x1ff, (p
>> 10) & 0x1ff, (p
>> 19) & 0x1ff);
2027 void rtl8380_sds_rst(int mac
)
2029 u32 offset
= (mac
== 24) ? 0 : 0x100;
2031 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0
+ offset
);
2032 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28
+ offset
);
2033 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28
+ offset
);
2034 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0
+ offset
);
2035 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0
+ offset
);
2036 pr_debug("SERDES reset: %d\n", mac
);
2039 int rtl8380_sds_power(int mac
, int val
)
2041 u32 mode
= (val
== 1) ? 0x4 : 0x9;
2042 u32 offset
= (mac
== 24) ? 5 : 0;
2044 if ((mac
!= 24) && (mac
!= 26)) {
2045 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
2049 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
2051 rtl8380_sds_rst(mac
);