1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <net/nexthop.h>
8 extern struct mutex smi_lock
;
10 // see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
11 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
12 enum template_field_id
{
13 TEMPLATE_FIELD_SPMMASK
= 0,
14 TEMPLATE_FIELD_SPM0
= 1, // Source portmask ports 0-15
15 TEMPLATE_FIELD_SPM1
= 2, // Source portmask ports 16-28
16 TEMPLATE_FIELD_RANGE_CHK
= 3,
17 TEMPLATE_FIELD_DMAC0
= 4, // Destination MAC [15:0]
18 TEMPLATE_FIELD_DMAC1
= 5, // Destination MAC [31:16]
19 TEMPLATE_FIELD_DMAC2
= 6, // Destination MAC [47:32]
20 TEMPLATE_FIELD_SMAC0
= 7, // Source MAC [15:0]
21 TEMPLATE_FIELD_SMAC1
= 8, // Source MAC [31:16]
22 TEMPLATE_FIELD_SMAC2
= 9, // Source MAC [47:32]
23 TEMPLATE_FIELD_ETHERTYPE
= 10, // Ethernet typ
24 TEMPLATE_FIELD_OTAG
= 11, // Outer VLAN tag
25 TEMPLATE_FIELD_ITAG
= 12, // Inner VLAN tag
26 TEMPLATE_FIELD_SIP0
= 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
27 // source protocol address in header
28 TEMPLATE_FIELD_SIP1
= 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
29 TEMPLATE_FIELD_DIP0
= 15, // IPv4 or IPv6 destination IP[15:0]
30 TEMPLATE_FIELD_DIP1
= 16, // IPv4 or IPv6 destination IP[31:16]
31 TEMPLATE_FIELD_IP_TOS_PROTO
= 17, // IPv4 TOS/IPv6 traffic class and
32 // IPv4 proto/IPv6 next header fields
33 TEMPLATE_FIELD_L34_HEADER
= 18, // packet with extra tag and IPv6 with auth, dest,
34 // frag, route, hop-by-hop option header,
35 // IGMP type, TCP flag
36 TEMPLATE_FIELD_L4_SPORT
= 19, // TCP/UDP source port
37 TEMPLATE_FIELD_L4_DPORT
= 20, // TCP/UDP destination port
38 TEMPLATE_FIELD_ICMP_IGMP
= 21,
39 TEMPLATE_FIELD_IP_RANGE
= 22,
40 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 23, // Field selector mask
41 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 24,
42 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 25,
43 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 26,
44 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 27,
45 TEMPLATE_FIELD_SIP2
= 28, // IPv6 source IP[47:32]
46 TEMPLATE_FIELD_SIP3
= 29, // IPv6 source IP[63:48]
47 TEMPLATE_FIELD_SIP4
= 30, // IPv6 source IP[79:64]
48 TEMPLATE_FIELD_SIP5
= 31, // IPv6 source IP[95:80]
49 TEMPLATE_FIELD_SIP6
= 32, // IPv6 source IP[111:96]
50 TEMPLATE_FIELD_SIP7
= 33, // IPv6 source IP[127:112]
51 TEMPLATE_FIELD_DIP2
= 34, // IPv6 destination IP[47:32]
52 TEMPLATE_FIELD_DIP3
= 35, // IPv6 destination IP[63:48]
53 TEMPLATE_FIELD_DIP4
= 36, // IPv6 destination IP[79:64]
54 TEMPLATE_FIELD_DIP5
= 37, // IPv6 destination IP[95:80]
55 TEMPLATE_FIELD_DIP6
= 38, // IPv6 destination IP[111:96]
56 TEMPLATE_FIELD_DIP7
= 39, // IPv6 destination IP[127:112]
57 TEMPLATE_FIELD_FWD_VID
= 40, // Forwarding VLAN-ID
58 TEMPLATE_FIELD_FLOW_LABEL
= 41,
62 * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
63 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
64 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
65 * templates. Additionally, 3 user-definable templates can be set up via the definitions
66 * in RTL838X_ACL_TMPLTE_CTRL control registers.
67 * TODO: See all src/app/diag_v2/src/diag_pie.c
69 #define N_FIXED_TEMPLATES 5
70 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
73 TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_OTAG
,
74 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
75 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
76 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_RANGE_CHK
78 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
79 TEMPLATE_FIELD_DIP1
,TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_L4_SPORT
,
80 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_ITAG
,
81 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
83 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
84 TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
85 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_SIP0
,
86 TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
88 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
89 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
90 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_L4_DPORT
,
91 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_IP_TOS_PROTO
93 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
94 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
95 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_ITAG
,
96 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
100 void rtl838x_print_matrix(void)
102 unsigned volatile int *ptr8
;
105 ptr8
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
106 for (i
= 0; i
< 28; i
+= 8)
107 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
108 ptr8
[i
+ 0], ptr8
[i
+ 1], ptr8
[i
+ 2], ptr8
[i
+ 3],
109 ptr8
[i
+ 4], ptr8
[i
+ 5], ptr8
[i
+ 6], ptr8
[i
+ 7]);
110 pr_debug("CPU_PORT> %8x\n", ptr8
[28]);
113 static inline int rtl838x_port_iso_ctrl(int p
)
115 return RTL838X_PORT_ISO_CTRL(p
);
118 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
120 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
121 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & BIT(15));
124 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
126 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
127 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & BIT(15));
130 static inline int rtl838x_tbl_access_data_0(int i
)
132 return RTL838X_TBL_ACCESS_DATA_0(i
);
135 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
138 // Read VLAN table (0) via register 0
139 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
141 rtl_table_read(r
, vlan
);
142 info
->tagged_ports
= sw_r32(rtl_table_data(r
, 0));
143 v
= sw_r32(rtl_table_data(r
, 1));
144 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan
, info
->tagged_ports
, v
);
145 rtl_table_release(r
);
147 info
->profile_id
= v
& 0x7;
148 info
->hash_mc_fid
= !!(v
& 0x8);
149 info
->hash_uc_fid
= !!(v
& 0x10);
150 info
->fid
= (v
>> 5) & 0x3f;
152 // Read UNTAG table (0) via table register 1
153 r
= rtl_table_get(RTL8380_TBL_1
, 0);
154 rtl_table_read(r
, vlan
);
155 info
->untagged_ports
= sw_r32(rtl_table_data(r
, 0));
156 rtl_table_release(r
);
159 static void rtl838x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
162 // Access VLAN table (0) via register 0
163 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
165 sw_w32(info
->tagged_ports
, rtl_table_data(r
, 0));
167 v
= info
->profile_id
;
168 v
|= info
->hash_mc_fid
? 0x8 : 0;
169 v
|= info
->hash_uc_fid
? 0x10 : 0;
170 v
|= ((u32
)info
->fid
) << 5;
171 sw_w32(v
, rtl_table_data(r
, 1));
173 rtl_table_write(r
, vlan
);
174 rtl_table_release(r
);
177 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
179 // Access UNTAG table (0) via register 1
180 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 0);
182 sw_w32(portmask
& 0x1fffffff, rtl_table_data(r
, 0));
183 rtl_table_write(r
, vlan
);
184 rtl_table_release(r
);
187 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
189 static void rtl838x_vlan_fwd_on_inner(int port
, bool is_set
)
192 sw_w32_mask(BIT(port
), 0, RTL838X_VLAN_PORT_FWD
);
194 sw_w32_mask(0, BIT(port
), RTL838X_VLAN_PORT_FWD
);
197 static u64
rtl838x_l2_hash_seed(u64 mac
, u32 vid
)
199 return mac
<< 12 | vid
;
203 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
204 * and returns a key into the L2 hash table
206 static u32
rtl838x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
210 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
211 h1
= (seed
>> 11) & 0x7ff;
212 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
214 h2
= (seed
>> 33) & 0x7ff;
215 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
217 h3
= (seed
>> 44) & 0x7ff;
218 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
220 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
221 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
223 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
224 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
225 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
231 static inline int rtl838x_mac_force_mode_ctrl(int p
)
233 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
236 static inline int rtl838x_mac_port_ctrl(int p
)
238 return RTL838X_MAC_PORT_CTRL(p
);
241 static inline int rtl838x_l2_port_new_salrn(int p
)
243 return RTL838X_L2_PORT_NEW_SALRN(p
);
246 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
248 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
251 static inline int rtl838x_mac_link_spd_sts(int p
)
253 return RTL838X_MAC_LINK_SPD_STS(p
);
256 inline static int rtl838x_trk_mbr_ctr(int group
)
258 return RTL838X_TRK_MBR_CTR
+ (group
<< 2);
262 * Fills an L2 entry structure from the SoC registers
264 static void rtl838x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
266 /* Table contains different entry types, we need to identify the right one:
267 * Check for MC entries, first
268 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
269 * identify valid entries
271 e
->is_ip_mc
= !!(r
[0] & BIT(22));
272 e
->is_ipv6_mc
= !!(r
[0] & BIT(21));
273 e
->type
= L2_INVALID
;
275 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
276 e
->mac
[0] = (r
[1] >> 20);
277 e
->mac
[1] = (r
[1] >> 12);
278 e
->mac
[2] = (r
[1] >> 4);
279 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
280 e
->mac
[4] = (r
[2] >> 20);
281 e
->mac
[5] = (r
[2] >> 12);
283 e
->rvid
= r
[2] & 0xfff;
284 e
->vid
= r
[0] & 0xfff;
286 /* Is it a unicast entry? check multicast bit */
287 if (!(e
->mac
[0] & 1)) {
288 e
->is_static
= !!((r
[0] >> 19) & 1);
289 e
->port
= (r
[0] >> 12) & 0x1f;
290 e
->block_da
= !!(r
[1] & BIT(30));
291 e
->block_sa
= !!(r
[1] & BIT(31));
292 e
->suspended
= !!(r
[1] & BIT(29));
293 e
->next_hop
= !!(r
[1] & BIT(28));
295 pr_debug("Found next hop entry, need to read extra data\n");
296 e
->nh_vlan_target
= !!(r
[0] & BIT(9));
297 e
->nh_route_id
= r
[0] & 0x1ff;
300 e
->age
= (r
[0] >> 17) & 0x3;
303 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
304 * next-hop or static entry bit set */
305 if (!(r
[0] & 0x007c0000) && !(r
[1] & 0xd0000000))
308 e
->type
= L2_UNICAST
;
309 } else { // L2 multicast
310 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
312 e
->type
= L2_MULTICAST
;
313 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
315 } else { // IPv4 and IPv6 multicast
317 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
318 e
->mc_gip
= (r
[1] << 20) | (r
[2] >> 12);
319 e
->rvid
= r
[2] & 0xfff;
322 e
->type
= IP4_MULTICAST
;
324 e
->type
= IP6_MULTICAST
;
328 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
330 static void rtl838x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
332 u64 mac
= ether_addr_to_u64(e
->mac
);
335 r
[0] = r
[1] = r
[2] = 0;
339 r
[0] = e
->is_ip_mc
? BIT(22) : 0;
340 r
[0] |= e
->is_ipv6_mc
? BIT(21) : 0;
342 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
344 r
[2] = (mac
& 0xfffff) << 12;
346 /* Is it a unicast entry? check multicast bit */
347 if (!(e
->mac
[0] & 1)) {
348 r
[0] |= e
->is_static
? BIT(19) : 0;
349 r
[0] |= (e
->port
& 0x3f) << 12;
351 r
[1] |= e
->block_da
? BIT(30) : 0;
352 r
[1] |= e
->block_sa
? BIT(31) : 0;
353 r
[1] |= e
->suspended
? BIT(29) : 0;
354 r
[2] |= e
->rvid
& 0xfff;
357 r
[0] |= e
->nh_vlan_target
? BIT(9) : 0;
358 r
[0] |= e
->nh_route_id
& 0x1ff;
360 r
[0] |= (e
->age
& 0x3) << 17;
361 } else { // L2 Multicast
362 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
363 r
[2] |= e
->rvid
& 0xfff;
364 r
[0] |= e
->vid
& 0xfff;
365 pr_debug("FILL MC: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
367 } else { // IPv4 and IPv6 multicast
368 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
369 r
[1] = e
->mc_gip
>> 20;
370 r
[2] = e
->mc_gip
<< 12;
376 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
377 * hash is the id of the bucket and pos is the position of the entry in that bucket
378 * The data read from the SoC is filled into rtl838x_l2_entry
380 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
384 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0); // Access L2 Table 0
385 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
388 rtl_table_read(q
, idx
);
389 for (i
= 0; i
< 3; i
++)
390 r
[i
] = sw_r32(rtl_table_data(q
, i
));
392 rtl_table_release(q
);
394 rtl838x_fill_l2_entry(r
, e
);
398 entry
= (((u64
) r
[1]) << 32) | (r
[2]); // mac and vid concatenated as hash seed
402 static void rtl838x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
405 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0);
408 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
410 rtl838x_fill_l2_row(r
, e
);
412 for (i
= 0; i
< 3; i
++)
413 sw_w32(r
[i
], rtl_table_data(q
, i
));
415 rtl_table_write(q
, idx
);
416 rtl_table_release(q
);
419 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
423 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
426 rtl_table_read(q
, idx
);
427 for (i
= 0; i
< 3; i
++)
428 r
[i
] = sw_r32(rtl_table_data(q
, i
));
430 rtl_table_release(q
);
432 rtl838x_fill_l2_entry(r
, e
);
436 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
438 // Return MAC with concatenated VID ac concatenated ID
439 entry
= (((u64
) r
[1]) << 32) | r
[2];
443 static void rtl838x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
446 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
449 rtl838x_fill_l2_row(r
, e
);
451 for (i
= 0; i
< 3; i
++)
452 sw_w32(r
[i
], rtl_table_data(q
, i
));
454 rtl_table_write(q
, idx
);
455 rtl_table_release(q
);
458 static u64
rtl838x_read_mcast_pmask(int idx
)
461 // Read MC_PMSK (2) via register RTL8380_TBL_L2
462 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
464 rtl_table_read(q
, idx
);
465 portmask
= sw_r32(rtl_table_data(q
, 0));
466 rtl_table_release(q
);
471 static void rtl838x_write_mcast_pmask(int idx
, u64 portmask
)
473 // Access MC_PMSK (2) via register RTL8380_TBL_L2
474 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
476 sw_w32(((u32
)portmask
) & 0x1fffffff, rtl_table_data(q
, 0));
477 rtl_table_write(q
, idx
);
478 rtl_table_release(q
);
481 static void rtl838x_vlan_profile_setup(int profile
)
483 u32 pmask_id
= UNKNOWN_MC_PMASK
;
484 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
485 u32 p
= 1 | pmask_id
<< 1 | pmask_id
<< 10 | pmask_id
<< 19;
487 sw_w32(p
, RTL838X_VLAN_PROFILE(profile
));
489 /* RTL8380 and RTL8390 use an index into the portmask table to set the
490 * unknown multicast portmask, setup a default at a safe location
491 * On RTL93XX, the portmask is directly set in the profile,
492 * see e.g. rtl9300_vlan_profile_setup
494 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x1fffffff);
497 static void rtl838x_l2_learning_setup(void)
499 /* Set portmask for broadcast traffic and unknown unicast address flooding
500 * to the reserved entry in the portmask table used also for
501 * multicast flooding */
502 sw_w32(UNKNOWN_MC_PMASK
<< 12 | UNKNOWN_MC_PMASK
, RTL838X_L2_FLD_PMSK
);
504 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
505 * and per vlan (bit 2) */
506 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN
);
508 // Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
509 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT
);
511 // Do not trap ARP packets to CPU_PORT
512 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL
);
515 static void rtl838x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
518 u32 cmd
= 1 << 15 /* Execute cmd */
520 | 2 << 12 /* Table type 0b10 */
522 priv
->r
->exec_tbl0_cmd(cmd
);
524 for (i
= 0; i
< 2; i
++)
525 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
528 static void rtl838x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
531 u32 cmd
= 1 << 15 /* Execute cmd */
532 | 0 << 14 /* Write */
533 | 2 << 12 /* Table type 0b10 */
536 for (i
= 0; i
< 2; i
++)
537 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
538 priv
->r
->exec_tbl0_cmd(cmd
);
541 u64
rtl838x_traffic_get(int source
)
543 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source
));
546 void rtl838x_traffic_set(int source
, u64 dest_matrix
)
548 rtl838x_set_port_reg(dest_matrix
, rtl838x_port_iso_ctrl(source
));
551 void rtl838x_traffic_enable(int source
, int dest
)
553 rtl838x_mask_port_reg(0, BIT(dest
), rtl838x_port_iso_ctrl(source
));
556 void rtl838x_traffic_disable(int source
, int dest
)
558 rtl838x_mask_port_reg(BIT(dest
), 0, rtl838x_port_iso_ctrl(source
));
562 * Enables or disables the EEE/EEEP capability of a port
564 static void rtl838x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
568 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
572 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
573 v
= enable
? 0x3 : 0x0;
575 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
576 sw_w32_mask(0x3 << 9, v
<< 9, priv
->r
->mac_force_mode_ctrl(port
));
578 // Set TX/RX EEE state
580 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_TX_EN
);
581 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_RX_EN
);
583 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_TX_EN
);
584 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_RX_EN
);
586 priv
->ports
[port
].eee_enabled
= enable
;
591 * Get EEE own capabilities and negotiation result
593 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv
*priv
,
594 struct ethtool_eee
*e
, int port
)
601 link
= rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS
);
602 if (!(link
& BIT(port
)))
605 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(9))
606 e
->advertised
|= ADVERTISED_100baseT_Full
;
608 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(10))
609 e
->advertised
|= ADVERTISED_1000baseT_Full
;
611 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & BIT(port
)) {
612 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
613 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
620 static void rtl838x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
624 pr_info("Setting up EEE, state: %d\n", enable
);
625 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
627 /* Set timers for EEE */
628 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
629 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
631 // Enable EEE MAC support on ports
632 for (i
= 0; i
< priv
->cpu_port
; i
++) {
633 if (priv
->ports
[i
].phy
)
634 rtl838x_port_eee_set(priv
, i
, enable
);
636 priv
->eee_enabled
= enable
;
639 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
641 int block
= index
/ PIE_BLOCK_SIZE
;
642 u32 block_state
= sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL
);
644 // Make sure rule-lookup is enabled in the block
645 if (!(block_state
& BIT(block
)))
646 sw_w32(block_state
| BIT(block
), RTL838X_ACL_BLK_LOOKUP_CTRL
);
649 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
651 int block_from
= index_from
/ PIE_BLOCK_SIZE
;
652 int block_to
= index_to
/ PIE_BLOCK_SIZE
;
653 u32 v
= (index_from
<< 1)| (index_to
<< 12 ) | BIT(0);
657 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
658 mutex_lock(&priv
->reg_mutex
);
660 // Remember currently active blocks
661 block_state
= sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL
);
663 // Make sure rule-lookup is disabled in the relevant blocks
664 for (block
= block_from
; block
<= block_to
; block
++) {
665 if (block_state
& BIT(block
))
666 sw_w32(block_state
& (~BIT(block
)), RTL838X_ACL_BLK_LOOKUP_CTRL
);
669 // Write from-to and execute bit into control register
670 sw_w32(v
, RTL838X_ACL_CLR_CTRL
);
672 // Wait until command has completed
674 } while (sw_r32(RTL838X_ACL_CLR_CTRL
) & BIT(0));
676 // Re-enable rule lookup
677 for (block
= block_from
; block
<= block_to
; block
++) {
678 if (!(block_state
& BIT(block
)))
679 sw_w32(block_state
| BIT(block
), RTL838X_ACL_BLK_LOOKUP_CTRL
);
682 mutex_unlock(&priv
->reg_mutex
);
686 * Reads the intermediate representation of the templated match-fields of the
687 * PIE rule in the pie_rule structure and fills in the raw data fields in the
688 * raw register space r[].
689 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
690 * however the RTL9310 has 2 more registers / fields and the physical field-ids
691 * are specific to every platform.
693 static void rtl838x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
696 enum template_field_id field_type
;
699 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
703 switch (field_type
) {
704 case TEMPLATE_FIELD_SPM0
:
708 case TEMPLATE_FIELD_SPM1
:
709 data
= pr
->spm
>> 16;
710 data_m
= pr
->spm_m
>> 16;
712 case TEMPLATE_FIELD_OTAG
:
716 case TEMPLATE_FIELD_SMAC0
:
718 data
= (data
<< 8) | pr
->smac
[5];
719 data_m
= pr
->smac_m
[4];
720 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
722 case TEMPLATE_FIELD_SMAC1
:
724 data
= (data
<< 8) | pr
->smac
[3];
725 data_m
= pr
->smac_m
[2];
726 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
728 case TEMPLATE_FIELD_SMAC2
:
730 data
= (data
<< 8) | pr
->smac
[1];
731 data_m
= pr
->smac_m
[0];
732 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
734 case TEMPLATE_FIELD_DMAC0
:
736 data
= (data
<< 8) | pr
->dmac
[5];
737 data_m
= pr
->dmac_m
[4];
738 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
740 case TEMPLATE_FIELD_DMAC1
:
742 data
= (data
<< 8) | pr
->dmac
[3];
743 data_m
= pr
->dmac_m
[2];
744 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
746 case TEMPLATE_FIELD_DMAC2
:
748 data
= (data
<< 8) | pr
->dmac
[1];
749 data_m
= pr
->dmac_m
[0];
750 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
752 case TEMPLATE_FIELD_ETHERTYPE
:
753 data
= pr
->ethertype
;
754 data_m
= pr
->ethertype_m
;
756 case TEMPLATE_FIELD_ITAG
:
760 case TEMPLATE_FIELD_RANGE_CHK
:
761 data
= pr
->field_range_check
;
762 data_m
= pr
->field_range_check_m
;
764 case TEMPLATE_FIELD_SIP0
:
766 data
= pr
->sip6
.s6_addr16
[7];
767 data_m
= pr
->sip6_m
.s6_addr16
[7];
773 case TEMPLATE_FIELD_SIP1
:
775 data
= pr
->sip6
.s6_addr16
[6];
776 data_m
= pr
->sip6_m
.s6_addr16
[6];
778 data
= pr
->sip
>> 16;
779 data_m
= pr
->sip_m
>> 16;
783 case TEMPLATE_FIELD_SIP2
:
784 case TEMPLATE_FIELD_SIP3
:
785 case TEMPLATE_FIELD_SIP4
:
786 case TEMPLATE_FIELD_SIP5
:
787 case TEMPLATE_FIELD_SIP6
:
788 case TEMPLATE_FIELD_SIP7
:
789 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
790 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
793 case TEMPLATE_FIELD_DIP0
:
795 data
= pr
->dip6
.s6_addr16
[7];
796 data_m
= pr
->dip6_m
.s6_addr16
[7];
803 case TEMPLATE_FIELD_DIP1
:
805 data
= pr
->dip6
.s6_addr16
[6];
806 data_m
= pr
->dip6_m
.s6_addr16
[6];
808 data
= pr
->dip
>> 16;
809 data_m
= pr
->dip_m
>> 16;
813 case TEMPLATE_FIELD_DIP2
:
814 case TEMPLATE_FIELD_DIP3
:
815 case TEMPLATE_FIELD_DIP4
:
816 case TEMPLATE_FIELD_DIP5
:
817 case TEMPLATE_FIELD_DIP6
:
818 case TEMPLATE_FIELD_DIP7
:
819 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
820 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
823 case TEMPLATE_FIELD_IP_TOS_PROTO
:
824 data
= pr
->tos_proto
;
825 data_m
= pr
->tos_proto_m
;
827 case TEMPLATE_FIELD_L4_SPORT
:
829 data_m
= pr
->sport_m
;
831 case TEMPLATE_FIELD_L4_DPORT
:
833 data_m
= pr
->dport_m
;
835 case TEMPLATE_FIELD_ICMP_IGMP
:
836 data
= pr
->icmp_igmp
;
837 data_m
= pr
->icmp_igmp_m
;
840 pr_info("%s: unknown field %d\n", __func__
, field_type
);
845 r
[12 - i
/ 2] = data_m
;
847 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
848 r
[12 - i
/ 2] |= ((u32
)data_m
) << 16;
854 * Creates the intermediate representation of the templated match-fields of the
855 * PIE rule in the pie_rule structure by reading the raw data fields in the
856 * raw register space r[].
857 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
858 * however the RTL9310 has 2 more registers / fields and the physical field-ids
860 static void rtl838x_read_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
863 enum template_field_id field_type
;
866 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
870 data_m
= r
[12 - i
/ 2];
872 data
= r
[5 - i
/ 2] >> 16;
873 data_m
= r
[12 - i
/ 2] >> 16;
876 switch (field_type
) {
877 case TEMPLATE_FIELD_SPM0
:
878 pr
->spm
= (pr
->spn
<< 16) | data
;
879 pr
->spm_m
= (pr
->spn
<< 16) | data_m
;
881 case TEMPLATE_FIELD_SPM1
:
885 case TEMPLATE_FIELD_OTAG
:
889 case TEMPLATE_FIELD_SMAC0
:
890 pr
->smac
[4] = data
>> 8;
892 pr
->smac_m
[4] = data
>> 8;
893 pr
->smac_m
[5] = data
;
895 case TEMPLATE_FIELD_SMAC1
:
896 pr
->smac
[2] = data
>> 8;
898 pr
->smac_m
[2] = data
>> 8;
899 pr
->smac_m
[3] = data
;
901 case TEMPLATE_FIELD_SMAC2
:
902 pr
->smac
[0] = data
>> 8;
904 pr
->smac_m
[0] = data
>> 8;
905 pr
->smac_m
[1] = data
;
907 case TEMPLATE_FIELD_DMAC0
:
908 pr
->dmac
[4] = data
>> 8;
910 pr
->dmac_m
[4] = data
>> 8;
911 pr
->dmac_m
[5] = data
;
913 case TEMPLATE_FIELD_DMAC1
:
914 pr
->dmac
[2] = data
>> 8;
916 pr
->dmac_m
[2] = data
>> 8;
917 pr
->dmac_m
[3] = data
;
919 case TEMPLATE_FIELD_DMAC2
:
920 pr
->dmac
[0] = data
>> 8;
922 pr
->dmac_m
[0] = data
>> 8;
923 pr
->dmac_m
[1] = data
;
925 case TEMPLATE_FIELD_ETHERTYPE
:
926 pr
->ethertype
= data
;
927 pr
->ethertype_m
= data_m
;
929 case TEMPLATE_FIELD_ITAG
:
933 case TEMPLATE_FIELD_RANGE_CHK
:
934 pr
->field_range_check
= data
;
935 pr
->field_range_check_m
= data_m
;
937 case TEMPLATE_FIELD_SIP0
:
941 case TEMPLATE_FIELD_SIP1
:
942 pr
->sip
= (pr
->sip
<< 16) | data
;
943 pr
->sip_m
= (pr
->sip
<< 16) | data_m
;
945 case TEMPLATE_FIELD_SIP2
:
947 // Make use of limitiations on the position of the match values
948 ipv6_addr_set(&pr
->sip6
, pr
->sip
, r
[5 - i
/ 2],
949 r
[4 - i
/ 2], r
[3 - i
/ 2]);
950 ipv6_addr_set(&pr
->sip6_m
, pr
->sip_m
, r
[5 - i
/ 2],
951 r
[4 - i
/ 2], r
[3 - i
/ 2]);
952 case TEMPLATE_FIELD_SIP3
:
953 case TEMPLATE_FIELD_SIP4
:
954 case TEMPLATE_FIELD_SIP5
:
955 case TEMPLATE_FIELD_SIP6
:
956 case TEMPLATE_FIELD_SIP7
:
959 case TEMPLATE_FIELD_DIP0
:
963 case TEMPLATE_FIELD_DIP1
:
964 pr
->dip
= (pr
->dip
<< 16) | data
;
965 pr
->dip_m
= (pr
->dip
<< 16) | data_m
;
967 case TEMPLATE_FIELD_DIP2
:
969 ipv6_addr_set(&pr
->dip6
, pr
->dip
, r
[5 - i
/ 2],
970 r
[4 - i
/ 2], r
[3 - i
/ 2]);
971 ipv6_addr_set(&pr
->dip6_m
, pr
->dip_m
, r
[5 - i
/ 2],
972 r
[4 - i
/ 2], r
[3 - i
/ 2]);
973 case TEMPLATE_FIELD_DIP3
:
974 case TEMPLATE_FIELD_DIP4
:
975 case TEMPLATE_FIELD_DIP5
:
976 case TEMPLATE_FIELD_DIP6
:
977 case TEMPLATE_FIELD_DIP7
:
979 case TEMPLATE_FIELD_IP_TOS_PROTO
:
980 pr
->tos_proto
= data
;
981 pr
->tos_proto_m
= data_m
;
983 case TEMPLATE_FIELD_L4_SPORT
:
985 pr
->sport_m
= data_m
;
987 case TEMPLATE_FIELD_L4_DPORT
:
989 pr
->dport_m
= data_m
;
991 case TEMPLATE_FIELD_ICMP_IGMP
:
992 pr
->icmp_igmp
= data
;
993 pr
->icmp_igmp_m
= data_m
;
996 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1001 static void rtl838x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1003 pr
->spmmask_fix
= (r
[6] >> 22) & 0x3;
1004 pr
->spn
= (r
[6] >> 16) & 0x3f;
1005 pr
->mgnt_vlan
= (r
[6] >> 15) & 1;
1006 pr
->dmac_hit_sw
= (r
[6] >> 14) & 1;
1007 pr
->not_first_frag
= (r
[6] >> 13) & 1;
1008 pr
->frame_type_l4
= (r
[6] >> 10) & 7;
1009 pr
->frame_type
= (r
[6] >> 8) & 3;
1010 pr
->otag_fmt
= (r
[6] >> 7) & 1;
1011 pr
->itag_fmt
= (r
[6] >> 6) & 1;
1012 pr
->otag_exist
= (r
[6] >> 5) & 1;
1013 pr
->itag_exist
= (r
[6] >> 4) & 1;
1014 pr
->frame_type_l2
= (r
[6] >> 2) & 3;
1017 pr
->spmmask_fix_m
= (r
[13] >> 22) & 0x3;
1018 pr
->spn_m
= (r
[13] >> 16) & 0x3f;
1019 pr
->mgnt_vlan_m
= (r
[13] >> 15) & 1;
1020 pr
->dmac_hit_sw_m
= (r
[13] >> 14) & 1;
1021 pr
->not_first_frag_m
= (r
[13] >> 13) & 1;
1022 pr
->frame_type_l4_m
= (r
[13] >> 10) & 7;
1023 pr
->frame_type_m
= (r
[13] >> 8) & 3;
1024 pr
->otag_fmt_m
= (r
[13] >> 7) & 1;
1025 pr
->itag_fmt_m
= (r
[13] >> 6) & 1;
1026 pr
->otag_exist_m
= (r
[13] >> 5) & 1;
1027 pr
->itag_exist_m
= (r
[13] >> 4) & 1;
1028 pr
->frame_type_l2_m
= (r
[13] >> 2) & 3;
1029 pr
->tid_m
= r
[13] & 3;
1031 pr
->valid
= r
[14] & BIT(31);
1032 pr
->cond_not
= r
[14] & BIT(30);
1033 pr
->cond_and1
= r
[14] & BIT(29);
1034 pr
->cond_and2
= r
[14] & BIT(28);
1035 pr
->ivalid
= r
[14] & BIT(27);
1037 pr
->drop
= (r
[17] >> 14) & 3;
1038 pr
->fwd_sel
= r
[17] & BIT(13);
1039 pr
->ovid_sel
= r
[17] & BIT(12);
1040 pr
->ivid_sel
= r
[17] & BIT(11);
1041 pr
->flt_sel
= r
[17] & BIT(10);
1042 pr
->log_sel
= r
[17] & BIT(9);
1043 pr
->rmk_sel
= r
[17] & BIT(8);
1044 pr
->meter_sel
= r
[17] & BIT(7);
1045 pr
->tagst_sel
= r
[17] & BIT(6);
1046 pr
->mir_sel
= r
[17] & BIT(5);
1047 pr
->nopri_sel
= r
[17] & BIT(4);
1048 pr
->cpupri_sel
= r
[17] & BIT(3);
1049 pr
->otpid_sel
= r
[17] & BIT(2);
1050 pr
->itpid_sel
= r
[17] & BIT(1);
1051 pr
->shaper_sel
= r
[17] & BIT(0);
1054 static void rtl838x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1056 r
[6] = ((u32
) (pr
->spmmask_fix
& 0x3)) << 22;
1057 r
[6] |= ((u32
) (pr
->spn
& 0x3f)) << 16;
1058 r
[6] |= pr
->mgnt_vlan
? BIT(15) : 0;
1059 r
[6] |= pr
->dmac_hit_sw
? BIT(14) : 0;
1060 r
[6] |= pr
->not_first_frag
? BIT(13) : 0;
1061 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 10;
1062 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 8;
1063 r
[6] |= pr
->otag_fmt
? BIT(7) : 0;
1064 r
[6] |= pr
->itag_fmt
? BIT(6) : 0;
1065 r
[6] |= pr
->otag_exist
? BIT(5) : 0;
1066 r
[6] |= pr
->itag_exist
? BIT(4) : 0;
1067 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 2;
1068 r
[6] |= ((u32
) (pr
->tid
& 0x3));
1070 r
[13] = ((u32
) (pr
->spmmask_fix_m
& 0x3)) << 22;
1071 r
[13] |= ((u32
) (pr
->spn_m
& 0x3f)) << 16;
1072 r
[13] |= pr
->mgnt_vlan_m
? BIT(15) : 0;
1073 r
[13] |= pr
->dmac_hit_sw_m
? BIT(14) : 0;
1074 r
[13] |= pr
->not_first_frag_m
? BIT(13) : 0;
1075 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 10;
1076 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 8;
1077 r
[13] |= pr
->otag_fmt_m
? BIT(7) : 0;
1078 r
[13] |= pr
->itag_fmt_m
? BIT(6) : 0;
1079 r
[13] |= pr
->otag_exist_m
? BIT(5) : 0;
1080 r
[13] |= pr
->itag_exist_m
? BIT(4) : 0;
1081 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 2;
1082 r
[13] |= ((u32
) (pr
->tid_m
& 0x3));
1084 r
[14] = pr
->valid
? BIT(31) : 0;
1085 r
[14] |= pr
->cond_not
? BIT(30) : 0;
1086 r
[14] |= pr
->cond_and1
? BIT(29) : 0;
1087 r
[14] |= pr
->cond_and2
? BIT(28) : 0;
1088 r
[14] |= pr
->ivalid
? BIT(27) : 0;
1091 r
[17] = 0x1 << 14; // Standard drop action
1094 r
[17] |= pr
->fwd_sel
? BIT(13) : 0;
1095 r
[17] |= pr
->ovid_sel
? BIT(12) : 0;
1096 r
[17] |= pr
->ivid_sel
? BIT(11) : 0;
1097 r
[17] |= pr
->flt_sel
? BIT(10) : 0;
1098 r
[17] |= pr
->log_sel
? BIT(9) : 0;
1099 r
[17] |= pr
->rmk_sel
? BIT(8) : 0;
1100 r
[17] |= pr
->meter_sel
? BIT(7) : 0;
1101 r
[17] |= pr
->tagst_sel
? BIT(6) : 0;
1102 r
[17] |= pr
->mir_sel
? BIT(5) : 0;
1103 r
[17] |= pr
->nopri_sel
? BIT(4) : 0;
1104 r
[17] |= pr
->cpupri_sel
? BIT(3) : 0;
1105 r
[17] |= pr
->otpid_sel
? BIT(2) : 0;
1106 r
[17] |= pr
->itpid_sel
? BIT(1) : 0;
1107 r
[17] |= pr
->shaper_sel
? BIT(0) : 0;
1110 static int rtl838x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1112 u16
*aif
= (u16
*)&r
[17];
1114 int fields_used
= 0;
1118 pr_debug("%s, at %08x\n", __func__
, (u32
)aif
);
1119 /* Multiple actions can be linked to a match of a PIE rule,
1120 * they have different precedence depending on their type and this precedence
1121 * defines which Action Information Field (0-4) in the IACL table stores
1122 * the additional data of the action (like e.g. the port number a packet is
1124 // TODO: count bits in selectors to limit to a maximum number of actions
1125 if (pr
->fwd_sel
) { // Forwarding action
1126 data
= pr
->fwd_act
<< 13;
1127 data
|= pr
->fwd_data
;
1128 data
|= pr
->bypass_all
? BIT(12) : 0;
1129 data
|= pr
->bypass_ibc_sc
? BIT(11) : 0;
1130 data
|= pr
->bypass_igr_stp
? BIT(10) : 0;
1135 if (pr
->ovid_sel
) { // Outer VID action
1136 data
= (pr
->ovid_act
& 0x3) << 12;
1137 data
|= pr
->ovid_data
;
1142 if (pr
->ivid_sel
) { // Inner VID action
1143 data
= (pr
->ivid_act
& 0x3) << 12;
1144 data
|= pr
->ivid_data
;
1149 if (pr
->flt_sel
) { // Filter action
1150 *aif
-- = pr
->flt_data
;
1154 if (pr
->log_sel
) { // Log action
1155 if (fields_used
>= 4)
1157 *aif
-- = pr
->log_data
;
1161 if (pr
->rmk_sel
) { // Remark action
1162 if (fields_used
>= 4)
1164 *aif
-- = pr
->rmk_data
;
1168 if (pr
->meter_sel
) { // Meter action
1169 if (fields_used
>= 4)
1171 *aif
-- = pr
->meter_data
;
1175 if (pr
->tagst_sel
) { // Egress Tag Status action
1176 if (fields_used
>= 4)
1178 *aif
-- = pr
->tagst_data
;
1182 if (pr
->mir_sel
) { // Mirror action
1183 if (fields_used
>= 4)
1185 *aif
-- = pr
->mir_data
;
1189 if (pr
->nopri_sel
) { // Normal Priority action
1190 if (fields_used
>= 4)
1192 *aif
-- = pr
->nopri_data
;
1196 if (pr
->cpupri_sel
) { // CPU Priority action
1197 if (fields_used
>= 4)
1199 *aif
-- = pr
->nopri_data
;
1203 if (pr
->otpid_sel
) { // OTPID action
1204 if (fields_used
>= 4)
1206 *aif
-- = pr
->otpid_data
;
1210 if (pr
->itpid_sel
) { // ITPID action
1211 if (fields_used
>= 4)
1213 *aif
-- = pr
->itpid_data
;
1217 if (pr
->shaper_sel
) { // Traffic shaper action
1218 if (fields_used
>= 4)
1220 *aif
-- = pr
->shaper_data
;
1227 static void rtl838x_read_pie_action(u32 r
[], struct pie_rule
*pr
)
1229 u16
*aif
= (u16
*)&r
[17];
1233 pr_debug("%s, at %08x\n", __func__
, (u32
)aif
);
1235 pr_debug("%s: Action Drop: %d", __func__
, pr
->drop
);
1237 if (pr
->fwd_sel
){ // Forwarding action
1238 pr
->fwd_act
= *aif
>> 13;
1239 pr
->fwd_data
= *aif
--;
1240 pr
->bypass_all
= pr
->fwd_data
& BIT(12);
1241 pr
->bypass_ibc_sc
= pr
->fwd_data
& BIT(11);
1242 pr
->bypass_igr_stp
= pr
->fwd_data
& BIT(10);
1243 if (pr
->bypass_all
|| pr
->bypass_ibc_sc
|| pr
->bypass_igr_stp
)
1244 pr
->bypass_sel
= true;
1246 if (pr
->ovid_sel
) // Outer VID action
1247 pr
->ovid_data
= *aif
--;
1248 if (pr
->ivid_sel
) // Inner VID action
1249 pr
->ivid_data
= *aif
--;
1250 if (pr
->flt_sel
) // Filter action
1251 pr
->flt_data
= *aif
--;
1252 if (pr
->log_sel
) // Log action
1253 pr
->log_data
= *aif
--;
1254 if (pr
->rmk_sel
) // Remark action
1255 pr
->rmk_data
= *aif
--;
1256 if (pr
->meter_sel
) // Meter action
1257 pr
->meter_data
= *aif
--;
1258 if (pr
->tagst_sel
) // Egress Tag Status action
1259 pr
->tagst_data
= *aif
--;
1260 if (pr
->mir_sel
) // Mirror action
1261 pr
->mir_data
= *aif
--;
1262 if (pr
->nopri_sel
) // Normal Priority action
1263 pr
->nopri_data
= *aif
--;
1264 if (pr
->cpupri_sel
) // CPU Priority action
1265 pr
->nopri_data
= *aif
--;
1266 if (pr
->otpid_sel
) // OTPID action
1267 pr
->otpid_data
= *aif
--;
1268 if (pr
->itpid_sel
) // ITPID action
1269 pr
->itpid_data
= *aif
--;
1270 if (pr
->shaper_sel
) // Traffic shaper action
1271 pr
->shaper_data
= *aif
--;
1274 static void rtl838x_pie_rule_dump_raw(u32 r
[])
1276 pr_info("Raw IACL table entry:\n");
1277 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1278 pr_info("Fixed : %08x\n", r
[6]);
1279 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r
[7], r
[8], r
[9], r
[10], r
[11], r
[12]);
1280 pr_info("Fixed M: %08x\n", r
[13]);
1281 pr_info("AIF : %08x %08x %08x\n", r
[14], r
[15], r
[16]);
1282 pr_info("Sel : %08x\n", r
[17]);
1285 static void rtl838x_pie_rule_dump(struct pie_rule
*pr
)
1287 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1288 pr
->drop
, pr
->fwd_sel
, pr
->ovid_sel
, pr
->ivid_sel
, pr
->flt_sel
, pr
->log_sel
, pr
->rmk_sel
, pr
->log_sel
, pr
->tagst_sel
, pr
->mir_sel
, pr
->nopri_sel
,
1289 pr
->cpupri_sel
, pr
->otpid_sel
, pr
->itpid_sel
, pr
->shaper_sel
);
1291 pr_info("FWD: %08x\n", pr
->fwd_data
);
1292 pr_info("TID: %x, %x\n", pr
->tid
, pr
->tid_m
);
1295 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1297 // Read IACL table (1) via register 0
1298 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 1);
1301 int block
= idx
/ PIE_BLOCK_SIZE
;
1302 u32 t_select
= sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
));
1304 memset(pr
, 0, sizeof(*pr
));
1305 rtl_table_read(q
, idx
);
1306 for (i
= 0; i
< 18; i
++)
1307 r
[i
] = sw_r32(rtl_table_data(q
, i
));
1309 rtl_table_release(q
);
1311 rtl838x_read_pie_fixed_fields(r
, pr
);
1315 pr_info("%s: template_selectors %08x, tid: %d\n", __func__
, t_select
, pr
->tid
);
1316 rtl838x_pie_rule_dump_raw(r
);
1318 rtl838x_read_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1320 rtl838x_read_pie_action(r
, pr
);
1325 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1327 // Access IACL table (1) via register 0
1328 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 1);
1331 int block
= idx
/ PIE_BLOCK_SIZE
;
1332 u32 t_select
= sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
));
1334 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1336 for (i
= 0; i
< 18; i
++)
1342 rtl838x_write_pie_fixed_fields(r
, pr
);
1344 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 3)) & 0x7);
1345 rtl838x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1347 if (rtl838x_write_pie_action(r
, pr
)) {
1348 pr_err("Rule actions too complex\n");
1352 // rtl838x_pie_rule_dump_raw(r);
1354 for (i
= 0; i
< 18; i
++)
1355 sw_w32(r
[i
], rtl_table_data(q
, i
));
1358 rtl_table_write(q
, idx
);
1359 rtl_table_release(q
);
1364 static bool rtl838x_pie_templ_has(int t
, enum template_field_id field_type
)
1367 enum template_field_id ft
;
1369 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1370 ft
= fixed_templates
[t
][i
];
1371 if (field_type
== ft
)
1378 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1379 struct pie_rule
*pr
, int t
, int block
)
1383 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1386 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1390 if ((pr
->sip6_m
.s6_addr32
[0] || pr
->sip6_m
.s6_addr32
[1]
1391 || pr
->sip6_m
.s6_addr32
[2] || pr
->sip6_m
.s6_addr32
[3])
1392 && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1394 if ((pr
->dip6_m
.s6_addr32
[0] || pr
->dip6_m
.s6_addr32
[1]
1395 || pr
->dip6_m
.s6_addr32
[2] || pr
->dip6_m
.s6_addr32
[3])
1396 && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1400 if (ether_addr_to_u64(pr
->smac
) && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1403 if (ether_addr_to_u64(pr
->dmac
) && !rtl838x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1408 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1410 if (i
>= PIE_BLOCK_SIZE
)
1413 return i
+ PIE_BLOCK_SIZE
* block
;
1416 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1418 int idx
, block
, j
, t
;
1420 pr_debug("In %s\n", __func__
);
1422 mutex_lock(&priv
->pie_mutex
);
1424 for (block
= 0; block
< priv
->n_pie_blocks
; block
++) {
1425 for (j
= 0; j
< 3; j
++) {
1426 t
= (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block
)) >> (j
* 3)) & 0x7;
1427 pr_debug("Testing block %d, template %d, template id %d\n", block
, j
, t
);
1428 idx
= rtl838x_pie_verify_template(priv
, pr
, t
, block
);
1436 if (block
>= priv
->n_pie_blocks
) {
1437 mutex_unlock(&priv
->pie_mutex
);
1441 pr_debug("Using block: %d, index %d, template-id %d\n", block
, idx
, j
);
1442 set_bit(idx
, priv
->pie_use_bm
);
1445 pr
->tid
= j
; // Mapped to template number
1449 rtl838x_pie_lookup_enable(priv
, idx
);
1450 rtl838x_pie_rule_write(priv
, idx
, pr
);
1452 mutex_unlock(&priv
->pie_mutex
);
1456 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1460 rtl838x_pie_rule_del(priv
, idx
, idx
);
1461 clear_bit(idx
, priv
->pie_use_bm
);
1465 * Initializes the Packet Inspection Engine:
1466 * powers it up, enables default matching templates for all blocks
1467 * and clears all rules possibly installed by u-boot
1469 static void rtl838x_pie_init(struct rtl838x_switch_priv
*priv
)
1472 u32 template_selectors
;
1474 mutex_init(&priv
->pie_mutex
);
1476 // Enable ACL lookup on all ports, including CPU_PORT
1477 for (i
= 0; i
<= priv
->cpu_port
; i
++)
1478 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i
));
1480 // Power on all PIE blocks
1481 for (i
= 0; i
< priv
->n_pie_blocks
; i
++)
1482 sw_w32_mask(0, BIT(i
), RTL838X_ACL_BLK_PWR_CTRL
);
1484 // Include IPG in metering
1485 sw_w32(1, RTL838X_METER_GLB_CTRL
);
1487 // Delete all present rules
1488 rtl838x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* PIE_BLOCK_SIZE
- 1);
1490 // Routing bypasses source port filter: disable write-protection, first
1491 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL
);
1492 sw_w32_mask(0, 1, RTL838X_DMY_REG27
);
1493 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL
);
1495 // Enable predefined templates 0, 1 and 2 for even blocks
1496 template_selectors
= 0 | (1 << 3) | (2 << 6);
1497 for (i
= 0; i
< 6; i
+= 2)
1498 sw_w32(template_selectors
, RTL838X_ACL_BLK_TMPLTE_CTRL(i
));
1500 // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
1501 template_selectors
= 0 | (3 << 3) | (4 << 6);
1502 for (i
= 1; i
< priv
->n_pie_blocks
; i
+= 2)
1503 sw_w32(template_selectors
, RTL838X_ACL_BLK_TMPLTE_CTRL(i
));
1505 // Group each pair of physical blocks together to a logical block
1506 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL
);
1509 static u32
rtl838x_packet_cntr_read(int counter
)
1513 // Read LOG table (3) via register RTL8380_TBL_0
1514 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 3);
1516 pr_debug("In %s, id %d\n", __func__
, counter
);
1517 rtl_table_read(r
, counter
/ 2);
1519 pr_debug("Registers: %08x %08x\n",
1520 sw_r32(rtl_table_data(r
, 0)), sw_r32(rtl_table_data(r
, 1)));
1521 // The table has a size of 2 registers
1523 v
= sw_r32(rtl_table_data(r
, 0));
1525 v
= sw_r32(rtl_table_data(r
, 1));
1527 rtl_table_release(r
);
1532 static void rtl838x_packet_cntr_clear(int counter
)
1534 // Access LOG table (3) via register RTL8380_TBL_0
1535 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 3);
1537 pr_debug("In %s, id %d\n", __func__
, counter
);
1538 // The table has a size of 2 registers
1540 sw_w32(0, rtl_table_data(r
, 0));
1542 sw_w32(0, rtl_table_data(r
, 1));
1544 rtl_table_write(r
, counter
/ 2);
1546 rtl_table_release(r
);
1549 static void rtl838x_route_read(int idx
, struct rtl83xx_route
*rt
)
1551 // Read ROUTING table (2) via register RTL8380_TBL_1
1552 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 2);
1554 pr_debug("In %s, id %d\n", __func__
, idx
);
1555 rtl_table_read(r
, idx
);
1557 // The table has a size of 2 registers
1558 rt
->nh
.gw
= sw_r32(rtl_table_data(r
, 0));
1560 rt
->nh
.gw
|= sw_r32(rtl_table_data(r
, 1));
1562 rtl_table_release(r
);
1565 static void rtl838x_route_write(int idx
, struct rtl83xx_route
*rt
)
1567 // Access ROUTING table (2) via register RTL8380_TBL_1
1568 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 2);
1570 pr_debug("In %s, id %d, gw: %016llx\n", __func__
, idx
, rt
->nh
.gw
);
1571 sw_w32(rt
->nh
.gw
>> 32, rtl_table_data(r
, 0));
1572 sw_w32(rt
->nh
.gw
, rtl_table_data(r
, 1));
1573 rtl_table_write(r
, idx
);
1575 rtl_table_release(r
);
1578 static int rtl838x_l3_setup(struct rtl838x_switch_priv
*priv
)
1580 // Nothing to be done
1584 const struct rtl838x_reg rtl838x_reg
= {
1585 .mask_port_reg_be
= rtl838x_mask_port_reg
,
1586 .set_port_reg_be
= rtl838x_set_port_reg
,
1587 .get_port_reg_be
= rtl838x_get_port_reg
,
1588 .mask_port_reg_le
= rtl838x_mask_port_reg
,
1589 .set_port_reg_le
= rtl838x_set_port_reg
,
1590 .get_port_reg_le
= rtl838x_get_port_reg
,
1591 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
1592 .stat_rst
= RTL838X_STAT_RST
,
1593 .stat_port_std_mib
= RTL838X_STAT_PORT_STD_MIB
,
1594 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
1595 .traffic_enable
= rtl838x_traffic_enable
,
1596 .traffic_disable
= rtl838x_traffic_disable
,
1597 .traffic_get
= rtl838x_traffic_get
,
1598 .traffic_set
= rtl838x_traffic_set
,
1599 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
1600 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
1601 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
1602 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
1603 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
1604 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
1605 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
1606 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
1607 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
1608 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
1609 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
1610 .imr_glb
= RTL838X_IMR_GLB
,
1611 .vlan_tables_read
= rtl838x_vlan_tables_read
,
1612 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
1613 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
1614 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
1615 .vlan_profile_dump
= rtl838x_vlan_profile_dump
,
1616 .vlan_profile_setup
= rtl838x_vlan_profile_setup
,
1617 .vlan_fwd_on_inner
= rtl838x_vlan_fwd_on_inner
,
1618 .stp_get
= rtl838x_stp_get
,
1619 .stp_set
= rtl838x_stp_set
,
1620 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
1621 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
1622 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
1623 .mir_ctrl
= RTL838X_MIR_CTRL
,
1624 .mir_dpm
= RTL838X_MIR_DPM_CTRL
,
1625 .mir_spm
= RTL838X_MIR_SPM_CTRL
,
1626 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
1627 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
1628 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
1629 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
1630 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
1631 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
1632 .write_l2_entry_using_hash
= rtl838x_write_l2_entry_using_hash
,
1633 .read_cam
= rtl838x_read_cam
,
1634 .write_cam
= rtl838x_write_cam
,
1635 .vlan_port_egr_filter
= RTL838X_VLAN_PORT_EGR_FLTR
,
1636 .vlan_port_igr_filter
= RTL838X_VLAN_PORT_IGR_FLTR
,
1637 .vlan_port_pb
= RTL838X_VLAN_PORT_PB_VLAN
,
1638 .vlan_port_tag_sts_ctrl
= RTL838X_VLAN_PORT_TAG_STS_CTRL
,
1639 .trk_mbr_ctr
= rtl838x_trk_mbr_ctr
,
1640 .rma_bpdu_fld_pmask
= RTL838X_RMA_BPDU_FLD_PMSK
,
1641 .spcl_trap_eapol_ctrl
= RTL838X_SPCL_TRAP_EAPOL_CTRL
,
1642 .init_eee
= rtl838x_init_eee
,
1643 .port_eee_set
= rtl838x_port_eee_set
,
1644 .eee_port_ability
= rtl838x_eee_port_ability
,
1645 .l2_hash_seed
= rtl838x_l2_hash_seed
,
1646 .l2_hash_key
= rtl838x_l2_hash_key
,
1647 .read_mcast_pmask
= rtl838x_read_mcast_pmask
,
1648 .write_mcast_pmask
= rtl838x_write_mcast_pmask
,
1649 .pie_init
= rtl838x_pie_init
,
1650 .pie_rule_read
= rtl838x_pie_rule_read
,
1651 .pie_rule_write
= rtl838x_pie_rule_write
,
1652 .pie_rule_add
= rtl838x_pie_rule_add
,
1653 .pie_rule_rm
= rtl838x_pie_rule_rm
,
1654 .l2_learning_setup
= rtl838x_l2_learning_setup
,
1655 .packet_cntr_read
= rtl838x_packet_cntr_read
,
1656 .packet_cntr_clear
= rtl838x_packet_cntr_clear
,
1657 .route_read
= rtl838x_route_read
,
1658 .route_write
= rtl838x_route_write
,
1659 .l3_setup
= rtl838x_l3_setup
,
1662 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
1664 struct dsa_switch
*ds
= dev_id
;
1665 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
1666 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
1671 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
1672 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
1674 for (i
= 0; i
< 28; i
++) {
1675 if (ports
& BIT(i
)) {
1676 link
= sw_r32(RTL838X_MAC_LINK_STS
);
1678 dsa_port_phylink_mac_change(ds
, i
, true);
1680 dsa_port_phylink_mac_change(ds
, i
, false);
1686 int rtl838x_smi_wait_op(int timeout
)
1691 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & 0x1) && (timeout
>= 0));
1698 * Reads a register in a page from the PHY
1700 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
1710 if (page
> 4095 || reg
> 31)
1713 mutex_lock(&smi_lock
);
1715 if (rtl838x_smi_wait_op(10000))
1718 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1720 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
1721 v
= reg
<< 20 | page
<< 3;
1722 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1723 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1725 if (rtl838x_smi_wait_op(10000))
1728 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1730 mutex_unlock(&smi_lock
);
1734 mutex_unlock(&smi_lock
);
1739 * Write to a register in a page of the PHY
1741 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
1747 if (port
> 31 || page
> 4095 || reg
> 31)
1750 mutex_lock(&smi_lock
);
1751 if (rtl838x_smi_wait_op(10000))
1754 sw_w32(BIT(port
), RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1757 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1759 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
1760 v
= reg
<< 20 | page
<< 3 | 0x4;
1761 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1762 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1764 if (rtl838x_smi_wait_op(10000))
1767 mutex_unlock(&smi_lock
);
1771 mutex_unlock(&smi_lock
);
1776 * Read an mmd register of a PHY
1778 int rtl838x_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
1782 mutex_lock(&smi_lock
);
1784 if (rtl838x_smi_wait_op(10000))
1787 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1790 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1792 v
= addr
<< 16 | reg
;
1793 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1795 /* mmd-access | read | cmd-start */
1796 v
= 1 << 1 | 0 << 2 | 1;
1797 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1799 if (rtl838x_smi_wait_op(10000))
1802 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1804 mutex_unlock(&smi_lock
);
1808 mutex_unlock(&smi_lock
);
1813 * Write to an mmd register of a PHY
1815 int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
1819 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
1821 mutex_lock(&smi_lock
);
1823 if (rtl838x_smi_wait_op(10000))
1826 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1829 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1831 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1832 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1833 /* mmd-access | write | cmd-start */
1834 v
= 1 << 1 | 1 << 2 | 1;
1835 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1837 if (rtl838x_smi_wait_op(10000))
1840 mutex_unlock(&smi_lock
);
1844 mutex_unlock(&smi_lock
);
1848 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
1850 u32 rw_save
, info_save
;
1853 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
1854 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
1856 info_save
= sw_r32(RTL838X_CHIP_INFO
);
1857 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
1859 info
= sw_r32(RTL838X_CHIP_INFO
);
1860 sw_w32(info_save
, RTL838X_CHIP_INFO
);
1861 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
1863 if ((info
& 0xFFFF) == 0x6275) {
1864 if (((info
>> 16) & 0x1F) == 0x1)
1865 priv
->version
= RTL8380_VERSION_A
;
1866 else if (((info
>> 16) & 0x1F) == 0x2)
1867 priv
->version
= RTL8380_VERSION_B
;
1869 priv
->version
= RTL8380_VERSION_B
;
1871 priv
->version
= '-';
1875 void rtl838x_vlan_profile_dump(int profile
)
1879 if (profile
< 0 || profile
> 7)
1882 p
= sw_r32(RTL838X_VLAN_PROFILE(profile
));
1884 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
1885 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
1886 profile
, p
& 1, (p
>> 1) & 0x1ff, (p
>> 10) & 0x1ff, (p
>> 19) & 0x1ff);
1889 void rtl8380_sds_rst(int mac
)
1891 u32 offset
= (mac
== 24) ? 0 : 0x100;
1893 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0
+ offset
);
1894 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28
+ offset
);
1895 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28
+ offset
);
1896 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0
+ offset
);
1897 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0
+ offset
);
1898 pr_debug("SERDES reset: %d\n", mac
);
1901 int rtl8380_sds_power(int mac
, int val
)
1903 u32 mode
= (val
== 1) ? 0x4 : 0x9;
1904 u32 offset
= (mac
== 24) ? 5 : 0;
1906 if ((mac
!= 24) && (mac
!= 26)) {
1907 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
1911 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
1913 rtl8380_sds_rst(mac
);