1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6 extern struct mutex smi_lock
;
8 void rtl838x_print_matrix(void)
10 unsigned volatile int *ptr8
;
13 ptr8
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
14 for (i
= 0; i
< 28; i
+= 8)
15 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
16 ptr8
[i
+ 0], ptr8
[i
+ 1], ptr8
[i
+ 2], ptr8
[i
+ 3],
17 ptr8
[i
+ 4], ptr8
[i
+ 5], ptr8
[i
+ 6], ptr8
[i
+ 7]);
18 pr_debug("CPU_PORT> %8x\n", ptr8
[28]);
21 static inline int rtl838x_port_iso_ctrl(int p
)
23 return RTL838X_PORT_ISO_CTRL(p
);
26 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
28 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
29 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & BIT(15));
32 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
34 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
35 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & BIT(15));
38 static inline int rtl838x_tbl_access_data_0(int i
)
40 return RTL838X_TBL_ACCESS_DATA_0(i
);
43 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
46 // Read VLAN table (0) via register 0
47 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
49 rtl_table_read(r
, vlan
);
50 info
->tagged_ports
= sw_r32(rtl_table_data(r
, 0));
51 v
= sw_r32(rtl_table_data(r
, 1));
52 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan
, info
->tagged_ports
, v
);
55 info
->profile_id
= v
& 0x7;
56 info
->hash_mc_fid
= !!(v
& 0x8);
57 info
->hash_uc_fid
= !!(v
& 0x10);
58 info
->fid
= (v
>> 5) & 0x3f;
60 // Read UNTAG table (0) via table register 1
61 r
= rtl_table_get(RTL8380_TBL_1
, 0);
62 rtl_table_read(r
, vlan
);
63 info
->untagged_ports
= sw_r32(rtl_table_data(r
, 0));
67 static void rtl838x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
70 // Access VLAN table (0) via register 0
71 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
73 sw_w32(info
->tagged_ports
, rtl_table_data(r
, 0));
76 v
|= info
->hash_mc_fid
? 0x8 : 0;
77 v
|= info
->hash_uc_fid
? 0x10 : 0;
78 v
|= ((u32
)info
->fid
) << 5;
79 sw_w32(v
, rtl_table_data(r
, 1));
81 rtl_table_write(r
, vlan
);
85 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
87 // Access UNTAG table (0) via register 1
88 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 0);
90 sw_w32(portmask
& 0x1fffffff, rtl_table_data(r
, 0));
91 rtl_table_write(r
, vlan
);
95 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
97 static void rtl838x_vlan_fwd_on_inner(int port
, bool is_set
)
100 sw_w32_mask(BIT(port
), 0, RTL838X_VLAN_PORT_FWD
);
102 sw_w32_mask(0, BIT(port
), RTL838X_VLAN_PORT_FWD
);
105 static u64
rtl838x_l2_hash_seed(u64 mac
, u32 vid
)
107 return mac
<< 12 | vid
;
111 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
112 * and returns a key into the L2 hash table
114 static u32
rtl838x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
118 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
119 h1
= (seed
>> 11) & 0x7ff;
120 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
122 h2
= (seed
>> 33) & 0x7ff;
123 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
125 h3
= (seed
>> 44) & 0x7ff;
126 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
128 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
129 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
131 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
132 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
133 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
139 static inline int rtl838x_mac_force_mode_ctrl(int p
)
141 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
144 static inline int rtl838x_mac_port_ctrl(int p
)
146 return RTL838X_MAC_PORT_CTRL(p
);
149 static inline int rtl838x_l2_port_new_salrn(int p
)
151 return RTL838X_L2_PORT_NEW_SALRN(p
);
154 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
156 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
159 static inline int rtl838x_mac_link_spd_sts(int p
)
161 return RTL838X_MAC_LINK_SPD_STS(p
);
164 inline static int rtl838x_trk_mbr_ctr(int group
)
166 return RTL838X_TRK_MBR_CTR
+ (group
<< 2);
170 * Fills an L2 entry structure from the SoC registers
172 static void rtl838x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
174 /* Table contains different entry types, we need to identify the right one:
175 * Check for MC entries, first
176 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
177 * identify valid entries
179 e
->is_ip_mc
= !!(r
[0] & BIT(22));
180 e
->is_ipv6_mc
= !!(r
[0] & BIT(21));
181 e
->type
= L2_INVALID
;
183 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
184 e
->mac
[0] = (r
[1] >> 20);
185 e
->mac
[1] = (r
[1] >> 12);
186 e
->mac
[2] = (r
[1] >> 4);
187 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
188 e
->mac
[4] = (r
[2] >> 20);
189 e
->mac
[5] = (r
[2] >> 12);
191 e
->rvid
= r
[2] & 0xfff;
192 e
->vid
= r
[0] & 0xfff;
194 /* Is it a unicast entry? check multicast bit */
195 if (!(e
->mac
[0] & 1)) {
196 e
->is_static
= !!((r
[0] >> 19) & 1);
197 e
->port
= (r
[0] >> 12) & 0x1f;
198 e
->block_da
= !!(r
[1] & BIT(30));
199 e
->block_sa
= !!(r
[1] & BIT(31));
200 e
->suspended
= !!(r
[1] & BIT(29));
201 e
->next_hop
= !!(r
[1] & BIT(28));
203 pr_info("Found next hop entry, need to read extra data\n");
204 e
->nh_vlan_target
= !!(r
[0] & BIT(9));
205 e
->nh_route_id
= r
[0] & 0x1ff;
207 e
->age
= (r
[0] >> 17) & 0x3;
210 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
211 * next-hop or static entry bit set */
212 if (!(r
[0] & 0x007c0000) && !(r
[1] & 0xd0000000))
215 e
->type
= L2_UNICAST
;
216 } else { // L2 multicast
217 pr_info("Got L2 MC entry: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
219 e
->type
= L2_MULTICAST
;
220 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
222 } else { // IPv4 and IPv6 multicast
224 e
->mc_portmask_index
= (r
[0] >> 12) & 0x1ff;
227 e
->rvid
= r
[0] & 0xfff;
230 e
->type
= IP4_MULTICAST
;
232 e
->type
= IP6_MULTICAST
;
236 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
238 static void rtl838x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
240 u64 mac
= ether_addr_to_u64(e
->mac
);
243 r
[0] = r
[1] = r
[2] = 0;
247 r
[0] = e
->is_ip_mc
? BIT(22) : 0;
248 r
[0] |= e
->is_ipv6_mc
? BIT(21) : 0;
250 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
252 r
[2] = (mac
& 0xfffff) << 12;
254 /* Is it a unicast entry? check multicast bit */
255 if (!(e
->mac
[0] & 1)) {
256 r
[0] |= e
->is_static
? BIT(19) : 0;
257 r
[0] |= (e
->port
& 0x3f) << 12;
259 r
[1] |= e
->block_da
? BIT(30) : 0;
260 r
[1] |= e
->block_sa
? BIT(31) : 0;
261 r
[1] |= e
->suspended
? BIT(29) : 0;
262 r
[2] |= e
->rvid
& 0xfff;
265 r
[0] |= e
->nh_vlan_target
? BIT(9) : 0;
266 r
[0] |= e
->nh_route_id
&0x1ff;
268 r
[0] |= (e
->age
& 0x3) << 17;
269 } else { // L2 Multicast
270 r
[0] |= (e
->mc_portmask_index
& 0x1ff) << 12;
271 r
[2] |= e
->rvid
& 0xfff;
272 r
[0] |= e
->vid
& 0xfff;
273 pr_info("FILL MC: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
275 } else { // IPv4 and IPv6 multicast
283 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
284 * hash is the id of the bucket and pos is the position of the entry in that bucket
285 * The data read from the SoC is filled into rtl838x_l2_entry
287 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
291 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0); // Access L2 Table 0
292 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
295 rtl_table_read(q
, idx
);
296 for (i
= 0; i
< 3; i
++)
297 r
[i
] = sw_r32(rtl_table_data(q
, i
));
299 rtl_table_release(q
);
301 rtl838x_fill_l2_entry(r
, e
);
305 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
309 static void rtl838x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
312 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 0);
315 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
317 rtl838x_fill_l2_row(r
, e
);
319 for (i
= 0; i
< 3; i
++)
320 sw_w32(r
[i
], rtl_table_data(q
, i
));
322 rtl_table_write(q
, idx
);
323 rtl_table_release(q
);
326 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
330 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
333 rtl_table_read(q
, idx
);
334 for (i
= 0; i
< 3; i
++)
335 r
[i
] = sw_r32(rtl_table_data(q
, i
));
337 rtl_table_release(q
);
339 rtl838x_fill_l2_entry(r
, e
);
343 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
345 // Return MAC with concatenated VID ac concatenated ID
346 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
350 static void rtl838x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
353 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 1); // Access L2 Table 1
356 rtl838x_fill_l2_row(r
, e
);
358 for (i
= 0; i
< 3; i
++)
359 sw_w32(r
[i
], rtl_table_data(q
, i
));
361 rtl_table_write(q
, idx
);
362 rtl_table_release(q
);
365 static u64
rtl838x_read_mcast_pmask(int idx
)
368 // Read MC_PMSK (2) via register RTL8380_TBL_L2
369 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
371 rtl_table_read(q
, idx
);
372 portmask
= sw_r32(rtl_table_data(q
, 0));
373 rtl_table_release(q
);
378 static void rtl838x_write_mcast_pmask(int idx
, u64 portmask
)
380 // Access MC_PMSK (2) via register RTL8380_TBL_L2
381 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
383 sw_w32(((u32
)portmask
) & 0x1fffffff, rtl_table_data(q
, 0));
384 rtl_table_write(q
, idx
);
385 rtl_table_release(q
);
388 static void rtl838x_vlan_profile_setup(int profile
)
390 u32 pmask_id
= UNKNOWN_MC_PMASK
;
391 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
392 u32 p
= 1 | pmask_id
<< 1 | pmask_id
<< 10 | pmask_id
<< 19;
394 sw_w32(p
, RTL838X_VLAN_PROFILE(profile
));
396 /* RTL8380 and RTL8390 use an index into the portmask table to set the
397 * unknown multicast portmask, setup a default at a safe location
398 * On RTL93XX, the portmask is directly set in the profile,
399 * see e.g. rtl9300_vlan_profile_setup
401 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x1fffffff);
404 static inline int rtl838x_vlan_port_egr_filter(int port
)
406 return RTL838X_VLAN_PORT_EGR_FLTR
;
409 static inline int rtl838x_vlan_port_igr_filter(int port
)
411 return RTL838X_VLAN_PORT_IGR_FLTR(port
);
414 static void rtl838x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
417 u32 cmd
= 1 << 15 /* Execute cmd */
419 | 2 << 12 /* Table type 0b10 */
421 priv
->r
->exec_tbl0_cmd(cmd
);
423 for (i
= 0; i
< 2; i
++)
424 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
427 static void rtl838x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
430 u32 cmd
= 1 << 15 /* Execute cmd */
431 | 0 << 14 /* Write */
432 | 2 << 12 /* Table type 0b10 */
435 for (i
= 0; i
< 2; i
++)
436 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
437 priv
->r
->exec_tbl0_cmd(cmd
);
440 u64
rtl838x_traffic_get(int source
)
442 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source
));
445 void rtl838x_traffic_set(int source
, u64 dest_matrix
)
447 rtl838x_set_port_reg(dest_matrix
, rtl838x_port_iso_ctrl(source
));
450 void rtl838x_traffic_enable(int source
, int dest
)
452 rtl838x_mask_port_reg(0, BIT(dest
), rtl838x_port_iso_ctrl(source
));
455 void rtl838x_traffic_disable(int source
, int dest
)
457 rtl838x_mask_port_reg(BIT(dest
), 0, rtl838x_port_iso_ctrl(source
));
461 * Enables or disables the EEE/EEEP capability of a port
463 static void rtl838x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
467 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
471 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
472 v
= enable
? 0x3 : 0x0;
474 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
475 sw_w32_mask(0x3 << 9, v
<< 9, priv
->r
->mac_force_mode_ctrl(port
));
477 // Set TX/RX EEE state
479 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_TX_EN
);
480 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_RX_EN
);
482 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_TX_EN
);
483 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_RX_EN
);
485 priv
->ports
[port
].eee_enabled
= enable
;
490 * Get EEE own capabilities and negotiation result
492 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv
*priv
,
493 struct ethtool_eee
*e
, int port
)
500 link
= rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS
);
501 if (!(link
& BIT(port
)))
504 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(9))
505 e
->advertised
|= ADVERTISED_100baseT_Full
;
507 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(10))
508 e
->advertised
|= ADVERTISED_1000baseT_Full
;
510 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & BIT(port
)) {
511 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
512 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
519 static void rtl838x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
523 pr_info("Setting up EEE, state: %d\n", enable
);
524 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
526 /* Set timers for EEE */
527 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
528 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
530 // Enable EEE MAC support on ports
531 for (i
= 0; i
< priv
->cpu_port
; i
++) {
532 if (priv
->ports
[i
].phy
)
533 rtl838x_port_eee_set(priv
, i
, enable
);
535 priv
->eee_enabled
= enable
;
538 const struct rtl838x_reg rtl838x_reg
= {
539 .mask_port_reg_be
= rtl838x_mask_port_reg
,
540 .set_port_reg_be
= rtl838x_set_port_reg
,
541 .get_port_reg_be
= rtl838x_get_port_reg
,
542 .mask_port_reg_le
= rtl838x_mask_port_reg
,
543 .set_port_reg_le
= rtl838x_set_port_reg
,
544 .get_port_reg_le
= rtl838x_get_port_reg
,
545 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
546 .stat_rst
= RTL838X_STAT_RST
,
547 .stat_port_std_mib
= RTL838X_STAT_PORT_STD_MIB
,
548 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
549 .traffic_enable
= rtl838x_traffic_enable
,
550 .traffic_disable
= rtl838x_traffic_disable
,
551 .traffic_get
= rtl838x_traffic_get
,
552 .traffic_set
= rtl838x_traffic_set
,
553 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
554 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
555 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
556 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
557 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
558 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
559 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
560 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
561 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
562 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
563 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
564 .imr_glb
= RTL838X_IMR_GLB
,
565 .vlan_tables_read
= rtl838x_vlan_tables_read
,
566 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
567 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
568 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
569 .vlan_profile_dump
= rtl838x_vlan_profile_dump
,
570 .vlan_profile_setup
= rtl838x_vlan_profile_setup
,
571 .vlan_fwd_on_inner
= rtl838x_vlan_fwd_on_inner
,
572 .stp_get
= rtl838x_stp_get
,
573 .stp_set
= rtl838x_stp_set
,
574 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
575 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
576 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
577 .mir_ctrl
= RTL838X_MIR_CTRL
,
578 .mir_dpm
= RTL838X_MIR_DPM_CTRL
,
579 .mir_spm
= RTL838X_MIR_SPM_CTRL
,
580 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
581 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
582 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
583 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
584 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
585 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
586 .write_l2_entry_using_hash
= rtl838x_write_l2_entry_using_hash
,
587 .read_cam
= rtl838x_read_cam
,
588 .write_cam
= rtl838x_write_cam
,
589 .vlan_port_egr_filter
= RTL838X_VLAN_PORT_EGR_FLTR
,
590 .vlan_port_igr_filter
= RTL838X_VLAN_PORT_IGR_FLTR(0),
591 .vlan_port_pb
= RTL838X_VLAN_PORT_PB_VLAN
,
592 .vlan_port_tag_sts_ctrl
= RTL838X_VLAN_PORT_TAG_STS_CTRL
,
593 .trk_mbr_ctr
= rtl838x_trk_mbr_ctr
,
594 .rma_bpdu_fld_pmask
= RTL838X_RMA_BPDU_FLD_PMSK
,
595 .spcl_trap_eapol_ctrl
= RTL838X_SPCL_TRAP_EAPOL_CTRL
,
596 .init_eee
= rtl838x_init_eee
,
597 .port_eee_set
= rtl838x_port_eee_set
,
598 .eee_port_ability
= rtl838x_eee_port_ability
,
599 .l2_hash_seed
= rtl838x_l2_hash_seed
,
600 .l2_hash_key
= rtl838x_l2_hash_key
,
601 .read_mcast_pmask
= rtl838x_read_mcast_pmask
,
602 .write_mcast_pmask
= rtl838x_write_mcast_pmask
,
605 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
607 struct dsa_switch
*ds
= dev_id
;
608 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
609 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
614 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
615 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
617 for (i
= 0; i
< 28; i
++) {
618 if (ports
& BIT(i
)) {
619 link
= sw_r32(RTL838X_MAC_LINK_STS
);
621 dsa_port_phylink_mac_change(ds
, i
, true);
623 dsa_port_phylink_mac_change(ds
, i
, false);
629 int rtl838x_smi_wait_op(int timeout
)
634 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & 0x1) && (timeout
>= 0));
641 * Reads a register in a page from the PHY
643 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
653 if (page
> 4095 || reg
> 31)
656 mutex_lock(&smi_lock
);
658 if (rtl838x_smi_wait_op(10000))
661 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
663 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
664 v
= reg
<< 20 | page
<< 3;
665 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
666 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
668 if (rtl838x_smi_wait_op(10000))
671 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
673 mutex_unlock(&smi_lock
);
677 mutex_unlock(&smi_lock
);
682 * Write to a register in a page of the PHY
684 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
690 if (port
> 31 || page
> 4095 || reg
> 31)
693 mutex_lock(&smi_lock
);
694 if (rtl838x_smi_wait_op(10000))
697 sw_w32(BIT(port
), RTL838X_SMI_ACCESS_PHY_CTRL_0
);
700 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
702 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
703 v
= reg
<< 20 | page
<< 3 | 0x4;
704 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
705 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
707 if (rtl838x_smi_wait_op(10000))
710 mutex_unlock(&smi_lock
);
714 mutex_unlock(&smi_lock
);
719 * Read an mmd register of a PHY
721 int rtl838x_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
725 mutex_lock(&smi_lock
);
727 if (rtl838x_smi_wait_op(10000))
730 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
733 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
735 v
= addr
<< 16 | reg
;
736 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
738 /* mmd-access | read | cmd-start */
739 v
= 1 << 1 | 0 << 2 | 1;
740 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
742 if (rtl838x_smi_wait_op(10000))
745 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
747 mutex_unlock(&smi_lock
);
751 mutex_unlock(&smi_lock
);
756 * Write to an mmd register of a PHY
758 int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
762 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
764 mutex_lock(&smi_lock
);
766 if (rtl838x_smi_wait_op(10000))
769 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
772 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
774 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
775 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
776 /* mmd-access | write | cmd-start */
777 v
= 1 << 1 | 1 << 2 | 1;
778 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
780 if (rtl838x_smi_wait_op(10000))
783 mutex_unlock(&smi_lock
);
787 mutex_unlock(&smi_lock
);
791 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
793 u32 rw_save
, info_save
;
796 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
797 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
799 info_save
= sw_r32(RTL838X_CHIP_INFO
);
800 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
802 info
= sw_r32(RTL838X_CHIP_INFO
);
803 sw_w32(info_save
, RTL838X_CHIP_INFO
);
804 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
806 if ((info
& 0xFFFF) == 0x6275) {
807 if (((info
>> 16) & 0x1F) == 0x1)
808 priv
->version
= RTL8380_VERSION_A
;
809 else if (((info
>> 16) & 0x1F) == 0x2)
810 priv
->version
= RTL8380_VERSION_B
;
812 priv
->version
= RTL8380_VERSION_B
;
818 void rtl838x_vlan_profile_dump(int profile
)
822 if (profile
< 0 || profile
> 7)
825 p
= sw_r32(RTL838X_VLAN_PROFILE(profile
));
827 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
828 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
829 profile
, p
& 1, (p
>> 1) & 0x1ff, (p
>> 10) & 0x1ff, (p
>> 19) & 0x1ff);
832 void rtl8380_sds_rst(int mac
)
834 u32 offset
= (mac
== 24) ? 0 : 0x100;
836 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0
+ offset
);
837 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28
+ offset
);
838 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28
+ offset
);
839 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0
+ offset
);
840 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0
+ offset
);
841 pr_debug("SERDES reset: %d\n", mac
);
844 int rtl8380_sds_power(int mac
, int val
)
846 u32 mode
= (val
== 1) ? 0x4 : 0x9;
847 u32 offset
= (mac
== 24) ? 5 : 0;
849 if ((mac
!= 24) && (mac
!= 26)) {
850 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
854 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
856 rtl8380_sds_rst(mac
);