1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
12 #define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
13 #define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6)))
14 #define RTL931X_MAC_PORT_CTRL (0x6004)
16 #define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6)))
17 #define RTL931X_MAC_L2_PORT_CTRL (0x6000)
19 #define RTL838X_RST_GLB_CTRL_0 (0x003c)
21 #define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
22 #define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
23 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
24 #define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC)
26 #define RTL838X_DMY_REG31 (0x3b28)
27 #define RTL838X_SDS_MODE_SEL (0x0028)
28 #define RTL838X_SDS_CFG_REG (0x0034)
29 #define RTL838X_INT_MODE_CTRL (0x005c)
30 #define RTL838X_CHIP_INFO (0x00d8)
31 #define RTL839X_CHIP_INFO (0x0ff4)
32 #define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
33 #define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
35 /* Packet statistics */
36 #define RTL838X_STAT_PORT_STD_MIB (0x1200)
37 #define RTL839X_STAT_PORT_STD_MIB (0xC000)
38 #define RTL930X_STAT_PORT_MIB_CNTR (0x0664)
39 #define RTL838X_STAT_RST (0x3100)
40 #define RTL839X_STAT_RST (0xF504)
41 #define RTL930X_STAT_RST (0x3240)
42 #define RTL931X_STAT_RST (0x7ef4)
43 #define RTL838X_STAT_PORT_RST (0x3104)
44 #define RTL839X_STAT_PORT_RST (0xF508)
45 #define RTL930X_STAT_PORT_RST (0x3244)
46 #define RTL931X_STAT_PORT_RST (0x7ef8)
47 #define RTL838X_STAT_CTRL (0x3108)
48 #define RTL839X_STAT_CTRL (0x04cc)
49 #define RTL930X_STAT_CTRL (0x3248)
50 #define RTL931X_STAT_CTRL (0x5720)
52 /* Registers of the internal Serdes of the 8390 */
53 #define RTL8390_SDS0_1_XSG0 (0xA000)
54 #define RTL8390_SDS0_1_XSG1 (0xA100)
55 #define RTL839X_SDS12_13_XSG0 (0xB800)
56 #define RTL839X_SDS12_13_XSG1 (0xB900)
57 #define RTL839X_SDS12_13_PWR0 (0xb880)
58 #define RTL839X_SDS12_13_PWR1 (0xb980)
60 /* Registers of the internal Serdes of the 8380 */
61 #define RTL838X_SDS4_FIB_REG0 (0xF800)
62 #define RTL838X_SDS4_REG28 (0xef80)
63 #define RTL838X_SDS4_DUMMY0 (0xef8c)
64 #define RTL838X_SDS5_EXT_REG6 (0xf18c)
67 #define RTL838X_VLAN_CTRL (0x3A74)
68 #define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
69 #define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
70 #define RTL838X_VLAN_PORT_PB_VLAN (0x3C00)
71 #define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C)
73 #define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3)))
74 #define RTL839X_VLAN_CTRL (0x26D4)
75 #define RTL839X_VLAN_PORT_PB_VLAN (0x26D8)
76 #define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4)
77 #define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4)
79 #define RTL930X_VLAN_PROFILE_SET(idx) (0x9c60 + (((idx) * 20)))
80 #define RTL930X_VLAN_CTRL (0x82D4)
81 #define RTL930X_VLAN_PORT_PB_VLAN (0x82D8)
82 #define RTL930X_VLAN_PORT_IGR_FLTR (0x83C0)
83 #define RTL930X_VLAN_PORT_EGR_FLTR (0x83C8)
85 #define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28)))
86 #define RTL931X_VLAN_CTRL (0x94E4)
87 #define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8)
88 #define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4)
89 #define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4)
91 /* Table access registers */
92 #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
93 #define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
94 #define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
95 #define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
97 #define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
98 #define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2))
99 #define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
100 #define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
101 #define RTL839X_TBL_ACCESS_CTRL_2 (0x611C)
102 #define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2)))
104 #define RTL930X_TBL_ACCESS_CTRL_0 (0xB340)
105 #define RTL930X_TBL_ACCESS_DATA_0(idx) (0xB344 + ((idx) << 2))
106 #define RTL930X_TBL_ACCESS_CTRL_1 (0xB3A0)
107 #define RTL930X_TBL_ACCESS_DATA_1(idx) (0xB3A4 + ((idx) << 2))
108 #define RTL930X_TBL_ACCESS_CTRL_2 (0xCE04)
109 #define RTL930X_TBL_ACCESS_DATA_2(i) (0xCE08 + (((i) << 2)))
111 #define RTL931X_TBL_ACCESS_CTRL_0 (0x8500)
112 #define RTL931X_TBL_ACCESS_DATA_0(idx) (0x8508 + ((idx) << 2))
113 #define RTL931X_TBL_ACCESS_CTRL_1 (0x40C0)
114 #define RTL931X_TBL_ACCESS_DATA_1(idx) (0x40C4 + ((idx) << 2))
115 #define RTL931X_TBL_ACCESS_CTRL_2 (0x8528)
116 #define RTL931X_TBL_ACCESS_DATA_2(i) (0x852C + (((i) << 2)))
117 #define RTL931X_TBL_ACCESS_CTRL_3 (0x0200)
118 #define RTL931X_TBL_ACCESS_DATA_3(i) (0x0204 + (((i) << 2)))
119 #define RTL931X_TBL_ACCESS_CTRL_4 (0x20DC)
120 #define RTL931X_TBL_ACCESS_DATA_4(i) (0x20E0 + (((i) << 2)))
121 #define RTL931X_TBL_ACCESS_CTRL_5 (0x7E1C)
122 #define RTL931X_TBL_ACCESS_DATA_5(i) (0x7E20 + (((i) << 2)))
125 #define RTL838X_MAC_LINK_STS (0xa188)
126 #define RTL839X_MAC_LINK_STS (0x0390)
127 #define RTL930X_MAC_LINK_STS (0xCB10)
128 #define RTL931X_MAC_LINK_STS (0x0EC0)
129 #define RTL838X_MAC_LINK_SPD_STS(p) (0xa190 + (((p >> 4) << 2)))
130 #define RTL839X_MAC_LINK_SPD_STS(p) (0x03a0 + (((p >> 4) << 2)))
131 #define RTL930X_MAC_LINK_SPD_STS(p) (0xCB18 + (((p >> 3) << 2)))
132 #define RTL931X_MAC_LINK_SPD_STS (0x0ED0)
133 #define RTL838X_MAC_LINK_DUP_STS (0xa19c)
134 #define RTL839X_MAC_LINK_DUP_STS (0x03b0)
135 #define RTL930X_MAC_LINK_DUP_STS (0xCB28)
136 #define RTL931X_MAC_LINK_DUP_STS (0x0EF0)
137 #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
138 #define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
139 #define RTL930X_MAC_TX_PAUSE_STS (0xCB2C)
140 #define RTL931X_MAC_TX_PAUSE_STS (0x0EF8)
141 #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
142 #define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
143 #define RTL930X_MAC_RX_PAUSE_STS (0xCB30)
144 #define RTL931X_MAC_RX_PAUSE_STS (0x0F00)
145 #define RTL930X_MAC_LINK_MEDIA_STS (0xCB14)
146 #define RTL931X_MAC_LINK_MEDIA_STS (0x0EC8)
148 /* MAC link state bits */
149 #define RTL838X_FORCE_EN (1 << 0)
150 #define RTL838X_FORCE_LINK_EN (1 << 1)
151 #define RTL838X_NWAY_EN (1 << 2)
152 #define RTL838X_DUPLEX_MODE (1 << 3)
153 #define RTL838X_TX_PAUSE_EN (1 << 6)
154 #define RTL838X_RX_PAUSE_EN (1 << 7)
155 #define RTL838X_MAC_FORCE_FC_EN (1 << 8)
157 #define RTL839X_FORCE_EN (1 << 0)
158 #define RTL839X_FORCE_LINK_EN (1 << 1)
159 #define RTL839X_DUPLEX_MODE (1 << 2)
160 #define RTL839X_TX_PAUSE_EN (1 << 5)
161 #define RTL839X_RX_PAUSE_EN (1 << 6)
162 #define RTL839X_MAC_FORCE_FC_EN (1 << 7)
164 #define RTL930X_FORCE_EN (1 << 0)
165 #define RTL930X_FORCE_LINK_EN (1 << 1)
166 #define RTL930X_DUPLEX_MODE (1 << 2)
167 #define RTL930X_TX_PAUSE_EN (1 << 7)
168 #define RTL930X_RX_PAUSE_EN (1 << 8)
169 #define RTL930X_MAC_FORCE_FC_EN (1 << 9)
171 #define RTL931X_FORCE_EN (1 << 9)
172 #define RTL931X_FORCE_LINK_EN (1 << 0)
173 #define RTL931X_DUPLEX_MODE (1 << 2)
174 #define RTL931X_MAC_FORCE_FC_EN (1 << 4)
175 #define RTL931X_TX_PAUSE_EN (1 << 16)
176 #define RTL931X_RX_PAUSE_EN (1 << 17)
179 #define RTL838X_MAC_EEE_ABLTY (0xa1a8)
180 #define RTL838X_EEE_PORT_TX_EN (0x014c)
181 #define RTL838X_EEE_PORT_RX_EN (0x0150)
182 #define RTL838X_EEE_CLK_STOP_CTRL (0x0148)
183 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
184 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
186 #define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C)
187 #define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430)
188 #define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434)
189 #define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7))
190 #define RTL839X_MAC_EEE_ABLTY (0x03C8)
192 #define RTL930X_MAC_EEE_ABLTY (0xCB34)
193 #define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6))
194 #define RTL930X_EEEP_PORT_CTRL(p) (0x3278 + ((p) << 6))
196 /* L2 functionality */
197 #define RTL838X_L2_CTRL_0 (0x3200)
198 #define RTL839X_L2_CTRL_0 (0x3800)
199 #define RTL930X_L2_CTRL (0x8FD8)
200 #define RTL931X_L2_CTRL (0xC800)
201 #define RTL838X_L2_CTRL_1 (0x3204)
202 #define RTL839X_L2_CTRL_1 (0x3804)
203 #define RTL930X_L2_AGE_CTRL (0x8FDC)
204 #define RTL931X_L2_AGE_CTRL (0xC804)
205 #define RTL838X_L2_PORT_AGING_OUT (0x3358)
206 #define RTL839X_L2_PORT_AGING_OUT (0x3b74)
207 #define RTL930X_L2_PORT_AGE_CTRL (0x8FE0)
208 #define RTL931X_L2_PORT_AGE_CTRL (0xc808)
209 #define RTL838X_TBL_ACCESS_L2_CTRL (0x6900)
210 #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
211 #define RTL930X_TBL_ACCESS_L2_CTRL (0xB320)
212 #define RTL930X_TBL_ACCESS_L2_METHOD_CTRL (0xB324)
213 #define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
214 #define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
215 #define RTL930X_TBL_ACCESS_L2_DATA(idx) (0xab08 + ((idx) << 2))
217 #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
218 #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
219 #define RTL930X_L2_TBL_FLUSH_CTRL (0x9404)
220 #define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C)
222 #define RTL838X_L2_LRN_CONSTRT (0x329C)
223 #define RTL839X_L2_LRN_CONSTRT (0x3910)
224 #define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c)
225 #define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964)
227 #define RTL838X_L2_FLD_PMSK (0x3288)
228 #define RTL839X_L2_FLD_PMSK (0x38EC)
229 #define RTL930X_L2_BC_FLD_PMSK (0x9068)
230 #define RTL931X_L2_BC_FLD_PMSK (0xC8FC)
232 #define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064)
233 #define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4)
235 #define RTL838X_L2_LRN_CONSTRT_EN (0x3368)
236 #define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0)
237 #define RTL839X_L2_PORT_LRN_CONSTRT (0x3914)
239 #define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2)))
240 #define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
241 #define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2)))
242 #define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2)))
244 #define SALRN_PORT_SHIFT(p) ((p % 16) * 2)
245 #define SALRN_MODE_MASK 0x3
246 #define SALRN_MODE_HARDWARE 0
247 #define SALRN_MODE_DISABLED 2
249 #define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2)))
250 #define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2)))
251 #define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2)))
252 #define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2)))
254 #define RTL838X_L2_PORT_MV_ACT(p) (0x335c + (((p >> 4) << 2)))
255 #define RTL839X_L2_PORT_MV_ACT(p) (0x3b80 + (((p >> 4) << 2)))
257 #define RTL838X_L2_PORT_STATIC_MV_ACT(p) (0x327c + (((p >> 4) << 2)))
258 #define RTL839X_L2_PORT_STATIC_MV_ACT(p) (0x38dc + (((p >> 4) << 2)))
260 #define MV_ACT_PORT_SHIFT(p) ((p % 16) * 2)
261 #define MV_ACT_MASK 0x3
262 #define MV_ACT_FORWARD 0
263 #define MV_ACT_DROP 1
264 #define MV_ACT_TRAP2CPU 2
265 #define MV_ACT_COPY2CPU 3
267 #define RTL930X_ST_CTRL (0x8798)
269 #define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
270 #define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
272 #define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2))
273 #define RTL838X_VLAN_PORT_FWD (0x3A78)
274 #define RTL839X_VLAN_PORT_FWD (0x27AC)
275 #define RTL930X_VLAN_PORT_FWD (0x834C)
276 #define RTL931X_VLAN_PORT_FWD (0x95CC)
277 #define RTL838X_VLAN_FID_CTRL (0x3aa8)
280 #define RTL838X_MIR_CTRL (0x5D00)
281 #define RTL838X_MIR_DPM_CTRL (0x5D20)
282 #define RTL838X_MIR_SPM_CTRL (0x5D10)
284 #define RTL839X_MIR_CTRL (0x2500)
285 #define RTL839X_MIR_DPM_CTRL (0x2530)
286 #define RTL839X_MIR_SPM_CTRL (0x2510)
288 #define RTL930X_MIR_CTRL (0xA2A0)
289 #define RTL930X_MIR_DPM_CTRL (0xA2C0)
290 #define RTL930X_MIR_SPM_CTRL (0xA2B0)
292 #define RTL931X_MIR_CTRL (0xAF00)
293 #define RTL931X_MIR_DPM_CTRL (0xAF30)
294 #define RTL931X_MIR_SPM_CTRL (0xAF10)
296 /* Storm/rate control and scheduling */
297 #define RTL838X_STORM_CTRL (0x4700)
298 #define RTL839X_STORM_CTRL (0x1800)
299 #define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2)))
300 #define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874)
301 #define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878)
302 #define RTL838X_STORM_CTRL_BURST_0 (0x487c)
303 #define RTL838X_STORM_CTRL_BURST_1 (0x4880)
304 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0 (0x1804)
305 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1 (0x1808)
306 #define RTL838X_SCHED_CTRL (0xB980)
307 #define RTL839X_SCHED_CTRL (0x60F4)
308 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58)
309 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C)
310 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804)
311 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808)
312 #define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000)
313 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0 (0x1604)
314 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1 (0x1608)
315 #define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60F8)
316 #define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL (0x6200)
317 #define RTL838X_SCHED_LB_THR (0xB984)
318 #define RTL839X_SCHED_LB_THR (0x60FC)
319 #define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7)))
320 #define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q) (0xC00C + (p << 7) + (((q) << 2)))
321 #define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
322 #define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
323 #define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
324 #define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2)))
325 #define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2)))
326 #define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2)))
327 #define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2)))
328 #define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2)))
329 #define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2)))
330 #define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3)))
331 #define RTL839X_STORM_CTRL_PORT_UC_1(p) (0x1860 + (((p) << 3)))
332 #define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3)))
333 #define RTL839X_STORM_CTRL_PORT_MC_1(p) (0x1a00 + (((p) << 3)))
334 #define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3)))
335 #define RTL839X_STORM_CTRL_PORT_BC_1(p) (0x1BA0 + (((p) << 3)))
336 #define RTL839X_TBL_ACCESS_CTRL_2 (0x611C)
337 #define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2)))
338 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p) (0x1618 + (((p) << 3)))
339 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p) (0x161C + (((p) << 3)))
340 #define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p) (0x1640 + (((p) << 3)))
341 #define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p) (0x1644 + (((p) << 3)))
342 #define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614)
344 /* Link aggregation (Trunking) */
345 #define TRUNK_DISTRIBUTION_ALGO_SPA_BIT 0x01
346 #define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT 0x02
347 #define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT 0x04
348 #define TRUNK_DISTRIBUTION_ALGO_SIP_BIT 0x08
349 #define TRUNK_DISTRIBUTION_ALGO_DIP_BIT 0x10
350 #define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT 0x20
351 #define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT 0x40
352 #define TRUNK_DISTRIBUTION_ALGO_MASKALL 0x7F
354 #define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01
355 #define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02
356 #define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04
357 #define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08
358 #define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF
360 #define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01
361 #define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02
362 #define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04
363 #define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08
364 #define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10
365 #define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20
366 #define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT 0x40
367 #define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT 0x80
368 #define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100
369 #define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT 0x200
370 #define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF
372 #define RTL838X_TRK_MBR_CTR (0x3E00)
373 #define RTL838X_TRK_HASH_IDX_CTRL (0x3E20)
374 #define RTL838X_TRK_HASH_CTRL (0x3E24)
376 #define RTL839X_TRK_MBR_CTR (0x2200)
377 #define RTL839X_TRK_HASH_IDX_CTRL (0x2280)
378 #define RTL839X_TRK_HASH_CTRL (0x2284)
380 #define RTL930X_TRK_MBR_CTRL (0xA41C)
381 #define RTL930X_TRK_HASH_CTRL (0x9F80)
383 #define RTL931X_TRK_MBR_CTRL (0xB8D0)
384 #define RTL931X_TRK_HASH_CTRL (0xBA70)
386 /* Attack prevention */
387 #define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
388 #define RTL838X_ATK_PRVNT_CTRL (0x5B04)
389 #define RTL838X_ATK_PRVNT_ACT (0x5B08)
390 #define RTL838X_ATK_PRVNT_STS (0x5B1C)
393 #define RTL838X_RMA_BPDU_FLD_PMSK (0x4348)
394 #define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18)
395 #define RTL931X_RMA_BPDU_FLD_PMSK (0x8950)
396 #define RTL839X_RMA_BPDU_FLD_PMSK (0x125C)
398 #define RTL838X_SPCL_TRAP_CTRL (0x6980)
399 #define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988)
400 #define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C)
401 #define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
402 #define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994)
403 #define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998)
405 #define RTL839X_SPCL_TRAP_CTRL (0x1054)
406 #define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C)
407 #define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060)
408 #define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
409 #define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064)
410 #define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068)
411 #define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C)
412 #define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070)
413 /* special port action controls */
416 0 = FORWARD (default)
419 3 = FLOOD IN ALL PORT
422 offset = CTRL + (port >> 4) << 2
423 value/mask = 3 << ((port&0xF) << 1)
445 #define RTL838X_RMA_BPDU_CTRL (0x4330)
446 #define RTL839X_RMA_BPDU_CTRL (0x122C)
447 #define RTL930X_RMA_BPDU_CTRL (0x9E7C)
448 #define RTL931X_RMA_BPDU_CTRL (0x881C)
450 #define RTL838X_RMA_PTP_CTRL (0x4338)
451 #define RTL839X_RMA_PTP_CTRL (0x123C)
452 #define RTL930X_RMA_PTP_CTRL (0x9E88)
453 #define RTL931X_RMA_PTP_CTRL (0x8834)
455 #define RTL838X_RMA_LLTP_CTRL (0x4340)
456 #define RTL839X_RMA_LLTP_CTRL (0x124C)
457 #define RTL930X_RMA_LLTP_CTRL (0x9EFC)
458 #define RTL931X_RMA_LLTP_CTRL (0x8918)
460 #define RTL930X_RMA_EAPOL_CTRL (0x9F08)
461 #define RTL931X_RMA_EAPOL_CTRL (0x8930)
462 #define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04)
465 #define RTL838X_QM_INTPRI2QID_CTRL (0x5F00)
466 #define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2))
467 #define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2)))
468 #define RTL838X_PRI_SEL_PORT_PRI(p) (0x5FB8 + (((p / 10) << 2)))
469 #define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2)))
470 #define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10)
471 #define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
472 #define RTL838X_PRI_SEL_CTRL (0x10E0)
473 #define RTL839X_PRI_SEL_CTRL (0x10E0)
474 #define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2)))
475 #define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2)))
476 #define RTL838X_QM_PKT2CPU_INTPRI_0 (0x5F04)
477 #define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08)
478 #define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C)
479 #define RTL839X_OAM_CTRL (0x2100)
480 #define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2)))
481 #define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2)))
482 #define RTL839X_PRI_SEL_IPRI_REMAP (0x1080)
483 #define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C)
484 #define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC)
485 #define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2)))
486 #define RTL839X_RMK_DEI_CTRL (0x6AA4)
487 #define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2))
488 #define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2))
489 #define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8)
490 #define RTL838X_RMK_IPRI_CTRL (0xA460)
491 #define RTL838X_RMK_OPRI_CTRL (0xA464)
492 #define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7)))
493 #define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7)))
494 #define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2)))
497 #define RTL930X_STAT_PRVTE_DROP_COUNTER0 (0xB5B8)
499 /* Packet Inspection Engine */
500 #define RTL838X_METER_GLB_CTRL (0x4B08)
501 #define RTL839X_METER_GLB_CTRL (0x1300)
502 #define RTL930X_METER_GLB_CTRL (0xa0a0)
503 #define RTL931X_METER_GLB_CTRL (0x411C)
505 #define RTL839X_ACL_CTRL (0x1288)
507 #define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100)
508 #define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280)
509 #define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0)
510 #define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180)
512 #define RTL838X_ACL_BLK_PWR_CTRL (0x6104)
513 #define RTL839X_PS_ACL_PWR_CTRL (0x049c)
515 #define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2))
516 #define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2))
517 #define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2))
518 #define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2))
520 #define RTL838X_ACL_BLK_GROUP_CTRL (0x615C)
521 #define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec)
523 #define RTL838X_ACL_CLR_CTRL (0x6168)
524 #define RTL839X_ACL_CLR_CTRL (0x12fc)
525 #define RTL930X_PIE_CLR_CTRL (0xa66c)
526 #define RTL931X_PIE_CLR_CTRL (0x42D8)
528 #define RTL838X_DMY_REG27 (0x3378)
530 #define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2)))
531 #define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2)))
532 #define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2)))
534 #define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4)
535 #define RTL931X_PIE_BLK_PHASE_CTRL (0x4184)
538 #define PIE_ACT_COPY_TO_PORT 2
539 #define PIE_ACT_REDIRECT_TO_PORT 4
540 #define PIE_ACT_ROUTE_UC 6
541 #define PIE_ACT_VID_ASSIGN 0
546 #define L3_TRAP2CPU 2
547 #define L3_COPY2CPU 3
548 #define L3_TRAP2MASTERCPU 4
549 #define L3_COPY2MASTERCPU 5
550 #define L3_HARDDROP 6
553 #define ROUTE_ACT_FORWARD 0
554 #define ROUTE_ACT_TRAP2CPU 1
555 #define ROUTE_ACT_COPY2CPU 2
556 #define ROUTE_ACT_DROP 3
559 #define RTL839X_ROUTING_SA_CTRL 0x6afc
560 #define RTL930X_L3_HOST_TBL_CTRL (0xAB48)
561 #define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C)
562 #define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50)
563 #define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54)
564 #define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58)
565 #define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2))
566 #define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2))
567 #define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C)
568 #define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0)
569 #define RTL930X_L3_HW_LU_CTRL (0xACC0)
570 #define RTL930X_L3_IP_ROUTE_CTRL 0xab44
572 /* Port LED Control */
573 #define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2)))
574 #define RTL930X_LED_SET0_0_CTRL (0xCC28)
575 #define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2)))
576 #define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2)))
577 #define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C)
578 #define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40)
579 #define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44)
581 #define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2)))
582 #define RTL931X_LED_SET0_0_CTRL (0x0630)
583 #define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2)))
584 #define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2)))
585 #define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654)
586 #define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c)
587 #define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664)
589 #define MAX_VLANS 4096
592 #define RTL930X_PORT_IGNORE 0x3f
593 #define MAX_MC_GROUPS 512
594 #define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1)
595 #define PIE_BLOCK_SIZE 128
596 #define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE)
597 #define N_FIXED_FIELDS 12
598 #define N_FIXED_FIELDS_RTL931X 14
599 #define MAX_COUNTERS 2048
600 #define MAX_ROUTES 512
601 #define MAX_HOST_ROUTES 1536
602 #define MAX_INTF_MTUS 8
603 #define DEFAULT_MTU 1536
604 #define MAX_INTERFACES 100
605 #define MAX_ROUTER_MACS 64
606 #define L3_EGRESS_DMACS 2048
612 PHY_RTL8218B_INT
= 2,
613 PHY_RTL8218B_EXT
= 3,
620 PBVLAN_TYPE_INNER
= 0,
625 PBVLAN_MODE_UNTAG_AND_PRITAG
= 0,
626 PBVLAN_MODE_UNTAG_ONLY
,
630 struct rtl838x_port
{
636 bool phy_is_integrated
;
641 const struct dsa_port
*dp
;
644 struct rtl838x_vlan_info
{
652 // The following fields are used only by the RTL931X
653 int if_id
; // Interface (index in L3_EGR_INTF_IDX)
654 u16 multicast_grp_mask
;
655 int l2_tunnel_list_id
;
666 struct rtl838x_l2_entry
{
672 enum l2_entry_type type
;
684 u16 mc_portmask_index
;
689 bool nh_vlan_target
; // Only RTL83xx: VLAN used for next hop
691 // The following is only valid on RTL931x
694 bool is_local_forward
;
695 bool is_remote_forward
;
698 int l2_tunnel_list_id
;
701 enum fwd_rule_action
{
702 FWD_RULE_ACTION_NONE
= 0,
703 FWD_RULE_ACTION_FWD
= 1,
722 /* Intermediate representation of a Packet Inspection Engine Rule
723 * as suggested by the Kernel's tc flower offload subsystem
724 * Field meaning is universal across SoC families, but data content is specific
725 * to SoC family (e.g. because of different port ranges) */
728 enum pie_phase phase
; // Phase in which this template is applied
729 int packet_cntr
; // ID of a packet counter assigned to this rule
730 int octet_cntr
; // ID of a byte counter assigned to this rule
734 // The following are requirements for the pie template
736 bool is_ipv6
; // This is a rule with IPv6 fields
738 // Fixed fields that are always matched against on RTL8380
740 u8 spn
; // Source port number
741 bool stacking_port
; // Source port is stacking port
742 bool mgnt_vlan
; // Packet arrived on management VLAN
743 bool dmac_hit_sw
; // The packet's destination MAC matches one of the device's
744 bool content_too_deep
; // The content of the packet cannot be parsed: too many layers
745 bool not_first_frag
; // Not the first IP fragment
746 u8 frame_type_l4
; // 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP
747 u8 frame_type
; // 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6
748 bool otag_fmt
; // 0: outer tag packet, 1: outer priority tag or untagged
749 bool itag_fmt
; // 0: inner tag packet, 1: inner priority tag or untagged
750 bool otag_exist
; // packet with outer tag
751 bool itag_exist
; // packet with inner tag
752 bool frame_type_l2
; // 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved
753 bool igr_normal_port
; // Ingress port is not cpu or stacking port
754 u8 tid
; // The template ID defining the what the templated fields mean
756 // Masks for the fields that are always matched against on RTL8380
759 bool stacking_port_m
;
762 bool content_too_deep_m
;
763 bool not_first_frag_m
;
770 bool frame_type_l2_m
;
771 bool igr_normal_port_m
;
774 // Logical operations between rules, special rules for rule numbers apply
776 bool cond_not
; // Matches when conditions not match
777 bool cond_and1
; // And this rule 2n with the next rule 2n+1 in same block
778 bool cond_and2
; // And this rule m in block 2n with rule m in block 2n+1
781 // Actions to be performed
782 bool drop
; // Drop the packet
783 bool fwd_sel
; // Forward packet: to port, portmask, dest route, next rule, drop
784 bool ovid_sel
; // So something to outer vlan-id: shift, re-assign
785 bool ivid_sel
; // Do something to inner vlan-id: shift, re-assign
786 bool flt_sel
; // Filter the packet when sending to certain ports
787 bool log_sel
; // Log the packet in one of the LOG-table counters
788 bool rmk_sel
; // Re-mark the packet, i.e. change the priority-tag
789 bool meter_sel
; // Meter the packet, i.e. limit rate of this type of packet
790 bool tagst_sel
; // Change the ergress tag
791 bool mir_sel
; // Mirror the packet to a Link Aggregation Group
792 bool nopri_sel
; // Change the normal priority
793 bool cpupri_sel
; // Change the CPU priority
794 bool otpid_sel
; // Change Outer Tag Protocol Identifier (802.1q)
795 bool itpid_sel
; // Change Inner Tag Protocol Identifier (802.1q)
796 bool shaper_sel
; // Apply traffic shaper
797 bool mpls_sel
; // MPLS actions
798 bool bypass_sel
; // Bypass actions
799 bool fwd_sa_lrn
; // Learn the source address when forwarding
800 bool fwd_mod_to_cpu
; // Forward the modified VLAN tag format to CPU-port
802 // Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300
803 u64 spm
; // Source Port Matrix
804 u16 otag
; // Outer VLAN-ID
805 u8 smac
[ETH_ALEN
]; // Source MAC address
806 u8 dmac
[ETH_ALEN
]; // Destination MAC address
807 u16 ethertype
; // Ethernet frame type field in ethernet header
808 u16 itag
; // Inner VLAN-ID
809 u16 field_range_check
;
810 u32 sip
; // Source IP
811 struct in6_addr sip6
; // IPv6 Source IP
812 u32 dip
; // Destination IP
813 struct in6_addr dip6
; // IPv6 Destination IP
814 u16 tos_proto
; // IPv4: TOS + Protocol fields, IPv6: Traffic class + next header
815 u16 sport
; // TCP/UDP source port
816 u16 dport
; // TCP/UDP destination port
819 u16 dsap_ssap
; // Destination / Source Service Access Point bytes (802.3)
827 u16 field_range_check_m
;
829 struct in6_addr sip6_m
; // IPv6 Source IP mask
831 struct in6_addr dip6_m
; // IPv6 Destination IP mask
839 // Data associated with actions
840 u8 fwd_act
; // Type of forwarding action
841 // 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask
842 // 4: redirect to portid, 5: redirect to portmask
843 // 6: route, 7: vlan leaky (only 8380)
844 u16 fwd_data
; // Additional data for forwarding action, e.g. destination port
846 u16 ovid_data
; // Outer VLAN ID
848 u16 ivid_data
; // Inner VLAN ID
849 u16 flt_data
; // Filtering data
850 u16 log_data
; // ID of packet or octet counter in LOG table, on RTL93xx
851 // unnecessary since PIE-Rule-ID == LOG-counter-ID
853 u8 mpls_act
; // MPLS action type
854 u16 mpls_lib_idx
; // MPLS action data
856 u16 rmk_data
; // Data for remarking
857 u16 meter_data
; // ID of meter for bandwidth control
866 // Bypass actions, ignored on RTL8380
867 bool bypass_all
; // Not clear
868 bool bypass_igr_stp
; // Bypass Ingress STP state
869 bool bypass_ibc_sc
; // Bypass Ingress Bandwidth Control and Storm Control
872 struct rtl838x_l3_intf
{
881 u8 ip4_icmp_redirect
;
882 u8 ip6_icmp_redirect
;
883 u8 ip4_pbr_icmp_redirect
;
884 u8 ip6_pbr_icmp_redirect
;
888 * An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point
889 * for the L3 routing system. Packets arriving and matching an entry in this table
890 * will be considered for routing.
891 * Mask fields state whether the corresponding data fields matter for matching
893 struct rtl93xx_rt_mac
{
894 bool valid
; // Valid or not
895 bool p_type
; // Individual (0) or trunk (1) port
896 bool p_mask
; // Whether the port type is used
898 u8 p_id_mask
; // Mask for the port
899 u8 action
; // Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU
900 // 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP
903 u64 mac
; // MAC address used as source MAC in the routed packet
907 struct rtl83xx_nexthop
{
908 u16 id
; // ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP
911 u16 vid
; // VLAN-ID for L2 table entry (saved from L2-UC entry)
912 u16 rvid
; // Relay VID/FID for the L2 table entry
913 u64 mac
; // The MAC address of the entry in the L2_NEXT_HOP table
915 u16 l2_id
; // Index of this next hop forwarding entry in L2 FIB table
916 u64 gw
; // The gateway MAC address packets are forwarded to
917 int if_id
; // Interface (into L3_EGR_INTF_IDX)
920 struct rtl838x_switch_priv
;
922 struct rtl83xx_flow
{
923 unsigned long cookie
;
924 struct rhash_head node
;
925 struct rcu_head rcu_head
;
926 struct rtl838x_switch_priv
*priv
;
927 struct pie_rule rule
;
931 struct rtl93xx_route_attr
{
943 struct rtl83xx_route
{
944 u32 gw_ip
; // IP of the route's gateway
945 u32 dst_ip
; // IP of the destination net
946 struct in6_addr dst_ip6
;
947 int prefix_len
; // Network prefix len of the destination net
949 int id
; // ID number of this route
950 struct rhlist_head linkage
;
951 u16 switch_mac_id
; // Index into switch's own MACs, RTL839X only
952 struct rtl83xx_nexthop nh
;
954 struct rtl93xx_route_attr attr
;
958 void (*mask_port_reg_be
)(u64 clear
, u64 set
, int reg
);
959 void (*set_port_reg_be
)(u64 set
, int reg
);
960 u64 (*get_port_reg_be
)(int reg
);
961 void (*mask_port_reg_le
)(u64 clear
, u64 set
, int reg
);
962 void (*set_port_reg_le
)(u64 set
, int reg
);
963 u64 (*get_port_reg_le
)(int reg
);
966 int stat_port_std_mib
;
967 int (*port_iso_ctrl
)(int p
);
968 void (*traffic_enable
)(int source
, int dest
);
969 void (*traffic_disable
)(int source
, int dest
);
970 void (*traffic_set
)(int source
, u64 dest_matrix
);
971 u64 (*traffic_get
)(int source
);
975 u32 l2_port_aging_out
;
976 int l2_tbl_flush_ctrl
;
977 void (*exec_tbl0_cmd
)(u32 cmd
);
978 void (*exec_tbl1_cmd
)(u32 cmd
);
979 int (*tbl_access_data_0
)(int i
);
981 int isr_port_link_sts_chg
;
982 int imr_port_link_sts_chg
;
984 void (*vlan_tables_read
)(u32 vlan
, struct rtl838x_vlan_info
*info
);
985 void (*vlan_set_tagged
)(u32 vlan
, struct rtl838x_vlan_info
*info
);
986 void (*vlan_set_untagged
)(u32 vlan
, u64 portmask
);
987 void (*vlan_profile_dump
)(int index
);
988 void (*vlan_profile_setup
)(int profile
);
989 void (*vlan_port_pvidmode_set
)(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
);
990 void (*vlan_port_pvid_set
)(int port
, enum pbvlan_type type
, int pvid
);
991 void (*vlan_port_keep_tag_set
)(int port
, bool keep_outer
, bool keep_inner
);
992 void (*set_vlan_igr_filter
)(int port
, enum igr_filter state
);
993 void (*set_vlan_egr_filter
)(int port
, enum egr_filter state
);
994 void (*enable_learning
)(int port
, bool enable
);
995 void (*enable_flood
)(int port
, bool enable
);
996 void (*enable_mcast_flood
)(int port
, bool enable
);
997 void (*enable_bcast_flood
)(int port
, bool enable
);
998 void (*set_static_move_action
)(int port
, bool forward
);
999 void (*stp_get
)(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[]);
1000 void (*stp_set
)(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[]);
1001 int (*mac_force_mode_ctrl
)(int port
);
1002 int (*mac_port_ctrl
)(int port
);
1003 int (*l2_port_new_salrn
)(int port
);
1004 int (*l2_port_new_sa_fwd
)(int port
);
1005 int (*set_ageing_time
)(unsigned long msec
);
1010 int mac_link_dup_sts
;
1011 int (*mac_link_spd_sts
)(int port
);
1012 int mac_rx_pause_sts
;
1013 int mac_tx_pause_sts
;
1014 u64 (*read_l2_entry_using_hash
)(u32 hash
, u32 position
, struct rtl838x_l2_entry
*e
);
1015 void (*write_l2_entry_using_hash
)(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
);
1016 u64 (*read_cam
)(int idx
, struct rtl838x_l2_entry
*e
);
1017 void (*write_cam
)(int idx
, struct rtl838x_l2_entry
*e
);
1018 int (*trk_mbr_ctr
)(int group
);
1019 int rma_bpdu_fld_pmask
;
1020 int spcl_trap_eapol_ctrl
;
1021 void (*init_eee
)(struct rtl838x_switch_priv
*priv
, bool enable
);
1022 void (*port_eee_set
)(struct rtl838x_switch_priv
*priv
, int port
, bool enable
);
1023 int (*eee_port_ability
)(struct rtl838x_switch_priv
*priv
,
1024 struct ethtool_eee
*e
, int port
);
1025 u64 (*l2_hash_seed
)(u64 mac
, u32 vid
);
1026 u32 (*l2_hash_key
)(struct rtl838x_switch_priv
*priv
, u64 seed
);
1027 u64 (*read_mcast_pmask
)(int idx
);
1028 void (*write_mcast_pmask
)(int idx
, u64 portmask
);
1029 void (*vlan_fwd_on_inner
)(int port
, bool is_set
);
1030 void (*pie_init
)(struct rtl838x_switch_priv
*priv
);
1031 int (*pie_rule_read
)(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
);
1032 int (*pie_rule_write
)(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
);
1033 int (*pie_rule_add
)(struct rtl838x_switch_priv
*priv
, struct pie_rule
*rule
);
1034 void (*pie_rule_rm
)(struct rtl838x_switch_priv
*priv
, struct pie_rule
*rule
);
1035 void (*l2_learning_setup
)(void);
1036 u32 (*packet_cntr_read
)(int counter
);
1037 void (*packet_cntr_clear
)(int counter
);
1038 void (*route_read
)(int idx
, struct rtl83xx_route
*rt
);
1039 void (*route_write
)(int idx
, struct rtl83xx_route
*rt
);
1040 void (*host_route_write
)(int idx
, struct rtl83xx_route
*rt
);
1041 int (*l3_setup
)(struct rtl838x_switch_priv
*priv
);
1042 void (*set_l3_nexthop
)(int idx
, u16 dmac_id
, u16 interface
);
1043 void (*get_l3_nexthop
)(int idx
, u16
*dmac_id
, u16
*interface
);
1044 u64 (*get_l3_egress_mac
)(u32 idx
);
1045 void (*set_l3_egress_mac
)(u32 idx
, u64 mac
);
1046 int (*find_l3_slot
)(struct rtl83xx_route
*rt
, bool must_exist
);
1047 int (*route_lookup_hw
)(struct rtl83xx_route
*rt
);
1048 void (*get_l3_router_mac
)(u32 idx
, struct rtl93xx_rt_mac
*m
);
1049 void (*set_l3_router_mac
)(u32 idx
, struct rtl93xx_rt_mac
*m
);
1050 void (*set_l3_egress_intf
)(int idx
, struct rtl838x_l3_intf
*intf
);
1051 void (*set_distribution_algorithm
)(int group
, int algoidx
, u32 algomask
);
1052 void (*set_receive_management_action
)(int port
, rma_ctrl_t type
, action_type_t action
);
1053 void (*led_init
)(struct rtl838x_switch_priv
*priv
);
1056 struct rtl838x_switch_priv
{
1057 /* Switch operation */
1058 struct dsa_switch
*ds
;
1063 struct rtl838x_port ports
[57];
1064 struct mutex reg_mutex
; // Mutex for individual register manipulations
1065 struct mutex pie_mutex
; // Mutex for Packet Inspection Engine
1067 int mirror_group_ports
[4];
1068 struct mii_bus
*mii_bus
;
1069 const struct rtl838x_reg
*r
;
1077 struct dentry
*dbgfs_dir
;
1079 u64 lags_port_members
[MAX_LAGS
];
1080 struct net_device
*lag_devs
[MAX_LAGS
];
1081 u32 lag_primary
[MAX_LAGS
];
1082 u32 is_lagmember
[57];
1084 struct notifier_block nb
; // TODO: change to different name
1085 struct notifier_block ne_nb
;
1086 struct notifier_block fib_nb
;
1088 unsigned long int mc_group_bm
[MAX_MC_GROUPS
>> 5];
1089 int mc_group_saves
[MAX_MC_GROUPS
];
1091 struct rhashtable tc_ht
;
1092 unsigned long int pie_use_bm
[MAX_PIE_ENTRIES
>> 5];
1094 unsigned long int octet_cntr_use_bm
[MAX_COUNTERS
>> 5];
1095 unsigned long int packet_cntr_use_bm
[MAX_COUNTERS
>> 4];
1096 struct rhltable routes
;
1097 unsigned long int route_use_bm
[MAX_ROUTES
>> 5];
1098 unsigned long int host_route_use_bm
[MAX_HOST_ROUTES
>> 5];
1099 struct rtl838x_l3_intf
*interfaces
[MAX_INTERFACES
];
1100 u16 intf_mtus
[MAX_INTF_MTUS
];
1101 int intf_mtu_count
[MAX_INTF_MTUS
];
1104 void rtl838x_dbgfs_init(struct rtl838x_switch_priv
*priv
);
1105 void rtl930x_dbgfs_init(struct rtl838x_switch_priv
*priv
);
1107 #endif /* _RTL838X_H */