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realtek: cleanup rtl83{8x,9x}_enable_learning/flood
[openwrt/staging/jow.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 extern struct mutex smi_lock;
7 extern struct rtl83xx_soc_info soc_info;
8
9 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
10 enum template_field_id {
11 TEMPLATE_FIELD_SPMMASK = 0,
12 TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
13 TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-31
14 TEMPLATE_FIELD_SPM2 = 3, // Source portmask ports 32-47
15 TEMPLATE_FIELD_SPM3 = 4, // Source portmask ports 48-56
16 TEMPLATE_FIELD_DMAC0 = 5, // Destination MAC [15:0]
17 TEMPLATE_FIELD_DMAC1 = 6, // Destination MAC [31:16]
18 TEMPLATE_FIELD_DMAC2 = 7, // Destination MAC [47:32]
19 TEMPLATE_FIELD_SMAC0 = 8, // Source MAC [15:0]
20 TEMPLATE_FIELD_SMAC1 = 9, // Source MAC [31:16]
21 TEMPLATE_FIELD_SMAC2 = 10, // Source MAC [47:32]
22 TEMPLATE_FIELD_ETHERTYPE = 11, // Ethernet frame type field
23 // Field-ID 12 is not used
24 TEMPLATE_FIELD_OTAG = 13,
25 TEMPLATE_FIELD_ITAG = 14,
26 TEMPLATE_FIELD_SIP0 = 15,
27 TEMPLATE_FIELD_SIP1 = 16,
28 TEMPLATE_FIELD_DIP0 = 17,
29 TEMPLATE_FIELD_DIP1 = 18,
30 TEMPLATE_FIELD_IP_TOS_PROTO = 19,
31 TEMPLATE_FIELD_IP_FLAG = 20,
32 TEMPLATE_FIELD_L4_SPORT = 21,
33 TEMPLATE_FIELD_L4_DPORT = 22,
34 TEMPLATE_FIELD_L34_HEADER = 23,
35 TEMPLATE_FIELD_ICMP_IGMP = 24,
36 TEMPLATE_FIELD_VID_RANG0 = 25,
37 TEMPLATE_FIELD_VID_RANG1 = 26,
38 TEMPLATE_FIELD_L4_PORT_RANG = 27,
39 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28,
40 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29,
41 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30,
42 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31,
43 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32,
44 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33,
45 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34,
46 TEMPLATE_FIELD_SIP2 = 35,
47 TEMPLATE_FIELD_SIP3 = 36,
48 TEMPLATE_FIELD_SIP4 = 37,
49 TEMPLATE_FIELD_SIP5 = 38,
50 TEMPLATE_FIELD_SIP6 = 39,
51 TEMPLATE_FIELD_SIP7 = 40,
52 TEMPLATE_FIELD_OLABEL = 41,
53 TEMPLATE_FIELD_ILABEL = 42,
54 TEMPLATE_FIELD_OILABEL = 43,
55 TEMPLATE_FIELD_DPMMASK = 44,
56 TEMPLATE_FIELD_DPM0 = 45,
57 TEMPLATE_FIELD_DPM1 = 46,
58 TEMPLATE_FIELD_DPM2 = 47,
59 TEMPLATE_FIELD_DPM3 = 48,
60 TEMPLATE_FIELD_L2DPM0 = 49,
61 TEMPLATE_FIELD_L2DPM1 = 50,
62 TEMPLATE_FIELD_L2DPM2 = 51,
63 TEMPLATE_FIELD_L2DPM3 = 52,
64 TEMPLATE_FIELD_IVLAN = 53,
65 TEMPLATE_FIELD_OVLAN = 54,
66 TEMPLATE_FIELD_FWD_VID = 55,
67 TEMPLATE_FIELD_DIP2 = 56,
68 TEMPLATE_FIELD_DIP3 = 57,
69 TEMPLATE_FIELD_DIP4 = 58,
70 TEMPLATE_FIELD_DIP5 = 59,
71 TEMPLATE_FIELD_DIP6 = 60,
72 TEMPLATE_FIELD_DIP7 = 61,
73 };
74
75 // Number of fixed templates predefined in the SoC
76 #define N_FIXED_TEMPLATES 5
77 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
78 {
79 {
80 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
81 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
82 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
83 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
84 }, {
85 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
86 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
87 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,
88 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
89 }, {
90 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
91 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
92 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
93 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
94 }, {
95 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
96 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
97 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
98 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
99 }, {
100 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
101 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
102 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0,
103 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
104 },
105 };
106
107 void rtl839x_print_matrix(void)
108 {
109 volatile u64 *ptr9;
110 int i;
111
112 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
113 for (i = 0; i < 52; i += 4)
114 pr_debug("> %16llx %16llx %16llx %16llx\n",
115 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
116 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
117 }
118
119 static inline int rtl839x_port_iso_ctrl(int p)
120 {
121 return RTL839X_PORT_ISO_CTRL(p);
122 }
123
124 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
125 {
126 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
127 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
128 }
129
130 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
131 {
132 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
133 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
134 }
135
136 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
137 {
138 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
139 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
140 }
141
142 static inline int rtl839x_tbl_access_data_0(int i)
143 {
144 return RTL839X_TBL_ACCESS_DATA_0(i);
145 }
146
147 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
148 {
149 u32 u, v, w;
150 // Read VLAN table (0) via register 0
151 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
152
153 rtl_table_read(r, vlan);
154 u = sw_r32(rtl_table_data(r, 0));
155 v = sw_r32(rtl_table_data(r, 1));
156 w = sw_r32(rtl_table_data(r, 2));
157 rtl_table_release(r);
158
159 info->tagged_ports = u;
160 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
161 info->profile_id = w >> 30 | ((v & 1) << 2);
162 info->hash_mc_fid = !!(w & BIT(2));
163 info->hash_uc_fid = !!(w & BIT(3));
164 info->fid = (v >> 3) & 0xff;
165
166 // Read UNTAG table (0) via table register 1
167 r = rtl_table_get(RTL8390_TBL_1, 0);
168 rtl_table_read(r, vlan);
169 u = sw_r32(rtl_table_data(r, 0));
170 v = sw_r32(rtl_table_data(r, 1));
171 rtl_table_release(r);
172
173 info->untagged_ports = u;
174 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
175 }
176
177 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
178 {
179 u32 u, v, w;
180 // Access VLAN table (0) via register 0
181 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
182
183 u = info->tagged_ports >> 21;
184 v = info->tagged_ports << 11;
185 v |= ((u32)info->fid) << 3;
186 v |= info->hash_uc_fid ? BIT(2) : 0;
187 v |= info->hash_mc_fid ? BIT(1) : 0;
188 v |= (info->profile_id & 0x4) ? 1 : 0;
189 w = ((u32)(info->profile_id & 3)) << 30;
190
191 sw_w32(u, rtl_table_data(r, 0));
192 sw_w32(v, rtl_table_data(r, 1));
193 sw_w32(w, rtl_table_data(r, 2));
194
195 rtl_table_write(r, vlan);
196 rtl_table_release(r);
197 }
198
199 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
200 {
201 u32 u, v;
202
203 // Access UNTAG table (0) via table register 1
204 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
205
206 u = portmask >> 21;
207 v = portmask << 11;
208
209 sw_w32(u, rtl_table_data(r, 0));
210 sw_w32(v, rtl_table_data(r, 1));
211 rtl_table_write(r, vlan);
212
213 rtl_table_release(r);
214 }
215
216 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
217 */
218 static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
219 {
220 if (is_set)
221 rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
222 else
223 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
224 }
225
226 /*
227 * Hash seed is vid (actually rvid) concatenated with the MAC address
228 */
229 static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)
230 {
231 u64 v = vid;
232
233 v <<= 48;
234 v |= mac;
235
236 return v;
237 }
238
239 /*
240 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
241 * and returns a key into the L2 hash table
242 */
243 static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
244 {
245 u32 h1, h2, h;
246
247 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
248 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
249 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
250 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
251 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
252 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
253 ^ (seed & 0x3f));
254 h = (h1 << 6) | h2;
255 } else {
256 h = (seed >> 60)
257 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
258 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
259 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
260 }
261
262 return h;
263 }
264
265 static inline int rtl839x_mac_force_mode_ctrl(int p)
266 {
267 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
268 }
269
270 static inline int rtl839x_mac_port_ctrl(int p)
271 {
272 return RTL839X_MAC_PORT_CTRL(p);
273 }
274
275 static inline int rtl839x_l2_port_new_salrn(int p)
276 {
277 return RTL839X_L2_PORT_NEW_SALRN(p);
278 }
279
280 static inline int rtl839x_l2_port_new_sa_fwd(int p)
281 {
282 return RTL839X_L2_PORT_NEW_SA_FWD(p);
283 }
284
285 static inline int rtl839x_mac_link_spd_sts(int p)
286 {
287 return RTL839X_MAC_LINK_SPD_STS(p);
288 }
289
290 static inline int rtl839x_trk_mbr_ctr(int group)
291 {
292 return RTL839X_TRK_MBR_CTR + (group << 3);
293 }
294
295 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
296 {
297 /* Table contains different entry types, we need to identify the right one:
298 * Check for MC entries, first
299 */
300 e->is_ip_mc = !!(r[2] & BIT(31));
301 e->is_ipv6_mc = !!(r[2] & BIT(30));
302 e->type = L2_INVALID;
303 if (!e->is_ip_mc && !e->is_ipv6_mc) {
304 e->mac[0] = (r[0] >> 12);
305 e->mac[1] = (r[0] >> 4);
306 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
307 e->mac[3] = (r[1] >> 20);
308 e->mac[4] = (r[1] >> 12);
309 e->mac[5] = (r[1] >> 4);
310
311 e->vid = (r[2] >> 4) & 0xfff;
312 e->rvid = (r[0] >> 20) & 0xfff;
313
314 /* Is it a unicast entry? check multicast bit */
315 if (!(e->mac[0] & 1)) {
316 e->is_static = !!((r[2] >> 18) & 1);
317 e->port = (r[2] >> 24) & 0x3f;
318 e->block_da = !!(r[2] & (1 << 19));
319 e->block_sa = !!(r[2] & (1 << 20));
320 e->suspended = !!(r[2] & (1 << 17));
321 e->next_hop = !!(r[2] & (1 << 16));
322 if (e->next_hop) {
323 pr_debug("Found next hop entry, need to read data\n");
324 e->nh_vlan_target = !!(r[2] & BIT(15));
325 e->nh_route_id = (r[2] >> 4) & 0x1ff;
326 e->vid = e->rvid;
327 }
328 e->age = (r[2] >> 21) & 3;
329 e->valid = true;
330 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
331 e->valid = false;
332 else
333 e->type = L2_UNICAST;
334 } else {
335 e->valid = true;
336 e->type = L2_MULTICAST;
337 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
338 e->vid = e->rvid;
339 }
340 } else { // IPv4 and IPv6 multicast
341 e->vid = e->rvid = (r[0] << 20) & 0xfff;
342 e->mc_gip = r[1];
343 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
344 }
345 if (e->is_ip_mc) {
346 e->valid = true;
347 e->type = IP4_MULTICAST;
348 }
349 if (e->is_ipv6_mc) {
350 e->valid = true;
351 e->type = IP6_MULTICAST;
352 }
353 // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid);
354 }
355
356 /*
357 * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry
358 */
359 static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
360 {
361 if (!e->valid) {
362 r[0] = r[1] = r[2] = 0;
363 return;
364 }
365
366 r[2] = e->is_ip_mc ? BIT(31) : 0;
367 r[2] |= e->is_ipv6_mc ? BIT(30) : 0;
368
369 if (!e->is_ip_mc && !e->is_ipv6_mc) {
370 r[0] = ((u32)e->mac[0]) << 12;
371 r[0] |= ((u32)e->mac[1]) << 4;
372 r[0] |= ((u32)e->mac[2]) >> 4;
373 r[1] = ((u32)e->mac[2]) << 28;
374 r[1] |= ((u32)e->mac[3]) << 20;
375 r[1] |= ((u32)e->mac[4]) << 12;
376 r[1] |= ((u32)e->mac[5]) << 4;
377
378 if (!(e->mac[0] & 1)) { // Not multicast
379 r[2] |= e->is_static ? BIT(18) : 0;
380 r[0] |= ((u32)e->rvid) << 20;
381 r[2] |= e->port << 24;
382 r[2] |= e->block_da ? BIT(19) : 0;
383 r[2] |= e->block_sa ? BIT(20) : 0;
384 r[2] |= e->suspended ? BIT(17) : 0;
385 r[2] |= ((u32)e->age) << 21;
386 if (e->next_hop) {
387 r[2] |= BIT(16);
388 r[2] |= e->nh_vlan_target ? BIT(15) : 0;
389 r[2] |= (e->nh_route_id & 0x7ff) << 4;
390 } else {
391 r[2] |= e->vid << 4;
392 }
393 pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]);
394 } else { // L2 Multicast
395 r[0] |= ((u32)e->rvid) << 20;
396 r[2] |= ((u32)e->mc_portmask_index) << 6;
397 }
398 } else { // IPv4 or IPv6 MC entry
399 r[0] = ((u32)e->rvid) << 20;
400 r[1] = e->mc_gip;
401 r[2] |= ((u32)e->mc_portmask_index) << 6;
402 }
403 }
404
405 /*
406 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
407 * hash is the id of the bucket and pos is the position of the entry in that bucket
408 * The data read from the SoC is filled into rtl838x_l2_entry
409 */
410 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
411 {
412 u32 r[3];
413 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
414 u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
415 int i;
416
417 rtl_table_read(q, idx);
418 for (i= 0; i < 3; i++)
419 r[i] = sw_r32(rtl_table_data(q, i));
420
421 rtl_table_release(q);
422
423 rtl839x_fill_l2_entry(r, e);
424 if (!e->valid)
425 return 0;
426
427 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
428 }
429
430 static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
431 {
432 u32 r[3];
433 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
434 int i;
435
436 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
437
438 rtl839x_fill_l2_row(r, e);
439
440 for (i= 0; i < 3; i++)
441 sw_w32(r[i], rtl_table_data(q, i));
442
443 rtl_table_write(q, idx);
444 rtl_table_release(q);
445 }
446
447 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
448 {
449 u32 r[3];
450 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
451 int i;
452
453 rtl_table_read(q, idx);
454 for (i= 0; i < 3; i++)
455 r[i] = sw_r32(rtl_table_data(q, i));
456
457 rtl_table_release(q);
458
459 rtl839x_fill_l2_entry(r, e);
460 if (!e->valid)
461 return 0;
462
463 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
464
465 // Return MAC with concatenated VID ac concatenated ID
466 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
467 }
468
469 static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)
470 {
471 u32 r[3];
472 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
473 int i;
474
475 rtl839x_fill_l2_row(r, e);
476
477 for (i= 0; i < 3; i++)
478 sw_w32(r[i], rtl_table_data(q, i));
479
480 rtl_table_write(q, idx);
481 rtl_table_release(q);
482 }
483
484 static u64 rtl839x_read_mcast_pmask(int idx)
485 {
486 u64 portmask;
487 // Read MC_PMSK (2) via register RTL8390_TBL_L2
488 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
489
490 rtl_table_read(q, idx);
491 portmask = sw_r32(rtl_table_data(q, 0));
492 portmask <<= 32;
493 portmask |= sw_r32(rtl_table_data(q, 1));
494 portmask >>= 11; // LSB is bit 11 in data registers
495 rtl_table_release(q);
496
497 return portmask;
498 }
499
500 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
501 {
502 // Access MC_PMSK (2) via register RTL8380_TBL_L2
503 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
504
505 portmask <<= 11; // LSB is bit 11 in data registers
506 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
507 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
508 rtl_table_write(q, idx);
509 rtl_table_release(q);
510 }
511
512 static void rtl839x_vlan_profile_setup(int profile)
513 {
514 u32 p[2];
515 u32 pmask_id = UNKNOWN_MC_PMASK;
516
517 p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding
518 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
519 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
520
521 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
522 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
523
524 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);
525 }
526
527 u64 rtl839x_traffic_get(int source)
528 {
529 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
530 }
531
532 void rtl839x_traffic_set(int source, u64 dest_matrix)
533 {
534 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
535 }
536
537 void rtl839x_traffic_enable(int source, int dest)
538 {
539 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
540 }
541
542 void rtl839x_traffic_disable(int source, int dest)
543 {
544 rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));
545 }
546
547 static void rtl839x_l2_learning_setup(void)
548 {
549 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
550 * address flooding to the reserved entry in the portmask table used
551 * also for multicast flooding */
552 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);
553
554 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
555 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT);
556
557 // Do not trap ARP packets to CPU_PORT
558 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL);
559 }
560
561 static void rtl839x_enable_learning(int port, bool enable)
562 {
563 // Limit learning to maximum: 32k entries
564
565 sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0,
566 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
567 }
568
569 static void rtl839x_enable_flood(int port, bool enable)
570 {
571 /*
572 * 0: Forward
573 * 1: Disable
574 * 2: to CPU
575 * 3: Copy to CPU
576 */
577 sw_w32_mask(0x3, enable ? 0 : 1,
578 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
579 }
580
581 static void rtl839x_enable_mcast_flood(int port, bool enable)
582 {
583
584 }
585
586 static void rtl839x_enable_bcast_flood(int port, bool enable)
587 {
588
589 }
590 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
591 {
592 struct dsa_switch *ds = dev_id;
593 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
594 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
595 u64 link;
596 int i;
597
598 /* Clear status */
599 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
600 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
601
602 for (i = 0; i < RTL839X_CPU_PORT; i++) {
603 if (ports & BIT_ULL(i)) {
604 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
605 if (link & BIT_ULL(i))
606 dsa_port_phylink_mac_change(ds, i, true);
607 else
608 dsa_port_phylink_mac_change(ds, i, false);
609 }
610 }
611 return IRQ_HANDLED;
612 }
613
614 // TODO: unused
615 int rtl8390_sds_power(int mac, int val)
616 {
617 u32 offset = (mac == 48) ? 0x0 : 0x100;
618 u32 mode = val ? 0 : 1;
619
620 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
621
622 if ((mac != 48) && (mac != 49)) {
623 pr_err("%s: not an SFP port: %d\n", __func__, mac);
624 return -1;
625 }
626
627 // Set bit 1003. 1000 starts at 7c
628 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
629
630 return 0;
631 }
632
633 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
634 {
635 u32 v;
636
637 if (port > 63 || page > 4095 || reg > 31)
638 return -ENOTSUPP;
639
640 // Take bug on RTL839x Rev <= C into account
641 if (port >= RTL839X_CPU_PORT)
642 return -EIO;
643
644 mutex_lock(&smi_lock);
645
646 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
647 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
648 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
649
650 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
651
652 v |= 1;
653 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
654
655 do {
656 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
657
658 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
659
660 mutex_unlock(&smi_lock);
661 return 0;
662 }
663
664 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
665 {
666 u32 v;
667 int err = 0;
668
669 val &= 0xffff;
670 if (port > 63 || page > 4095 || reg > 31)
671 return -ENOTSUPP;
672
673 // Take bug on RTL839x Rev <= C into account
674 if (port >= RTL839X_CPU_PORT)
675 return -EIO;
676
677 mutex_lock(&smi_lock);
678
679 // Set PHY to access
680 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
681
682 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
683
684 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
685 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
686
687 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
688
689 v |= BIT(3) | 1; /* Write operation and execute */
690 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
691
692 do {
693 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
694
695 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
696 err = -EIO;
697
698 mutex_unlock(&smi_lock);
699 return err;
700 }
701
702 /*
703 * Read an mmd register of the PHY
704 */
705 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
706 {
707 int err = 0;
708 u32 v;
709
710 // Take bug on RTL839x Rev <= C into account
711 if (port >= RTL839X_CPU_PORT)
712 return -EIO;
713
714 mutex_lock(&smi_lock);
715
716 // Set PHY to access
717 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
718
719 // Set MMD device number and register to write to
720 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
721
722 v = BIT(2) | BIT(0); // MMD-access | EXEC
723 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
724
725 do {
726 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
727 } while (v & BIT(0));
728 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
729 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
730 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
731
732 mutex_unlock(&smi_lock);
733
734 return err;
735 }
736
737 /*
738 * Write to an mmd register of the PHY
739 */
740 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
741 {
742 int err = 0;
743 u32 v;
744
745 // Take bug on RTL839x Rev <= C into account
746 if (port >= RTL839X_CPU_PORT)
747 return -EIO;
748
749 mutex_lock(&smi_lock);
750
751 // Set PHY to access
752 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
753
754 // Set data to write
755 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
756
757 // Set MMD device number and register to write to
758 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
759
760 v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
761 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
762
763 do {
764 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
765 } while (v & BIT(0));
766
767 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
768 mutex_unlock(&smi_lock);
769 return err;
770 }
771
772 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
773 {
774 u32 info, model;
775
776 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
777 info = sw_r32(RTL839X_CHIP_INFO);
778
779 model = sw_r32(RTL839X_MODEL_NAME_INFO);
780 priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);
781
782 pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
783 }
784
785 void rtl839x_vlan_profile_dump(int profile)
786 {
787 u32 p[2];
788
789 if (profile < 0 || profile > 7)
790 return;
791
792 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
793 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
794
795 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
796 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
797 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
798 (p[0]) & 0xfff);
799 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
800 }
801
802 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
803 {
804 int i;
805 u32 cmd = 1 << 16 /* Execute cmd */
806 | 0 << 15 /* Read */
807 | 5 << 12 /* Table type 0b101 */
808 | (msti & 0xfff);
809 priv->r->exec_tbl0_cmd(cmd);
810
811 for (i = 0; i < 4; i++)
812 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
813 }
814
815 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
816 {
817 int i;
818 u32 cmd = 1 << 16 /* Execute cmd */
819 | 1 << 15 /* Write */
820 | 5 << 12 /* Table type 0b101 */
821 | (msti & 0xfff);
822 for (i = 0; i < 4; i++)
823 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
824 priv->r->exec_tbl0_cmd(cmd);
825 }
826
827 /*
828 * Enables or disables the EEE/EEEP capability of a port
829 */
830 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
831 {
832 u32 v;
833
834 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
835 if (port >= 48)
836 return;
837
838 enable = true;
839 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
840 v = enable ? 0xf : 0x0;
841
842 // Set EEE for 100, 500, 1000MBit and 10GBit
843 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
844
845 // Set TX/RX EEE state
846 v = enable ? 0x3 : 0x0;
847 sw_w32(v, RTL839X_EEE_CTRL(port));
848
849 priv->ports[port].eee_enabled = enable;
850 }
851
852 /*
853 * Get EEE own capabilities and negotiation result
854 */
855 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
856 {
857 u64 link, a;
858
859 if (port >= 48)
860 return 0;
861
862 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
863 if (!(link & BIT_ULL(port)))
864 return 0;
865
866 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
867 e->advertised |= ADVERTISED_100baseT_Full;
868
869 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
870 e->advertised |= ADVERTISED_1000baseT_Full;
871
872 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
873 pr_info("Link partner: %016llx\n", a);
874 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
875 e->lp_advertised = ADVERTISED_100baseT_Full;
876 e->lp_advertised |= ADVERTISED_1000baseT_Full;
877 return 1;
878 }
879
880 return 0;
881 }
882
883 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
884 {
885 int i;
886
887 pr_info("Setting up EEE, state: %d\n", enable);
888
889 // Set wake timer for TX and pause timer both to 0x21
890 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
891 // Set pause wake timer for GIGA-EEE to 0x11
892 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
893 // Set pause wake timer for 10GBit ports to 0x11
894 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
895
896 // Setup EEE on all ports
897 for (i = 0; i < priv->cpu_port; i++) {
898 if (priv->ports[i].phy)
899 rtl839x_port_eee_set(priv, i, enable);
900 }
901 priv->eee_enabled = enable;
902 }
903
904 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
905 {
906 int block = index / PIE_BLOCK_SIZE;
907
908 sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL);
909 }
910
911 /*
912 * Delete a range of Packet Inspection Engine rules
913 */
914 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
915 {
916 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
917
918 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
919 mutex_lock(&priv->reg_mutex);
920
921 // Write from-to and execute bit into control register
922 sw_w32(v, RTL839X_ACL_CLR_CTRL);
923
924 // Wait until command has completed
925 do {
926 } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0));
927
928 mutex_unlock(&priv->reg_mutex);
929 return 0;
930 }
931
932 /*
933 * Reads the intermediate representation of the templated match-fields of the
934 * PIE rule in the pie_rule structure and fills in the raw data fields in the
935 * raw register space r[].
936 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
937 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
938 * on all SoCs
939 * On the RTL8390 the template mask registers are not word-aligned!
940 */
941 static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
942 {
943 int i;
944 enum template_field_id field_type;
945 u16 data, data_m;
946
947 for (i = 0; i < N_FIXED_FIELDS; i++) {
948 field_type = t[i];
949 data = data_m = 0;
950
951 switch (field_type) {
952 case TEMPLATE_FIELD_SPM0:
953 data = pr->spm;
954 data_m = pr->spm_m;
955 break;
956 case TEMPLATE_FIELD_SPM1:
957 data = pr->spm >> 16;
958 data_m = pr->spm_m >> 16;
959 break;
960 case TEMPLATE_FIELD_SPM2:
961 data = pr->spm >> 32;
962 data_m = pr->spm_m >> 32;
963 break;
964 case TEMPLATE_FIELD_SPM3:
965 data = pr->spm >> 48;
966 data_m = pr->spm_m >> 48;
967 break;
968 case TEMPLATE_FIELD_OTAG:
969 data = pr->otag;
970 data_m = pr->otag_m;
971 break;
972 case TEMPLATE_FIELD_SMAC0:
973 data = pr->smac[4];
974 data = (data << 8) | pr->smac[5];
975 data_m = pr->smac_m[4];
976 data_m = (data_m << 8) | pr->smac_m[5];
977 break;
978 case TEMPLATE_FIELD_SMAC1:
979 data = pr->smac[2];
980 data = (data << 8) | pr->smac[3];
981 data_m = pr->smac_m[2];
982 data_m = (data_m << 8) | pr->smac_m[3];
983 break;
984 case TEMPLATE_FIELD_SMAC2:
985 data = pr->smac[0];
986 data = (data << 8) | pr->smac[1];
987 data_m = pr->smac_m[0];
988 data_m = (data_m << 8) | pr->smac_m[1];
989 break;
990 case TEMPLATE_FIELD_DMAC0:
991 data = pr->dmac[4];
992 data = (data << 8) | pr->dmac[5];
993 data_m = pr->dmac_m[4];
994 data_m = (data_m << 8) | pr->dmac_m[5];
995 break;
996 case TEMPLATE_FIELD_DMAC1:
997 data = pr->dmac[2];
998 data = (data << 8) | pr->dmac[3];
999 data_m = pr->dmac_m[2];
1000 data_m = (data_m << 8) | pr->dmac_m[3];
1001 break;
1002 case TEMPLATE_FIELD_DMAC2:
1003 data = pr->dmac[0];
1004 data = (data << 8) | pr->dmac[1];
1005 data_m = pr->dmac_m[0];
1006 data_m = (data_m << 8) | pr->dmac_m[1];
1007 break;
1008 case TEMPLATE_FIELD_ETHERTYPE:
1009 data = pr->ethertype;
1010 data_m = pr->ethertype_m;
1011 break;
1012 case TEMPLATE_FIELD_ITAG:
1013 data = pr->itag;
1014 data_m = pr->itag_m;
1015 break;
1016 case TEMPLATE_FIELD_SIP0:
1017 if (pr->is_ipv6) {
1018 data = pr->sip6.s6_addr16[7];
1019 data_m = pr->sip6_m.s6_addr16[7];
1020 } else {
1021 data = pr->sip;
1022 data_m = pr->sip_m;
1023 }
1024 break;
1025 case TEMPLATE_FIELD_SIP1:
1026 if (pr->is_ipv6) {
1027 data = pr->sip6.s6_addr16[6];
1028 data_m = pr->sip6_m.s6_addr16[6];
1029 } else {
1030 data = pr->sip >> 16;
1031 data_m = pr->sip_m >> 16;
1032 }
1033 break;
1034
1035 case TEMPLATE_FIELD_SIP2:
1036 case TEMPLATE_FIELD_SIP3:
1037 case TEMPLATE_FIELD_SIP4:
1038 case TEMPLATE_FIELD_SIP5:
1039 case TEMPLATE_FIELD_SIP6:
1040 case TEMPLATE_FIELD_SIP7:
1041 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1042 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1043 break;
1044
1045 case TEMPLATE_FIELD_DIP0:
1046 if (pr->is_ipv6) {
1047 data = pr->dip6.s6_addr16[7];
1048 data_m = pr->dip6_m.s6_addr16[7];
1049 } else {
1050 data = pr->dip;
1051 data_m = pr->dip_m;
1052 }
1053 break;
1054
1055 case TEMPLATE_FIELD_DIP1:
1056 if (pr->is_ipv6) {
1057 data = pr->dip6.s6_addr16[6];
1058 data_m = pr->dip6_m.s6_addr16[6];
1059 } else {
1060 data = pr->dip >> 16;
1061 data_m = pr->dip_m >> 16;
1062 }
1063 break;
1064
1065 case TEMPLATE_FIELD_DIP2:
1066 case TEMPLATE_FIELD_DIP3:
1067 case TEMPLATE_FIELD_DIP4:
1068 case TEMPLATE_FIELD_DIP5:
1069 case TEMPLATE_FIELD_DIP6:
1070 case TEMPLATE_FIELD_DIP7:
1071 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1072 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1073 break;
1074
1075 case TEMPLATE_FIELD_IP_TOS_PROTO:
1076 data = pr->tos_proto;
1077 data_m = pr->tos_proto_m;
1078 break;
1079 case TEMPLATE_FIELD_L4_SPORT:
1080 data = pr->sport;
1081 data_m = pr->sport_m;
1082 break;
1083 case TEMPLATE_FIELD_L4_DPORT:
1084 data = pr->dport;
1085 data_m = pr->dport_m;
1086 break;
1087 case TEMPLATE_FIELD_ICMP_IGMP:
1088 data = pr->icmp_igmp;
1089 data_m = pr->icmp_igmp_m;
1090 break;
1091 default:
1092 pr_info("%s: unknown field %d\n", __func__, field_type);
1093 }
1094
1095 // On the RTL8390, the mask fields are not word aligned!
1096 if (!(i % 2)) {
1097 r[5 - i / 2] = data;
1098 r[12 - i / 2] |= ((u32)data_m << 8);
1099 } else {
1100 r[5 - i / 2] |= ((u32)data) << 16;
1101 r[12 - i / 2] |= ((u32)data_m) << 24;
1102 r[11 - i / 2] |= ((u32)data_m) >> 8;
1103 }
1104 }
1105 }
1106
1107 /*
1108 * Creates the intermediate representation of the templated match-fields of the
1109 * PIE rule in the pie_rule structure by reading the raw data fields in the
1110 * raw register space r[].
1111 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1112 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1113 * On the RTL8390 the template mask registers are not word-aligned!
1114 */
1115 void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1116 {
1117 int i;
1118 enum template_field_id field_type;
1119 u16 data, data_m;
1120
1121 for (i = 0; i < N_FIXED_FIELDS; i++) {
1122 field_type = t[i];
1123 if (!(i % 2)) {
1124 data = r[5 - i / 2];
1125 data_m = r[12 - i / 2];
1126 } else {
1127 data = r[5 - i / 2] >> 16;
1128 data_m = r[12 - i / 2] >> 16;
1129 }
1130
1131 switch (field_type) {
1132 case TEMPLATE_FIELD_SPM0:
1133 pr->spm = (pr->spn << 16) | data;
1134 pr->spm_m = (pr->spn << 16) | data_m;
1135 break;
1136 case TEMPLATE_FIELD_SPM1:
1137 pr->spm = data;
1138 pr->spm_m = data_m;
1139 break;
1140 case TEMPLATE_FIELD_OTAG:
1141 pr->otag = data;
1142 pr->otag_m = data_m;
1143 break;
1144 case TEMPLATE_FIELD_SMAC0:
1145 pr->smac[4] = data >> 8;
1146 pr->smac[5] = data;
1147 pr->smac_m[4] = data >> 8;
1148 pr->smac_m[5] = data;
1149 break;
1150 case TEMPLATE_FIELD_SMAC1:
1151 pr->smac[2] = data >> 8;
1152 pr->smac[3] = data;
1153 pr->smac_m[2] = data >> 8;
1154 pr->smac_m[3] = data;
1155 break;
1156 case TEMPLATE_FIELD_SMAC2:
1157 pr->smac[0] = data >> 8;
1158 pr->smac[1] = data;
1159 pr->smac_m[0] = data >> 8;
1160 pr->smac_m[1] = data;
1161 break;
1162 case TEMPLATE_FIELD_DMAC0:
1163 pr->dmac[4] = data >> 8;
1164 pr->dmac[5] = data;
1165 pr->dmac_m[4] = data >> 8;
1166 pr->dmac_m[5] = data;
1167 break;
1168 case TEMPLATE_FIELD_DMAC1:
1169 pr->dmac[2] = data >> 8;
1170 pr->dmac[3] = data;
1171 pr->dmac_m[2] = data >> 8;
1172 pr->dmac_m[3] = data;
1173 break;
1174 case TEMPLATE_FIELD_DMAC2:
1175 pr->dmac[0] = data >> 8;
1176 pr->dmac[1] = data;
1177 pr->dmac_m[0] = data >> 8;
1178 pr->dmac_m[1] = data;
1179 break;
1180 case TEMPLATE_FIELD_ETHERTYPE:
1181 pr->ethertype = data;
1182 pr->ethertype_m = data_m;
1183 break;
1184 case TEMPLATE_FIELD_ITAG:
1185 pr->itag = data;
1186 pr->itag_m = data_m;
1187 break;
1188 case TEMPLATE_FIELD_SIP0:
1189 pr->sip = data;
1190 pr->sip_m = data_m;
1191 break;
1192 case TEMPLATE_FIELD_SIP1:
1193 pr->sip = (pr->sip << 16) | data;
1194 pr->sip_m = (pr->sip << 16) | data_m;
1195 break;
1196 case TEMPLATE_FIELD_SIP2:
1197 pr->is_ipv6 = true;
1198 // Make use of limitiations on the position of the match values
1199 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
1200 r[4 - i / 2], r[3 - i / 2]);
1201 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
1202 r[4 - i / 2], r[3 - i / 2]);
1203 case TEMPLATE_FIELD_SIP3:
1204 case TEMPLATE_FIELD_SIP4:
1205 case TEMPLATE_FIELD_SIP5:
1206 case TEMPLATE_FIELD_SIP6:
1207 case TEMPLATE_FIELD_SIP7:
1208 break;
1209
1210 case TEMPLATE_FIELD_DIP0:
1211 pr->dip = data;
1212 pr->dip_m = data_m;
1213 break;
1214
1215 case TEMPLATE_FIELD_DIP1:
1216 pr->dip = (pr->dip << 16) | data;
1217 pr->dip_m = (pr->dip << 16) | data_m;
1218 break;
1219
1220 case TEMPLATE_FIELD_DIP2:
1221 pr->is_ipv6 = true;
1222 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1223 r[4 - i / 2], r[3 - i / 2]);
1224 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1225 r[4 - i / 2], r[3 - i / 2]);
1226 case TEMPLATE_FIELD_DIP3:
1227 case TEMPLATE_FIELD_DIP4:
1228 case TEMPLATE_FIELD_DIP5:
1229 case TEMPLATE_FIELD_DIP6:
1230 case TEMPLATE_FIELD_DIP7:
1231 break;
1232 case TEMPLATE_FIELD_IP_TOS_PROTO:
1233 pr->tos_proto = data;
1234 pr->tos_proto_m = data_m;
1235 break;
1236 case TEMPLATE_FIELD_L4_SPORT:
1237 pr->sport = data;
1238 pr->sport_m = data_m;
1239 break;
1240 case TEMPLATE_FIELD_L4_DPORT:
1241 pr->dport = data;
1242 pr->dport_m = data_m;
1243 break;
1244 case TEMPLATE_FIELD_ICMP_IGMP:
1245 pr->icmp_igmp = data;
1246 pr->icmp_igmp_m = data_m;
1247 break;
1248 default:
1249 pr_info("%s: unknown field %d\n", __func__, field_type);
1250 }
1251 }
1252 }
1253
1254 static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1255 {
1256 pr->spmmask_fix = (r[6] >> 30) & 0x3;
1257 pr->spn = (r[6] >> 24) & 0x3f;
1258 pr->mgnt_vlan = (r[6] >> 23) & 1;
1259 pr->dmac_hit_sw = (r[6] >> 22) & 1;
1260 pr->not_first_frag = (r[6] >> 21) & 1;
1261 pr->frame_type_l4 = (r[6] >> 18) & 7;
1262 pr->frame_type = (r[6] >> 16) & 3;
1263 pr->otag_fmt = (r[6] >> 15) & 1;
1264 pr->itag_fmt = (r[6] >> 14) & 1;
1265 pr->otag_exist = (r[6] >> 13) & 1;
1266 pr->itag_exist = (r[6] >> 12) & 1;
1267 pr->frame_type_l2 = (r[6] >> 10) & 3;
1268 pr->tid = (r[6] >> 8) & 3;
1269
1270 pr->spmmask_fix_m = (r[12] >> 6) & 0x3;
1271 pr->spn_m = r[12] & 0x3f;
1272 pr->mgnt_vlan_m = (r[13] >> 31) & 1;
1273 pr->dmac_hit_sw_m = (r[13] >> 30) & 1;
1274 pr->not_first_frag_m = (r[13] >> 29) & 1;
1275 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1276 pr->frame_type_m = (r[13] >> 24) & 3;
1277 pr->otag_fmt_m = (r[13] >> 23) & 1;
1278 pr->itag_fmt_m = (r[13] >> 22) & 1;
1279 pr->otag_exist_m = (r[13] >> 21) & 1;
1280 pr->itag_exist_m = (r[13] >> 20) & 1;
1281 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1282 pr->tid_m = (r[13] >> 16) & 3;
1283
1284 pr->valid = r[13] & BIT(15);
1285 pr->cond_not = r[13] & BIT(14);
1286 pr->cond_and1 = r[13] & BIT(13);
1287 pr->cond_and2 = r[13] & BIT(12);
1288 }
1289
1290 static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1291 {
1292 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;
1293 r[6] |= ((u32) (pr->spn & 0x3f)) << 24;
1294 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1295 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1296 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1297 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1298 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1299 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1300 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1301 r[6] |= pr->otag_exist ? BIT(13) : 0;
1302 r[6] |= pr->itag_exist ? BIT(12) : 0;
1303 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1304 r[6] |= ((u32) (pr->tid & 0x3)) << 8;
1305
1306 r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;
1307 r[12] |= (u32) (pr->spn_m & 0x3f);
1308 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1309 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1310 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1311 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1312 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1313 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1314 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1315 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1316 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1317 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1318 r[13] |= ((u32) (pr->tid_m & 0x3)) << 16;
1319
1320 r[13] |= pr->valid ? BIT(15) : 0;
1321 r[13] |= pr->cond_not ? BIT(14) : 0;
1322 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1323 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1324 }
1325
1326 static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr)
1327 {
1328 if (pr->drop) {
1329 r[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP
1330 r[13] |= BIT(3);
1331 } else {
1332 r[13] |= pr->fwd_sel ? BIT(3) : 0;
1333 r[13] |= pr->fwd_act;
1334 }
1335 r[13] |= pr->bypass_sel ? BIT(11) : 0;
1336 r[13] |= pr->mpls_sel ? BIT(10) : 0;
1337 r[13] |= pr->nopri_sel ? BIT(9) : 0;
1338 r[13] |= pr->ovid_sel ? BIT(8) : 0;
1339 r[13] |= pr->ivid_sel ? BIT(7) : 0;
1340 r[13] |= pr->meter_sel ? BIT(6) : 0;
1341 r[13] |= pr->mir_sel ? BIT(5) : 0;
1342 r[13] |= pr->log_sel ? BIT(4) : 0;
1343
1344 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18;
1345 r[14] |= pr->log_octets ? BIT(17) : 0;
1346 r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4;
1347 r[14] |= (pr->mir_data & 0x3) << 3;
1348 r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7;
1349 r[15] |= (u32)(pr->meter_data) << 26;
1350 r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3;
1351 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1352 r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3;
1353 r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff;
1354 r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28;
1355 r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20;
1356 r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20;
1357 r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20;
1358 r[16] |= pr->bypass_all ? BIT(9) : 0;
1359 r[16] |= pr->bypass_igr_stp ? BIT(8) : 0;
1360 r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0;
1361 }
1362
1363 static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr)
1364 {
1365 if (r[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop?
1366 if ((r[14] & 0x7) == 1) {
1367 pr->drop = true;
1368 } else {
1369 pr->fwd_sel = true;
1370 pr->fwd_act = r[14] & 0x7;
1371 }
1372 }
1373
1374 pr->bypass_sel = r[13] & BIT(11);
1375 pr->mpls_sel = r[13] & BIT(10);
1376 pr->nopri_sel = r[13] & BIT(9);
1377 pr->ovid_sel = r[13] & BIT(8);
1378 pr->ivid_sel = r[13] & BIT(7);
1379 pr->meter_sel = r[13] & BIT(6);
1380 pr->mir_sel = r[13] & BIT(5);
1381 pr->log_sel = r[13] & BIT(4);
1382
1383 // TODO: Read in data fields
1384
1385 pr->bypass_all = r[16] & BIT(9);
1386 pr->bypass_igr_stp = r[16] & BIT(8);
1387 pr->bypass_ibc_sc = r[16] & BIT(7);
1388 }
1389
1390 void rtl839x_pie_rule_dump_raw(u32 r[])
1391 {
1392 pr_info("Raw IACL table entry:\n");
1393 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1394 pr_info("Fixed : %06x\n", r[6] >> 8);
1395 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1396 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1397 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1398 (r[11] << 24) | (r[12] >> 8));
1399 pr_info("R[13]: %08x\n", r[13]);
1400 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1401 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1402 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1403 }
1404
1405 void rtl839x_pie_rule_dump(struct pie_rule *pr)
1406 {
1407 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1408 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1409 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1410 if (pr->fwd_sel)
1411 pr_info("FWD: %08x\n", pr->fwd_data);
1412 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1413 }
1414
1415 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1416 {
1417 // Read IACL table (2) via register 0
1418 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2);
1419 u32 r[17];
1420 int i;
1421 int block = idx / PIE_BLOCK_SIZE;
1422 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1423
1424 memset(pr, 0, sizeof(*pr));
1425 rtl_table_read(q, idx);
1426 for (i = 0; i < 17; i++)
1427 r[i] = sw_r32(rtl_table_data(q, i));
1428
1429 rtl_table_release(q);
1430
1431 rtl839x_read_pie_fixed_fields(r, pr);
1432 if (!pr->valid)
1433 return 0;
1434
1435 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1436 rtl839x_pie_rule_dump_raw(r);
1437
1438 rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1439
1440 rtl839x_read_pie_action(r, pr);
1441
1442 return 0;
1443 }
1444
1445 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1446 {
1447 // Access IACL table (2) via register 0
1448 struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2);
1449 u32 r[17];
1450 int i;
1451 int block = idx / PIE_BLOCK_SIZE;
1452 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1453
1454 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1455
1456 for (i = 0; i < 17; i++)
1457 r[i] = 0;
1458
1459 if (!pr->valid) {
1460 rtl_table_write(q, idx);
1461 rtl_table_release(q);
1462 return 0;
1463 }
1464 rtl839x_write_pie_fixed_fields(r, pr);
1465
1466 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1467 rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1468
1469 rtl839x_write_pie_action(r, pr);
1470
1471 // rtl839x_pie_rule_dump_raw(r);
1472
1473 for (i = 0; i < 17; i++)
1474 sw_w32(r[i], rtl_table_data(q, i));
1475
1476 rtl_table_write(q, idx);
1477 rtl_table_release(q);
1478
1479 return 0;
1480 }
1481
1482 static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)
1483 {
1484 int i;
1485 enum template_field_id ft;
1486
1487 for (i = 0; i < N_FIXED_FIELDS; i++) {
1488 ft = fixed_templates[t][i];
1489 if (field_type == ft)
1490 return true;
1491 }
1492
1493 return false;
1494 }
1495
1496 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv,
1497 struct pie_rule *pr, int t, int block)
1498 {
1499 int i;
1500
1501 if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1502 return -1;
1503
1504 if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1505 return -1;
1506
1507 if (pr->is_ipv6) {
1508 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1509 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1510 && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1511 return -1;
1512 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1513 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1514 && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1515 return -1;
1516 }
1517
1518 if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1519 return -1;
1520
1521 if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1522 return -1;
1523
1524 // TODO: Check more
1525
1526 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1527
1528 if (i >= PIE_BLOCK_SIZE)
1529 return -1;
1530
1531 return i + PIE_BLOCK_SIZE * block;
1532 }
1533
1534 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1535 {
1536 int idx, block, j, t;
1537 int min_block = 0;
1538 int max_block = priv->n_pie_blocks / 2;
1539
1540 if (pr->is_egress) {
1541 min_block = max_block;
1542 max_block = priv->n_pie_blocks;
1543 }
1544
1545 mutex_lock(&priv->pie_mutex);
1546
1547 for (block = min_block; block < max_block; block++) {
1548 for (j = 0; j < 2; j++) {
1549 t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1550 idx = rtl839x_pie_verify_template(priv, pr, t, block);
1551 if (idx >= 0)
1552 break;
1553 }
1554 if (j < 2)
1555 break;
1556 }
1557
1558 if (block >= priv->n_pie_blocks) {
1559 mutex_unlock(&priv->pie_mutex);
1560 return -EOPNOTSUPP;
1561 }
1562
1563 set_bit(idx, priv->pie_use_bm);
1564
1565 pr->valid = true;
1566 pr->tid = j; // Mapped to template number
1567 pr->tid_m = 0x3;
1568 pr->id = idx;
1569
1570 rtl839x_pie_lookup_enable(priv, idx);
1571 rtl839x_pie_rule_write(priv, idx, pr);
1572
1573 mutex_unlock(&priv->pie_mutex);
1574 return 0;
1575 }
1576
1577 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1578 {
1579 int idx = pr->id;
1580
1581 rtl839x_pie_rule_del(priv, idx, idx);
1582 clear_bit(idx, priv->pie_use_bm);
1583 }
1584
1585 static void rtl839x_pie_init(struct rtl838x_switch_priv *priv)
1586 {
1587 int i;
1588 u32 template_selectors;
1589
1590 mutex_init(&priv->pie_mutex);
1591
1592 // Power on all PIE blocks
1593 for (i = 0; i < priv->n_pie_blocks; i++)
1594 sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL);
1595
1596 // Set ingress and egress ACL blocks to 50/50: first Egress block is 9
1597 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); // Writes 9 to cutline field
1598
1599 // Include IPG in metering
1600 sw_w32(1, RTL839X_METER_GLB_CTRL);
1601
1602 // Delete all present rules
1603 rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1604
1605 // Enable predefined templates 0, 1 for blocks 0-2
1606 template_selectors = 0 | (1 << 3);
1607 for (i = 0; i < 3; i++)
1608 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1609
1610 // Enable predefined templates 2, 3 for blocks 3-5
1611 template_selectors = 2 | (3 << 3);
1612 for (i = 3; i < 6; i++)
1613 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1614
1615 // Enable predefined templates 1, 4 for blocks 6-8
1616 template_selectors = 2 | (3 << 3);
1617 for (i = 6; i < 9; i++)
1618 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1619
1620 // Enable predefined templates 0, 1 for blocks 9-11
1621 template_selectors = 0 | (1 << 3);
1622 for (i = 9; i < 12; i++)
1623 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1624
1625 // Enable predefined templates 2, 3 for blocks 12-14
1626 template_selectors = 2 | (3 << 3);
1627 for (i = 12; i < 15; i++)
1628 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1629
1630 // Enable predefined templates 1, 4 for blocks 15-17
1631 template_selectors = 2 | (3 << 3);
1632 for (i = 15; i < 18; i++)
1633 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1634 }
1635
1636 static u32 rtl839x_packet_cntr_read(int counter)
1637 {
1638 u32 v;
1639
1640 // Read LOG table (4) via register RTL8390_TBL_0
1641 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1642
1643 pr_debug("In %s, id %d\n", __func__, counter);
1644 rtl_table_read(r, counter / 2);
1645
1646 // The table has a size of 2 registers
1647 if (counter % 2)
1648 v = sw_r32(rtl_table_data(r, 0));
1649 else
1650 v = sw_r32(rtl_table_data(r, 1));
1651
1652 rtl_table_release(r);
1653
1654 return v;
1655 }
1656
1657 static void rtl839x_packet_cntr_clear(int counter)
1658 {
1659 // Access LOG table (4) via register RTL8390_TBL_0
1660 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1661
1662 pr_debug("In %s, id %d\n", __func__, counter);
1663 // The table has a size of 2 registers
1664 if (counter % 2)
1665 sw_w32(0, rtl_table_data(r, 0));
1666 else
1667 sw_w32(0, rtl_table_data(r, 1));
1668
1669 rtl_table_write(r, counter / 2);
1670
1671 rtl_table_release(r);
1672 }
1673
1674 static void rtl839x_route_read(int idx, struct rtl83xx_route *rt)
1675 {
1676 u64 v;
1677 // Read ROUTING table (2) via register RTL8390_TBL_1
1678 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1679
1680 pr_debug("In %s\n", __func__);
1681 rtl_table_read(r, idx);
1682
1683 // The table has a size of 2 registers
1684 v = sw_r32(rtl_table_data(r, 0));
1685 v <<= 32;
1686 v |= sw_r32(rtl_table_data(r, 1));
1687 rt->switch_mac_id = (v >> 12) & 0xf;
1688 rt->nh.gw = v >> 16;
1689
1690 rtl_table_release(r);
1691 }
1692
1693 static void rtl839x_route_write(int idx, struct rtl83xx_route *rt)
1694 {
1695 u32 v;
1696
1697 // Read ROUTING table (2) via register RTL8390_TBL_1
1698 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1699
1700 pr_debug("In %s\n", __func__);
1701 sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0));
1702 v = rt->nh.gw << 16;
1703 v |= rt->switch_mac_id << 12;
1704 sw_w32(v, rtl_table_data(r, 1));
1705 rtl_table_write(r, idx);
1706
1707 rtl_table_release(r);
1708 }
1709
1710 /*
1711 * Configure the switch's own MAC addresses used when routing packets
1712 */
1713 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)
1714 {
1715 int i;
1716 struct net_device *dev;
1717 u64 mac;
1718
1719 pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp);
1720 dev = priv->ports[priv->cpu_port].dp->slave;
1721 mac = ether_addr_to_u64(dev->dev_addr);
1722
1723 for (i = 0; i < 15; i++) {
1724 mac++; // BUG: VRRP for testing
1725 sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8);
1726 sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4);
1727 }
1728 }
1729
1730 int rtl839x_l3_setup(struct rtl838x_switch_priv *priv)
1731 {
1732 rtl839x_setup_port_macs(priv);
1733
1734 return 0;
1735 }
1736
1737 void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1738 {
1739 if (type == PBVLAN_TYPE_INNER)
1740 sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1741 else
1742 sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1743 }
1744
1745 void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1746 {
1747 if (type == PBVLAN_TYPE_INNER)
1748 sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1749 else
1750 sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1751 }
1752
1753 static int rtl839x_set_ageing_time(unsigned long msec)
1754 {
1755 int t = sw_r32(RTL839X_L2_CTRL_1);
1756
1757 t &= 0x1FFFFF;
1758 t = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1759 pr_debug("L2 AGING time: %d sec\n", t);
1760
1761 t = (msec * 5 + 2000) / 3000;
1762 t = t > 0x1FFFFF ? 0x1FFFFF : t;
1763 sw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1);
1764 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT));
1765
1766 return 0;
1767 }
1768
1769 static void rtl839x_set_igr_filter(int port, enum igr_filter state)
1770 {
1771 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1772 RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1773 }
1774
1775 static void rtl839x_set_egr_filter(int port, enum egr_filter state)
1776 {
1777 sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
1778 RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
1779 }
1780
1781 void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1782 {
1783 sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1),
1784 RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2));
1785 sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2));
1786 }
1787
1788 void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1789 {
1790 switch(type) {
1791 case BPDU:
1792 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1793 RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1794 break;
1795 case PTP:
1796 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1797 RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
1798 break;
1799 case LLTP:
1800 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1801 RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1802 break;
1803 default:
1804 break;
1805 }
1806 }
1807
1808 const struct rtl838x_reg rtl839x_reg = {
1809 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1810 .set_port_reg_be = rtl839x_set_port_reg_be,
1811 .get_port_reg_be = rtl839x_get_port_reg_be,
1812 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1813 .set_port_reg_le = rtl839x_set_port_reg_le,
1814 .get_port_reg_le = rtl839x_get_port_reg_le,
1815 .stat_port_rst = RTL839X_STAT_PORT_RST,
1816 .stat_rst = RTL839X_STAT_RST,
1817 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
1818 .traffic_enable = rtl839x_traffic_enable,
1819 .traffic_disable = rtl839x_traffic_disable,
1820 .traffic_get = rtl839x_traffic_get,
1821 .traffic_set = rtl839x_traffic_set,
1822 .port_iso_ctrl = rtl839x_port_iso_ctrl,
1823 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
1824 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
1825 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
1826 .set_ageing_time = rtl839x_set_ageing_time,
1827 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
1828 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
1829 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
1830 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
1831 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
1832 .isr_glb_src = RTL839X_ISR_GLB_SRC,
1833 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
1834 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
1835 .imr_glb = RTL839X_IMR_GLB,
1836 .vlan_tables_read = rtl839x_vlan_tables_read,
1837 .vlan_set_tagged = rtl839x_vlan_set_tagged,
1838 .vlan_set_untagged = rtl839x_vlan_set_untagged,
1839 .vlan_profile_dump = rtl839x_vlan_profile_dump,
1840 .vlan_profile_setup = rtl839x_vlan_profile_setup,
1841 .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
1842 .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set,
1843 .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set,
1844 .set_vlan_igr_filter = rtl839x_set_igr_filter,
1845 .set_vlan_egr_filter = rtl839x_set_egr_filter,
1846 .enable_learning = rtl839x_enable_learning,
1847 .enable_flood = rtl839x_enable_flood,
1848 .enable_mcast_flood = rtl839x_enable_mcast_flood,
1849 .enable_bcast_flood = rtl839x_enable_bcast_flood,
1850 .stp_get = rtl839x_stp_get,
1851 .stp_set = rtl839x_stp_set,
1852 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
1853 .mac_port_ctrl = rtl839x_mac_port_ctrl,
1854 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
1855 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
1856 .mir_ctrl = RTL839X_MIR_CTRL,
1857 .mir_dpm = RTL839X_MIR_DPM_CTRL,
1858 .mir_spm = RTL839X_MIR_SPM_CTRL,
1859 .mac_link_sts = RTL839X_MAC_LINK_STS,
1860 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
1861 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
1862 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
1863 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
1864 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
1865 .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,
1866 .read_cam = rtl839x_read_cam,
1867 .write_cam = rtl839x_write_cam,
1868 .vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
1869 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
1870 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
1871 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
1872 .init_eee = rtl839x_init_eee,
1873 .port_eee_set = rtl839x_port_eee_set,
1874 .eee_port_ability = rtl839x_eee_port_ability,
1875 .l2_hash_seed = rtl839x_l2_hash_seed,
1876 .l2_hash_key = rtl839x_l2_hash_key,
1877 .read_mcast_pmask = rtl839x_read_mcast_pmask,
1878 .write_mcast_pmask = rtl839x_write_mcast_pmask,
1879 .pie_init = rtl839x_pie_init,
1880 .pie_rule_read = rtl839x_pie_rule_read,
1881 .pie_rule_write = rtl839x_pie_rule_write,
1882 .pie_rule_add = rtl839x_pie_rule_add,
1883 .pie_rule_rm = rtl839x_pie_rule_rm,
1884 .l2_learning_setup = rtl839x_l2_learning_setup,
1885 .packet_cntr_read = rtl839x_packet_cntr_read,
1886 .packet_cntr_clear = rtl839x_packet_cntr_clear,
1887 .route_read = rtl839x_route_read,
1888 .route_write = rtl839x_route_write,
1889 .l3_setup = rtl839x_l3_setup,
1890 .set_distribution_algorithm = rtl839x_set_distribution_algorithm,
1891 .set_receive_management_action = rtl839x_set_receive_management_action,
1892 };
Staging tree of Jo-Philipp Wich