1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6 extern struct mutex smi_lock
;
7 extern struct rtl83xx_soc_info soc_info
;
9 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
10 enum template_field_id
{
11 TEMPLATE_FIELD_SPMMASK
= 0,
12 TEMPLATE_FIELD_SPM0
= 1, // Source portmask ports 0-15
13 TEMPLATE_FIELD_SPM1
= 2, // Source portmask ports 16-31
14 TEMPLATE_FIELD_SPM2
= 3, // Source portmask ports 32-47
15 TEMPLATE_FIELD_SPM3
= 4, // Source portmask ports 48-56
16 TEMPLATE_FIELD_DMAC0
= 5, // Destination MAC [15:0]
17 TEMPLATE_FIELD_DMAC1
= 6, // Destination MAC [31:16]
18 TEMPLATE_FIELD_DMAC2
= 7, // Destination MAC [47:32]
19 TEMPLATE_FIELD_SMAC0
= 8, // Source MAC [15:0]
20 TEMPLATE_FIELD_SMAC1
= 9, // Source MAC [31:16]
21 TEMPLATE_FIELD_SMAC2
= 10, // Source MAC [47:32]
22 TEMPLATE_FIELD_ETHERTYPE
= 11, // Ethernet frame type field
23 // Field-ID 12 is not used
24 TEMPLATE_FIELD_OTAG
= 13,
25 TEMPLATE_FIELD_ITAG
= 14,
26 TEMPLATE_FIELD_SIP0
= 15,
27 TEMPLATE_FIELD_SIP1
= 16,
28 TEMPLATE_FIELD_DIP0
= 17,
29 TEMPLATE_FIELD_DIP1
= 18,
30 TEMPLATE_FIELD_IP_TOS_PROTO
= 19,
31 TEMPLATE_FIELD_IP_FLAG
= 20,
32 TEMPLATE_FIELD_L4_SPORT
= 21,
33 TEMPLATE_FIELD_L4_DPORT
= 22,
34 TEMPLATE_FIELD_L34_HEADER
= 23,
35 TEMPLATE_FIELD_ICMP_IGMP
= 24,
36 TEMPLATE_FIELD_VID_RANG0
= 25,
37 TEMPLATE_FIELD_VID_RANG1
= 26,
38 TEMPLATE_FIELD_L4_PORT_RANG
= 27,
39 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 28,
40 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 29,
41 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 30,
42 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 31,
43 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 32,
44 TEMPLATE_FIELD_FIELD_SELECTOR_4
= 33,
45 TEMPLATE_FIELD_FIELD_SELECTOR_5
= 34,
46 TEMPLATE_FIELD_SIP2
= 35,
47 TEMPLATE_FIELD_SIP3
= 36,
48 TEMPLATE_FIELD_SIP4
= 37,
49 TEMPLATE_FIELD_SIP5
= 38,
50 TEMPLATE_FIELD_SIP6
= 39,
51 TEMPLATE_FIELD_SIP7
= 40,
52 TEMPLATE_FIELD_OLABEL
= 41,
53 TEMPLATE_FIELD_ILABEL
= 42,
54 TEMPLATE_FIELD_OILABEL
= 43,
55 TEMPLATE_FIELD_DPMMASK
= 44,
56 TEMPLATE_FIELD_DPM0
= 45,
57 TEMPLATE_FIELD_DPM1
= 46,
58 TEMPLATE_FIELD_DPM2
= 47,
59 TEMPLATE_FIELD_DPM3
= 48,
60 TEMPLATE_FIELD_L2DPM0
= 49,
61 TEMPLATE_FIELD_L2DPM1
= 50,
62 TEMPLATE_FIELD_L2DPM2
= 51,
63 TEMPLATE_FIELD_L2DPM3
= 52,
64 TEMPLATE_FIELD_IVLAN
= 53,
65 TEMPLATE_FIELD_OVLAN
= 54,
66 TEMPLATE_FIELD_FWD_VID
= 55,
67 TEMPLATE_FIELD_DIP2
= 56,
68 TEMPLATE_FIELD_DIP3
= 57,
69 TEMPLATE_FIELD_DIP4
= 58,
70 TEMPLATE_FIELD_DIP5
= 59,
71 TEMPLATE_FIELD_DIP6
= 60,
72 TEMPLATE_FIELD_DIP7
= 61,
75 // Number of fixed templates predefined in the SoC
76 #define N_FIXED_TEMPLATES 5
77 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
80 TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_ITAG
,
81 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
82 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
83 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
85 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
86 TEMPLATE_FIELD_DIP1
,TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_L4_SPORT
,
87 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_SPM0
,
88 TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
90 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
91 TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
92 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_SIP0
,
93 TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
95 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
96 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
97 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_L4_DPORT
,
98 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_IP_TOS_PROTO
100 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
101 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
102 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_SPM0
,
103 TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
107 void rtl839x_print_matrix(void)
112 ptr9
= RTL838X_SW_BASE
+ RTL839X_PORT_ISO_CTRL(0);
113 for (i
= 0; i
< 52; i
+= 4)
114 pr_debug("> %16llx %16llx %16llx %16llx\n",
115 ptr9
[i
+ 0], ptr9
[i
+ 1], ptr9
[i
+ 2], ptr9
[i
+ 3]);
116 pr_debug("CPU_PORT> %16llx\n", ptr9
[52]);
119 static inline int rtl839x_port_iso_ctrl(int p
)
121 return RTL839X_PORT_ISO_CTRL(p
);
124 static inline void rtl839x_exec_tbl0_cmd(u32 cmd
)
126 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_0
);
127 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0
) & BIT(16));
130 static inline void rtl839x_exec_tbl1_cmd(u32 cmd
)
132 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_1
);
133 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1
) & BIT(16));
136 inline void rtl839x_exec_tbl2_cmd(u32 cmd
)
138 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_2
);
139 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2
) & (1 << 9));
142 static inline int rtl839x_tbl_access_data_0(int i
)
144 return RTL839X_TBL_ACCESS_DATA_0(i
);
147 static void rtl839x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
150 // Read VLAN table (0) via register 0
151 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
153 rtl_table_read(r
, vlan
);
154 u
= sw_r32(rtl_table_data(r
, 0));
155 v
= sw_r32(rtl_table_data(r
, 1));
156 w
= sw_r32(rtl_table_data(r
, 2));
157 rtl_table_release(r
);
159 info
->tagged_ports
= u
;
160 info
->tagged_ports
= (info
->tagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
161 info
->profile_id
= w
>> 30 | ((v
& 1) << 2);
162 info
->hash_mc_fid
= !!(w
& BIT(2));
163 info
->hash_uc_fid
= !!(w
& BIT(3));
164 info
->fid
= (v
>> 3) & 0xff;
166 // Read UNTAG table (0) via table register 1
167 r
= rtl_table_get(RTL8390_TBL_1
, 0);
168 rtl_table_read(r
, vlan
);
169 u
= sw_r32(rtl_table_data(r
, 0));
170 v
= sw_r32(rtl_table_data(r
, 1));
171 rtl_table_release(r
);
173 info
->untagged_ports
= u
;
174 info
->untagged_ports
= (info
->untagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
177 static void rtl839x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
180 // Access VLAN table (0) via register 0
181 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
183 u
= info
->tagged_ports
>> 21;
184 v
= info
->tagged_ports
<< 11;
185 v
|= ((u32
)info
->fid
) << 3;
186 v
|= info
->hash_uc_fid
? BIT(2) : 0;
187 v
|= info
->hash_mc_fid
? BIT(1) : 0;
188 v
|= (info
->profile_id
& 0x4) ? 1 : 0;
189 w
= ((u32
)(info
->profile_id
& 3)) << 30;
191 sw_w32(u
, rtl_table_data(r
, 0));
192 sw_w32(v
, rtl_table_data(r
, 1));
193 sw_w32(w
, rtl_table_data(r
, 2));
195 rtl_table_write(r
, vlan
);
196 rtl_table_release(r
);
199 static void rtl839x_vlan_set_untagged(u32 vlan
, u64 portmask
)
203 // Access UNTAG table (0) via table register 1
204 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 0);
209 sw_w32(u
, rtl_table_data(r
, 0));
210 sw_w32(v
, rtl_table_data(r
, 1));
211 rtl_table_write(r
, vlan
);
213 rtl_table_release(r
);
216 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
218 static void rtl839x_vlan_fwd_on_inner(int port
, bool is_set
)
221 rtl839x_mask_port_reg_be(BIT_ULL(port
), 0ULL, RTL839X_VLAN_PORT_FWD
);
223 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port
), RTL839X_VLAN_PORT_FWD
);
227 * Hash seed is vid (actually rvid) concatenated with the MAC address
229 static u64
rtl839x_l2_hash_seed(u64 mac
, u32 vid
)
240 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
241 * and returns a key into the L2 hash table
243 static u32
rtl839x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
247 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
248 h1
= (u32
) (((seed
>> 60) & 0x3f) ^ ((seed
>> 54) & 0x3f)
249 ^ ((seed
>> 36) & 0x3f) ^ ((seed
>> 30) & 0x3f)
250 ^ ((seed
>> 12) & 0x3f) ^ ((seed
>> 6) & 0x3f));
251 h2
= (u32
) (((seed
>> 48) & 0x3f) ^ ((seed
>> 42) & 0x3f)
252 ^ ((seed
>> 24) & 0x3f) ^ ((seed
>> 18) & 0x3f)
257 ^ ((((seed
>> 48) & 0x3f) << 6) | ((seed
>> 54) & 0x3f))
258 ^ ((seed
>> 36) & 0xfff) ^ ((seed
>> 24) & 0xfff)
259 ^ ((seed
>> 12) & 0xfff) ^ (seed
& 0xfff);
265 static inline int rtl839x_mac_force_mode_ctrl(int p
)
267 return RTL839X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
270 static inline int rtl839x_mac_port_ctrl(int p
)
272 return RTL839X_MAC_PORT_CTRL(p
);
275 static inline int rtl839x_l2_port_new_salrn(int p
)
277 return RTL839X_L2_PORT_NEW_SALRN(p
);
280 static inline int rtl839x_l2_port_new_sa_fwd(int p
)
282 return RTL839X_L2_PORT_NEW_SA_FWD(p
);
285 static inline int rtl839x_mac_link_spd_sts(int p
)
287 return RTL839X_MAC_LINK_SPD_STS(p
);
290 static inline int rtl839x_trk_mbr_ctr(int group
)
292 return RTL839X_TRK_MBR_CTR
+ (group
<< 3);
295 static void rtl839x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
297 /* Table contains different entry types, we need to identify the right one:
298 * Check for MC entries, first
300 e
->is_ip_mc
= !!(r
[2] & BIT(31));
301 e
->is_ipv6_mc
= !!(r
[2] & BIT(30));
302 e
->type
= L2_INVALID
;
303 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
304 e
->mac
[0] = (r
[0] >> 12);
305 e
->mac
[1] = (r
[0] >> 4);
306 e
->mac
[2] = ((r
[1] >> 28) | (r
[0] << 4));
307 e
->mac
[3] = (r
[1] >> 20);
308 e
->mac
[4] = (r
[1] >> 12);
309 e
->mac
[5] = (r
[1] >> 4);
311 e
->vid
= (r
[2] >> 4) & 0xfff;
312 e
->rvid
= (r
[0] >> 20) & 0xfff;
314 /* Is it a unicast entry? check multicast bit */
315 if (!(e
->mac
[0] & 1)) {
316 e
->is_static
= !!((r
[2] >> 18) & 1);
317 e
->port
= (r
[2] >> 24) & 0x3f;
318 e
->block_da
= !!(r
[2] & (1 << 19));
319 e
->block_sa
= !!(r
[2] & (1 << 20));
320 e
->suspended
= !!(r
[2] & (1 << 17));
321 e
->next_hop
= !!(r
[2] & (1 << 16));
323 pr_debug("Found next hop entry, need to read data\n");
324 e
->nh_vlan_target
= !!(r
[2] & BIT(15));
325 e
->nh_route_id
= (r
[2] >> 4) & 0x1ff;
328 e
->age
= (r
[2] >> 21) & 3;
330 if (!(r
[2] & 0xc0fd0000)) /* Check for valid entry */
333 e
->type
= L2_UNICAST
;
336 e
->type
= L2_MULTICAST
;
337 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
340 } else { // IPv4 and IPv6 multicast
341 e
->vid
= e
->rvid
= (r
[0] << 20) & 0xfff;
343 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
347 e
->type
= IP4_MULTICAST
;
351 e
->type
= IP6_MULTICAST
;
353 // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid);
357 * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry
359 static void rtl839x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
362 r
[0] = r
[1] = r
[2] = 0;
366 r
[2] = e
->is_ip_mc
? BIT(31) : 0;
367 r
[2] |= e
->is_ipv6_mc
? BIT(30) : 0;
369 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
370 r
[0] = ((u32
)e
->mac
[0]) << 12;
371 r
[0] |= ((u32
)e
->mac
[1]) << 4;
372 r
[0] |= ((u32
)e
->mac
[2]) >> 4;
373 r
[1] = ((u32
)e
->mac
[2]) << 28;
374 r
[1] |= ((u32
)e
->mac
[3]) << 20;
375 r
[1] |= ((u32
)e
->mac
[4]) << 12;
376 r
[1] |= ((u32
)e
->mac
[5]) << 4;
378 if (!(e
->mac
[0] & 1)) { // Not multicast
379 r
[2] |= e
->is_static
? BIT(18) : 0;
380 r
[0] |= ((u32
)e
->rvid
) << 20;
381 r
[2] |= e
->port
<< 24;
382 r
[2] |= e
->block_da
? BIT(19) : 0;
383 r
[2] |= e
->block_sa
? BIT(20) : 0;
384 r
[2] |= e
->suspended
? BIT(17) : 0;
385 r
[2] |= ((u32
)e
->age
) << 21;
388 r
[2] |= e
->nh_vlan_target
? BIT(15) : 0;
389 r
[2] |= (e
->nh_route_id
& 0x7ff) << 4;
393 pr_debug("Write L2 NH: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
394 } else { // L2 Multicast
395 r
[0] |= ((u32
)e
->rvid
) << 20;
396 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
398 } else { // IPv4 or IPv6 MC entry
399 r
[0] = ((u32
)e
->rvid
) << 20;
401 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
406 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
407 * hash is the id of the bucket and pos is the position of the entry in that bucket
408 * The data read from the SoC is filled into rtl838x_l2_entry
410 static u64
rtl839x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
413 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
414 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
417 rtl_table_read(q
, idx
);
418 for (i
= 0; i
< 3; i
++)
419 r
[i
] = sw_r32(rtl_table_data(q
, i
));
421 rtl_table_release(q
);
423 rtl839x_fill_l2_entry(r
, e
);
427 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
430 static void rtl839x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
433 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
436 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
438 rtl839x_fill_l2_row(r
, e
);
440 for (i
= 0; i
< 3; i
++)
441 sw_w32(r
[i
], rtl_table_data(q
, i
));
443 rtl_table_write(q
, idx
);
444 rtl_table_release(q
);
447 static u64
rtl839x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
450 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); // Access L2 Table 1
453 rtl_table_read(q
, idx
);
454 for (i
= 0; i
< 3; i
++)
455 r
[i
] = sw_r32(rtl_table_data(q
, i
));
457 rtl_table_release(q
);
459 rtl839x_fill_l2_entry(r
, e
);
463 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
465 // Return MAC with concatenated VID ac concatenated ID
466 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
469 static void rtl839x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
472 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); // Access L2 Table 1
475 rtl839x_fill_l2_row(r
, e
);
477 for (i
= 0; i
< 3; i
++)
478 sw_w32(r
[i
], rtl_table_data(q
, i
));
480 rtl_table_write(q
, idx
);
481 rtl_table_release(q
);
484 static u64
rtl839x_read_mcast_pmask(int idx
)
487 // Read MC_PMSK (2) via register RTL8390_TBL_L2
488 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
490 rtl_table_read(q
, idx
);
491 portmask
= sw_r32(rtl_table_data(q
, 0));
493 portmask
|= sw_r32(rtl_table_data(q
, 1));
494 portmask
>>= 11; // LSB is bit 11 in data registers
495 rtl_table_release(q
);
500 static void rtl839x_write_mcast_pmask(int idx
, u64 portmask
)
502 // Access MC_PMSK (2) via register RTL8380_TBL_L2
503 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
505 portmask
<<= 11; // LSB is bit 11 in data registers
506 sw_w32((u32
)(portmask
>> 32), rtl_table_data(q
, 0));
507 sw_w32((u32
)((portmask
& 0xfffff800)), rtl_table_data(q
, 1));
508 rtl_table_write(q
, idx
);
509 rtl_table_release(q
);
512 static void rtl839x_vlan_profile_setup(int profile
)
515 u32 pmask_id
= UNKNOWN_MC_PMASK
;
517 p
[0] = pmask_id
; // Use portmaks 0xfff for unknown IPv6 MC flooding
518 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
519 p
[1] = 1 | pmask_id
<< 1 | pmask_id
<< 13;
521 sw_w32(p
[0], RTL839X_VLAN_PROFILE(profile
));
522 sw_w32(p
[1], RTL839X_VLAN_PROFILE(profile
) + 4);
524 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x001fffffffffffff);
527 u64
rtl839x_traffic_get(int source
)
529 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source
));
532 void rtl839x_traffic_set(int source
, u64 dest_matrix
)
534 rtl839x_set_port_reg_be(dest_matrix
, rtl839x_port_iso_ctrl(source
));
537 void rtl839x_traffic_enable(int source
, int dest
)
539 rtl839x_mask_port_reg_be(0, BIT_ULL(dest
), rtl839x_port_iso_ctrl(source
));
542 void rtl839x_traffic_disable(int source
, int dest
)
544 rtl839x_mask_port_reg_be(BIT_ULL(dest
), 0, rtl839x_port_iso_ctrl(source
));
547 static void rtl839x_l2_learning_setup(void)
549 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
550 * address flooding to the reserved entry in the portmask table used
551 * also for multicast flooding */
552 sw_w32(UNKNOWN_MC_PMASK
<< 12 | UNKNOWN_MC_PMASK
, RTL839X_L2_FLD_PMSK
);
554 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
555 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT
);
557 // Do not trap ARP packets to CPU_PORT
558 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL
);
561 static void rtl839x_enable_learning(int port
, bool enable
)
563 // Limit learning to maximum: 32k entries
565 sw_w32_mask(0x7fff << 2, enable
? (0x7fff << 2) : 0,
566 RTL839X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
569 static void rtl839x_enable_flood(int port
, bool enable
)
577 sw_w32_mask(0x3, enable
? 0 : 1,
578 RTL839X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
581 static void rtl839x_enable_mcast_flood(int port
, bool enable
)
586 static void rtl839x_enable_bcast_flood(int port
, bool enable
)
590 irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
)
592 struct dsa_switch
*ds
= dev_id
;
593 u32 status
= sw_r32(RTL839X_ISR_GLB_SRC
);
594 u64 ports
= rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG
);
599 rtl839x_set_port_reg_le(ports
, RTL839X_ISR_PORT_LINK_STS_CHG
);
600 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status
, ports
);
602 for (i
= 0; i
< RTL839X_CPU_PORT
; i
++) {
603 if (ports
& BIT_ULL(i
)) {
604 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
605 if (link
& BIT_ULL(i
))
606 dsa_port_phylink_mac_change(ds
, i
, true);
608 dsa_port_phylink_mac_change(ds
, i
, false);
615 int rtl8390_sds_power(int mac
, int val
)
617 u32 offset
= (mac
== 48) ? 0x0 : 0x100;
618 u32 mode
= val
? 0 : 1;
620 pr_debug("In %s: mac %d, set %d\n", __func__
, mac
, val
);
622 if ((mac
!= 48) && (mac
!= 49)) {
623 pr_err("%s: not an SFP port: %d\n", __func__
, mac
);
627 // Set bit 1003. 1000 starts at 7c
628 sw_w32_mask(BIT(11), mode
<< 11, RTL839X_SDS12_13_PWR0
+ offset
);
633 static int rtl839x_smi_wait_op(int timeout
)
638 ret
= readx_poll_timeout(sw_r32
, RTL839X_PHYREG_ACCESS_CTRL
,
639 val
, !(val
& 0x1), 20, timeout
);
641 pr_err("%s: timeout\n", __func__
);
646 int rtl839x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
651 if (port
> 63 || page
> 4095 || reg
> 31)
654 // Take bug on RTL839x Rev <= C into account
655 if (port
>= RTL839X_CPU_PORT
)
658 mutex_lock(&smi_lock
);
660 sw_w32_mask(0xffff0000, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
661 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
662 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
664 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
667 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
669 err
= rtl839x_smi_wait_op(100000);
673 *val
= sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff;
676 mutex_unlock(&smi_lock
);
680 int rtl839x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
686 if (port
> 63 || page
> 4095 || reg
> 31)
689 // Take bug on RTL839x Rev <= C into account
690 if (port
>= RTL839X_CPU_PORT
)
693 mutex_lock(&smi_lock
);
696 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
698 sw_w32_mask(0xffff0000, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
700 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
701 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
703 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
705 v
|= BIT(3) | 1; /* Write operation and execute */
706 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
708 err
= rtl839x_smi_wait_op(100000);
712 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x2)
716 mutex_unlock(&smi_lock
);
721 * Read an mmd register of the PHY
723 int rtl839x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
728 // Take bug on RTL839x Rev <= C into account
729 if (port
>= RTL839X_CPU_PORT
)
732 mutex_lock(&smi_lock
);
735 sw_w32_mask(0xffff << 16, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
737 // Set MMD device number and register to write to
738 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
740 v
= BIT(2) | BIT(0); // MMD-access | EXEC
741 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
743 err
= rtl839x_smi_wait_op(100000);
747 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
748 *val
= (sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff);
749 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, *val
, err
);
752 mutex_unlock(&smi_lock
);
757 * Write to an mmd register of the PHY
759 int rtl839x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
)
764 // Take bug on RTL839x Rev <= C into account
765 if (port
>= RTL839X_CPU_PORT
)
768 mutex_lock(&smi_lock
);
771 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
774 sw_w32_mask(0xffff << 16, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
776 // Set MMD device number and register to write to
777 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
779 v
= BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
780 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
782 err
= rtl839x_smi_wait_op(100000);
786 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, val
, err
);
789 mutex_unlock(&smi_lock
);
793 void rtl8390_get_version(struct rtl838x_switch_priv
*priv
)
797 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO
);
798 info
= sw_r32(RTL839X_CHIP_INFO
);
800 model
= sw_r32(RTL839X_MODEL_NAME_INFO
);
801 priv
->version
= RTL8390_VERSION_A
+ ((model
& 0x3f) >> 1);
803 pr_info("RTL839X Chip-Info: %x, version %c\n", info
, priv
->version
);
806 void rtl839x_vlan_profile_dump(int profile
)
810 if (profile
< 0 || profile
> 7)
813 p
[0] = sw_r32(RTL839X_VLAN_PROFILE(profile
));
814 p
[1] = sw_r32(RTL839X_VLAN_PROFILE(profile
) + 4);
816 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
817 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
818 profile
, p
[1] & 1, (p
[1] >> 1) & 0xfff, (p
[1] >> 13) & 0xfff,
820 pr_info("VLAN profile %d: raw %08x, %08x\n", profile
, p
[0], p
[1]);
823 static void rtl839x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
826 u32 cmd
= 1 << 16 /* Execute cmd */
828 | 5 << 12 /* Table type 0b101 */
830 priv
->r
->exec_tbl0_cmd(cmd
);
832 for (i
= 0; i
< 4; i
++)
833 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
836 static void rtl839x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
839 u32 cmd
= 1 << 16 /* Execute cmd */
840 | 1 << 15 /* Write */
841 | 5 << 12 /* Table type 0b101 */
843 for (i
= 0; i
< 4; i
++)
844 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
845 priv
->r
->exec_tbl0_cmd(cmd
);
849 * Enables or disables the EEE/EEEP capability of a port
851 void rtl839x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
855 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
860 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
861 v
= enable
? 0xf : 0x0;
863 // Set EEE for 100, 500, 1000MBit and 10GBit
864 sw_w32_mask(0xf << 8, v
<< 8, rtl839x_mac_force_mode_ctrl(port
));
866 // Set TX/RX EEE state
867 v
= enable
? 0x3 : 0x0;
868 sw_w32(v
, RTL839X_EEE_CTRL(port
));
870 priv
->ports
[port
].eee_enabled
= enable
;
874 * Get EEE own capabilities and negotiation result
876 int rtl839x_eee_port_ability(struct rtl838x_switch_priv
*priv
, struct ethtool_eee
*e
, int port
)
883 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
884 if (!(link
& BIT_ULL(port
)))
887 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(8))
888 e
->advertised
|= ADVERTISED_100baseT_Full
;
890 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(10))
891 e
->advertised
|= ADVERTISED_1000baseT_Full
;
893 a
= rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
);
894 pr_info("Link partner: %016llx\n", a
);
895 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
) & BIT_ULL(port
)) {
896 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
897 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
904 static void rtl839x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
908 pr_info("Setting up EEE, state: %d\n", enable
);
910 // Set wake timer for TX and pause timer both to 0x21
911 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL
);
912 // Set pause wake timer for GIGA-EEE to 0x11
913 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL
);
914 // Set pause wake timer for 10GBit ports to 0x11
915 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL
);
917 // Setup EEE on all ports
918 for (i
= 0; i
< priv
->cpu_port
; i
++) {
919 if (priv
->ports
[i
].phy
)
920 rtl839x_port_eee_set(priv
, i
, enable
);
922 priv
->eee_enabled
= enable
;
925 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
927 int block
= index
/ PIE_BLOCK_SIZE
;
929 sw_w32_mask(0, BIT(block
), RTL839X_ACL_BLK_LOOKUP_CTRL
);
933 * Delete a range of Packet Inspection Engine rules
935 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
937 u32 v
= (index_from
<< 1)| (index_to
<< 13 ) | BIT(0);
939 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
940 mutex_lock(&priv
->reg_mutex
);
942 // Write from-to and execute bit into control register
943 sw_w32(v
, RTL839X_ACL_CLR_CTRL
);
945 // Wait until command has completed
947 } while (sw_r32(RTL839X_ACL_CLR_CTRL
) & BIT(0));
949 mutex_unlock(&priv
->reg_mutex
);
954 * Reads the intermediate representation of the templated match-fields of the
955 * PIE rule in the pie_rule structure and fills in the raw data fields in the
956 * raw register space r[].
957 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
958 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
960 * On the RTL8390 the template mask registers are not word-aligned!
962 static void rtl839x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
965 enum template_field_id field_type
;
968 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
972 switch (field_type
) {
973 case TEMPLATE_FIELD_SPM0
:
977 case TEMPLATE_FIELD_SPM1
:
978 data
= pr
->spm
>> 16;
979 data_m
= pr
->spm_m
>> 16;
981 case TEMPLATE_FIELD_SPM2
:
982 data
= pr
->spm
>> 32;
983 data_m
= pr
->spm_m
>> 32;
985 case TEMPLATE_FIELD_SPM3
:
986 data
= pr
->spm
>> 48;
987 data_m
= pr
->spm_m
>> 48;
989 case TEMPLATE_FIELD_OTAG
:
993 case TEMPLATE_FIELD_SMAC0
:
995 data
= (data
<< 8) | pr
->smac
[5];
996 data_m
= pr
->smac_m
[4];
997 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
999 case TEMPLATE_FIELD_SMAC1
:
1001 data
= (data
<< 8) | pr
->smac
[3];
1002 data_m
= pr
->smac_m
[2];
1003 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
1005 case TEMPLATE_FIELD_SMAC2
:
1007 data
= (data
<< 8) | pr
->smac
[1];
1008 data_m
= pr
->smac_m
[0];
1009 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
1011 case TEMPLATE_FIELD_DMAC0
:
1013 data
= (data
<< 8) | pr
->dmac
[5];
1014 data_m
= pr
->dmac_m
[4];
1015 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
1017 case TEMPLATE_FIELD_DMAC1
:
1019 data
= (data
<< 8) | pr
->dmac
[3];
1020 data_m
= pr
->dmac_m
[2];
1021 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
1023 case TEMPLATE_FIELD_DMAC2
:
1025 data
= (data
<< 8) | pr
->dmac
[1];
1026 data_m
= pr
->dmac_m
[0];
1027 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
1029 case TEMPLATE_FIELD_ETHERTYPE
:
1030 data
= pr
->ethertype
;
1031 data_m
= pr
->ethertype_m
;
1033 case TEMPLATE_FIELD_ITAG
:
1035 data_m
= pr
->itag_m
;
1037 case TEMPLATE_FIELD_SIP0
:
1039 data
= pr
->sip6
.s6_addr16
[7];
1040 data_m
= pr
->sip6_m
.s6_addr16
[7];
1046 case TEMPLATE_FIELD_SIP1
:
1048 data
= pr
->sip6
.s6_addr16
[6];
1049 data_m
= pr
->sip6_m
.s6_addr16
[6];
1051 data
= pr
->sip
>> 16;
1052 data_m
= pr
->sip_m
>> 16;
1056 case TEMPLATE_FIELD_SIP2
:
1057 case TEMPLATE_FIELD_SIP3
:
1058 case TEMPLATE_FIELD_SIP4
:
1059 case TEMPLATE_FIELD_SIP5
:
1060 case TEMPLATE_FIELD_SIP6
:
1061 case TEMPLATE_FIELD_SIP7
:
1062 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1063 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1066 case TEMPLATE_FIELD_DIP0
:
1068 data
= pr
->dip6
.s6_addr16
[7];
1069 data_m
= pr
->dip6_m
.s6_addr16
[7];
1076 case TEMPLATE_FIELD_DIP1
:
1078 data
= pr
->dip6
.s6_addr16
[6];
1079 data_m
= pr
->dip6_m
.s6_addr16
[6];
1081 data
= pr
->dip
>> 16;
1082 data_m
= pr
->dip_m
>> 16;
1086 case TEMPLATE_FIELD_DIP2
:
1087 case TEMPLATE_FIELD_DIP3
:
1088 case TEMPLATE_FIELD_DIP4
:
1089 case TEMPLATE_FIELD_DIP5
:
1090 case TEMPLATE_FIELD_DIP6
:
1091 case TEMPLATE_FIELD_DIP7
:
1092 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1093 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1096 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1097 data
= pr
->tos_proto
;
1098 data_m
= pr
->tos_proto_m
;
1100 case TEMPLATE_FIELD_L4_SPORT
:
1102 data_m
= pr
->sport_m
;
1104 case TEMPLATE_FIELD_L4_DPORT
:
1106 data_m
= pr
->dport_m
;
1108 case TEMPLATE_FIELD_ICMP_IGMP
:
1109 data
= pr
->icmp_igmp
;
1110 data_m
= pr
->icmp_igmp_m
;
1113 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1116 // On the RTL8390, the mask fields are not word aligned!
1118 r
[5 - i
/ 2] = data
;
1119 r
[12 - i
/ 2] |= ((u32
)data_m
<< 8);
1121 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
1122 r
[12 - i
/ 2] |= ((u32
)data_m
) << 24;
1123 r
[11 - i
/ 2] |= ((u32
)data_m
) >> 8;
1129 * Creates the intermediate representation of the templated match-fields of the
1130 * PIE rule in the pie_rule structure by reading the raw data fields in the
1131 * raw register space r[].
1132 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1133 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1134 * On the RTL8390 the template mask registers are not word-aligned!
1136 void rtl839x_read_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
1139 enum template_field_id field_type
;
1142 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1145 data
= r
[5 - i
/ 2];
1146 data_m
= r
[12 - i
/ 2];
1148 data
= r
[5 - i
/ 2] >> 16;
1149 data_m
= r
[12 - i
/ 2] >> 16;
1152 switch (field_type
) {
1153 case TEMPLATE_FIELD_SPM0
:
1154 pr
->spm
= (pr
->spn
<< 16) | data
;
1155 pr
->spm_m
= (pr
->spn
<< 16) | data_m
;
1157 case TEMPLATE_FIELD_SPM1
:
1161 case TEMPLATE_FIELD_OTAG
:
1163 pr
->otag_m
= data_m
;
1165 case TEMPLATE_FIELD_SMAC0
:
1166 pr
->smac
[4] = data
>> 8;
1168 pr
->smac_m
[4] = data
>> 8;
1169 pr
->smac_m
[5] = data
;
1171 case TEMPLATE_FIELD_SMAC1
:
1172 pr
->smac
[2] = data
>> 8;
1174 pr
->smac_m
[2] = data
>> 8;
1175 pr
->smac_m
[3] = data
;
1177 case TEMPLATE_FIELD_SMAC2
:
1178 pr
->smac
[0] = data
>> 8;
1180 pr
->smac_m
[0] = data
>> 8;
1181 pr
->smac_m
[1] = data
;
1183 case TEMPLATE_FIELD_DMAC0
:
1184 pr
->dmac
[4] = data
>> 8;
1186 pr
->dmac_m
[4] = data
>> 8;
1187 pr
->dmac_m
[5] = data
;
1189 case TEMPLATE_FIELD_DMAC1
:
1190 pr
->dmac
[2] = data
>> 8;
1192 pr
->dmac_m
[2] = data
>> 8;
1193 pr
->dmac_m
[3] = data
;
1195 case TEMPLATE_FIELD_DMAC2
:
1196 pr
->dmac
[0] = data
>> 8;
1198 pr
->dmac_m
[0] = data
>> 8;
1199 pr
->dmac_m
[1] = data
;
1201 case TEMPLATE_FIELD_ETHERTYPE
:
1202 pr
->ethertype
= data
;
1203 pr
->ethertype_m
= data_m
;
1205 case TEMPLATE_FIELD_ITAG
:
1207 pr
->itag_m
= data_m
;
1209 case TEMPLATE_FIELD_SIP0
:
1213 case TEMPLATE_FIELD_SIP1
:
1214 pr
->sip
= (pr
->sip
<< 16) | data
;
1215 pr
->sip_m
= (pr
->sip
<< 16) | data_m
;
1217 case TEMPLATE_FIELD_SIP2
:
1219 // Make use of limitiations on the position of the match values
1220 ipv6_addr_set(&pr
->sip6
, pr
->sip
, r
[5 - i
/ 2],
1221 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1222 ipv6_addr_set(&pr
->sip6_m
, pr
->sip_m
, r
[5 - i
/ 2],
1223 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1224 case TEMPLATE_FIELD_SIP3
:
1225 case TEMPLATE_FIELD_SIP4
:
1226 case TEMPLATE_FIELD_SIP5
:
1227 case TEMPLATE_FIELD_SIP6
:
1228 case TEMPLATE_FIELD_SIP7
:
1231 case TEMPLATE_FIELD_DIP0
:
1236 case TEMPLATE_FIELD_DIP1
:
1237 pr
->dip
= (pr
->dip
<< 16) | data
;
1238 pr
->dip_m
= (pr
->dip
<< 16) | data_m
;
1241 case TEMPLATE_FIELD_DIP2
:
1243 ipv6_addr_set(&pr
->dip6
, pr
->dip
, r
[5 - i
/ 2],
1244 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1245 ipv6_addr_set(&pr
->dip6_m
, pr
->dip_m
, r
[5 - i
/ 2],
1246 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1247 case TEMPLATE_FIELD_DIP3
:
1248 case TEMPLATE_FIELD_DIP4
:
1249 case TEMPLATE_FIELD_DIP5
:
1250 case TEMPLATE_FIELD_DIP6
:
1251 case TEMPLATE_FIELD_DIP7
:
1253 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1254 pr
->tos_proto
= data
;
1255 pr
->tos_proto_m
= data_m
;
1257 case TEMPLATE_FIELD_L4_SPORT
:
1259 pr
->sport_m
= data_m
;
1261 case TEMPLATE_FIELD_L4_DPORT
:
1263 pr
->dport_m
= data_m
;
1265 case TEMPLATE_FIELD_ICMP_IGMP
:
1266 pr
->icmp_igmp
= data
;
1267 pr
->icmp_igmp_m
= data_m
;
1270 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1275 static void rtl839x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1277 pr
->spmmask_fix
= (r
[6] >> 30) & 0x3;
1278 pr
->spn
= (r
[6] >> 24) & 0x3f;
1279 pr
->mgnt_vlan
= (r
[6] >> 23) & 1;
1280 pr
->dmac_hit_sw
= (r
[6] >> 22) & 1;
1281 pr
->not_first_frag
= (r
[6] >> 21) & 1;
1282 pr
->frame_type_l4
= (r
[6] >> 18) & 7;
1283 pr
->frame_type
= (r
[6] >> 16) & 3;
1284 pr
->otag_fmt
= (r
[6] >> 15) & 1;
1285 pr
->itag_fmt
= (r
[6] >> 14) & 1;
1286 pr
->otag_exist
= (r
[6] >> 13) & 1;
1287 pr
->itag_exist
= (r
[6] >> 12) & 1;
1288 pr
->frame_type_l2
= (r
[6] >> 10) & 3;
1289 pr
->tid
= (r
[6] >> 8) & 3;
1291 pr
->spmmask_fix_m
= (r
[12] >> 6) & 0x3;
1292 pr
->spn_m
= r
[12] & 0x3f;
1293 pr
->mgnt_vlan_m
= (r
[13] >> 31) & 1;
1294 pr
->dmac_hit_sw_m
= (r
[13] >> 30) & 1;
1295 pr
->not_first_frag_m
= (r
[13] >> 29) & 1;
1296 pr
->frame_type_l4_m
= (r
[13] >> 26) & 7;
1297 pr
->frame_type_m
= (r
[13] >> 24) & 3;
1298 pr
->otag_fmt_m
= (r
[13] >> 23) & 1;
1299 pr
->itag_fmt_m
= (r
[13] >> 22) & 1;
1300 pr
->otag_exist_m
= (r
[13] >> 21) & 1;
1301 pr
->itag_exist_m
= (r
[13] >> 20) & 1;
1302 pr
->frame_type_l2_m
= (r
[13] >> 18) & 3;
1303 pr
->tid_m
= (r
[13] >> 16) & 3;
1305 pr
->valid
= r
[13] & BIT(15);
1306 pr
->cond_not
= r
[13] & BIT(14);
1307 pr
->cond_and1
= r
[13] & BIT(13);
1308 pr
->cond_and2
= r
[13] & BIT(12);
1311 static void rtl839x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1313 r
[6] = ((u32
) (pr
->spmmask_fix
& 0x3)) << 30;
1314 r
[6] |= ((u32
) (pr
->spn
& 0x3f)) << 24;
1315 r
[6] |= pr
->mgnt_vlan
? BIT(23) : 0;
1316 r
[6] |= pr
->dmac_hit_sw
? BIT(22) : 0;
1317 r
[6] |= pr
->not_first_frag
? BIT(21) : 0;
1318 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 18;
1319 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 16;
1320 r
[6] |= pr
->otag_fmt
? BIT(15) : 0;
1321 r
[6] |= pr
->itag_fmt
? BIT(14) : 0;
1322 r
[6] |= pr
->otag_exist
? BIT(13) : 0;
1323 r
[6] |= pr
->itag_exist
? BIT(12) : 0;
1324 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 10;
1325 r
[6] |= ((u32
) (pr
->tid
& 0x3)) << 8;
1327 r
[12] |= ((u32
) (pr
->spmmask_fix_m
& 0x3)) << 6;
1328 r
[12] |= (u32
) (pr
->spn_m
& 0x3f);
1329 r
[13] |= pr
->mgnt_vlan_m
? BIT(31) : 0;
1330 r
[13] |= pr
->dmac_hit_sw_m
? BIT(30) : 0;
1331 r
[13] |= pr
->not_first_frag_m
? BIT(29) : 0;
1332 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 26;
1333 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 24;
1334 r
[13] |= pr
->otag_fmt_m
? BIT(23) : 0;
1335 r
[13] |= pr
->itag_fmt_m
? BIT(22) : 0;
1336 r
[13] |= pr
->otag_exist_m
? BIT(21) : 0;
1337 r
[13] |= pr
->itag_exist_m
? BIT(20) : 0;
1338 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 18;
1339 r
[13] |= ((u32
) (pr
->tid_m
& 0x3)) << 16;
1341 r
[13] |= pr
->valid
? BIT(15) : 0;
1342 r
[13] |= pr
->cond_not
? BIT(14) : 0;
1343 r
[13] |= pr
->cond_and1
? BIT(13) : 0;
1344 r
[13] |= pr
->cond_and2
? BIT(12) : 0;
1347 static void rtl839x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1350 r
[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP
1353 r
[13] |= pr
->fwd_sel
? BIT(3) : 0;
1354 r
[13] |= pr
->fwd_act
;
1356 r
[13] |= pr
->bypass_sel
? BIT(11) : 0;
1357 r
[13] |= pr
->mpls_sel
? BIT(10) : 0;
1358 r
[13] |= pr
->nopri_sel
? BIT(9) : 0;
1359 r
[13] |= pr
->ovid_sel
? BIT(8) : 0;
1360 r
[13] |= pr
->ivid_sel
? BIT(7) : 0;
1361 r
[13] |= pr
->meter_sel
? BIT(6) : 0;
1362 r
[13] |= pr
->mir_sel
? BIT(5) : 0;
1363 r
[13] |= pr
->log_sel
? BIT(4) : 0;
1365 r
[14] |= ((u32
)(pr
->fwd_data
& 0x3fff)) << 18;
1366 r
[14] |= pr
->log_octets
? BIT(17) : 0;
1367 r
[14] |= ((u32
)(pr
->log_data
& 0x7ff)) << 4;
1368 r
[14] |= (pr
->mir_data
& 0x3) << 3;
1369 r
[14] |= ((u32
)(pr
->meter_data
>> 7)) & 0x7;
1370 r
[15] |= (u32
)(pr
->meter_data
) << 26;
1371 r
[15] |= ((u32
)(pr
->ivid_act
) << 23) & 0x3;
1372 r
[15] |= ((u32
)(pr
->ivid_data
) << 9) & 0xfff;
1373 r
[15] |= ((u32
)(pr
->ovid_act
) << 6) & 0x3;
1374 r
[15] |= ((u32
)(pr
->ovid_data
) >> 4) & 0xff;
1375 r
[16] |= ((u32
)(pr
->ovid_data
) & 0xf) << 28;
1376 r
[16] |= ((u32
)(pr
->nopri_data
) & 0x7) << 20;
1377 r
[16] |= ((u32
)(pr
->mpls_act
) & 0x7) << 20;
1378 r
[16] |= ((u32
)(pr
->mpls_lib_idx
) & 0x7) << 20;
1379 r
[16] |= pr
->bypass_all
? BIT(9) : 0;
1380 r
[16] |= pr
->bypass_igr_stp
? BIT(8) : 0;
1381 r
[16] |= pr
->bypass_ibc_sc
? BIT(7) : 0;
1384 static void rtl839x_read_pie_action(u32 r
[], struct pie_rule
*pr
)
1386 if (r
[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop?
1387 if ((r
[14] & 0x7) == 1) {
1391 pr
->fwd_act
= r
[14] & 0x7;
1395 pr
->bypass_sel
= r
[13] & BIT(11);
1396 pr
->mpls_sel
= r
[13] & BIT(10);
1397 pr
->nopri_sel
= r
[13] & BIT(9);
1398 pr
->ovid_sel
= r
[13] & BIT(8);
1399 pr
->ivid_sel
= r
[13] & BIT(7);
1400 pr
->meter_sel
= r
[13] & BIT(6);
1401 pr
->mir_sel
= r
[13] & BIT(5);
1402 pr
->log_sel
= r
[13] & BIT(4);
1404 // TODO: Read in data fields
1406 pr
->bypass_all
= r
[16] & BIT(9);
1407 pr
->bypass_igr_stp
= r
[16] & BIT(8);
1408 pr
->bypass_ibc_sc
= r
[16] & BIT(7);
1411 void rtl839x_pie_rule_dump_raw(u32 r
[])
1413 pr_info("Raw IACL table entry:\n");
1414 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1415 pr_info("Fixed : %06x\n", r
[6] >> 8);
1416 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1417 (r
[6] << 24) | (r
[7] >> 8), (r
[7] << 24) | (r
[8] >> 8), (r
[8] << 24) | (r
[9] >> 8),
1418 (r
[9] << 24) | (r
[10] >> 8), (r
[10] << 24) | (r
[11] >> 8),
1419 (r
[11] << 24) | (r
[12] >> 8));
1420 pr_info("R[13]: %08x\n", r
[13]);
1421 pr_info("Fixed M: %06x\n", ((r
[12] << 16) | (r
[13] >> 16)) & 0xffffff);
1422 pr_info("Valid / not / and1 / and2 : %1x\n", (r
[13] >> 12) & 0xf);
1423 pr_info("r 13-16: %08x %08x %08x %08x\n", r
[13], r
[14], r
[15], r
[16]);
1426 void rtl839x_pie_rule_dump(struct pie_rule
*pr
)
1428 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1429 pr
->drop
, pr
->fwd_sel
, pr
->ovid_sel
, pr
->ivid_sel
, pr
->flt_sel
, pr
->log_sel
, pr
->rmk_sel
, pr
->log_sel
, pr
->tagst_sel
, pr
->mir_sel
, pr
->nopri_sel
,
1430 pr
->cpupri_sel
, pr
->otpid_sel
, pr
->itpid_sel
, pr
->shaper_sel
);
1432 pr_info("FWD: %08x\n", pr
->fwd_data
);
1433 pr_info("TID: %x, %x\n", pr
->tid
, pr
->tid_m
);
1436 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1438 // Read IACL table (2) via register 0
1439 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 2);
1442 int block
= idx
/ PIE_BLOCK_SIZE
;
1443 u32 t_select
= sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
));
1445 memset(pr
, 0, sizeof(*pr
));
1446 rtl_table_read(q
, idx
);
1447 for (i
= 0; i
< 17; i
++)
1448 r
[i
] = sw_r32(rtl_table_data(q
, i
));
1450 rtl_table_release(q
);
1452 rtl839x_read_pie_fixed_fields(r
, pr
);
1456 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__
, t_select
, pr
->tid
);
1457 rtl839x_pie_rule_dump_raw(r
);
1459 rtl839x_read_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1461 rtl839x_read_pie_action(r
, pr
);
1466 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1468 // Access IACL table (2) via register 0
1469 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_0
, 2);
1472 int block
= idx
/ PIE_BLOCK_SIZE
;
1473 u32 t_select
= sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
));
1475 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1477 for (i
= 0; i
< 17; i
++)
1481 rtl_table_write(q
, idx
);
1482 rtl_table_release(q
);
1485 rtl839x_write_pie_fixed_fields(r
, pr
);
1487 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 3)) & 0x7);
1488 rtl839x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1490 rtl839x_write_pie_action(r
, pr
);
1492 // rtl839x_pie_rule_dump_raw(r);
1494 for (i
= 0; i
< 17; i
++)
1495 sw_w32(r
[i
], rtl_table_data(q
, i
));
1497 rtl_table_write(q
, idx
);
1498 rtl_table_release(q
);
1503 static bool rtl839x_pie_templ_has(int t
, enum template_field_id field_type
)
1506 enum template_field_id ft
;
1508 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1509 ft
= fixed_templates
[t
][i
];
1510 if (field_type
== ft
)
1517 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1518 struct pie_rule
*pr
, int t
, int block
)
1522 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1525 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1529 if ((pr
->sip6_m
.s6_addr32
[0] || pr
->sip6_m
.s6_addr32
[1]
1530 || pr
->sip6_m
.s6_addr32
[2] || pr
->sip6_m
.s6_addr32
[3])
1531 && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1533 if ((pr
->dip6_m
.s6_addr32
[0] || pr
->dip6_m
.s6_addr32
[1]
1534 || pr
->dip6_m
.s6_addr32
[2] || pr
->dip6_m
.s6_addr32
[3])
1535 && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1539 if (ether_addr_to_u64(pr
->smac
) && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1542 if (ether_addr_to_u64(pr
->dmac
) && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1547 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1549 if (i
>= PIE_BLOCK_SIZE
)
1552 return i
+ PIE_BLOCK_SIZE
* block
;
1555 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1557 int idx
, block
, j
, t
;
1559 int max_block
= priv
->n_pie_blocks
/ 2;
1561 if (pr
->is_egress
) {
1562 min_block
= max_block
;
1563 max_block
= priv
->n_pie_blocks
;
1566 mutex_lock(&priv
->pie_mutex
);
1568 for (block
= min_block
; block
< max_block
; block
++) {
1569 for (j
= 0; j
< 2; j
++) {
1570 t
= (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
)) >> (j
* 3)) & 0x7;
1571 idx
= rtl839x_pie_verify_template(priv
, pr
, t
, block
);
1579 if (block
>= priv
->n_pie_blocks
) {
1580 mutex_unlock(&priv
->pie_mutex
);
1584 set_bit(idx
, priv
->pie_use_bm
);
1587 pr
->tid
= j
; // Mapped to template number
1591 rtl839x_pie_lookup_enable(priv
, idx
);
1592 rtl839x_pie_rule_write(priv
, idx
, pr
);
1594 mutex_unlock(&priv
->pie_mutex
);
1598 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1602 rtl839x_pie_rule_del(priv
, idx
, idx
);
1603 clear_bit(idx
, priv
->pie_use_bm
);
1606 static void rtl839x_pie_init(struct rtl838x_switch_priv
*priv
)
1609 u32 template_selectors
;
1611 mutex_init(&priv
->pie_mutex
);
1613 // Power on all PIE blocks
1614 for (i
= 0; i
< priv
->n_pie_blocks
; i
++)
1615 sw_w32_mask(0, BIT(i
), RTL839X_PS_ACL_PWR_CTRL
);
1617 // Set ingress and egress ACL blocks to 50/50: first Egress block is 9
1618 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL
); // Writes 9 to cutline field
1620 // Include IPG in metering
1621 sw_w32(1, RTL839X_METER_GLB_CTRL
);
1623 // Delete all present rules
1624 rtl839x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* PIE_BLOCK_SIZE
- 1);
1626 // Enable predefined templates 0, 1 for blocks 0-2
1627 template_selectors
= 0 | (1 << 3);
1628 for (i
= 0; i
< 3; i
++)
1629 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1631 // Enable predefined templates 2, 3 for blocks 3-5
1632 template_selectors
= 2 | (3 << 3);
1633 for (i
= 3; i
< 6; i
++)
1634 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1636 // Enable predefined templates 1, 4 for blocks 6-8
1637 template_selectors
= 2 | (3 << 3);
1638 for (i
= 6; i
< 9; i
++)
1639 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1641 // Enable predefined templates 0, 1 for blocks 9-11
1642 template_selectors
= 0 | (1 << 3);
1643 for (i
= 9; i
< 12; i
++)
1644 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1646 // Enable predefined templates 2, 3 for blocks 12-14
1647 template_selectors
= 2 | (3 << 3);
1648 for (i
= 12; i
< 15; i
++)
1649 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1651 // Enable predefined templates 1, 4 for blocks 15-17
1652 template_selectors
= 2 | (3 << 3);
1653 for (i
= 15; i
< 18; i
++)
1654 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1657 static u32
rtl839x_packet_cntr_read(int counter
)
1661 // Read LOG table (4) via register RTL8390_TBL_0
1662 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 4);
1664 pr_debug("In %s, id %d\n", __func__
, counter
);
1665 rtl_table_read(r
, counter
/ 2);
1667 // The table has a size of 2 registers
1669 v
= sw_r32(rtl_table_data(r
, 0));
1671 v
= sw_r32(rtl_table_data(r
, 1));
1673 rtl_table_release(r
);
1678 static void rtl839x_packet_cntr_clear(int counter
)
1680 // Access LOG table (4) via register RTL8390_TBL_0
1681 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 4);
1683 pr_debug("In %s, id %d\n", __func__
, counter
);
1684 // The table has a size of 2 registers
1686 sw_w32(0, rtl_table_data(r
, 0));
1688 sw_w32(0, rtl_table_data(r
, 1));
1690 rtl_table_write(r
, counter
/ 2);
1692 rtl_table_release(r
);
1695 static void rtl839x_route_read(int idx
, struct rtl83xx_route
*rt
)
1698 // Read ROUTING table (2) via register RTL8390_TBL_1
1699 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 2);
1701 pr_debug("In %s\n", __func__
);
1702 rtl_table_read(r
, idx
);
1704 // The table has a size of 2 registers
1705 v
= sw_r32(rtl_table_data(r
, 0));
1707 v
|= sw_r32(rtl_table_data(r
, 1));
1708 rt
->switch_mac_id
= (v
>> 12) & 0xf;
1709 rt
->nh
.gw
= v
>> 16;
1711 rtl_table_release(r
);
1714 static void rtl839x_route_write(int idx
, struct rtl83xx_route
*rt
)
1718 // Read ROUTING table (2) via register RTL8390_TBL_1
1719 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 2);
1721 pr_debug("In %s\n", __func__
);
1722 sw_w32(rt
->nh
.gw
>> 16, rtl_table_data(r
, 0));
1723 v
= rt
->nh
.gw
<< 16;
1724 v
|= rt
->switch_mac_id
<< 12;
1725 sw_w32(v
, rtl_table_data(r
, 1));
1726 rtl_table_write(r
, idx
);
1728 rtl_table_release(r
);
1732 * Configure the switch's own MAC addresses used when routing packets
1734 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv
*priv
)
1737 struct net_device
*dev
;
1740 pr_debug("%s: got port %08x\n", __func__
, (u32
)priv
->ports
[priv
->cpu_port
].dp
);
1741 dev
= priv
->ports
[priv
->cpu_port
].dp
->slave
;
1742 mac
= ether_addr_to_u64(dev
->dev_addr
);
1744 for (i
= 0; i
< 15; i
++) {
1745 mac
++; // BUG: VRRP for testing
1746 sw_w32(mac
>> 32, RTL839X_ROUTING_SA_CTRL
+ i
* 8);
1747 sw_w32(mac
, RTL839X_ROUTING_SA_CTRL
+ i
* 8 + 4);
1751 int rtl839x_l3_setup(struct rtl838x_switch_priv
*priv
)
1753 rtl839x_setup_port_macs(priv
);
1758 void rtl839x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
1760 if (type
== PBVLAN_TYPE_INNER
)
1761 sw_w32_mask(0x3, mode
, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1763 sw_w32_mask(0x3 << 14, mode
<< 14, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1766 void rtl839x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
1768 if (type
== PBVLAN_TYPE_INNER
)
1769 sw_w32_mask(0xfff << 2, pvid
<< 2, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1771 sw_w32_mask(0xfff << 16, pvid
<< 16, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1774 static int rtl839x_set_ageing_time(unsigned long msec
)
1776 int t
= sw_r32(RTL839X_L2_CTRL_1
);
1779 t
= t
* 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1780 pr_debug("L2 AGING time: %d sec\n", t
);
1782 t
= (msec
* 5 + 2000) / 3000;
1783 t
= t
> 0x1FFFFF ? 0x1FFFFF : t
;
1784 sw_w32_mask(0x1FFFFF, t
, RTL839X_L2_CTRL_1
);
1785 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT
));
1790 static void rtl839x_set_igr_filter(int port
, enum igr_filter state
)
1792 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
1793 RTL839X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
1796 static void rtl839x_set_egr_filter(int port
, enum egr_filter state
)
1798 sw_w32_mask(0x1 << (port
% 0x20), state
<< (port
% 0x20),
1799 RTL839X_VLAN_PORT_EGR_FLTR
+ (((port
>> 5) << 2)));
1802 void rtl839x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
1804 sw_w32_mask(3 << ((group
& 0xf) << 1), algoidx
<< ((group
& 0xf) << 1),
1805 RTL839X_TRK_HASH_IDX_CTRL
+ ((group
>> 4) << 2));
1806 sw_w32(algomsk
, RTL839X_TRK_HASH_CTRL
+ (algoidx
<< 2));
1809 void rtl839x_set_receive_management_action(int port
, rma_ctrl_t type
, action_type_t action
)
1813 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1814 RTL839X_RMA_BPDU_CTRL
+ ((port
>> 4) << 2));
1817 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1818 RTL839X_RMA_PTP_CTRL
+ ((port
>> 4) << 2));
1821 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1822 RTL839X_RMA_LLTP_CTRL
+ ((port
>> 4) << 2));
1829 const struct rtl838x_reg rtl839x_reg
= {
1830 .mask_port_reg_be
= rtl839x_mask_port_reg_be
,
1831 .set_port_reg_be
= rtl839x_set_port_reg_be
,
1832 .get_port_reg_be
= rtl839x_get_port_reg_be
,
1833 .mask_port_reg_le
= rtl839x_mask_port_reg_le
,
1834 .set_port_reg_le
= rtl839x_set_port_reg_le
,
1835 .get_port_reg_le
= rtl839x_get_port_reg_le
,
1836 .stat_port_rst
= RTL839X_STAT_PORT_RST
,
1837 .stat_rst
= RTL839X_STAT_RST
,
1838 .stat_port_std_mib
= RTL839X_STAT_PORT_STD_MIB
,
1839 .traffic_enable
= rtl839x_traffic_enable
,
1840 .traffic_disable
= rtl839x_traffic_disable
,
1841 .traffic_get
= rtl839x_traffic_get
,
1842 .traffic_set
= rtl839x_traffic_set
,
1843 .port_iso_ctrl
= rtl839x_port_iso_ctrl
,
1844 .l2_ctrl_0
= RTL839X_L2_CTRL_0
,
1845 .l2_ctrl_1
= RTL839X_L2_CTRL_1
,
1846 .l2_port_aging_out
= RTL839X_L2_PORT_AGING_OUT
,
1847 .set_ageing_time
= rtl839x_set_ageing_time
,
1848 .smi_poll_ctrl
= RTL839X_SMI_PORT_POLLING_CTRL
,
1849 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
1850 .exec_tbl0_cmd
= rtl839x_exec_tbl0_cmd
,
1851 .exec_tbl1_cmd
= rtl839x_exec_tbl1_cmd
,
1852 .tbl_access_data_0
= rtl839x_tbl_access_data_0
,
1853 .isr_glb_src
= RTL839X_ISR_GLB_SRC
,
1854 .isr_port_link_sts_chg
= RTL839X_ISR_PORT_LINK_STS_CHG
,
1855 .imr_port_link_sts_chg
= RTL839X_IMR_PORT_LINK_STS_CHG
,
1856 .imr_glb
= RTL839X_IMR_GLB
,
1857 .vlan_tables_read
= rtl839x_vlan_tables_read
,
1858 .vlan_set_tagged
= rtl839x_vlan_set_tagged
,
1859 .vlan_set_untagged
= rtl839x_vlan_set_untagged
,
1860 .vlan_profile_dump
= rtl839x_vlan_profile_dump
,
1861 .vlan_profile_setup
= rtl839x_vlan_profile_setup
,
1862 .vlan_fwd_on_inner
= rtl839x_vlan_fwd_on_inner
,
1863 .vlan_port_pvidmode_set
= rtl839x_vlan_port_pvidmode_set
,
1864 .vlan_port_pvid_set
= rtl839x_vlan_port_pvid_set
,
1865 .set_vlan_igr_filter
= rtl839x_set_igr_filter
,
1866 .set_vlan_egr_filter
= rtl839x_set_egr_filter
,
1867 .enable_learning
= rtl839x_enable_learning
,
1868 .enable_flood
= rtl839x_enable_flood
,
1869 .enable_mcast_flood
= rtl839x_enable_mcast_flood
,
1870 .enable_bcast_flood
= rtl839x_enable_bcast_flood
,
1871 .stp_get
= rtl839x_stp_get
,
1872 .stp_set
= rtl839x_stp_set
,
1873 .mac_force_mode_ctrl
= rtl839x_mac_force_mode_ctrl
,
1874 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
1875 .l2_port_new_salrn
= rtl839x_l2_port_new_salrn
,
1876 .l2_port_new_sa_fwd
= rtl839x_l2_port_new_sa_fwd
,
1877 .mir_ctrl
= RTL839X_MIR_CTRL
,
1878 .mir_dpm
= RTL839X_MIR_DPM_CTRL
,
1879 .mir_spm
= RTL839X_MIR_SPM_CTRL
,
1880 .mac_link_sts
= RTL839X_MAC_LINK_STS
,
1881 .mac_link_dup_sts
= RTL839X_MAC_LINK_DUP_STS
,
1882 .mac_link_spd_sts
= rtl839x_mac_link_spd_sts
,
1883 .mac_rx_pause_sts
= RTL839X_MAC_RX_PAUSE_STS
,
1884 .mac_tx_pause_sts
= RTL839X_MAC_TX_PAUSE_STS
,
1885 .read_l2_entry_using_hash
= rtl839x_read_l2_entry_using_hash
,
1886 .write_l2_entry_using_hash
= rtl839x_write_l2_entry_using_hash
,
1887 .read_cam
= rtl839x_read_cam
,
1888 .write_cam
= rtl839x_write_cam
,
1889 .vlan_port_tag_sts_ctrl
= RTL839X_VLAN_PORT_TAG_STS_CTRL
,
1890 .trk_mbr_ctr
= rtl839x_trk_mbr_ctr
,
1891 .rma_bpdu_fld_pmask
= RTL839X_RMA_BPDU_FLD_PMSK
,
1892 .spcl_trap_eapol_ctrl
= RTL839X_SPCL_TRAP_EAPOL_CTRL
,
1893 .init_eee
= rtl839x_init_eee
,
1894 .port_eee_set
= rtl839x_port_eee_set
,
1895 .eee_port_ability
= rtl839x_eee_port_ability
,
1896 .l2_hash_seed
= rtl839x_l2_hash_seed
,
1897 .l2_hash_key
= rtl839x_l2_hash_key
,
1898 .read_mcast_pmask
= rtl839x_read_mcast_pmask
,
1899 .write_mcast_pmask
= rtl839x_write_mcast_pmask
,
1900 .pie_init
= rtl839x_pie_init
,
1901 .pie_rule_read
= rtl839x_pie_rule_read
,
1902 .pie_rule_write
= rtl839x_pie_rule_write
,
1903 .pie_rule_add
= rtl839x_pie_rule_add
,
1904 .pie_rule_rm
= rtl839x_pie_rule_rm
,
1905 .l2_learning_setup
= rtl839x_l2_learning_setup
,
1906 .packet_cntr_read
= rtl839x_packet_cntr_read
,
1907 .packet_cntr_clear
= rtl839x_packet_cntr_clear
,
1908 .route_read
= rtl839x_route_read
,
1909 .route_write
= rtl839x_route_write
,
1910 .l3_setup
= rtl839x_l3_setup
,
1911 .set_distribution_algorithm
= rtl839x_set_distribution_algorithm
,
1912 .set_receive_management_action
= rtl839x_set_receive_management_action
,