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[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 uint16_t cpu_tag[10];
62 } __packed __aligned(1);
63
64 struct n_event {
65 uint32_t type:2;
66 uint32_t fidVid:12;
67 uint64_t mac:48;
68 uint32_t slp:6;
69 uint32_t valid:1;
70 uint32_t reserved:27;
71 } __packed __aligned(1);
72
73 struct ring_b {
74 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
75 uint32_t tx_r[TXRINGS][TXRINGLEN];
76 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
77 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
78 uint32_t c_rx[MAX_RXRINGS];
79 uint32_t c_tx[TXRINGS];
80 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
81 uint8_t *rx_space;
82 };
83
84 struct notify_block {
85 struct n_event events[NOTIFY_EVENTS];
86 };
87
88 struct notify_b {
89 struct notify_block blocks[NOTIFY_BLOCKS];
90 u32 reserved1[8];
91 u32 ring[NOTIFY_BLOCKS];
92 u32 reserved2[8];
93 };
94
95 static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
96 {
97 prio &= 0x7;
98
99 if (dest_port > 0) {
100 // cpu_tag[0] is reserved on the RTL83XX SoCs
101 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
102 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
103 h->cpu_tag[3] = 0x0000;
104 h->cpu_tag[4] = BIT(dest_port) >> 16;
105 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
106 // Set internal priority and AS_PRIO
107 if (prio >= 0)
108 h->cpu_tag[2] |= (prio | 0x8) << 12;
109 }
110 }
111
112 static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
113 {
114 prio &= 0x7;
115
116 if (dest_port > 0) {
117 // cpu_tag[0] is reserved on the RTL83XX SoCs
118 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
119 h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
120 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
121 if (dest_port >= 32) {
122 dest_port -= 32;
123 h->cpu_tag[2] = BIT(dest_port) >> 16;
124 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
125 } else {
126 h->cpu_tag[4] = BIT(dest_port) >> 16;
127 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
128 }
129 h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
130 h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
131 // Set internal priority and AS_PRIO
132 if (prio >= 0)
133 h->cpu_tag[1] |= prio | BIT(3);
134 }
135 }
136
137 static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
138 {
139 h->cpu_tag[0] = 0x8000; // CPU tag marker
140 h->cpu_tag[1] = h->cpu_tag[2] = 0;
141 if (prio >= 0)
142 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
143 h->cpu_tag[3] = 0;
144 h->cpu_tag[4] = 0;
145 h->cpu_tag[5] = 0;
146 h->cpu_tag[6] = BIT(dest_port) >> 16;
147 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
148 }
149
150 static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
151 {
152 h->cpu_tag[0] = 0x8000; // CPU tag marker
153 h->cpu_tag[1] = h->cpu_tag[2] = 0;
154 if (prio >= 0)
155 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
156 h->cpu_tag[3] = 0;
157 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
158 if (dest_port >= 32) {
159 dest_port -= 32;
160 h->cpu_tag[4] = BIT(dest_port) >> 16;
161 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
162 } else {
163 h->cpu_tag[6] = BIT(dest_port) >> 16;
164 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
165 }
166 }
167
168 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
169 {
170 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
171 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 h->cpu_tag[3] |= (vlan & 0xff) << 8;
173 }
174
175 struct rtl838x_rx_q {
176 int id;
177 struct rtl838x_eth_priv *priv;
178 struct napi_struct napi;
179 };
180
181 struct rtl838x_eth_priv {
182 struct net_device *netdev;
183 struct platform_device *pdev;
184 void *membase;
185 spinlock_t lock;
186 struct mii_bus *mii_bus;
187 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
188 struct phylink *phylink;
189 struct phylink_config phylink_config;
190 u16 id;
191 u16 family_id;
192 const struct rtl838x_eth_reg *r;
193 u8 cpu_port;
194 u32 lastEvent;
195 u16 rxrings;
196 u16 rxringlen;
197 u8 smi_bus[MAX_PORTS];
198 u8 smi_addr[MAX_PORTS];
199 u32 sds_id[MAX_PORTS];
200 bool smi_bus_isc45[MAX_SMI_BUSSES];
201 bool phy_is_internal[MAX_PORTS];
202 };
203
204 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
205 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
206 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
207 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
208 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
209 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
210 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
211 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
212 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
213 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
214 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
215 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
216
217 /*
218 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
219 * the rings. Writing x into these registers substracts x from its content.
220 * When the content reaches the ring size, the ASIC no longer adds
221 * packets to this receive queue.
222 */
223 void rtl838x_update_cntr(int r, int released)
224 {
225 // This feature is not available on RTL838x SoCs
226 }
227
228 void rtl839x_update_cntr(int r, int released)
229 {
230 // This feature is not available on RTL839x SoCs
231 }
232
233 void rtl930x_update_cntr(int r, int released)
234 {
235 int pos = (r % 3) * 10;
236 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
237 u32 v = sw_r32(reg);
238
239 v = (v >> pos) & 0x3ff;
240 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
241 sw_w32_mask(0x3ff << pos, released << pos, reg);
242 sw_w32(v, reg);
243 }
244
245 void rtl931x_update_cntr(int r, int released)
246 {
247 int pos = (r % 3) * 10;
248 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
249 u32 v = sw_r32(reg);
250
251 v = (v >> pos) & 0x3ff;
252 sw_w32_mask(0x3ff << pos, released << pos, reg);
253 sw_w32(v, reg);
254 }
255
256 struct dsa_tag {
257 u8 reason;
258 u8 queue;
259 u16 port;
260 u8 l2_offloaded;
261 u8 prio;
262 bool crc_error;
263 };
264
265 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
266 {
267 t->reason = h->cpu_tag[3] & 0xf;
268 t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
269 t->port = h->cpu_tag[1] & 0x1f;
270 t->crc_error = t->reason == 13;
271
272 pr_debug("Reason: %d\n", t->reason);
273 if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
274 t->l2_offloaded = 1;
275 else
276 t->l2_offloaded = 0;
277
278 return t->l2_offloaded;
279 }
280
281 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
282 {
283 t->reason = h->cpu_tag[4] & 0x1f;
284 t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
285 t->port = h->cpu_tag[1] & 0x3f;
286 t->crc_error = h->cpu_tag[3] & BIT(2);
287
288 pr_debug("Reason: %d\n", t->reason);
289 if ((t->reason != 7) && (t->reason != 8)) // NIC_RX_REASON_RMA_USR
290 t->l2_offloaded = 1;
291 else
292 t->l2_offloaded = 0;
293
294 return t->l2_offloaded;
295 }
296
297 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
298 {
299 t->reason = h->cpu_tag[7] & 0x3f;
300 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
301 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
302 t->crc_error = h->cpu_tag[1] & BIT(6);
303
304 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
305 if (t->reason >= 19 && t->reason <= 27)
306 t->l2_offloaded = 0;
307 else
308 t->l2_offloaded = 1;
309
310 return t->l2_offloaded;
311 }
312
313 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
314 {
315 t->reason = h->cpu_tag[7] & 0x3f;
316 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
317 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
318 t->crc_error = h->cpu_tag[1] & BIT(6);
319
320 if (t->reason != 63)
321 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
322 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
323 t->l2_offloaded = 0;
324 else
325 t->l2_offloaded = 1;
326
327 return t->l2_offloaded;
328 }
329
330 /*
331 * Discard the RX ring-buffers, called as part of the net-ISR
332 * when the buffer runs over
333 * Caller needs to hold priv->lock
334 */
335 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
336 {
337 int r;
338 u32 *last;
339 struct p_hdr *h;
340 struct ring_b *ring = priv->membase;
341
342 for (r = 0; r < priv->rxrings; r++) {
343 pr_debug("In %s working on r: %d\n", __func__, r);
344 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
345 do {
346 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
347 break;
348 pr_debug("Got something: %d\n", ring->c_rx[r]);
349 h = &ring->rx_header[r][ring->c_rx[r]];
350 memset(h, 0, sizeof(struct p_hdr));
351 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
352 + r * priv->rxringlen * RING_BUFFER
353 + ring->c_rx[r] * RING_BUFFER);
354 h->size = RING_BUFFER;
355 /* make sure the header is visible to the ASIC */
356 mb();
357
358 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
359 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
360 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
361 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
362 }
363 }
364
365 struct fdb_update_work {
366 struct work_struct work;
367 struct net_device *ndev;
368 u64 macs[NOTIFY_EVENTS + 1];
369 };
370
371 void rtl838x_fdb_sync(struct work_struct *work)
372 {
373 const struct fdb_update_work *uw =
374 container_of(work, struct fdb_update_work, work);
375 struct switchdev_notifier_fdb_info info;
376 u8 addr[ETH_ALEN];
377 int i = 0;
378 int action;
379
380 while (uw->macs[i]) {
381 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
382 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
383 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
384 info.addr = &addr[0];
385 info.vid = 0;
386 info.offloaded = 1;
387 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
388 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
389 i++;
390 }
391 kfree(work);
392 }
393
394 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
395 {
396 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
397 u32 e = priv->lastEvent;
398 struct n_event *event;
399 int i;
400 u64 mac;
401 struct fdb_update_work *w;
402
403 while (!(nb->ring[e] & 1)) {
404 w = kzalloc(sizeof(*w), GFP_ATOMIC);
405 if (!w) {
406 pr_err("Out of memory: %s", __func__);
407 return;
408 }
409 INIT_WORK(&w->work, rtl838x_fdb_sync);
410
411 for (i = 0; i < NOTIFY_EVENTS; i++) {
412 event = &nb->blocks[e].events[i];
413 if (!event->valid)
414 continue;
415 mac = event->mac;
416 if (event->type)
417 mac |= 1ULL << 63;
418 w->ndev = priv->netdev;
419 w->macs[i] = mac;
420 }
421
422 /* Hand the ring entry back to the switch */
423 nb->ring[e] = nb->ring[e] | 1;
424 e = (e + 1) % NOTIFY_BLOCKS;
425
426 w->macs[i] = 0ULL;
427 schedule_work(&w->work);
428 }
429 priv->lastEvent = e;
430 }
431
432 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
433 {
434 struct net_device *dev = dev_id;
435 struct rtl838x_eth_priv *priv = netdev_priv(dev);
436 u32 status = sw_r32(priv->r->dma_if_intr_sts);
437 int i;
438
439 pr_debug("IRQ: %08x\n", status);
440
441 spin_lock(&priv->lock);
442 /* Ignore TX interrupt */
443 if ((status & 0xf0000)) {
444 /* Clear ISR */
445 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
446 }
447
448 /* RX interrupt */
449 if (status & 0x0ff00) {
450 /* ACK and disable RX interrupt for this ring */
451 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
452 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
453 for (i = 0; i < priv->rxrings; i++) {
454 if (status & BIT(i + 8)) {
455 pr_debug("Scheduling queue: %d\n", i);
456 napi_schedule(&priv->rx_qs[i].napi);
457 }
458 }
459 }
460
461 /* RX buffer overrun */
462 if (status & 0x000ff) {
463 pr_debug("RX buffer overrun: status %x, mask: %x\n",
464 status, sw_r32(priv->r->dma_if_intr_msk));
465 sw_w32(status, priv->r->dma_if_intr_sts);
466 rtl838x_rb_cleanup(priv, status & 0xff);
467 }
468
469 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
470 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
471 rtl839x_l2_notification_handler(priv);
472 }
473
474 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
475 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
476 rtl839x_l2_notification_handler(priv);
477 }
478
479 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
480 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
481 rtl839x_l2_notification_handler(priv);
482 }
483
484 spin_unlock(&priv->lock);
485 return IRQ_HANDLED;
486 }
487
488 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
489 {
490 struct net_device *dev = dev_id;
491 struct rtl838x_eth_priv *priv = netdev_priv(dev);
492 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
493 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
494 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
495 int i;
496
497 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
498 __func__, status_tx, status_rx, status_rx_r);
499 spin_lock(&priv->lock);
500
501 /* Ignore TX interrupt */
502 if (status_tx) {
503 /* Clear ISR */
504 pr_debug("TX done\n");
505 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
506 }
507
508 /* RX interrupt */
509 if (status_rx) {
510 pr_debug("RX IRQ\n");
511 /* ACK and disable RX interrupt for given rings */
512 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
513 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
514 for (i = 0; i < priv->rxrings; i++) {
515 if (status_rx & BIT(i)) {
516 pr_debug("Scheduling queue: %d\n", i);
517 napi_schedule(&priv->rx_qs[i].napi);
518 }
519 }
520 }
521
522 /* RX buffer overrun */
523 if (status_rx_r) {
524 pr_debug("RX buffer overrun: status %x, mask: %x\n",
525 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
526 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
527 rtl838x_rb_cleanup(priv, status_rx_r);
528 }
529
530 spin_unlock(&priv->lock);
531 return IRQ_HANDLED;
532 }
533
534 static const struct rtl838x_eth_reg rtl838x_reg = {
535 .net_irq = rtl83xx_net_irq,
536 .mac_port_ctrl = rtl838x_mac_port_ctrl,
537 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
538 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
539 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
540 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
541 .dma_rx_base = RTL838X_DMA_RX_BASE,
542 .dma_tx_base = RTL838X_DMA_TX_BASE,
543 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
544 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
545 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
546 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
547 .get_mac_link_sts = rtl838x_get_mac_link_sts,
548 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
549 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
550 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
551 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
552 .mac = RTL838X_MAC,
553 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
554 .update_cntr = rtl838x_update_cntr,
555 .create_tx_header = rtl838x_create_tx_header,
556 .decode_tag = rtl838x_decode_tag,
557 };
558
559 static const struct rtl838x_eth_reg rtl839x_reg = {
560 .net_irq = rtl83xx_net_irq,
561 .mac_port_ctrl = rtl839x_mac_port_ctrl,
562 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
563 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
564 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
565 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
566 .dma_rx_base = RTL839X_DMA_RX_BASE,
567 .dma_tx_base = RTL839X_DMA_TX_BASE,
568 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
569 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
570 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
571 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
572 .get_mac_link_sts = rtl839x_get_mac_link_sts,
573 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
574 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
575 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
576 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
577 .mac = RTL839X_MAC,
578 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
579 .update_cntr = rtl839x_update_cntr,
580 .create_tx_header = rtl839x_create_tx_header,
581 .decode_tag = rtl839x_decode_tag,
582 };
583
584 static const struct rtl838x_eth_reg rtl930x_reg = {
585 .net_irq = rtl93xx_net_irq,
586 .mac_port_ctrl = rtl930x_mac_port_ctrl,
587 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
588 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
589 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
590 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
591 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
592 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
593 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
594 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
595 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
596 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
597 .dma_rx_base = RTL930X_DMA_RX_BASE,
598 .dma_tx_base = RTL930X_DMA_TX_BASE,
599 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
600 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
601 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
602 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
603 .get_mac_link_sts = rtl930x_get_mac_link_sts,
604 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
605 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
606 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
607 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
608 .mac = RTL930X_MAC_L2_ADDR_CTRL,
609 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
610 .update_cntr = rtl930x_update_cntr,
611 .create_tx_header = rtl930x_create_tx_header,
612 .decode_tag = rtl930x_decode_tag,
613 };
614
615 static const struct rtl838x_eth_reg rtl931x_reg = {
616 .net_irq = rtl93xx_net_irq,
617 .mac_port_ctrl = rtl931x_mac_port_ctrl,
618 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
619 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
620 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
621 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
622 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
623 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
624 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
625 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
626 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
627 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
628 .dma_rx_base = RTL931X_DMA_RX_BASE,
629 .dma_tx_base = RTL931X_DMA_TX_BASE,
630 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
631 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
632 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
633 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
634 .get_mac_link_sts = rtl931x_get_mac_link_sts,
635 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
636 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
637 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
638 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
639 .mac = RTL931X_MAC_L2_ADDR_CTRL,
640 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
641 .update_cntr = rtl931x_update_cntr,
642 .create_tx_header = rtl931x_create_tx_header,
643 .decode_tag = rtl931x_decode_tag,
644 };
645
646 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
647 {
648 u32 int_saved, nbuf;
649 u32 reset_mask;
650 int i, pos;
651
652 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
653 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
654 mdelay(100);
655
656 /* Disable and clear interrupts */
657 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
658 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
659 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
660 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
661 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
662 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
663 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
664 } else {
665 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
666 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
667 }
668
669 if (priv->family_id == RTL8390_FAMILY_ID) {
670 /* Preserve L2 notification and NBUF settings */
671 int_saved = sw_r32(priv->r->dma_if_intr_msk);
672 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
673
674 /* Disable link change interrupt on RTL839x */
675 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
676 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
677
678 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
679 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
680 }
681
682 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
683 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
684 reset_mask = 0x6;
685 else
686 reset_mask = 0xc;
687
688 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
689
690 do { /* Wait for reset of NIC and Queues done */
691 udelay(20);
692 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
693 mdelay(100);
694
695 /* Setup Head of Line */
696 if (priv->family_id == RTL8380_FAMILY_ID)
697 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
698 if (priv->family_id == RTL8390_FAMILY_ID)
699 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
700 if (priv->family_id == RTL9300_FAMILY_ID) {
701 for (i = 0; i < priv->rxrings; i++) {
702 pos = (i % 3) * 10;
703 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
704 sw_w32_mask(0x3ff << pos, priv->rxringlen,
705 priv->r->dma_if_rx_ring_cntr(i));
706 }
707 }
708
709 /* Re-enable link change interrupt */
710 if (priv->family_id == RTL8390_FAMILY_ID) {
711 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
712 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
713 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
714 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
715
716 /* Restore notification settings: on RTL838x these bits are null */
717 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
718 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
719 }
720 }
721
722 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
723 {
724 int i;
725 struct ring_b *ring = priv->membase;
726
727 for (i = 0; i < priv->rxrings; i++)
728 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
729
730 for (i = 0; i < TXRINGS; i++)
731 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
732 }
733
734 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
735 {
736 /* Disable Head of Line features for all RX rings */
737 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
738
739 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
740 sw_w32(0x06400020, priv->r->dma_if_ctrl);
741
742 /* Enable RX done, RX overflow and TX done interrupts */
743 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
744
745 /* Enable DMA, engine expects empty FCS field */
746 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
747
748 /* Restart TX/RX to CPU port */
749 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
750 /* Set Speed, duplex, flow control
751 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
752 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
753 * | MEDIA_SEL
754 */
755 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
756
757 /* Enable CRC checks on CPU-port */
758 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
759 }
760
761 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
762 {
763 /* Setup CPU-Port: RX Buffer */
764 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
765
766 /* Enable Notify, RX done, RX overflow and TX done interrupts */
767 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
768
769 /* Enable DMA */
770 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
771
772 /* Restart TX/RX to CPU port, enable CRC checking */
773 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
774
775 /* CPU port joins Lookup Miss Flooding Portmask */
776 // TODO: The code below should also work for the RTL838x
777 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
778 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
779 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
780
781 /* Force CPU port link up */
782 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
783 }
784
785 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
786 {
787 int i, pos;
788 u32 v;
789
790 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
791 sw_w32(0x06400040, priv->r->dma_if_ctrl);
792
793 for (i = 0; i < priv->rxrings; i++) {
794 pos = (i % 3) * 10;
795 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
796
797 // Some SoCs have issues with missing underflow protection
798 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
799 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
800 }
801
802 /* Enable Notify, RX done, RX overflow and TX done interrupts */
803 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
804 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
805 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
806
807 /* Enable DMA */
808 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
809
810 /* Restart TX/RX to CPU port, enable CRC checking */
811 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
812
813 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
814 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
815 }
816
817 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
818 {
819 int i, j;
820
821 struct p_hdr *h;
822
823 for (i = 0; i < priv->rxrings; i++) {
824 for (j = 0; j < priv->rxringlen; j++) {
825 h = &ring->rx_header[i][j];
826 memset(h, 0, sizeof(struct p_hdr));
827 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
828 + i * priv->rxringlen * RING_BUFFER
829 + j * RING_BUFFER);
830 h->size = RING_BUFFER;
831 /* All rings owned by switch, last one wraps */
832 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
833 | (j == (priv->rxringlen - 1) ? WRAP : 0);
834 }
835 ring->c_rx[i] = 0;
836 }
837
838 for (i = 0; i < TXRINGS; i++) {
839 for (j = 0; j < TXRINGLEN; j++) {
840 h = &ring->tx_header[i][j];
841 memset(h, 0, sizeof(struct p_hdr));
842 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
843 + i * TXRINGLEN * RING_BUFFER
844 + j * RING_BUFFER);
845 h->size = RING_BUFFER;
846 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
847 }
848 /* Last header is wrapping around */
849 ring->tx_r[i][j-1] |= WRAP;
850 ring->c_tx[i] = 0;
851 }
852 }
853
854 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
855 {
856 int i;
857 struct notify_b *b = priv->membase + sizeof(struct ring_b);
858
859 for (i = 0; i < NOTIFY_BLOCKS; i++)
860 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
861
862 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
863 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
864
865 /* Setup notification events */
866 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
867 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
868
869 /* Enable Notification */
870 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
871 priv->lastEvent = 0;
872 }
873
874 static int rtl838x_eth_open(struct net_device *ndev)
875 {
876 unsigned long flags;
877 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
878 struct ring_b *ring = priv->membase;
879 int i, err;
880
881 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
882 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
883
884 spin_lock_irqsave(&priv->lock, flags);
885 rtl838x_hw_reset(priv);
886 rtl838x_setup_ring_buffer(priv, ring);
887 if (priv->family_id == RTL8390_FAMILY_ID) {
888 rtl839x_setup_notify_ring_buffer(priv);
889 /* Make sure the ring structure is visible to the ASIC */
890 mb();
891 flush_cache_all();
892 }
893
894 rtl838x_hw_ring_setup(priv);
895 err = request_irq(ndev->irq, priv->r->net_irq, IRQF_SHARED, ndev->name, ndev);
896 if (err) {
897 netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
898 __func__, err);
899 return err;
900 }
901 phylink_start(priv->phylink);
902
903 for (i = 0; i < priv->rxrings; i++)
904 napi_enable(&priv->rx_qs[i].napi);
905
906 switch (priv->family_id) {
907 case RTL8380_FAMILY_ID:
908 rtl838x_hw_en_rxtx(priv);
909 /* Trap IGMP/MLD traffic to CPU-Port */
910 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
911 /* Flush learned FDB entries on link down of a port */
912 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
913 break;
914
915 case RTL8390_FAMILY_ID:
916 rtl839x_hw_en_rxtx(priv);
917 // Trap MLD and IGMP messages to CPU_PORT
918 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
919 /* Flush learned FDB entries on link down of a port */
920 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
921 break;
922
923 case RTL9300_FAMILY_ID:
924 rtl93xx_hw_en_rxtx(priv);
925 /* Flush learned FDB entries on link down of a port */
926 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
927 // Trap MLD and IGMP messages to CPU_PORT
928 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
929 break;
930
931 case RTL9310_FAMILY_ID:
932 rtl93xx_hw_en_rxtx(priv);
933 break;
934 }
935
936 netif_tx_start_all_queues(ndev);
937
938 spin_unlock_irqrestore(&priv->lock, flags);
939
940 return 0;
941 }
942
943 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
944 {
945 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
946 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
947 int i;
948
949 // Disable RX/TX from/to CPU-port
950 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
951
952 /* Disable traffic */
953 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
954 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
955 else
956 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
957 mdelay(200); // Test, whether this is needed
958
959 /* Block all ports */
960 if (priv->family_id == RTL8380_FAMILY_ID) {
961 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
962 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
963 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
964 }
965
966 /* Flush L2 address cache */
967 if (priv->family_id == RTL8380_FAMILY_ID) {
968 for (i = 0; i <= priv->cpu_port; i++) {
969 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
970 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
971 }
972 } else if (priv->family_id == RTL8390_FAMILY_ID) {
973 for (i = 0; i <= priv->cpu_port; i++) {
974 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
975 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
976 }
977 }
978 // TODO: L2 flush register is 64 bit on RTL931X and 930X
979
980 /* CPU-Port: Link down */
981 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
982 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
983 else
984 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
985 mdelay(100);
986
987 /* Disable all TX/RX interrupts */
988 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
989 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
990 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
991 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
992 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
993 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
994 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
995 } else {
996 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
997 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
998 }
999
1000 /* Disable TX/RX DMA */
1001 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1002 mdelay(200);
1003 }
1004
1005 static int rtl838x_eth_stop(struct net_device *ndev)
1006 {
1007 unsigned long flags;
1008 int i;
1009 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1010
1011 pr_info("in %s\n", __func__);
1012
1013 spin_lock_irqsave(&priv->lock, flags);
1014 phylink_stop(priv->phylink);
1015 rtl838x_hw_stop(priv);
1016 free_irq(ndev->irq, ndev);
1017
1018 for (i = 0; i < priv->rxrings; i++)
1019 napi_disable(&priv->rx_qs[i].napi);
1020
1021 netif_tx_stop_all_queues(ndev);
1022
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024
1025 return 0;
1026 }
1027
1028 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1029 {
1030 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1031 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1032 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1033 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1034 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1035 }
1036 if (ndev->flags & IFF_ALLMULTI) {
1037 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1038 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1039 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1040 }
1041 if (ndev->flags & IFF_PROMISC) {
1042 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1043 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1044 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1045 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1046 }
1047 }
1048
1049 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1050 {
1051 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1052
1053 if (priv->family_id == RTL8390_FAMILY_ID)
1054 return rtl839x_eth_set_multicast_list(ndev);
1055
1056 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1057 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1058 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1059 }
1060 if (ndev->flags & IFF_ALLMULTI)
1061 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1062 if (ndev->flags & IFF_PROMISC) {
1063 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1064 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1065 }
1066 }
1067
1068 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1069 {
1070 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1071 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1072 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1073 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1074 }
1075 if (ndev->flags & IFF_ALLMULTI) {
1076 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1077 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1078 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1079 }
1080 if (ndev->flags & IFF_PROMISC) {
1081 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1082 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1083 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1084 }
1085 }
1086
1087 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1088 {
1089 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1090 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1091 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1092 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1093 }
1094 if (ndev->flags & IFF_ALLMULTI) {
1095 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1096 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1097 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1098 }
1099 if (ndev->flags & IFF_PROMISC) {
1100 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1101 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1102 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1103 }
1104 }
1105
1106 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1107 {
1108 unsigned long flags;
1109 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1110
1111 pr_warn("%s\n", __func__);
1112 spin_lock_irqsave(&priv->lock, flags);
1113 rtl838x_hw_stop(priv);
1114 rtl838x_hw_ring_setup(priv);
1115 rtl838x_hw_en_rxtx(priv);
1116 netif_trans_update(ndev);
1117 netif_start_queue(ndev);
1118 spin_unlock_irqrestore(&priv->lock, flags);
1119 }
1120
1121 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1122 {
1123 int len, i;
1124 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1125 struct ring_b *ring = priv->membase;
1126 uint32_t val;
1127 int ret;
1128 unsigned long flags;
1129 struct p_hdr *h;
1130 int dest_port = -1;
1131 int q = skb_get_queue_mapping(skb) % TXRINGS;
1132
1133 if (q) // Check for high prio queue
1134 pr_debug("SKB priority: %d\n", skb->priority);
1135
1136 spin_lock_irqsave(&priv->lock, flags);
1137 len = skb->len;
1138
1139 /* Check for DSA tagging at the end of the buffer */
1140 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
1141 && skb->data[len-3] < priv->cpu_port && skb->data[len-2] == 0x10
1142 && skb->data[len-1] == 0x00) {
1143 /* Reuse tag space for CRC if possible */
1144 dest_port = skb->data[len-3];
1145 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1146 len -= 4;
1147 }
1148
1149 len += 4; // Add space for CRC
1150
1151 if (skb_padto(skb, len)) {
1152 ret = NETDEV_TX_OK;
1153 goto txdone;
1154 }
1155
1156 /* We can send this packet if CPU owns the descriptor */
1157 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1158
1159 /* Set descriptor for tx */
1160 h = &ring->tx_header[q][ring->c_tx[q]];
1161 h->size = len;
1162 h->len = len;
1163 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1164 if (priv->family_id == RTL8380_FAMILY_ID) {
1165 if (len < ETH_ZLEN - 4)
1166 h->len -= 4;
1167 }
1168
1169 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1170
1171 /* Copy packet data to tx buffer */
1172 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1173 /* Make sure packet data is visible to ASIC */
1174 wmb();
1175
1176 /* Hand over to switch */
1177 ring->tx_r[q][ring->c_tx[q]] |= 1;
1178
1179 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1180 if (priv->family_id == RTL8380_FAMILY_ID) {
1181 for (i = 0; i < 10; i++) {
1182 val = sw_r32(priv->r->dma_if_ctrl);
1183 if ((val & 0xc) == 0xc)
1184 break;
1185 }
1186 }
1187
1188 /* Tell switch to send data */
1189 if (priv->family_id == RTL9310_FAMILY_ID
1190 || priv->family_id == RTL9300_FAMILY_ID) {
1191 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1192 if (!q)
1193 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1194 else
1195 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1196 } else {
1197 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1198 }
1199
1200 dev->stats.tx_packets++;
1201 dev->stats.tx_bytes += len;
1202 dev_kfree_skb(skb);
1203 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1204 ret = NETDEV_TX_OK;
1205 } else {
1206 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1207 ret = NETDEV_TX_BUSY;
1208 }
1209 txdone:
1210 spin_unlock_irqrestore(&priv->lock, flags);
1211 return ret;
1212 }
1213
1214 /*
1215 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1216 * so we do round-robin
1217 */
1218 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1219 struct net_device *sb_dev)
1220 {
1221 static u8 last = 0;
1222
1223 last++;
1224 return last % TXRINGS;
1225 }
1226
1227 /*
1228 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1229 */
1230 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1231 struct net_device *sb_dev)
1232 {
1233 if (skb->priority >= TC_PRIO_CONTROL)
1234 return 1;
1235 return 0;
1236 }
1237
1238 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1239 {
1240 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1241 struct ring_b *ring = priv->membase;
1242 struct sk_buff *skb;
1243 unsigned long flags;
1244 int i, len, work_done = 0;
1245 u8 *data, *skb_data;
1246 unsigned int val;
1247 u32 *last;
1248 struct p_hdr *h;
1249 bool dsa = netdev_uses_dsa(dev);
1250 struct dsa_tag tag;
1251
1252 spin_lock_irqsave(&priv->lock, flags);
1253 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1254 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1255
1256 do {
1257 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1258 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1259 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1260 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1261 }
1262 break;
1263 }
1264
1265 h = &ring->rx_header[r][ring->c_rx[r]];
1266 data = (u8 *)KSEG1ADDR(h->buf);
1267 len = h->len;
1268 if (!len)
1269 break;
1270 work_done++;
1271
1272 len -= 4; /* strip the CRC */
1273 /* Add 4 bytes for cpu_tag */
1274 if (dsa)
1275 len += 4;
1276
1277 skb = alloc_skb(len + 4, GFP_KERNEL);
1278 skb_reserve(skb, NET_IP_ALIGN);
1279
1280 if (likely(skb)) {
1281 /* BUG: Prevent bug on RTL838x SoCs*/
1282 if (priv->family_id == RTL8380_FAMILY_ID) {
1283 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1284 for (i = 0; i < priv->rxrings; i++) {
1285 /* Update each ring cnt */
1286 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1287 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1288 }
1289 }
1290
1291 skb_data = skb_put(skb, len);
1292 /* Make sure data is visible */
1293 mb();
1294 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1295 /* Overwrite CRC with cpu_tag */
1296 if (dsa) {
1297 priv->r->decode_tag(h, &tag);
1298 skb->data[len-4] = 0x80;
1299 skb->data[len-3] = tag.port;
1300 skb->data[len-2] = 0x10;
1301 skb->data[len-1] = 0x00;
1302 if (tag.l2_offloaded)
1303 skb->data[len-3] |= 0x40;
1304 }
1305
1306 if (tag.queue >= 0)
1307 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1308 tag.queue, len, tag.reason, tag.port);
1309
1310 skb->protocol = eth_type_trans(skb, dev);
1311 if (dev->features & NETIF_F_RXCSUM) {
1312 if (tag.crc_error)
1313 skb_checksum_none_assert(skb);
1314 else
1315 skb->ip_summed = CHECKSUM_UNNECESSARY;
1316 }
1317 dev->stats.rx_packets++;
1318 dev->stats.rx_bytes += len;
1319
1320 netif_receive_skb(skb);
1321 } else {
1322 if (net_ratelimit())
1323 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1324 dev->stats.rx_dropped++;
1325 }
1326
1327 /* Reset header structure */
1328 memset(h, 0, sizeof(struct p_hdr));
1329 h->buf = data;
1330 h->size = RING_BUFFER;
1331
1332 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1333 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1334 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1335 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1336 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1337
1338 // Update counters
1339 priv->r->update_cntr(r, 0);
1340
1341 spin_unlock_irqrestore(&priv->lock, flags);
1342 return work_done;
1343 }
1344
1345 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1346 {
1347 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1348 struct rtl838x_eth_priv *priv = rx_q->priv;
1349 int work_done = 0;
1350 int r = rx_q->id;
1351 int work;
1352
1353 while (work_done < budget) {
1354 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1355 if (!work)
1356 break;
1357 work_done += work;
1358 }
1359
1360 if (work_done < budget) {
1361 napi_complete_done(napi, work_done);
1362
1363 /* Enable RX interrupt */
1364 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1365 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1366 else
1367 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1368 }
1369 return work_done;
1370 }
1371
1372
1373 static void rtl838x_validate(struct phylink_config *config,
1374 unsigned long *supported,
1375 struct phylink_link_state *state)
1376 {
1377 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1378
1379 pr_debug("In %s\n", __func__);
1380
1381 if (!phy_interface_mode_is_rgmii(state->interface) &&
1382 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1383 state->interface != PHY_INTERFACE_MODE_MII &&
1384 state->interface != PHY_INTERFACE_MODE_REVMII &&
1385 state->interface != PHY_INTERFACE_MODE_GMII &&
1386 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1387 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1388 state->interface != PHY_INTERFACE_MODE_SGMII) {
1389 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1390 pr_err("Unsupported interface: %d\n", state->interface);
1391 return;
1392 }
1393
1394 /* Allow all the expected bits */
1395 phylink_set(mask, Autoneg);
1396 phylink_set_port_modes(mask);
1397 phylink_set(mask, Pause);
1398 phylink_set(mask, Asym_Pause);
1399
1400 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1401 * including Half duplex
1402 */
1403 if (state->interface != PHY_INTERFACE_MODE_MII &&
1404 state->interface != PHY_INTERFACE_MODE_REVMII) {
1405 phylink_set(mask, 1000baseT_Full);
1406 phylink_set(mask, 1000baseT_Half);
1407 }
1408
1409 phylink_set(mask, 10baseT_Half);
1410 phylink_set(mask, 10baseT_Full);
1411 phylink_set(mask, 100baseT_Half);
1412 phylink_set(mask, 100baseT_Full);
1413
1414 bitmap_and(supported, supported, mask,
1415 __ETHTOOL_LINK_MODE_MASK_NBITS);
1416 bitmap_and(state->advertising, state->advertising, mask,
1417 __ETHTOOL_LINK_MODE_MASK_NBITS);
1418 }
1419
1420
1421 static void rtl838x_mac_config(struct phylink_config *config,
1422 unsigned int mode,
1423 const struct phylink_link_state *state)
1424 {
1425 /* This is only being called for the master device,
1426 * i.e. the CPU-Port. We don't need to do anything.
1427 */
1428
1429 pr_info("In %s, mode %x\n", __func__, mode);
1430 }
1431
1432 static void rtl838x_mac_an_restart(struct phylink_config *config)
1433 {
1434 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1435 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1436
1437 /* This works only on RTL838x chips */
1438 if (priv->family_id != RTL8380_FAMILY_ID)
1439 return;
1440
1441 pr_debug("In %s\n", __func__);
1442 /* Restart by disabling and re-enabling link */
1443 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1444 mdelay(20);
1445 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1446 }
1447
1448 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1449 struct phylink_link_state *state)
1450 {
1451 u32 speed;
1452 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1453 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1454 int port = priv->cpu_port;
1455
1456 pr_debug("In %s\n", __func__);
1457
1458 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1459 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1460
1461 speed = priv->r->get_mac_link_spd_sts(port);
1462 switch (speed) {
1463 case 0:
1464 state->speed = SPEED_10;
1465 break;
1466 case 1:
1467 state->speed = SPEED_100;
1468 break;
1469 case 2:
1470 state->speed = SPEED_1000;
1471 break;
1472 default:
1473 state->speed = SPEED_UNKNOWN;
1474 break;
1475 }
1476
1477 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1478 if (priv->r->get_mac_rx_pause_sts(port))
1479 state->pause |= MLO_PAUSE_RX;
1480 if (priv->r->get_mac_tx_pause_sts(port))
1481 state->pause |= MLO_PAUSE_TX;
1482 }
1483
1484 static void rtl838x_mac_link_down(struct phylink_config *config,
1485 unsigned int mode,
1486 phy_interface_t interface)
1487 {
1488 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1489 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1490
1491 pr_debug("In %s\n", __func__);
1492 /* Stop TX/RX to port */
1493 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1494 }
1495
1496 static void rtl838x_mac_link_up(struct phylink_config *config,
1497 struct phy_device *phy, unsigned int mode,
1498 phy_interface_t interface, int speed, int duplex,
1499 bool tx_pause, bool rx_pause)
1500 {
1501 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1502 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1503
1504 pr_debug("In %s\n", __func__);
1505 /* Restart TX/RX to port */
1506 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1507 }
1508
1509 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1510 {
1511 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1512 unsigned long flags;
1513
1514 spin_lock_irqsave(&priv->lock, flags);
1515 pr_debug("In %s\n", __func__);
1516 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1517 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1518
1519 if (priv->family_id == RTL8380_FAMILY_ID) {
1520 /* 2 more registers, ALE/MAC block */
1521 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1522 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1523 (RTL838X_MAC_ALE + 4));
1524
1525 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1526 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1527 RTL838X_MAC2 + 4);
1528 }
1529 spin_unlock_irqrestore(&priv->lock, flags);
1530 }
1531
1532 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1533 {
1534 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1535 const struct sockaddr *addr = p;
1536 u8 *mac = (u8 *) (addr->sa_data);
1537
1538 if (!is_valid_ether_addr(addr->sa_data))
1539 return -EADDRNOTAVAIL;
1540
1541 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1542 rtl838x_set_mac_hw(dev, mac);
1543
1544 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1545 return 0;
1546 }
1547
1548 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1549 {
1550 // We will need to set-up EEE and the egress-rate limitation
1551 return 0;
1552 }
1553
1554 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1555 {
1556 int i;
1557
1558 if (priv->family_id == 0x8390)
1559 return rtl8390_init_mac(priv);
1560
1561 pr_info("%s\n", __func__);
1562 /* fix timer for EEE */
1563 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1564 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1565
1566 /* Init VLAN */
1567 if (priv->id == 0x8382) {
1568 for (i = 0; i <= 28; i++)
1569 sw_w32(0, 0xd57c + i * 0x80);
1570 }
1571 if (priv->id == 0x8380) {
1572 for (i = 8; i <= 28; i++)
1573 sw_w32(0, 0xd57c + i * 0x80);
1574 }
1575 return 0;
1576 }
1577
1578 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1579 struct ethtool_link_ksettings *cmd)
1580 {
1581 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1582
1583 pr_debug("%s called\n", __func__);
1584 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1585 }
1586
1587 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1588 const struct ethtool_link_ksettings *cmd)
1589 {
1590 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1591
1592 pr_debug("%s called\n", __func__);
1593 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1594 }
1595
1596 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1597 {
1598 u32 val;
1599 int err;
1600 struct rtl838x_eth_priv *priv = bus->priv;
1601
1602 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1603 return rtl838x_read_sds_phy(mii_id, regnum);
1604 err = rtl838x_read_phy(mii_id, 0, regnum, &val);
1605 if (err)
1606 return err;
1607 return val;
1608 }
1609
1610 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1611 {
1612 u32 val;
1613 int err;
1614 struct rtl838x_eth_priv *priv = bus->priv;
1615
1616 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1617 return rtl839x_read_sds_phy(mii_id, regnum);
1618
1619 err = rtl839x_read_phy(mii_id, 0, regnum, &val);
1620 if (err)
1621 return err;
1622 return val;
1623 }
1624
1625 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1626 {
1627 u32 val;
1628 int err;
1629
1630 // TODO: These are hard-coded for the 2 Fibre Ports of the XGS1210
1631 if (mii_id >= 26 && mii_id <= 27)
1632 return rtl930x_read_sds_phy(mii_id - 18, 0, regnum);
1633
1634 if (regnum & MII_ADDR_C45) {
1635 regnum &= ~MII_ADDR_C45;
1636 err = rtl930x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
1637 } else {
1638 err = rtl930x_read_phy(mii_id, 0, regnum, &val);
1639 }
1640 if (err)
1641 return err;
1642 return val;
1643 }
1644
1645 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1646 {
1647 u32 val;
1648 int err;
1649 // struct rtl838x_eth_priv *priv = bus->priv;
1650
1651 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1652 // return rtl839x_read_sds_phy(mii_id, regnum);
1653
1654 err = rtl931x_read_phy(mii_id, 0, regnum, &val);
1655 if (err)
1656 return err;
1657 return val;
1658 }
1659
1660 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1661 int regnum, u16 value)
1662 {
1663 u32 offset = 0;
1664 struct rtl838x_eth_priv *priv = bus->priv;
1665
1666 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1667 if (mii_id == 26)
1668 offset = 0x100;
1669 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1670 return 0;
1671 }
1672 return rtl838x_write_phy(mii_id, 0, regnum, value);
1673 }
1674
1675 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1676 int regnum, u16 value)
1677 {
1678 struct rtl838x_eth_priv *priv = bus->priv;
1679
1680 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1681 return rtl839x_write_sds_phy(mii_id, regnum, value);
1682
1683 return rtl839x_write_phy(mii_id, 0, regnum, value);
1684 }
1685
1686 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1687 int regnum, u16 value)
1688 {
1689 // struct rtl838x_eth_priv *priv = bus->priv;
1690
1691 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1692 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1693 if (regnum & MII_ADDR_C45) {
1694 regnum &= ~MII_ADDR_C45;
1695 return rtl930x_write_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, value);
1696 }
1697
1698 return rtl930x_write_phy(mii_id, 0, regnum, value);
1699 }
1700
1701 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1702 int regnum, u16 value)
1703 {
1704 // struct rtl838x_eth_priv *priv = bus->priv;
1705
1706 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1707 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1708
1709 return rtl931x_write_phy(mii_id, 0, regnum, value);
1710 }
1711
1712 static int rtl838x_mdio_reset(struct mii_bus *bus)
1713 {
1714 pr_debug("%s called\n", __func__);
1715 /* Disable MAC polling the PHY so that we can start configuration */
1716 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1717
1718 /* Enable PHY control via SoC */
1719 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1720
1721 // Probably should reset all PHYs here...
1722 return 0;
1723 }
1724
1725 static int rtl839x_mdio_reset(struct mii_bus *bus)
1726 {
1727 return 0;
1728
1729 pr_debug("%s called\n", __func__);
1730 /* BUG: The following does not work, but should! */
1731 /* Disable MAC polling the PHY so that we can start configuration */
1732 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1733 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1734 /* Disable PHY polling via SoC */
1735 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1736
1737 // Probably should reset all PHYs here...
1738 return 0;
1739 }
1740
1741 static int rtl930x_mdio_reset(struct mii_bus *bus)
1742 {
1743 int i;
1744 int pos;
1745 struct rtl838x_eth_priv *priv = bus->priv;
1746 u32 c45_mask = 0;
1747 u32 poll_sel[2];
1748 u32 poll_ctrl = 0;
1749
1750 // Mapping of port to phy-addresses on an SMI bus
1751 poll_sel[0] = poll_sel[1] = 0;
1752 for (i = 0; i < 28; i++) {
1753 pos = (i % 6) * 5;
1754 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1755 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1756
1757 pos = (i * 2) % 32;
1758 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1759 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1760 }
1761
1762 // Configure which SMI bus is behind which port number
1763 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1764 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1765
1766 // Enable polling on the respective SMI busses
1767 sw_w32_mask(0, poll_ctrl, RTL930X_SMI_GLB_CTRL);
1768
1769 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1770 for (i = 0; i < 4; i++)
1771 if (priv->smi_bus_isc45[i])
1772 c45_mask |= BIT(i + 16);
1773
1774 pr_info("c45_mask: %08x\n", c45_mask);
1775 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1776
1777 // Ports 24 to 27 are 2.5 or 10Gig, set this type (1) or (0) for internal SerDes
1778 for (i = 24; i < 28; i++) {
1779 pos = (i - 24) * 3 + 12;
1780 if (priv->phy_is_internal[i])
1781 sw_w32_mask(0x7 << pos, 0 << pos, RTL930X_SMI_MAC_TYPE_CTRL);
1782 else
1783 sw_w32_mask(0x7 << pos, 1 << pos, RTL930X_SMI_MAC_TYPE_CTRL);
1784 }
1785
1786 // TODO: Set up RTL9300_SMI_10GPHY_POLLING_SEL_0 for Aquantia PHYs on e.g. XGS 1250
1787
1788 return 0;
1789 }
1790
1791 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
1792 {
1793 struct device_node *mii_np, *dn;
1794 u32 pn;
1795 int ret;
1796
1797 pr_debug("%s called\n", __func__);
1798 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
1799
1800 if (!mii_np) {
1801 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
1802 return -ENODEV;
1803 }
1804
1805 if (!of_device_is_available(mii_np)) {
1806 ret = -ENODEV;
1807 goto err_put_node;
1808 }
1809
1810 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
1811 if (!priv->mii_bus) {
1812 ret = -ENOMEM;
1813 goto err_put_node;
1814 }
1815
1816 switch(priv->family_id) {
1817 case RTL8380_FAMILY_ID:
1818 priv->mii_bus->name = "rtl838x-eth-mdio";
1819 priv->mii_bus->read = rtl838x_mdio_read;
1820 priv->mii_bus->write = rtl838x_mdio_write;
1821 priv->mii_bus->reset = rtl838x_mdio_reset;
1822 break;
1823 case RTL8390_FAMILY_ID:
1824 priv->mii_bus->name = "rtl839x-eth-mdio";
1825 priv->mii_bus->read = rtl839x_mdio_read;
1826 priv->mii_bus->write = rtl839x_mdio_write;
1827 priv->mii_bus->reset = rtl839x_mdio_reset;
1828 break;
1829 case RTL9300_FAMILY_ID:
1830 priv->mii_bus->name = "rtl930x-eth-mdio";
1831 priv->mii_bus->read = rtl930x_mdio_read;
1832 priv->mii_bus->write = rtl930x_mdio_write;
1833 priv->mii_bus->reset = rtl930x_mdio_reset;
1834 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1835 break;
1836 case RTL9310_FAMILY_ID:
1837 priv->mii_bus->name = "rtl931x-eth-mdio";
1838 priv->mii_bus->read = rtl931x_mdio_read;
1839 priv->mii_bus->write = rtl931x_mdio_write;
1840 priv->mii_bus->reset = rtl931x_mdio_reset;
1841 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1842 break;
1843 }
1844 priv->mii_bus->priv = priv;
1845 priv->mii_bus->parent = &priv->pdev->dev;
1846
1847 for_each_node_by_name(dn, "ethernet-phy") {
1848 u32 smi_addr[2];
1849
1850 if (of_property_read_u32(dn, "reg", &pn))
1851 continue;
1852
1853 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
1854 smi_addr[0] = 0;
1855 smi_addr[1] = pn;
1856 }
1857
1858 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
1859 priv->sds_id[pn] = -1;
1860 else {
1861 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
1862 }
1863
1864 if (pn < MAX_PORTS) {
1865 priv->smi_bus[pn] = smi_addr[0];
1866 priv->smi_addr[pn] = smi_addr[1];
1867 } else {
1868 pr_err("%s: illegal port number %d\n", __func__, pn);
1869 }
1870
1871 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
1872 priv->smi_bus_isc45[smi_addr[0]] = true;
1873
1874 if (of_property_read_bool(dn, "phy-is-integrated")) {
1875 priv->phy_is_internal[pn] = true;
1876 }
1877
1878 }
1879
1880 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
1881 ret = of_mdiobus_register(priv->mii_bus, mii_np);
1882
1883 err_put_node:
1884 of_node_put(mii_np);
1885 return ret;
1886 }
1887
1888 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
1889 {
1890 pr_debug("%s called\n", __func__);
1891 if (!priv->mii_bus)
1892 return 0;
1893
1894 mdiobus_unregister(priv->mii_bus);
1895 mdiobus_free(priv->mii_bus);
1896
1897 return 0;
1898 }
1899
1900 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
1901 netdev_features_t features)
1902 {
1903 return features;
1904 }
1905
1906 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
1907 {
1908 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1909
1910 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
1911 if (!(features & NETIF_F_RXCSUM))
1912 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
1913 else
1914 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
1915 }
1916
1917 return 0;
1918 }
1919
1920 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
1921 {
1922 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1923
1924 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
1925 if (!(features & NETIF_F_RXCSUM))
1926 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
1927 else
1928 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
1929 }
1930
1931 return 0;
1932 }
1933
1934 static const struct net_device_ops rtl838x_eth_netdev_ops = {
1935 .ndo_open = rtl838x_eth_open,
1936 .ndo_stop = rtl838x_eth_stop,
1937 .ndo_start_xmit = rtl838x_eth_tx,
1938 .ndo_select_queue = rtl83xx_pick_tx_queue,
1939 .ndo_set_mac_address = rtl838x_set_mac_address,
1940 .ndo_validate_addr = eth_validate_addr,
1941 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
1942 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1943 .ndo_set_features = rtl83xx_set_features,
1944 .ndo_fix_features = rtl838x_fix_features,
1945 .ndo_setup_tc = rtl83xx_setup_tc,
1946 };
1947
1948 static const struct net_device_ops rtl839x_eth_netdev_ops = {
1949 .ndo_open = rtl838x_eth_open,
1950 .ndo_stop = rtl838x_eth_stop,
1951 .ndo_start_xmit = rtl838x_eth_tx,
1952 .ndo_select_queue = rtl83xx_pick_tx_queue,
1953 .ndo_set_mac_address = rtl838x_set_mac_address,
1954 .ndo_validate_addr = eth_validate_addr,
1955 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
1956 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1957 .ndo_set_features = rtl83xx_set_features,
1958 .ndo_fix_features = rtl838x_fix_features,
1959 .ndo_setup_tc = rtl83xx_setup_tc,
1960 };
1961
1962 static const struct net_device_ops rtl930x_eth_netdev_ops = {
1963 .ndo_open = rtl838x_eth_open,
1964 .ndo_stop = rtl838x_eth_stop,
1965 .ndo_start_xmit = rtl838x_eth_tx,
1966 .ndo_select_queue = rtl93xx_pick_tx_queue,
1967 .ndo_set_mac_address = rtl838x_set_mac_address,
1968 .ndo_validate_addr = eth_validate_addr,
1969 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
1970 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1971 .ndo_set_features = rtl93xx_set_features,
1972 .ndo_fix_features = rtl838x_fix_features,
1973 .ndo_setup_tc = rtl83xx_setup_tc,
1974 };
1975
1976 static const struct net_device_ops rtl931x_eth_netdev_ops = {
1977 .ndo_open = rtl838x_eth_open,
1978 .ndo_stop = rtl838x_eth_stop,
1979 .ndo_start_xmit = rtl838x_eth_tx,
1980 .ndo_select_queue = rtl93xx_pick_tx_queue,
1981 .ndo_set_mac_address = rtl838x_set_mac_address,
1982 .ndo_validate_addr = eth_validate_addr,
1983 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
1984 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1985 .ndo_set_features = rtl93xx_set_features,
1986 .ndo_fix_features = rtl838x_fix_features,
1987 };
1988
1989 static const struct phylink_mac_ops rtl838x_phylink_ops = {
1990 .validate = rtl838x_validate,
1991 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
1992 .mac_an_restart = rtl838x_mac_an_restart,
1993 .mac_config = rtl838x_mac_config,
1994 .mac_link_down = rtl838x_mac_link_down,
1995 .mac_link_up = rtl838x_mac_link_up,
1996 };
1997
1998 static const struct ethtool_ops rtl838x_ethtool_ops = {
1999 .get_link_ksettings = rtl838x_get_link_ksettings,
2000 .set_link_ksettings = rtl838x_set_link_ksettings,
2001 };
2002
2003 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2004 {
2005 struct net_device *dev;
2006 struct device_node *dn = pdev->dev.of_node;
2007 struct rtl838x_eth_priv *priv;
2008 struct resource *res, *mem;
2009 phy_interface_t phy_mode;
2010 struct phylink *phylink;
2011 int err = 0, i, rxrings, rxringlen;
2012 struct ring_b *ring;
2013
2014 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2015 (u32)pdev, (u32)(&(pdev->dev)));
2016
2017 if (!dn) {
2018 dev_err(&pdev->dev, "No DT found\n");
2019 return -EINVAL;
2020 }
2021
2022 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2023 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2024 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2025 rxringlen = MAX_ENTRIES / rxrings;
2026 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2027
2028 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2029 if (!dev) {
2030 err = -ENOMEM;
2031 goto err_free;
2032 }
2033 SET_NETDEV_DEV(dev, &pdev->dev);
2034 priv = netdev_priv(dev);
2035
2036 /* obtain buffer memory space */
2037 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2038 if (res) {
2039 mem = devm_request_mem_region(&pdev->dev, res->start,
2040 resource_size(res), res->name);
2041 if (!mem) {
2042 dev_err(&pdev->dev, "cannot request memory space\n");
2043 err = -ENXIO;
2044 goto err_free;
2045 }
2046
2047 dev->mem_start = mem->start;
2048 dev->mem_end = mem->end;
2049 } else {
2050 dev_err(&pdev->dev, "cannot request IO resource\n");
2051 err = -ENXIO;
2052 goto err_free;
2053 }
2054
2055 /* Allocate buffer memory */
2056 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2057 + sizeof(struct ring_b) + sizeof(struct notify_b),
2058 (void *)&dev->mem_start, GFP_KERNEL);
2059 if (!priv->membase) {
2060 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2061 err = -ENOMEM;
2062 goto err_free;
2063 }
2064
2065 // Allocate ring-buffer space at the end of the allocated memory
2066 ring = priv->membase;
2067 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2068
2069 spin_lock_init(&priv->lock);
2070
2071 /* obtain device IRQ number */
2072 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2073 if (!res) {
2074 dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n");
2075 dev->irq = 24;
2076 } else {
2077 dev->irq = res->start;
2078 }
2079 dev->ethtool_ops = &rtl838x_ethtool_ops;
2080 dev->min_mtu = ETH_ZLEN;
2081 dev->max_mtu = 1536;
2082 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2083 dev->hw_features = NETIF_F_RXCSUM;
2084
2085 priv->id = soc_info.id;
2086 priv->family_id = soc_info.family;
2087 if (priv->id) {
2088 pr_info("Found SoC ID: %4x: %s, family %x\n",
2089 priv->id, soc_info.name, priv->family_id);
2090 } else {
2091 pr_err("Unknown chip id (%04x)\n", priv->id);
2092 return -ENODEV;
2093 }
2094
2095 switch (priv->family_id) {
2096 case RTL8380_FAMILY_ID:
2097 priv->cpu_port = RTL838X_CPU_PORT;
2098 priv->r = &rtl838x_reg;
2099 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2100 break;
2101 case RTL8390_FAMILY_ID:
2102 priv->cpu_port = RTL839X_CPU_PORT;
2103 priv->r = &rtl839x_reg;
2104 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2105 break;
2106 case RTL9300_FAMILY_ID:
2107 priv->cpu_port = RTL930X_CPU_PORT;
2108 priv->r = &rtl930x_reg;
2109 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2110 break;
2111 case RTL9310_FAMILY_ID:
2112 priv->cpu_port = RTL931X_CPU_PORT;
2113 priv->r = &rtl931x_reg;
2114 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2115 break;
2116 default:
2117 pr_err("Unknown SoC family\n");
2118 return -ENODEV;
2119 }
2120 priv->rxringlen = rxringlen;
2121 priv->rxrings = rxrings;
2122
2123 rtl8380_init_mac(priv);
2124
2125 /* try to get mac address in the following order:
2126 * 1) from device tree data
2127 * 2) from internal registers set by bootloader
2128 */
2129 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2130 if (is_valid_ether_addr(dev->dev_addr)) {
2131 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2132 } else {
2133 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2134 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2135 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2136 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2137 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2138 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2139 }
2140 /* if the address is invalid, use a random value */
2141 if (!is_valid_ether_addr(dev->dev_addr)) {
2142 struct sockaddr sa = { AF_UNSPEC };
2143
2144 netdev_warn(dev, "Invalid MAC address, using random\n");
2145 eth_hw_addr_random(dev);
2146 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2147 if (rtl838x_set_mac_address(dev, &sa))
2148 netdev_warn(dev, "Failed to set MAC address.\n");
2149 }
2150 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2151 sw_r32(priv->r->mac + 4));
2152 strcpy(dev->name, "eth%d");
2153 priv->pdev = pdev;
2154 priv->netdev = dev;
2155
2156 err = rtl838x_mdio_init(priv);
2157 if (err)
2158 goto err_free;
2159
2160 err = register_netdev(dev);
2161 if (err)
2162 goto err_free;
2163
2164 for (i = 0; i < priv->rxrings; i++) {
2165 priv->rx_qs[i].id = i;
2166 priv->rx_qs[i].priv = priv;
2167 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2168 }
2169
2170 platform_set_drvdata(pdev, dev);
2171
2172 phy_mode = PHY_INTERFACE_MODE_NA;
2173 err = of_get_phy_mode(dn, &phy_mode);
2174 if (err < 0) {
2175 dev_err(&pdev->dev, "incorrect phy-mode\n");
2176 err = -EINVAL;
2177 goto err_free;
2178 }
2179 priv->phylink_config.dev = &dev->dev;
2180 priv->phylink_config.type = PHYLINK_NETDEV;
2181
2182 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2183 phy_mode, &rtl838x_phylink_ops);
2184 if (IS_ERR(phylink)) {
2185 err = PTR_ERR(phylink);
2186 goto err_free;
2187 }
2188 priv->phylink = phylink;
2189
2190 return 0;
2191
2192 err_free:
2193 pr_err("Error setting up netdev, freeing it again.\n");
2194 free_netdev(dev);
2195 return err;
2196 }
2197
2198 static int rtl838x_eth_remove(struct platform_device *pdev)
2199 {
2200 struct net_device *dev = platform_get_drvdata(pdev);
2201 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2202 int i;
2203
2204 if (dev) {
2205 pr_info("Removing platform driver for rtl838x-eth\n");
2206 rtl838x_mdio_remove(priv);
2207 rtl838x_hw_stop(priv);
2208
2209 netif_tx_stop_all_queues(dev);
2210
2211 for (i = 0; i < priv->rxrings; i++)
2212 netif_napi_del(&priv->rx_qs[i].napi);
2213
2214 unregister_netdev(dev);
2215 free_netdev(dev);
2216 }
2217 return 0;
2218 }
2219
2220 static const struct of_device_id rtl838x_eth_of_ids[] = {
2221 { .compatible = "realtek,rtl838x-eth"},
2222 { /* sentinel */ }
2223 };
2224 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2225
2226 static struct platform_driver rtl838x_eth_driver = {
2227 .probe = rtl838x_eth_probe,
2228 .remove = rtl838x_eth_remove,
2229 .driver = {
2230 .name = "rtl838x-eth",
2231 .pm = NULL,
2232 .of_match_table = rtl838x_eth_of_ids,
2233 },
2234 };
2235
2236 module_platform_driver(rtl838x_eth_driver);
2237
2238 MODULE_AUTHOR("B. Koblitz");
2239 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2240 MODULE_LICENSE("GPL");
Staging tree of Christian Lamparter