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realtek: fix locking issues
[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 uint16_t cpu_tag[10];
62 } __packed __aligned(1);
63
64 struct n_event {
65 uint32_t type:2;
66 uint32_t fidVid:12;
67 uint64_t mac:48;
68 uint32_t slp:6;
69 uint32_t valid:1;
70 uint32_t reserved:27;
71 } __packed __aligned(1);
72
73 struct ring_b {
74 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
75 uint32_t tx_r[TXRINGS][TXRINGLEN];
76 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
77 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
78 uint32_t c_rx[MAX_RXRINGS];
79 uint32_t c_tx[TXRINGS];
80 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
81 uint8_t *rx_space;
82 };
83
84 struct notify_block {
85 struct n_event events[NOTIFY_EVENTS];
86 };
87
88 struct notify_b {
89 struct notify_block blocks[NOTIFY_BLOCKS];
90 u32 reserved1[8];
91 u32 ring[NOTIFY_BLOCKS];
92 u32 reserved2[8];
93 };
94
95 static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
96 {
97 prio &= 0x7;
98
99 if (dest_port > 0) {
100 // cpu_tag[0] is reserved on the RTL83XX SoCs
101 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
102 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
103 h->cpu_tag[3] = 0x0000;
104 h->cpu_tag[4] = BIT(dest_port) >> 16;
105 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
106 // Set internal priority and AS_PRIO
107 if (prio >= 0)
108 h->cpu_tag[2] |= (prio | 0x8) << 12;
109 }
110 }
111
112 static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
113 {
114 prio &= 0x7;
115
116 if (dest_port > 0) {
117 // cpu_tag[0] is reserved on the RTL83XX SoCs
118 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
119 h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
120 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
121 if (dest_port >= 32) {
122 dest_port -= 32;
123 h->cpu_tag[2] = BIT(dest_port) >> 16;
124 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
125 } else {
126 h->cpu_tag[4] = BIT(dest_port) >> 16;
127 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
128 }
129 h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
130 h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
131 // Set internal priority and AS_PRIO
132 if (prio >= 0)
133 h->cpu_tag[1] |= prio | BIT(3);
134 }
135 }
136
137 static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
138 {
139 h->cpu_tag[0] = 0x8000; // CPU tag marker
140 h->cpu_tag[1] = h->cpu_tag[2] = 0;
141 if (prio >= 0)
142 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
143 h->cpu_tag[3] = 0;
144 h->cpu_tag[4] = 0;
145 h->cpu_tag[5] = 0;
146 h->cpu_tag[6] = BIT(dest_port) >> 16;
147 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
148 }
149
150 static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
151 {
152 h->cpu_tag[0] = 0x8000; // CPU tag marker
153 h->cpu_tag[1] = h->cpu_tag[2] = 0;
154 if (prio >= 0)
155 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
156 h->cpu_tag[3] = 0;
157 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
158 if (dest_port >= 32) {
159 dest_port -= 32;
160 h->cpu_tag[4] = BIT(dest_port) >> 16;
161 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
162 } else {
163 h->cpu_tag[6] = BIT(dest_port) >> 16;
164 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
165 }
166 }
167
168 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
169 {
170 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
171 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 h->cpu_tag[3] |= (vlan & 0xff) << 8;
173 }
174
175 struct rtl838x_rx_q {
176 int id;
177 struct rtl838x_eth_priv *priv;
178 struct napi_struct napi;
179 };
180
181 struct rtl838x_eth_priv {
182 struct net_device *netdev;
183 struct platform_device *pdev;
184 void *membase;
185 spinlock_t lock;
186 struct mii_bus *mii_bus;
187 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
188 struct phylink *phylink;
189 struct phylink_config phylink_config;
190 u16 id;
191 u16 family_id;
192 const struct rtl838x_eth_reg *r;
193 u8 cpu_port;
194 u32 lastEvent;
195 u16 rxrings;
196 u16 rxringlen;
197 u8 smi_bus[MAX_PORTS];
198 u8 smi_addr[MAX_PORTS];
199 u32 sds_id[MAX_PORTS];
200 bool smi_bus_isc45[MAX_SMI_BUSSES];
201 bool phy_is_internal[MAX_PORTS];
202 phy_interface_t interfaces[MAX_PORTS];
203 };
204
205 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
206 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
207 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
208 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
209 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
210 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
211 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
212 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
213 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
214 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
215 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
216 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
217
218 /*
219 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
220 * the rings. Writing x into these registers substracts x from its content.
221 * When the content reaches the ring size, the ASIC no longer adds
222 * packets to this receive queue.
223 */
224 void rtl838x_update_cntr(int r, int released)
225 {
226 // This feature is not available on RTL838x SoCs
227 }
228
229 void rtl839x_update_cntr(int r, int released)
230 {
231 // This feature is not available on RTL839x SoCs
232 }
233
234 void rtl930x_update_cntr(int r, int released)
235 {
236 int pos = (r % 3) * 10;
237 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
238 u32 v = sw_r32(reg);
239
240 v = (v >> pos) & 0x3ff;
241 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
242 sw_w32_mask(0x3ff << pos, released << pos, reg);
243 sw_w32(v, reg);
244 }
245
246 void rtl931x_update_cntr(int r, int released)
247 {
248 int pos = (r % 3) * 10;
249 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
250 u32 v = sw_r32(reg);
251
252 v = (v >> pos) & 0x3ff;
253 sw_w32_mask(0x3ff << pos, released << pos, reg);
254 sw_w32(v, reg);
255 }
256
257 struct dsa_tag {
258 u8 reason;
259 u8 queue;
260 u16 port;
261 u8 l2_offloaded;
262 u8 prio;
263 bool crc_error;
264 };
265
266 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
267 {
268 t->reason = h->cpu_tag[3] & 0xf;
269 t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
270 t->port = h->cpu_tag[1] & 0x1f;
271 t->crc_error = t->reason == 13;
272
273 pr_debug("Reason: %d\n", t->reason);
274 if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
275 t->l2_offloaded = 1;
276 else
277 t->l2_offloaded = 0;
278
279 return t->l2_offloaded;
280 }
281
282 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
283 {
284 t->reason = h->cpu_tag[5] & 0x1f;
285 t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
286 t->port = h->cpu_tag[1] & 0x3f;
287 t->crc_error = h->cpu_tag[3] & BIT(2);
288
289 pr_debug("Reason: %d\n", t->reason);
290 if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA
291 (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP
292 t->l2_offloaded = 0;
293 else
294 t->l2_offloaded = 1;
295
296 return t->l2_offloaded;
297 }
298
299 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
300 {
301 t->reason = h->cpu_tag[7] & 0x3f;
302 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
303 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
304 t->crc_error = h->cpu_tag[1] & BIT(6);
305
306 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
307 if (t->reason >= 19 && t->reason <= 27)
308 t->l2_offloaded = 0;
309 else
310 t->l2_offloaded = 1;
311
312 return t->l2_offloaded;
313 }
314
315 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
316 {
317 t->reason = h->cpu_tag[7] & 0x3f;
318 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
319 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
320 t->crc_error = h->cpu_tag[1] & BIT(6);
321
322 if (t->reason != 63)
323 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
324 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
325 t->l2_offloaded = 0;
326 else
327 t->l2_offloaded = 1;
328
329 return t->l2_offloaded;
330 }
331
332 /*
333 * Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
335 */
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
337 {
338 int r;
339 u32 *last;
340 struct p_hdr *h;
341 struct ring_b *ring = priv->membase;
342
343 for (r = 0; r < priv->rxrings; r++) {
344 pr_debug("In %s working on r: %d\n", __func__, r);
345 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
346 do {
347 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
348 break;
349 pr_debug("Got something: %d\n", ring->c_rx[r]);
350 h = &ring->rx_header[r][ring->c_rx[r]];
351 memset(h, 0, sizeof(struct p_hdr));
352 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
353 + r * priv->rxringlen * RING_BUFFER
354 + ring->c_rx[r] * RING_BUFFER);
355 h->size = RING_BUFFER;
356 /* make sure the header is visible to the ASIC */
357 mb();
358
359 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
360 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
361 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
362 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
363 }
364 }
365
366 struct fdb_update_work {
367 struct work_struct work;
368 struct net_device *ndev;
369 u64 macs[NOTIFY_EVENTS + 1];
370 };
371
372 void rtl838x_fdb_sync(struct work_struct *work)
373 {
374 const struct fdb_update_work *uw =
375 container_of(work, struct fdb_update_work, work);
376 struct switchdev_notifier_fdb_info info;
377 u8 addr[ETH_ALEN];
378 int i = 0;
379 int action;
380
381 while (uw->macs[i]) {
382 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
383 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
384 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
385 info.addr = &addr[0];
386 info.vid = 0;
387 info.offloaded = 1;
388 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
389 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
390 i++;
391 }
392 kfree(work);
393 }
394
395 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
396 {
397 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
398 u32 e = priv->lastEvent;
399 struct n_event *event;
400 int i;
401 u64 mac;
402 struct fdb_update_work *w;
403
404 while (!(nb->ring[e] & 1)) {
405 w = kzalloc(sizeof(*w), GFP_ATOMIC);
406 if (!w) {
407 pr_err("Out of memory: %s", __func__);
408 return;
409 }
410 INIT_WORK(&w->work, rtl838x_fdb_sync);
411
412 for (i = 0; i < NOTIFY_EVENTS; i++) {
413 event = &nb->blocks[e].events[i];
414 if (!event->valid)
415 continue;
416 mac = event->mac;
417 if (event->type)
418 mac |= 1ULL << 63;
419 w->ndev = priv->netdev;
420 w->macs[i] = mac;
421 }
422
423 /* Hand the ring entry back to the switch */
424 nb->ring[e] = nb->ring[e] | 1;
425 e = (e + 1) % NOTIFY_BLOCKS;
426
427 w->macs[i] = 0ULL;
428 schedule_work(&w->work);
429 }
430 priv->lastEvent = e;
431 }
432
433 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct rtl838x_eth_priv *priv = netdev_priv(dev);
437 u32 status = sw_r32(priv->r->dma_if_intr_sts);
438 int i;
439
440 pr_debug("IRQ: %08x\n", status);
441
442 /* Ignore TX interrupt */
443 if ((status & 0xf0000)) {
444 /* Clear ISR */
445 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
446 }
447
448 /* RX interrupt */
449 if (status & 0x0ff00) {
450 /* ACK and disable RX interrupt for this ring */
451 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
452 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
453 for (i = 0; i < priv->rxrings; i++) {
454 if (status & BIT(i + 8)) {
455 pr_debug("Scheduling queue: %d\n", i);
456 napi_schedule(&priv->rx_qs[i].napi);
457 }
458 }
459 }
460
461 /* RX buffer overrun */
462 if (status & 0x000ff) {
463 pr_debug("RX buffer overrun: status %x, mask: %x\n",
464 status, sw_r32(priv->r->dma_if_intr_msk));
465 sw_w32(status, priv->r->dma_if_intr_sts);
466 rtl838x_rb_cleanup(priv, status & 0xff);
467 }
468
469 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
470 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
471 rtl839x_l2_notification_handler(priv);
472 }
473
474 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
475 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
476 rtl839x_l2_notification_handler(priv);
477 }
478
479 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
480 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
481 rtl839x_l2_notification_handler(priv);
482 }
483
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
488 {
489 struct net_device *dev = dev_id;
490 struct rtl838x_eth_priv *priv = netdev_priv(dev);
491 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
492 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
493 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
494 int i;
495
496 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
497 __func__, status_tx, status_rx, status_rx_r);
498
499 /* Ignore TX interrupt */
500 if (status_tx) {
501 /* Clear ISR */
502 pr_debug("TX done\n");
503 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
504 }
505
506 /* RX interrupt */
507 if (status_rx) {
508 pr_debug("RX IRQ\n");
509 /* ACK and disable RX interrupt for given rings */
510 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
511 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
512 for (i = 0; i < priv->rxrings; i++) {
513 if (status_rx & BIT(i)) {
514 pr_debug("Scheduling queue: %d\n", i);
515 napi_schedule(&priv->rx_qs[i].napi);
516 }
517 }
518 }
519
520 /* RX buffer overrun */
521 if (status_rx_r) {
522 pr_debug("RX buffer overrun: status %x, mask: %x\n",
523 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
524 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
525 rtl838x_rb_cleanup(priv, status_rx_r);
526 }
527
528 return IRQ_HANDLED;
529 }
530
531 static const struct rtl838x_eth_reg rtl838x_reg = {
532 .net_irq = rtl83xx_net_irq,
533 .mac_port_ctrl = rtl838x_mac_port_ctrl,
534 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
535 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
536 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
537 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
538 .dma_rx_base = RTL838X_DMA_RX_BASE,
539 .dma_tx_base = RTL838X_DMA_TX_BASE,
540 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
541 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
542 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
543 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
544 .get_mac_link_sts = rtl838x_get_mac_link_sts,
545 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
546 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
547 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
548 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
549 .mac = RTL838X_MAC,
550 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
551 .update_cntr = rtl838x_update_cntr,
552 .create_tx_header = rtl838x_create_tx_header,
553 .decode_tag = rtl838x_decode_tag,
554 };
555
556 static const struct rtl838x_eth_reg rtl839x_reg = {
557 .net_irq = rtl83xx_net_irq,
558 .mac_port_ctrl = rtl839x_mac_port_ctrl,
559 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
560 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
561 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
562 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
563 .dma_rx_base = RTL839X_DMA_RX_BASE,
564 .dma_tx_base = RTL839X_DMA_TX_BASE,
565 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
566 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
567 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
568 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
569 .get_mac_link_sts = rtl839x_get_mac_link_sts,
570 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
571 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
572 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
573 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
574 .mac = RTL839X_MAC,
575 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
576 .update_cntr = rtl839x_update_cntr,
577 .create_tx_header = rtl839x_create_tx_header,
578 .decode_tag = rtl839x_decode_tag,
579 };
580
581 static const struct rtl838x_eth_reg rtl930x_reg = {
582 .net_irq = rtl93xx_net_irq,
583 .mac_port_ctrl = rtl930x_mac_port_ctrl,
584 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
585 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
586 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
587 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
588 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
589 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
590 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
591 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
592 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
593 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
594 .dma_rx_base = RTL930X_DMA_RX_BASE,
595 .dma_tx_base = RTL930X_DMA_TX_BASE,
596 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
597 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
598 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
599 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
600 .get_mac_link_sts = rtl930x_get_mac_link_sts,
601 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
602 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
603 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
604 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
605 .mac = RTL930X_MAC_L2_ADDR_CTRL,
606 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
607 .update_cntr = rtl930x_update_cntr,
608 .create_tx_header = rtl930x_create_tx_header,
609 .decode_tag = rtl930x_decode_tag,
610 };
611
612 static const struct rtl838x_eth_reg rtl931x_reg = {
613 .net_irq = rtl93xx_net_irq,
614 .mac_port_ctrl = rtl931x_mac_port_ctrl,
615 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
616 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
617 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
618 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
619 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
620 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
621 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
622 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
623 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
624 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
625 .dma_rx_base = RTL931X_DMA_RX_BASE,
626 .dma_tx_base = RTL931X_DMA_TX_BASE,
627 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
628 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
629 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
630 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
631 .get_mac_link_sts = rtl931x_get_mac_link_sts,
632 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
633 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
634 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
635 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
636 .mac = RTL931X_MAC_L2_ADDR_CTRL,
637 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
638 .update_cntr = rtl931x_update_cntr,
639 .create_tx_header = rtl931x_create_tx_header,
640 .decode_tag = rtl931x_decode_tag,
641 };
642
643 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
644 {
645 u32 int_saved, nbuf;
646 u32 reset_mask;
647 int i, pos;
648
649 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
650 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
651 mdelay(100);
652
653 /* Disable and clear interrupts */
654 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
655 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
656 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
657 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
658 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
659 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
660 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
661 } else {
662 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
663 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
664 }
665
666 if (priv->family_id == RTL8390_FAMILY_ID) {
667 /* Preserve L2 notification and NBUF settings */
668 int_saved = sw_r32(priv->r->dma_if_intr_msk);
669 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
670
671 /* Disable link change interrupt on RTL839x */
672 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
673 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
674
675 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
676 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
677 }
678
679 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
680 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
681 reset_mask = 0x6;
682 else
683 reset_mask = 0xc;
684
685 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
686
687 do { /* Wait for reset of NIC and Queues done */
688 udelay(20);
689 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
690 mdelay(100);
691
692 /* Setup Head of Line */
693 if (priv->family_id == RTL8380_FAMILY_ID)
694 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
695 if (priv->family_id == RTL8390_FAMILY_ID)
696 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
697 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
698 for (i = 0; i < priv->rxrings; i++) {
699 pos = (i % 3) * 10;
700 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
701 sw_w32_mask(0x3ff << pos, priv->rxringlen,
702 priv->r->dma_if_rx_ring_cntr(i));
703 }
704 }
705
706 /* Re-enable link change interrupt */
707 if (priv->family_id == RTL8390_FAMILY_ID) {
708 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
709 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
710 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
711 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
712
713 /* Restore notification settings: on RTL838x these bits are null */
714 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
715 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
716 }
717 }
718
719 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
720 {
721 int i;
722 struct ring_b *ring = priv->membase;
723
724 for (i = 0; i < priv->rxrings; i++)
725 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
726
727 for (i = 0; i < TXRINGS; i++)
728 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
729 }
730
731 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
732 {
733 /* Disable Head of Line features for all RX rings */
734 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
735
736 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
737 sw_w32(0x06400020, priv->r->dma_if_ctrl);
738
739 /* Enable RX done, RX overflow and TX done interrupts */
740 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
741
742 /* Enable DMA, engine expects empty FCS field */
743 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
744
745 /* Restart TX/RX to CPU port */
746 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
747 /* Set Speed, duplex, flow control
748 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
749 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
750 * | MEDIA_SEL
751 */
752 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
753
754 /* Enable CRC checks on CPU-port */
755 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
756 }
757
758 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
759 {
760 /* Setup CPU-Port: RX Buffer */
761 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
762
763 /* Enable Notify, RX done, RX overflow and TX done interrupts */
764 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
765
766 /* Enable DMA */
767 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
768
769 /* Restart TX/RX to CPU port, enable CRC checking */
770 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
771
772 /* CPU port joins Lookup Miss Flooding Portmask */
773 // TODO: The code below should also work for the RTL838x
774 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
775 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
776 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
777
778 /* Force CPU port link up */
779 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
780 }
781
782 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
783 {
784 int i, pos;
785 u32 v;
786
787 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
788 sw_w32(0x06400040, priv->r->dma_if_ctrl);
789
790 for (i = 0; i < priv->rxrings; i++) {
791 pos = (i % 3) * 10;
792 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
793
794 // Some SoCs have issues with missing underflow protection
795 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
796 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
797 }
798
799 /* Enable Notify, RX done, RX overflow and TX done interrupts */
800 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
801 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
802 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
803
804 /* Enable DMA */
805 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
806
807 /* Restart TX/RX to CPU port, enable CRC checking */
808 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
809
810 if (priv->family_id == RTL9300_FAMILY_ID)
811 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
812 else
813 sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
814
815 if (priv->family_id == RTL9300_FAMILY_ID)
816 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
817 else
818 sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
819 }
820
821 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
822 {
823 int i, j;
824
825 struct p_hdr *h;
826
827 for (i = 0; i < priv->rxrings; i++) {
828 for (j = 0; j < priv->rxringlen; j++) {
829 h = &ring->rx_header[i][j];
830 memset(h, 0, sizeof(struct p_hdr));
831 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
832 + i * priv->rxringlen * RING_BUFFER
833 + j * RING_BUFFER);
834 h->size = RING_BUFFER;
835 /* All rings owned by switch, last one wraps */
836 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
837 | (j == (priv->rxringlen - 1) ? WRAP : 0);
838 }
839 ring->c_rx[i] = 0;
840 }
841
842 for (i = 0; i < TXRINGS; i++) {
843 for (j = 0; j < TXRINGLEN; j++) {
844 h = &ring->tx_header[i][j];
845 memset(h, 0, sizeof(struct p_hdr));
846 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
847 + i * TXRINGLEN * RING_BUFFER
848 + j * RING_BUFFER);
849 h->size = RING_BUFFER;
850 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
851 }
852 /* Last header is wrapping around */
853 ring->tx_r[i][j-1] |= WRAP;
854 ring->c_tx[i] = 0;
855 }
856 }
857
858 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
859 {
860 int i;
861 struct notify_b *b = priv->membase + sizeof(struct ring_b);
862
863 for (i = 0; i < NOTIFY_BLOCKS; i++)
864 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
865
866 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
867 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
868
869 /* Setup notification events */
870 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
871 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
872
873 /* Enable Notification */
874 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
875 priv->lastEvent = 0;
876 }
877
878 static int rtl838x_eth_open(struct net_device *ndev)
879 {
880 unsigned long flags;
881 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
882 struct ring_b *ring = priv->membase;
883 int i;
884
885 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
886 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
887
888 spin_lock_irqsave(&priv->lock, flags);
889 rtl838x_hw_reset(priv);
890 rtl838x_setup_ring_buffer(priv, ring);
891 if (priv->family_id == RTL8390_FAMILY_ID) {
892 rtl839x_setup_notify_ring_buffer(priv);
893 /* Make sure the ring structure is visible to the ASIC */
894 mb();
895 flush_cache_all();
896 }
897
898 rtl838x_hw_ring_setup(priv);
899 phylink_start(priv->phylink);
900
901 for (i = 0; i < priv->rxrings; i++)
902 napi_enable(&priv->rx_qs[i].napi);
903
904 switch (priv->family_id) {
905 case RTL8380_FAMILY_ID:
906 rtl838x_hw_en_rxtx(priv);
907 /* Trap IGMP/MLD traffic to CPU-Port */
908 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
909 /* Flush learned FDB entries on link down of a port */
910 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
911 break;
912
913 case RTL8390_FAMILY_ID:
914 rtl839x_hw_en_rxtx(priv);
915 // Trap MLD and IGMP messages to CPU_PORT
916 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
917 /* Flush learned FDB entries on link down of a port */
918 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
919 break;
920
921 case RTL9300_FAMILY_ID:
922 rtl93xx_hw_en_rxtx(priv);
923 /* Flush learned FDB entries on link down of a port */
924 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
925 // Trap MLD and IGMP messages to CPU_PORT
926 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
927 break;
928
929 case RTL9310_FAMILY_ID:
930 rtl93xx_hw_en_rxtx(priv);
931
932 // Trap MLD and IGMP messages to CPU_PORT
933 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
934
935 // Disable External CPU access to switch, clear EXT_CPU_EN
936 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
937
938 // Set PCIE_PWR_DOWN
939 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
940 break;
941 }
942
943 netif_tx_start_all_queues(ndev);
944
945 spin_unlock_irqrestore(&priv->lock, flags);
946
947 return 0;
948 }
949
950 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
951 {
952 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
953 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
954 int i;
955
956 // Disable RX/TX from/to CPU-port
957 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
958
959 /* Disable traffic */
960 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
961 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
962 else
963 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
964 mdelay(200); // Test, whether this is needed
965
966 /* Block all ports */
967 if (priv->family_id == RTL8380_FAMILY_ID) {
968 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
969 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
970 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
971 }
972
973 /* Flush L2 address cache */
974 if (priv->family_id == RTL8380_FAMILY_ID) {
975 for (i = 0; i <= priv->cpu_port; i++) {
976 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
977 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
978 }
979 } else if (priv->family_id == RTL8390_FAMILY_ID) {
980 for (i = 0; i <= priv->cpu_port; i++) {
981 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
982 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
983 }
984 }
985 // TODO: L2 flush register is 64 bit on RTL931X and 930X
986
987 /* CPU-Port: Link down */
988 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
989 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
990 else if (priv->family_id == RTL9300_FAMILY_ID)
991 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
992 else if (priv->family_id == RTL9310_FAMILY_ID)
993 sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
994 mdelay(100);
995
996 /* Disable all TX/RX interrupts */
997 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
998 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
999 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
1000 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
1001 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
1002 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
1003 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
1004 } else {
1005 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
1006 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
1007 }
1008
1009 /* Disable TX/RX DMA */
1010 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1011 mdelay(200);
1012 }
1013
1014 static int rtl838x_eth_stop(struct net_device *ndev)
1015 {
1016 unsigned long flags;
1017 int i;
1018 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1019
1020 pr_info("in %s\n", __func__);
1021
1022 phylink_stop(priv->phylink);
1023 rtl838x_hw_stop(priv);
1024
1025 for (i = 0; i < priv->rxrings; i++)
1026 napi_disable(&priv->rx_qs[i].napi);
1027
1028 netif_tx_stop_all_queues(ndev);
1029
1030 return 0;
1031 }
1032
1033 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1034 {
1035 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1036 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1037 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1038 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1039 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1040 }
1041 if (ndev->flags & IFF_ALLMULTI) {
1042 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1043 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1044 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1045 }
1046 if (ndev->flags & IFF_PROMISC) {
1047 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1048 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1049 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1050 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1051 }
1052 }
1053
1054 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1055 {
1056 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1057
1058 if (priv->family_id == RTL8390_FAMILY_ID)
1059 return rtl839x_eth_set_multicast_list(ndev);
1060
1061 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1062 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1063 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1064 }
1065 if (ndev->flags & IFF_ALLMULTI)
1066 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1067 if (ndev->flags & IFF_PROMISC) {
1068 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1069 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1070 }
1071 }
1072
1073 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1074 {
1075 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1076 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1077 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1078 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1079 }
1080 if (ndev->flags & IFF_ALLMULTI) {
1081 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1082 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1083 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1084 }
1085 if (ndev->flags & IFF_PROMISC) {
1086 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1087 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1088 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1089 }
1090 }
1091
1092 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1093 {
1094 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1095 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1096 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1097 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1098 }
1099 if (ndev->flags & IFF_ALLMULTI) {
1100 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1101 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1102 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1103 }
1104 if (ndev->flags & IFF_PROMISC) {
1105 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1106 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1107 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1108 }
1109 }
1110
1111 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1112 {
1113 unsigned long flags;
1114 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1115
1116 pr_warn("%s\n", __func__);
1117 spin_lock_irqsave(&priv->lock, flags);
1118 rtl838x_hw_stop(priv);
1119 rtl838x_hw_ring_setup(priv);
1120 rtl838x_hw_en_rxtx(priv);
1121 netif_trans_update(ndev);
1122 netif_start_queue(ndev);
1123 spin_unlock_irqrestore(&priv->lock, flags);
1124 }
1125
1126 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1127 {
1128 int len, i;
1129 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1130 struct ring_b *ring = priv->membase;
1131 uint32_t val;
1132 int ret;
1133 unsigned long flags;
1134 struct p_hdr *h;
1135 int dest_port = -1;
1136 int q = skb_get_queue_mapping(skb) % TXRINGS;
1137
1138 if (q) // Check for high prio queue
1139 pr_debug("SKB priority: %d\n", skb->priority);
1140
1141 spin_lock_irqsave(&priv->lock, flags);
1142 len = skb->len;
1143
1144 /* Check for DSA tagging at the end of the buffer */
1145 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
1146 && skb->data[len-3] < priv->cpu_port && skb->data[len-2] == 0x10
1147 && skb->data[len-1] == 0x00) {
1148 /* Reuse tag space for CRC if possible */
1149 dest_port = skb->data[len-3];
1150 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1151 len -= 4;
1152 }
1153
1154 len += 4; // Add space for CRC
1155
1156 if (skb_padto(skb, len)) {
1157 ret = NETDEV_TX_OK;
1158 goto txdone;
1159 }
1160
1161 /* We can send this packet if CPU owns the descriptor */
1162 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1163
1164 /* Set descriptor for tx */
1165 h = &ring->tx_header[q][ring->c_tx[q]];
1166 h->size = len;
1167 h->len = len;
1168 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1169 if (priv->family_id == RTL8380_FAMILY_ID) {
1170 if (len < ETH_ZLEN - 4)
1171 h->len -= 4;
1172 }
1173
1174 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1175
1176 /* Copy packet data to tx buffer */
1177 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1178 /* Make sure packet data is visible to ASIC */
1179 wmb();
1180
1181 /* Hand over to switch */
1182 ring->tx_r[q][ring->c_tx[q]] |= 1;
1183
1184 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1185 if (priv->family_id == RTL8380_FAMILY_ID) {
1186 for (i = 0; i < 10; i++) {
1187 val = sw_r32(priv->r->dma_if_ctrl);
1188 if ((val & 0xc) == 0xc)
1189 break;
1190 }
1191 }
1192
1193 /* Tell switch to send data */
1194 if (priv->family_id == RTL9310_FAMILY_ID
1195 || priv->family_id == RTL9300_FAMILY_ID) {
1196 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1197 if (!q)
1198 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1199 else
1200 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1201 } else {
1202 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1203 }
1204
1205 dev->stats.tx_packets++;
1206 dev->stats.tx_bytes += len;
1207 dev_kfree_skb(skb);
1208 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1209 ret = NETDEV_TX_OK;
1210 } else {
1211 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1212 ret = NETDEV_TX_BUSY;
1213 }
1214 txdone:
1215 spin_unlock_irqrestore(&priv->lock, flags);
1216 return ret;
1217 }
1218
1219 /*
1220 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1221 * so we do round-robin
1222 */
1223 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1224 struct net_device *sb_dev)
1225 {
1226 static u8 last = 0;
1227
1228 last++;
1229 return last % TXRINGS;
1230 }
1231
1232 /*
1233 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1234 */
1235 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1236 struct net_device *sb_dev)
1237 {
1238 if (skb->priority >= TC_PRIO_CONTROL)
1239 return 1;
1240 return 0;
1241 }
1242
1243 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1244 {
1245 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1246 struct ring_b *ring = priv->membase;
1247 struct sk_buff *skb;
1248 unsigned long flags;
1249 int i, len, work_done = 0;
1250 u8 *data, *skb_data;
1251 unsigned int val;
1252 u32 *last;
1253 struct p_hdr *h;
1254 bool dsa = netdev_uses_dsa(dev);
1255 struct dsa_tag tag;
1256
1257 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1258 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1259
1260 do {
1261 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1262 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1263 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1264 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1265 }
1266 break;
1267 }
1268
1269 h = &ring->rx_header[r][ring->c_rx[r]];
1270 data = (u8 *)KSEG1ADDR(h->buf);
1271 len = h->len;
1272 if (!len)
1273 break;
1274 work_done++;
1275
1276 len -= 4; /* strip the CRC */
1277 /* Add 4 bytes for cpu_tag */
1278 if (dsa)
1279 len += 4;
1280
1281 skb = netdev_alloc_skb(dev, len + 4);
1282 skb_reserve(skb, NET_IP_ALIGN);
1283
1284 if (likely(skb)) {
1285 /* BUG: Prevent bug on RTL838x SoCs*/
1286 if (priv->family_id == RTL8380_FAMILY_ID) {
1287 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1288 for (i = 0; i < priv->rxrings; i++) {
1289 /* Update each ring cnt */
1290 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1291 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1292 }
1293 }
1294
1295 skb_data = skb_put(skb, len);
1296 /* Make sure data is visible */
1297 mb();
1298 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1299 /* Overwrite CRC with cpu_tag */
1300 if (dsa) {
1301 priv->r->decode_tag(h, &tag);
1302 skb->data[len-4] = 0x80;
1303 skb->data[len-3] = tag.port;
1304 skb->data[len-2] = 0x10;
1305 skb->data[len-1] = 0x00;
1306 if (tag.l2_offloaded)
1307 skb->data[len-3] |= 0x40;
1308 }
1309
1310 if (tag.queue >= 0)
1311 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1312 tag.queue, len, tag.reason, tag.port);
1313
1314 skb->protocol = eth_type_trans(skb, dev);
1315 if (dev->features & NETIF_F_RXCSUM) {
1316 if (tag.crc_error)
1317 skb_checksum_none_assert(skb);
1318 else
1319 skb->ip_summed = CHECKSUM_UNNECESSARY;
1320 }
1321 dev->stats.rx_packets++;
1322 dev->stats.rx_bytes += len;
1323
1324 netif_receive_skb(skb);
1325 } else {
1326 if (net_ratelimit())
1327 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1328 dev->stats.rx_dropped++;
1329 }
1330
1331 /* Reset header structure */
1332 spin_lock_irqsave(&priv->lock, flags);
1333 memset(h, 0, sizeof(struct p_hdr));
1334 h->buf = data;
1335 h->size = RING_BUFFER;
1336
1337 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1338 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1339 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1340 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1341 spin_unlock_irqrestore(&priv->lock, flags);
1342 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1343
1344 // Update counters
1345 priv->r->update_cntr(r, 0);
1346
1347 return work_done;
1348 }
1349
1350 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1351 {
1352 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1353 struct rtl838x_eth_priv *priv = rx_q->priv;
1354 int work_done = 0;
1355 int r = rx_q->id;
1356 int work;
1357
1358 while (work_done < budget) {
1359 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1360 if (!work)
1361 break;
1362 work_done += work;
1363 }
1364
1365 if (work_done < budget) {
1366 napi_complete_done(napi, work_done);
1367
1368 /* Enable RX interrupt */
1369 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1370 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1371 else
1372 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1373 }
1374 return work_done;
1375 }
1376
1377
1378 static void rtl838x_validate(struct phylink_config *config,
1379 unsigned long *supported,
1380 struct phylink_link_state *state)
1381 {
1382 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1383
1384 pr_debug("In %s\n", __func__);
1385
1386 if (!phy_interface_mode_is_rgmii(state->interface) &&
1387 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1388 state->interface != PHY_INTERFACE_MODE_MII &&
1389 state->interface != PHY_INTERFACE_MODE_REVMII &&
1390 state->interface != PHY_INTERFACE_MODE_GMII &&
1391 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1392 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1393 state->interface != PHY_INTERFACE_MODE_SGMII) {
1394 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1395 pr_err("Unsupported interface: %d\n", state->interface);
1396 return;
1397 }
1398
1399 /* Allow all the expected bits */
1400 phylink_set(mask, Autoneg);
1401 phylink_set_port_modes(mask);
1402 phylink_set(mask, Pause);
1403 phylink_set(mask, Asym_Pause);
1404
1405 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1406 * including Half duplex
1407 */
1408 if (state->interface != PHY_INTERFACE_MODE_MII &&
1409 state->interface != PHY_INTERFACE_MODE_REVMII) {
1410 phylink_set(mask, 1000baseT_Full);
1411 phylink_set(mask, 1000baseT_Half);
1412 }
1413
1414 phylink_set(mask, 10baseT_Half);
1415 phylink_set(mask, 10baseT_Full);
1416 phylink_set(mask, 100baseT_Half);
1417 phylink_set(mask, 100baseT_Full);
1418
1419 bitmap_and(supported, supported, mask,
1420 __ETHTOOL_LINK_MODE_MASK_NBITS);
1421 bitmap_and(state->advertising, state->advertising, mask,
1422 __ETHTOOL_LINK_MODE_MASK_NBITS);
1423 }
1424
1425
1426 static void rtl838x_mac_config(struct phylink_config *config,
1427 unsigned int mode,
1428 const struct phylink_link_state *state)
1429 {
1430 /* This is only being called for the master device,
1431 * i.e. the CPU-Port. We don't need to do anything.
1432 */
1433
1434 pr_info("In %s, mode %x\n", __func__, mode);
1435 }
1436
1437 static void rtl838x_mac_an_restart(struct phylink_config *config)
1438 {
1439 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1440 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1441
1442 /* This works only on RTL838x chips */
1443 if (priv->family_id != RTL8380_FAMILY_ID)
1444 return;
1445
1446 pr_debug("In %s\n", __func__);
1447 /* Restart by disabling and re-enabling link */
1448 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1449 mdelay(20);
1450 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1451 }
1452
1453 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1454 struct phylink_link_state *state)
1455 {
1456 u32 speed;
1457 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1458 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1459 int port = priv->cpu_port;
1460
1461 pr_info("In %s\n", __func__);
1462
1463 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1464 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1465
1466 pr_info("%s link status is %d\n", __func__, state->link);
1467 speed = priv->r->get_mac_link_spd_sts(port);
1468 switch (speed) {
1469 case 0:
1470 state->speed = SPEED_10;
1471 break;
1472 case 1:
1473 state->speed = SPEED_100;
1474 break;
1475 case 2:
1476 state->speed = SPEED_1000;
1477 break;
1478 case 5:
1479 state->speed = SPEED_2500;
1480 break;
1481 case 6:
1482 state->speed = SPEED_5000;
1483 break;
1484 case 4:
1485 state->speed = SPEED_10000;
1486 break;
1487 default:
1488 state->speed = SPEED_UNKNOWN;
1489 break;
1490 }
1491
1492 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1493 if (priv->r->get_mac_rx_pause_sts(port))
1494 state->pause |= MLO_PAUSE_RX;
1495 if (priv->r->get_mac_tx_pause_sts(port))
1496 state->pause |= MLO_PAUSE_TX;
1497 }
1498
1499 static void rtl838x_mac_link_down(struct phylink_config *config,
1500 unsigned int mode,
1501 phy_interface_t interface)
1502 {
1503 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1504 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1505
1506 pr_debug("In %s\n", __func__);
1507 /* Stop TX/RX to port */
1508 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1509 }
1510
1511 static void rtl838x_mac_link_up(struct phylink_config *config,
1512 struct phy_device *phy, unsigned int mode,
1513 phy_interface_t interface, int speed, int duplex,
1514 bool tx_pause, bool rx_pause)
1515 {
1516 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1517 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1518
1519 pr_debug("In %s\n", __func__);
1520 /* Restart TX/RX to port */
1521 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1522 }
1523
1524 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1525 {
1526 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1527 unsigned long flags;
1528
1529 spin_lock_irqsave(&priv->lock, flags);
1530 pr_debug("In %s\n", __func__);
1531 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1532 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1533
1534 if (priv->family_id == RTL8380_FAMILY_ID) {
1535 /* 2 more registers, ALE/MAC block */
1536 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1537 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1538 (RTL838X_MAC_ALE + 4));
1539
1540 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1541 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1542 RTL838X_MAC2 + 4);
1543 }
1544 spin_unlock_irqrestore(&priv->lock, flags);
1545 }
1546
1547 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1548 {
1549 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1550 const struct sockaddr *addr = p;
1551 u8 *mac = (u8 *) (addr->sa_data);
1552
1553 if (!is_valid_ether_addr(addr->sa_data))
1554 return -EADDRNOTAVAIL;
1555
1556 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1557 rtl838x_set_mac_hw(dev, mac);
1558
1559 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1560 return 0;
1561 }
1562
1563 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1564 {
1565 // We will need to set-up EEE and the egress-rate limitation
1566 return 0;
1567 }
1568
1569 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1570 {
1571 int i;
1572
1573 if (priv->family_id == 0x8390)
1574 return rtl8390_init_mac(priv);
1575
1576 // At present we do not know how to set up EEE on any other SoC than RTL8380
1577 if (priv->family_id != 0x8380)
1578 return 0;
1579
1580 pr_info("%s\n", __func__);
1581 /* fix timer for EEE */
1582 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1583 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1584
1585 /* Init VLAN. TODO: Understand what is being done, here */
1586 if (priv->id == 0x8382) {
1587 for (i = 0; i <= 28; i++)
1588 sw_w32(0, 0xd57c + i * 0x80);
1589 }
1590 if (priv->id == 0x8380) {
1591 for (i = 8; i <= 28; i++)
1592 sw_w32(0, 0xd57c + i * 0x80);
1593 }
1594 return 0;
1595 }
1596
1597 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1598 struct ethtool_link_ksettings *cmd)
1599 {
1600 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1601
1602 pr_debug("%s called\n", __func__);
1603 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1604 }
1605
1606 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1607 const struct ethtool_link_ksettings *cmd)
1608 {
1609 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1610
1611 pr_debug("%s called\n", __func__);
1612 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1613 }
1614
1615 static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1616 {
1617 u32 val;
1618 int err;
1619 struct rtl838x_eth_priv *priv = bus->priv;
1620
1621 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1622 return rtl838x_read_sds_phy(mii_id, regnum);
1623
1624 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1625 err = rtl838x_read_mmd_phy(mii_id,
1626 mdiobus_c45_devad(regnum),
1627 regnum, &val);
1628 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1629 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1630 val, err);
1631 } else {
1632 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1633 err = rtl838x_read_phy(mii_id, page, regnum, &val);
1634 }
1635 if (err)
1636 return err;
1637 return val;
1638 }
1639
1640 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1641 {
1642 return rtl838x_mdio_read_paged(bus, mii_id, 0, regnum);
1643 }
1644
1645 static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1646 {
1647 u32 val;
1648 int err;
1649 struct rtl838x_eth_priv *priv = bus->priv;
1650
1651 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1652 return rtl839x_read_sds_phy(mii_id, regnum);
1653
1654 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1655 err = rtl839x_read_mmd_phy(mii_id,
1656 mdiobus_c45_devad(regnum),
1657 regnum, &val);
1658 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1659 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1660 val, err);
1661 } else {
1662 err = rtl839x_read_phy(mii_id, page, regnum, &val);
1663 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1664 }
1665 if (err)
1666 return err;
1667 return val;
1668 }
1669
1670 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1671 {
1672 return rtl839x_mdio_read_paged(bus, mii_id, 0, regnum);
1673 }
1674
1675 static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1676 {
1677 u32 val;
1678 int err;
1679 struct rtl838x_eth_priv *priv = bus->priv;
1680
1681 if (priv->phy_is_internal[mii_id])
1682 return rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1683
1684 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1685 err = rtl930x_read_mmd_phy(mii_id,
1686 mdiobus_c45_devad(regnum),
1687 regnum, &val);
1688 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1689 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1690 val, err);
1691 } else {
1692 err = rtl930x_read_phy(mii_id, page, regnum, &val);
1693 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1694 }
1695 if (err)
1696 return err;
1697 return val;
1698 }
1699
1700 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1701 {
1702 return rtl930x_mdio_read_paged(bus, mii_id, 0, regnum);
1703 }
1704
1705 static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1706 {
1707 u32 val;
1708 int err, v;
1709 struct rtl838x_eth_priv *priv = bus->priv;
1710
1711 pr_debug("%s: In here, port %d\n", __func__, mii_id);
1712 if (priv->phy_is_internal[mii_id]) {
1713 v = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1714 if (v < 0) {
1715 err = v;
1716 } else {
1717 err = 0;
1718 val = v;
1719 }
1720 } else {
1721 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1722 err = rtl931x_read_mmd_phy(mii_id,
1723 mdiobus_c45_devad(regnum),
1724 regnum, &val);
1725 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1726 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1727 val, err);
1728 } else {
1729 err = rtl931x_read_phy(mii_id, page, regnum, &val);
1730 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1731 }
1732 }
1733
1734 if (err)
1735 return err;
1736 return val;
1737 }
1738
1739 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1740 {
1741 return rtl931x_mdio_read_paged(bus, mii_id, 0, regnum);
1742 }
1743
1744 static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1745 int regnum, u16 value)
1746 {
1747 u32 offset = 0;
1748 struct rtl838x_eth_priv *priv = bus->priv;
1749 int err;
1750
1751 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1752 if (mii_id == 26)
1753 offset = 0x100;
1754 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1755 return 0;
1756 }
1757
1758 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1759 err = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1760 regnum, value);
1761 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1762 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1763 value, err);
1764
1765 return err;
1766 }
1767 err = rtl838x_write_phy(mii_id, page, regnum, value);
1768 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1769 return err;
1770 }
1771
1772 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1773 int regnum, u16 value)
1774 {
1775 return rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1776 }
1777
1778 static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1779 int regnum, u16 value)
1780 {
1781 struct rtl838x_eth_priv *priv = bus->priv;
1782 int err;
1783
1784 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1785 return rtl839x_write_sds_phy(mii_id, regnum, value);
1786
1787 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1788 err = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1789 regnum, value);
1790 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1791 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1792 value, err);
1793
1794 return err;
1795 }
1796
1797 err = rtl839x_write_phy(mii_id, page, regnum, value);
1798 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1799 return err;
1800 }
1801
1802 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1803 int regnum, u16 value)
1804 {
1805 return rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1806 }
1807
1808 static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1809 int regnum, u16 value)
1810 {
1811 struct rtl838x_eth_priv *priv = bus->priv;
1812 int err;
1813
1814 if (priv->phy_is_internal[mii_id])
1815 return rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1816
1817 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD))
1818 return rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1819 regnum, value);
1820
1821 err = rtl930x_write_phy(mii_id, page, regnum, value);
1822 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1823 return err;
1824 }
1825
1826 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1827 int regnum, u16 value)
1828 {
1829 return rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1830 }
1831
1832 static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1833 int regnum, u16 value)
1834 {
1835 struct rtl838x_eth_priv *priv = bus->priv;
1836 int err;
1837
1838 if (priv->phy_is_internal[mii_id])
1839 return rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1840
1841 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1842 err = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1843 regnum, value);
1844 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1845 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1846 value, err);
1847
1848 return err;
1849 }
1850
1851 err = rtl931x_write_phy(mii_id, page, regnum, value);
1852 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1853 return err;
1854 }
1855
1856 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1857 int regnum, u16 value)
1858 {
1859 return rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1860 }
1861
1862 static int rtl838x_mdio_reset(struct mii_bus *bus)
1863 {
1864 pr_debug("%s called\n", __func__);
1865 /* Disable MAC polling the PHY so that we can start configuration */
1866 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1867
1868 /* Enable PHY control via SoC */
1869 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1870
1871 // Probably should reset all PHYs here...
1872 return 0;
1873 }
1874
1875 static int rtl839x_mdio_reset(struct mii_bus *bus)
1876 {
1877 return 0;
1878
1879 pr_debug("%s called\n", __func__);
1880 /* BUG: The following does not work, but should! */
1881 /* Disable MAC polling the PHY so that we can start configuration */
1882 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1883 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1884 /* Disable PHY polling via SoC */
1885 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1886
1887 // Probably should reset all PHYs here...
1888 return 0;
1889 }
1890
1891 u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1892 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1893
1894 static int rtl930x_mdio_reset(struct mii_bus *bus)
1895 {
1896 int i;
1897 int pos;
1898 struct rtl838x_eth_priv *priv = bus->priv;
1899 u32 c45_mask = 0;
1900 u32 poll_sel[2];
1901 u32 poll_ctrl = 0;
1902 u32 private_poll_mask = 0;
1903 u32 v;
1904 bool uses_usxgmii = false; // For the Aquantia PHYs
1905 bool uses_hisgmii = false; // For the RTL8221/8226
1906
1907 // Mapping of port to phy-addresses on an SMI bus
1908 poll_sel[0] = poll_sel[1] = 0;
1909 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1910 if (priv->smi_bus[i] > 3)
1911 continue;
1912 pos = (i % 6) * 5;
1913 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1914 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1915
1916 pos = (i * 2) % 32;
1917 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1918 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1919 }
1920
1921 // Configure which SMI bus is behind which port number
1922 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1923 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1924
1925 // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+)
1926 sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
1927
1928 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1929 for (i = 0; i < 4; i++)
1930 if (priv->smi_bus_isc45[i])
1931 c45_mask |= BIT(i + 16);
1932
1933 pr_info("c45_mask: %08x\n", c45_mask);
1934 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1935
1936 // Set the MAC type of each port according to the PHY-interface
1937 // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0
1938 v = 0;
1939 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1940 switch (priv->interfaces[i]) {
1941 case PHY_INTERFACE_MODE_10GBASER:
1942 break; // Serdes: Value = 0
1943
1944 case PHY_INTERFACE_MODE_HSGMII:
1945 private_poll_mask |= BIT(i);
1946 // fallthrough
1947 case PHY_INTERFACE_MODE_USXGMII:
1948 v |= BIT(mac_type_bit[i]);
1949 uses_usxgmii = true;
1950 break;
1951
1952 case PHY_INTERFACE_MODE_QSGMII:
1953 private_poll_mask |= BIT(i);
1954 v |= 3 << mac_type_bit[i];
1955 break;
1956
1957 default:
1958 break;
1959 }
1960 }
1961 sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);
1962
1963 // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones)
1964 sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);
1965
1966 /* The following magic values are found in the port configuration, they seem to
1967 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1968 * the XGS1250 and the RTL8226 of the XGS1210 */
1969 if (uses_usxgmii) {
1970 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1971 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1972 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1973 }
1974 if (uses_hisgmii) {
1975 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1976 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1977 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1978 }
1979
1980 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__,
1981 sw_r32(RTL930X_SMI_GLB_CTRL));
1982 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__,
1983 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));
1984 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__,
1985 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
1986 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__,
1987 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));
1988 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__,
1989 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));
1990 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__,
1991 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));
1992 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__,
1993 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));
1994 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__,
1995 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));
1996 return 0;
1997 }
1998
1999 static int rtl931x_mdio_reset(struct mii_bus *bus)
2000 {
2001 int i;
2002 int pos;
2003 struct rtl838x_eth_priv *priv = bus->priv;
2004 u32 c45_mask = 0;
2005 u32 poll_sel[4];
2006 u32 poll_ctrl = 0;
2007 bool mdc_on[4];
2008
2009 pr_info("%s called\n", __func__);
2010 // Disable port polling for configuration purposes
2011 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
2012 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
2013 msleep(100);
2014
2015 mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
2016 // Mapping of port to phy-addresses on an SMI bus
2017 poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
2018 for (i = 0; i < 56; i++) {
2019 pos = (i % 6) * 5;
2020 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
2021 pos = (i * 2) % 32;
2022 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
2023 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
2024 mdc_on[priv->smi_bus[i]] = true;
2025 }
2026
2027 // Configure which SMI bus is behind which port number
2028 for (i = 0; i < 4; i++) {
2029 pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
2030 sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
2031 }
2032
2033 // Configure which SMI busses
2034 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2035 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2036 for (i = 0; i < 4; i++) {
2037 // bus is polled in c45
2038 if (priv->smi_bus_isc45[i])
2039 c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3
2040 // Enable bus access via MDC
2041 if (mdc_on[i])
2042 sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
2043 }
2044
2045 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2046 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2047
2048 /* We have a 10G PHY enable polling
2049 sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
2050 sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
2051 sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
2052 */
2053 sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
2054
2055 return 0;
2056 }
2057
2058 static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
2059 {
2060 pr_info("In %s\n", __func__);
2061
2062 // Initialize Encapsulation memory and wait until finished
2063 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
2064 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
2065 pr_info("%s: init ENCAP done\n", __func__);
2066
2067 // Initialize Managemen Information Base memory and wait until finished
2068 sw_w32(0x1, RTL931X_MEM_MIB_INIT);
2069 do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
2070 pr_info("%s: init MIB done\n", __func__);
2071
2072 // Initialize ACL (PIE) memory and wait until finished
2073 sw_w32(0x1, RTL931X_MEM_ACL_INIT);
2074 do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
2075 pr_info("%s: init ACL done\n", __func__);
2076
2077 // Initialize ALE memory and wait until finished
2078 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
2079 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
2080 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
2081 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
2082 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
2083 pr_info("%s: init ALE done\n", __func__);
2084
2085 // Enable ESD auto recovery
2086 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
2087
2088 // Init SPI, is this for thermal control or what?
2089 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
2090
2091 return 0;
2092 }
2093
2094 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
2095 {
2096 struct device_node *mii_np, *dn;
2097 u32 pn;
2098 int ret;
2099
2100 pr_debug("%s called\n", __func__);
2101 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
2102
2103 if (!mii_np) {
2104 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
2105 return -ENODEV;
2106 }
2107
2108 if (!of_device_is_available(mii_np)) {
2109 ret = -ENODEV;
2110 goto err_put_node;
2111 }
2112
2113 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
2114 if (!priv->mii_bus) {
2115 ret = -ENOMEM;
2116 goto err_put_node;
2117 }
2118
2119 switch(priv->family_id) {
2120 case RTL8380_FAMILY_ID:
2121 priv->mii_bus->name = "rtl838x-eth-mdio";
2122 priv->mii_bus->read = rtl838x_mdio_read;
2123 priv->mii_bus->read_paged = rtl838x_mdio_read_paged;
2124 priv->mii_bus->write = rtl838x_mdio_write;
2125 priv->mii_bus->write_paged = rtl838x_mdio_write_paged;
2126 priv->mii_bus->reset = rtl838x_mdio_reset;
2127 break;
2128 case RTL8390_FAMILY_ID:
2129 priv->mii_bus->name = "rtl839x-eth-mdio";
2130 priv->mii_bus->read = rtl839x_mdio_read;
2131 priv->mii_bus->read_paged = rtl839x_mdio_read_paged;
2132 priv->mii_bus->write = rtl839x_mdio_write;
2133 priv->mii_bus->write_paged = rtl839x_mdio_write_paged;
2134 priv->mii_bus->reset = rtl839x_mdio_reset;
2135 break;
2136 case RTL9300_FAMILY_ID:
2137 priv->mii_bus->name = "rtl930x-eth-mdio";
2138 priv->mii_bus->read = rtl930x_mdio_read;
2139 priv->mii_bus->read_paged = rtl930x_mdio_read_paged;
2140 priv->mii_bus->write = rtl930x_mdio_write;
2141 priv->mii_bus->write_paged = rtl930x_mdio_write_paged;
2142 priv->mii_bus->reset = rtl930x_mdio_reset;
2143 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2144 break;
2145 case RTL9310_FAMILY_ID:
2146 priv->mii_bus->name = "rtl931x-eth-mdio";
2147 priv->mii_bus->read = rtl931x_mdio_read;
2148 priv->mii_bus->read_paged = rtl931x_mdio_read_paged;
2149 priv->mii_bus->write = rtl931x_mdio_write;
2150 priv->mii_bus->write_paged = rtl931x_mdio_write_paged;
2151 priv->mii_bus->reset = rtl931x_mdio_reset;
2152 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2153 break;
2154 }
2155 priv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD;
2156 priv->mii_bus->priv = priv;
2157 priv->mii_bus->parent = &priv->pdev->dev;
2158
2159 for_each_node_by_name(dn, "ethernet-phy") {
2160 u32 smi_addr[2];
2161
2162 if (of_property_read_u32(dn, "reg", &pn))
2163 continue;
2164
2165 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
2166 smi_addr[0] = 0;
2167 smi_addr[1] = pn;
2168 }
2169
2170 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
2171 priv->sds_id[pn] = -1;
2172 else {
2173 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
2174 }
2175
2176 if (pn < MAX_PORTS) {
2177 priv->smi_bus[pn] = smi_addr[0];
2178 priv->smi_addr[pn] = smi_addr[1];
2179 } else {
2180 pr_err("%s: illegal port number %d\n", __func__, pn);
2181 }
2182
2183 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
2184 priv->smi_bus_isc45[smi_addr[0]] = true;
2185
2186 if (of_property_read_bool(dn, "phy-is-integrated")) {
2187 priv->phy_is_internal[pn] = true;
2188 }
2189 }
2190
2191 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
2192 if (!dn) {
2193 dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n");
2194 return -ENODEV;
2195 }
2196
2197 for_each_node_by_name(dn, "port") {
2198 if (of_property_read_u32(dn, "reg", &pn))
2199 continue;
2200 pr_debug("%s Looking at port %d\n", __func__, pn);
2201 if (pn > priv->cpu_port)
2202 continue;
2203 if (of_get_phy_mode(dn, &priv->interfaces[pn]))
2204 priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
2205 pr_debug("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn]));
2206 }
2207
2208 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
2209 ret = of_mdiobus_register(priv->mii_bus, mii_np);
2210
2211 err_put_node:
2212 of_node_put(mii_np);
2213 return ret;
2214 }
2215
2216 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
2217 {
2218 pr_debug("%s called\n", __func__);
2219 if (!priv->mii_bus)
2220 return 0;
2221
2222 mdiobus_unregister(priv->mii_bus);
2223 mdiobus_free(priv->mii_bus);
2224
2225 return 0;
2226 }
2227
2228 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
2229 netdev_features_t features)
2230 {
2231 return features;
2232 }
2233
2234 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
2235 {
2236 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2237
2238 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2239 if (!(features & NETIF_F_RXCSUM))
2240 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2241 else
2242 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2243 }
2244
2245 return 0;
2246 }
2247
2248 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
2249 {
2250 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2251
2252 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2253 if (!(features & NETIF_F_RXCSUM))
2254 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2255 else
2256 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2257 }
2258
2259 return 0;
2260 }
2261
2262 static const struct net_device_ops rtl838x_eth_netdev_ops = {
2263 .ndo_open = rtl838x_eth_open,
2264 .ndo_stop = rtl838x_eth_stop,
2265 .ndo_start_xmit = rtl838x_eth_tx,
2266 .ndo_select_queue = rtl83xx_pick_tx_queue,
2267 .ndo_set_mac_address = rtl838x_set_mac_address,
2268 .ndo_validate_addr = eth_validate_addr,
2269 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
2270 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2271 .ndo_set_features = rtl83xx_set_features,
2272 .ndo_fix_features = rtl838x_fix_features,
2273 .ndo_setup_tc = rtl83xx_setup_tc,
2274 };
2275
2276 static const struct net_device_ops rtl839x_eth_netdev_ops = {
2277 .ndo_open = rtl838x_eth_open,
2278 .ndo_stop = rtl838x_eth_stop,
2279 .ndo_start_xmit = rtl838x_eth_tx,
2280 .ndo_select_queue = rtl83xx_pick_tx_queue,
2281 .ndo_set_mac_address = rtl838x_set_mac_address,
2282 .ndo_validate_addr = eth_validate_addr,
2283 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
2284 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2285 .ndo_set_features = rtl83xx_set_features,
2286 .ndo_fix_features = rtl838x_fix_features,
2287 .ndo_setup_tc = rtl83xx_setup_tc,
2288 };
2289
2290 static const struct net_device_ops rtl930x_eth_netdev_ops = {
2291 .ndo_open = rtl838x_eth_open,
2292 .ndo_stop = rtl838x_eth_stop,
2293 .ndo_start_xmit = rtl838x_eth_tx,
2294 .ndo_select_queue = rtl93xx_pick_tx_queue,
2295 .ndo_set_mac_address = rtl838x_set_mac_address,
2296 .ndo_validate_addr = eth_validate_addr,
2297 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
2298 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2299 .ndo_set_features = rtl93xx_set_features,
2300 .ndo_fix_features = rtl838x_fix_features,
2301 .ndo_setup_tc = rtl83xx_setup_tc,
2302 };
2303
2304 static const struct net_device_ops rtl931x_eth_netdev_ops = {
2305 .ndo_open = rtl838x_eth_open,
2306 .ndo_stop = rtl838x_eth_stop,
2307 .ndo_start_xmit = rtl838x_eth_tx,
2308 .ndo_select_queue = rtl93xx_pick_tx_queue,
2309 .ndo_set_mac_address = rtl838x_set_mac_address,
2310 .ndo_validate_addr = eth_validate_addr,
2311 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
2312 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2313 .ndo_set_features = rtl93xx_set_features,
2314 .ndo_fix_features = rtl838x_fix_features,
2315 };
2316
2317 static const struct phylink_mac_ops rtl838x_phylink_ops = {
2318 .validate = rtl838x_validate,
2319 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
2320 .mac_an_restart = rtl838x_mac_an_restart,
2321 .mac_config = rtl838x_mac_config,
2322 .mac_link_down = rtl838x_mac_link_down,
2323 .mac_link_up = rtl838x_mac_link_up,
2324 };
2325
2326 static const struct ethtool_ops rtl838x_ethtool_ops = {
2327 .get_link_ksettings = rtl838x_get_link_ksettings,
2328 .set_link_ksettings = rtl838x_set_link_ksettings,
2329 };
2330
2331 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2332 {
2333 struct net_device *dev;
2334 struct device_node *dn = pdev->dev.of_node;
2335 struct rtl838x_eth_priv *priv;
2336 struct resource *res, *mem;
2337 phy_interface_t phy_mode;
2338 struct phylink *phylink;
2339 int err = 0, i, rxrings, rxringlen;
2340 struct ring_b *ring;
2341
2342 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2343 (u32)pdev, (u32)(&(pdev->dev)));
2344
2345 if (!dn) {
2346 dev_err(&pdev->dev, "No DT found\n");
2347 return -EINVAL;
2348 }
2349
2350 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2351 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2352 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2353 rxringlen = MAX_ENTRIES / rxrings;
2354 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2355
2356 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2357 if (!dev) {
2358 err = -ENOMEM;
2359 goto err_free;
2360 }
2361 SET_NETDEV_DEV(dev, &pdev->dev);
2362 priv = netdev_priv(dev);
2363
2364 /* obtain buffer memory space */
2365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2366 if (res) {
2367 mem = devm_request_mem_region(&pdev->dev, res->start,
2368 resource_size(res), res->name);
2369 if (!mem) {
2370 dev_err(&pdev->dev, "cannot request memory space\n");
2371 err = -ENXIO;
2372 goto err_free;
2373 }
2374
2375 dev->mem_start = mem->start;
2376 dev->mem_end = mem->end;
2377 } else {
2378 dev_err(&pdev->dev, "cannot request IO resource\n");
2379 err = -ENXIO;
2380 goto err_free;
2381 }
2382
2383 /* Allocate buffer memory */
2384 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2385 + sizeof(struct ring_b) + sizeof(struct notify_b),
2386 (void *)&dev->mem_start, GFP_KERNEL);
2387 if (!priv->membase) {
2388 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2389 err = -ENOMEM;
2390 goto err_free;
2391 }
2392
2393 // Allocate ring-buffer space at the end of the allocated memory
2394 ring = priv->membase;
2395 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2396
2397 spin_lock_init(&priv->lock);
2398
2399 dev->ethtool_ops = &rtl838x_ethtool_ops;
2400 dev->min_mtu = ETH_ZLEN;
2401 dev->max_mtu = 1536;
2402 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2403 dev->hw_features = NETIF_F_RXCSUM;
2404
2405 priv->id = soc_info.id;
2406 priv->family_id = soc_info.family;
2407 if (priv->id) {
2408 pr_info("Found SoC ID: %4x: %s, family %x\n",
2409 priv->id, soc_info.name, priv->family_id);
2410 } else {
2411 pr_err("Unknown chip id (%04x)\n", priv->id);
2412 return -ENODEV;
2413 }
2414
2415 switch (priv->family_id) {
2416 case RTL8380_FAMILY_ID:
2417 priv->cpu_port = RTL838X_CPU_PORT;
2418 priv->r = &rtl838x_reg;
2419 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2420 break;
2421 case RTL8390_FAMILY_ID:
2422 priv->cpu_port = RTL839X_CPU_PORT;
2423 priv->r = &rtl839x_reg;
2424 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2425 break;
2426 case RTL9300_FAMILY_ID:
2427 priv->cpu_port = RTL930X_CPU_PORT;
2428 priv->r = &rtl930x_reg;
2429 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2430 break;
2431 case RTL9310_FAMILY_ID:
2432 priv->cpu_port = RTL931X_CPU_PORT;
2433 priv->r = &rtl931x_reg;
2434 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2435 rtl931x_chip_init(priv);
2436 break;
2437 default:
2438 pr_err("Unknown SoC family\n");
2439 return -ENODEV;
2440 }
2441 priv->rxringlen = rxringlen;
2442 priv->rxrings = rxrings;
2443
2444 /* Obtain device IRQ number */
2445 dev->irq = platform_get_irq(pdev, 0);
2446 if (dev->irq < 0) {
2447 dev_err(&pdev->dev, "cannot obtain network-device IRQ\n");
2448 goto err_free;
2449 }
2450
2451 err = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq,
2452 IRQF_SHARED, dev->name, dev);
2453 if (err) {
2454 dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n",
2455 __func__, err);
2456 goto err_free;
2457 }
2458
2459 rtl8380_init_mac(priv);
2460
2461 /* try to get mac address in the following order:
2462 * 1) from device tree data
2463 * 2) from internal registers set by bootloader
2464 */
2465 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2466 if (is_valid_ether_addr(dev->dev_addr)) {
2467 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2468 } else {
2469 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2470 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2471 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2472 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2473 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2474 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2475 }
2476 /* if the address is invalid, use a random value */
2477 if (!is_valid_ether_addr(dev->dev_addr)) {
2478 struct sockaddr sa = { AF_UNSPEC };
2479
2480 netdev_warn(dev, "Invalid MAC address, using random\n");
2481 eth_hw_addr_random(dev);
2482 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2483 if (rtl838x_set_mac_address(dev, &sa))
2484 netdev_warn(dev, "Failed to set MAC address.\n");
2485 }
2486 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2487 sw_r32(priv->r->mac + 4));
2488 strcpy(dev->name, "eth%d");
2489 priv->pdev = pdev;
2490 priv->netdev = dev;
2491
2492 err = rtl838x_mdio_init(priv);
2493 if (err)
2494 goto err_free;
2495
2496 err = register_netdev(dev);
2497 if (err)
2498 goto err_free;
2499
2500 for (i = 0; i < priv->rxrings; i++) {
2501 priv->rx_qs[i].id = i;
2502 priv->rx_qs[i].priv = priv;
2503 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2504 }
2505
2506 platform_set_drvdata(pdev, dev);
2507
2508 phy_mode = PHY_INTERFACE_MODE_NA;
2509 err = of_get_phy_mode(dn, &phy_mode);
2510 if (err < 0) {
2511 dev_err(&pdev->dev, "incorrect phy-mode\n");
2512 err = -EINVAL;
2513 goto err_free;
2514 }
2515 priv->phylink_config.dev = &dev->dev;
2516 priv->phylink_config.type = PHYLINK_NETDEV;
2517
2518 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2519 phy_mode, &rtl838x_phylink_ops);
2520
2521 if (IS_ERR(phylink)) {
2522 err = PTR_ERR(phylink);
2523 goto err_free;
2524 }
2525 priv->phylink = phylink;
2526
2527 return 0;
2528
2529 err_free:
2530 pr_err("Error setting up netdev, freeing it again.\n");
2531 free_netdev(dev);
2532 return err;
2533 }
2534
2535 static int rtl838x_eth_remove(struct platform_device *pdev)
2536 {
2537 struct net_device *dev = platform_get_drvdata(pdev);
2538 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2539 int i;
2540
2541 if (dev) {
2542 pr_info("Removing platform driver for rtl838x-eth\n");
2543 rtl838x_mdio_remove(priv);
2544 rtl838x_hw_stop(priv);
2545
2546 netif_tx_stop_all_queues(dev);
2547
2548 for (i = 0; i < priv->rxrings; i++)
2549 netif_napi_del(&priv->rx_qs[i].napi);
2550
2551 unregister_netdev(dev);
2552 free_netdev(dev);
2553 }
2554 return 0;
2555 }
2556
2557 static const struct of_device_id rtl838x_eth_of_ids[] = {
2558 { .compatible = "realtek,rtl838x-eth"},
2559 { /* sentinel */ }
2560 };
2561 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2562
2563 static struct platform_driver rtl838x_eth_driver = {
2564 .probe = rtl838x_eth_probe,
2565 .remove = rtl838x_eth_remove,
2566 .driver = {
2567 .name = "rtl838x-eth",
2568 .pm = NULL,
2569 .of_match_table = rtl838x_eth_of_ids,
2570 },
2571 };
2572
2573 module_platform_driver(rtl838x_eth_driver);
2574
2575 MODULE_AUTHOR("B. Koblitz");
2576 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2577 MODULE_LICENSE("GPL");
Staging tree of Christian Lamparter