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[openwrt/staging/neocturne.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 /* cpu_tag[0] is a reserved uint16_t on RTL83xx */
62 uint16_t cpu_tag[10];
63 } __packed __aligned(1);
64
65 struct n_event {
66 uint32_t type:2;
67 uint32_t fidVid:12;
68 uint64_t mac:48;
69 uint32_t slp:6;
70 uint32_t valid:1;
71 uint32_t reserved:27;
72 } __packed __aligned(1);
73
74 struct ring_b {
75 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
76 uint32_t tx_r[TXRINGS][TXRINGLEN];
77 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
78 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
79 uint32_t c_rx[MAX_RXRINGS];
80 uint32_t c_tx[TXRINGS];
81 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
82 uint8_t *rx_space;
83 };
84
85 struct notify_block {
86 struct n_event events[NOTIFY_EVENTS];
87 };
88
89 struct notify_b {
90 struct notify_block blocks[NOTIFY_BLOCKS];
91 u32 reserved1[8];
92 u32 ring[NOTIFY_BLOCKS];
93 u32 reserved2[8];
94 };
95
96 static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
97 {
98 // cpu_tag[0] is reserved on the RTL83XX SoCs
99 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
100 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
101 h->cpu_tag[3] = 0x0000;
102 h->cpu_tag[4] = BIT(dest_port) >> 16;
103 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
104
105 /* Set internal priority (PRI) and enable (AS_PRI) */
106 if (prio >= 0)
107 h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
108 }
109
110 static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
111 {
112 // cpu_tag[0] is reserved on the RTL83XX SoCs
113 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
114 h->cpu_tag[2] = BIT(4) | BIT(7); /* AS_DPM (4) and L2LEARNING (7) flags */
115 h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
116 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
117 if (dest_port >= 32) {
118 dest_port -= 32;
119 h->cpu_tag[2] |= (BIT(dest_port) >> 16) & 0xf;
120 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
121 } else {
122 h->cpu_tag[4] = BIT(dest_port) >> 16;
123 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
124 }
125
126 /* Set internal priority (PRI) and enable (AS_PRI) */
127 if (prio >= 0)
128 h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
129 }
130
131 static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
132 {
133 h->cpu_tag[0] = 0x8000; // CPU tag marker
134 h->cpu_tag[1] = h->cpu_tag[2] = 0;
135 h->cpu_tag[3] = 0;
136 h->cpu_tag[4] = 0;
137 h->cpu_tag[5] = 0;
138 h->cpu_tag[6] = BIT(dest_port) >> 16;
139 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
140
141 /* Enable (AS_QID) and set priority queue (QID) */
142 if (prio >= 0)
143 h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
144 }
145
146 static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
147 {
148 h->cpu_tag[0] = 0x8000; // CPU tag marker
149 h->cpu_tag[1] = h->cpu_tag[2] = 0;
150 h->cpu_tag[3] = 0;
151 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
152 if (dest_port >= 32) {
153 dest_port -= 32;
154 h->cpu_tag[4] = BIT(dest_port) >> 16;
155 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
156 } else {
157 h->cpu_tag[6] = BIT(dest_port) >> 16;
158 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
159 }
160
161 /* Enable (AS_QID) and set priority queue (QID) */
162 if (prio >= 0)
163 h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
164 }
165
166 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
167 {
168 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
169 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
170 h->cpu_tag[3] |= (vlan & 0xff) << 8;
171 }
172
173 struct rtl838x_rx_q {
174 int id;
175 struct rtl838x_eth_priv *priv;
176 struct napi_struct napi;
177 };
178
179 struct rtl838x_eth_priv {
180 struct net_device *netdev;
181 struct platform_device *pdev;
182 void *membase;
183 spinlock_t lock;
184 struct mii_bus *mii_bus;
185 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
186 struct phylink *phylink;
187 struct phylink_config phylink_config;
188 u16 id;
189 u16 family_id;
190 const struct rtl838x_eth_reg *r;
191 u8 cpu_port;
192 u32 lastEvent;
193 u16 rxrings;
194 u16 rxringlen;
195 u8 smi_bus[MAX_PORTS];
196 u8 smi_addr[MAX_PORTS];
197 u32 sds_id[MAX_PORTS];
198 bool smi_bus_isc45[MAX_SMI_BUSSES];
199 bool phy_is_internal[MAX_PORTS];
200 phy_interface_t interfaces[MAX_PORTS];
201 };
202
203 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
204 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
205 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
206 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
207 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
208 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
209 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
210 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
211 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
212 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
213 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
214 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
215
216 /*
217 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
218 * the rings. Writing x into these registers substracts x from its content.
219 * When the content reaches the ring size, the ASIC no longer adds
220 * packets to this receive queue.
221 */
222 void rtl838x_update_cntr(int r, int released)
223 {
224 // This feature is not available on RTL838x SoCs
225 }
226
227 void rtl839x_update_cntr(int r, int released)
228 {
229 // This feature is not available on RTL839x SoCs
230 }
231
232 void rtl930x_update_cntr(int r, int released)
233 {
234 int pos = (r % 3) * 10;
235 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
236 u32 v = sw_r32(reg);
237
238 v = (v >> pos) & 0x3ff;
239 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
240 sw_w32_mask(0x3ff << pos, released << pos, reg);
241 sw_w32(v, reg);
242 }
243
244 void rtl931x_update_cntr(int r, int released)
245 {
246 int pos = (r % 3) * 10;
247 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
248 u32 v = sw_r32(reg);
249
250 v = (v >> pos) & 0x3ff;
251 sw_w32_mask(0x3ff << pos, released << pos, reg);
252 sw_w32(v, reg);
253 }
254
255 struct dsa_tag {
256 u8 reason;
257 u8 queue;
258 u16 port;
259 u8 l2_offloaded;
260 u8 prio;
261 bool crc_error;
262 };
263
264 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
265 {
266 /* cpu_tag[0] is reserved. Fields are off-by-one */
267 t->reason = h->cpu_tag[4] & 0xf;
268 t->queue = (h->cpu_tag[1] & 0xe0) >> 5;
269 t->port = h->cpu_tag[1] & 0x1f;
270 t->crc_error = t->reason == 13;
271
272 pr_debug("Reason: %d\n", t->reason);
273 if (t->reason != 6) // NIC_RX_REASON_SPECIAL_TRAP
274 t->l2_offloaded = 1;
275 else
276 t->l2_offloaded = 0;
277
278 return t->l2_offloaded;
279 }
280
281 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
282 {
283 /* cpu_tag[0] is reserved. Fields are off-by-one */
284 t->reason = h->cpu_tag[5] & 0x1f;
285 t->queue = (h->cpu_tag[4] & 0xe000) >> 13;
286 t->port = h->cpu_tag[1] & 0x3f;
287 t->crc_error = h->cpu_tag[4] & BIT(6);
288
289 pr_debug("Reason: %d\n", t->reason);
290 if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA
291 (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP
292 t->l2_offloaded = 0;
293 else
294 t->l2_offloaded = 1;
295
296 return t->l2_offloaded;
297 }
298
299 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
300 {
301 t->reason = h->cpu_tag[7] & 0x3f;
302 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
303 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
304 t->crc_error = h->cpu_tag[1] & BIT(6);
305
306 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
307 if (t->reason >= 19 && t->reason <= 27)
308 t->l2_offloaded = 0;
309 else
310 t->l2_offloaded = 1;
311
312 return t->l2_offloaded;
313 }
314
315 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
316 {
317 t->reason = h->cpu_tag[7] & 0x3f;
318 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
319 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
320 t->crc_error = h->cpu_tag[1] & BIT(6);
321
322 if (t->reason != 63)
323 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
324 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
325 t->l2_offloaded = 0;
326 else
327 t->l2_offloaded = 1;
328
329 return t->l2_offloaded;
330 }
331
332 /*
333 * Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
335 */
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
337 {
338 int r;
339 u32 *last;
340 struct p_hdr *h;
341 struct ring_b *ring = priv->membase;
342
343 for (r = 0; r < priv->rxrings; r++) {
344 pr_debug("In %s working on r: %d\n", __func__, r);
345 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
346 do {
347 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
348 break;
349 pr_debug("Got something: %d\n", ring->c_rx[r]);
350 h = &ring->rx_header[r][ring->c_rx[r]];
351 memset(h, 0, sizeof(struct p_hdr));
352 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
353 + r * priv->rxringlen * RING_BUFFER
354 + ring->c_rx[r] * RING_BUFFER);
355 h->size = RING_BUFFER;
356 /* make sure the header is visible to the ASIC */
357 mb();
358
359 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
360 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
361 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
362 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
363 }
364 }
365
366 struct fdb_update_work {
367 struct work_struct work;
368 struct net_device *ndev;
369 u64 macs[NOTIFY_EVENTS + 1];
370 };
371
372 void rtl838x_fdb_sync(struct work_struct *work)
373 {
374 const struct fdb_update_work *uw =
375 container_of(work, struct fdb_update_work, work);
376 struct switchdev_notifier_fdb_info info;
377 u8 addr[ETH_ALEN];
378 int i = 0;
379 int action;
380
381 while (uw->macs[i]) {
382 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
383 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
384 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
385 info.addr = &addr[0];
386 info.vid = 0;
387 info.offloaded = 1;
388 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
389 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
390 i++;
391 }
392 kfree(work);
393 }
394
395 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
396 {
397 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
398 u32 e = priv->lastEvent;
399 struct n_event *event;
400 int i;
401 u64 mac;
402 struct fdb_update_work *w;
403
404 while (!(nb->ring[e] & 1)) {
405 w = kzalloc(sizeof(*w), GFP_ATOMIC);
406 if (!w) {
407 pr_err("Out of memory: %s", __func__);
408 return;
409 }
410 INIT_WORK(&w->work, rtl838x_fdb_sync);
411
412 for (i = 0; i < NOTIFY_EVENTS; i++) {
413 event = &nb->blocks[e].events[i];
414 if (!event->valid)
415 continue;
416 mac = event->mac;
417 if (event->type)
418 mac |= 1ULL << 63;
419 w->ndev = priv->netdev;
420 w->macs[i] = mac;
421 }
422
423 /* Hand the ring entry back to the switch */
424 nb->ring[e] = nb->ring[e] | 1;
425 e = (e + 1) % NOTIFY_BLOCKS;
426
427 w->macs[i] = 0ULL;
428 schedule_work(&w->work);
429 }
430 priv->lastEvent = e;
431 }
432
433 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct rtl838x_eth_priv *priv = netdev_priv(dev);
437 u32 status = sw_r32(priv->r->dma_if_intr_sts);
438 int i;
439
440 pr_debug("IRQ: %08x\n", status);
441
442 /* Ignore TX interrupt */
443 if ((status & 0xf0000)) {
444 /* Clear ISR */
445 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
446 }
447
448 /* RX interrupt */
449 if (status & 0x0ff00) {
450 /* ACK and disable RX interrupt for this ring */
451 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
452 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
453 for (i = 0; i < priv->rxrings; i++) {
454 if (status & BIT(i + 8)) {
455 pr_debug("Scheduling queue: %d\n", i);
456 napi_schedule(&priv->rx_qs[i].napi);
457 }
458 }
459 }
460
461 /* RX buffer overrun */
462 if (status & 0x000ff) {
463 pr_debug("RX buffer overrun: status %x, mask: %x\n",
464 status, sw_r32(priv->r->dma_if_intr_msk));
465 sw_w32(status, priv->r->dma_if_intr_sts);
466 rtl838x_rb_cleanup(priv, status & 0xff);
467 }
468
469 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
470 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
471 rtl839x_l2_notification_handler(priv);
472 }
473
474 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
475 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
476 rtl839x_l2_notification_handler(priv);
477 }
478
479 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
480 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
481 rtl839x_l2_notification_handler(priv);
482 }
483
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
488 {
489 struct net_device *dev = dev_id;
490 struct rtl838x_eth_priv *priv = netdev_priv(dev);
491 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
492 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
493 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
494 int i;
495
496 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
497 __func__, status_tx, status_rx, status_rx_r);
498
499 /* Ignore TX interrupt */
500 if (status_tx) {
501 /* Clear ISR */
502 pr_debug("TX done\n");
503 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
504 }
505
506 /* RX interrupt */
507 if (status_rx) {
508 pr_debug("RX IRQ\n");
509 /* ACK and disable RX interrupt for given rings */
510 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
511 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
512 for (i = 0; i < priv->rxrings; i++) {
513 if (status_rx & BIT(i)) {
514 pr_debug("Scheduling queue: %d\n", i);
515 napi_schedule(&priv->rx_qs[i].napi);
516 }
517 }
518 }
519
520 /* RX buffer overrun */
521 if (status_rx_r) {
522 pr_debug("RX buffer overrun: status %x, mask: %x\n",
523 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
524 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
525 rtl838x_rb_cleanup(priv, status_rx_r);
526 }
527
528 return IRQ_HANDLED;
529 }
530
531 static const struct rtl838x_eth_reg rtl838x_reg = {
532 .net_irq = rtl83xx_net_irq,
533 .mac_port_ctrl = rtl838x_mac_port_ctrl,
534 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
535 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
536 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
537 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
538 .dma_rx_base = RTL838X_DMA_RX_BASE,
539 .dma_tx_base = RTL838X_DMA_TX_BASE,
540 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
541 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
542 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
543 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
544 .get_mac_link_sts = rtl838x_get_mac_link_sts,
545 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
546 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
547 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
548 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
549 .mac = RTL838X_MAC,
550 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
551 .update_cntr = rtl838x_update_cntr,
552 .create_tx_header = rtl838x_create_tx_header,
553 .decode_tag = rtl838x_decode_tag,
554 };
555
556 static const struct rtl838x_eth_reg rtl839x_reg = {
557 .net_irq = rtl83xx_net_irq,
558 .mac_port_ctrl = rtl839x_mac_port_ctrl,
559 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
560 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
561 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
562 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
563 .dma_rx_base = RTL839X_DMA_RX_BASE,
564 .dma_tx_base = RTL839X_DMA_TX_BASE,
565 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
566 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
567 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
568 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
569 .get_mac_link_sts = rtl839x_get_mac_link_sts,
570 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
571 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
572 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
573 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
574 .mac = RTL839X_MAC,
575 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
576 .update_cntr = rtl839x_update_cntr,
577 .create_tx_header = rtl839x_create_tx_header,
578 .decode_tag = rtl839x_decode_tag,
579 };
580
581 static const struct rtl838x_eth_reg rtl930x_reg = {
582 .net_irq = rtl93xx_net_irq,
583 .mac_port_ctrl = rtl930x_mac_port_ctrl,
584 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
585 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
586 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
587 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
588 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
589 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
590 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
591 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
592 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
593 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
594 .dma_rx_base = RTL930X_DMA_RX_BASE,
595 .dma_tx_base = RTL930X_DMA_TX_BASE,
596 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
597 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
598 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
599 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
600 .get_mac_link_sts = rtl930x_get_mac_link_sts,
601 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
602 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
603 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
604 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
605 .mac = RTL930X_MAC_L2_ADDR_CTRL,
606 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
607 .update_cntr = rtl930x_update_cntr,
608 .create_tx_header = rtl930x_create_tx_header,
609 .decode_tag = rtl930x_decode_tag,
610 };
611
612 static const struct rtl838x_eth_reg rtl931x_reg = {
613 .net_irq = rtl93xx_net_irq,
614 .mac_port_ctrl = rtl931x_mac_port_ctrl,
615 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
616 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
617 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
618 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
619 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
620 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
621 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
622 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
623 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
624 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
625 .dma_rx_base = RTL931X_DMA_RX_BASE,
626 .dma_tx_base = RTL931X_DMA_TX_BASE,
627 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
628 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
629 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
630 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
631 .get_mac_link_sts = rtl931x_get_mac_link_sts,
632 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
633 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
634 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
635 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
636 .mac = RTL931X_MAC_L2_ADDR_CTRL,
637 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
638 .update_cntr = rtl931x_update_cntr,
639 .create_tx_header = rtl931x_create_tx_header,
640 .decode_tag = rtl931x_decode_tag,
641 };
642
643 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
644 {
645 u32 int_saved, nbuf;
646 u32 reset_mask;
647 int i, pos;
648
649 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
650 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
651 mdelay(100);
652
653 /* Disable and clear interrupts */
654 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
655 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
656 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
657 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
658 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
659 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
660 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
661 } else {
662 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
663 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
664 }
665
666 if (priv->family_id == RTL8390_FAMILY_ID) {
667 /* Preserve L2 notification and NBUF settings */
668 int_saved = sw_r32(priv->r->dma_if_intr_msk);
669 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
670
671 /* Disable link change interrupt on RTL839x */
672 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
673 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
674
675 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
676 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
677 }
678
679 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
680 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
681 reset_mask = 0x6;
682 else
683 reset_mask = 0xc;
684
685 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
686
687 do { /* Wait for reset of NIC and Queues done */
688 udelay(20);
689 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
690 mdelay(100);
691
692 /* Setup Head of Line */
693 if (priv->family_id == RTL8380_FAMILY_ID)
694 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
695 if (priv->family_id == RTL8390_FAMILY_ID)
696 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
697 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
698 for (i = 0; i < priv->rxrings; i++) {
699 pos = (i % 3) * 10;
700 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
701 sw_w32_mask(0x3ff << pos, priv->rxringlen,
702 priv->r->dma_if_rx_ring_cntr(i));
703 }
704 }
705
706 /* Re-enable link change interrupt */
707 if (priv->family_id == RTL8390_FAMILY_ID) {
708 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
709 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
710 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
711 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
712
713 /* Restore notification settings: on RTL838x these bits are null */
714 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
715 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
716 }
717 }
718
719 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
720 {
721 int i;
722 struct ring_b *ring = priv->membase;
723
724 for (i = 0; i < priv->rxrings; i++)
725 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
726
727 for (i = 0; i < TXRINGS; i++)
728 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
729 }
730
731 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
732 {
733 /* Disable Head of Line features for all RX rings */
734 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
735
736 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
737 sw_w32(0x06400020, priv->r->dma_if_ctrl);
738
739 /* Enable RX done, RX overflow and TX done interrupts */
740 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
741
742 /* Enable DMA, engine expects empty FCS field */
743 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
744
745 /* Restart TX/RX to CPU port */
746 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
747 /* Set Speed, duplex, flow control
748 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
749 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
750 * | MEDIA_SEL
751 */
752 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
753
754 /* Enable CRC checks on CPU-port */
755 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
756 }
757
758 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
759 {
760 /* Setup CPU-Port: RX Buffer */
761 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
762
763 /* Enable Notify, RX done, RX overflow and TX done interrupts */
764 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
765
766 /* Enable DMA */
767 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
768
769 /* Restart TX/RX to CPU port, enable CRC checking */
770 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
771
772 /* CPU port joins Lookup Miss Flooding Portmask */
773 // TODO: The code below should also work for the RTL838x
774 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
775 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
776 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
777
778 /* Force CPU port link up */
779 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
780 }
781
782 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
783 {
784 int i, pos;
785 u32 v;
786
787 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
788 sw_w32(0x06400040, priv->r->dma_if_ctrl);
789
790 for (i = 0; i < priv->rxrings; i++) {
791 pos = (i % 3) * 10;
792 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
793
794 // Some SoCs have issues with missing underflow protection
795 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
796 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
797 }
798
799 /* Enable Notify, RX done, RX overflow and TX done interrupts */
800 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
801 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
802 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
803
804 /* Enable DMA */
805 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
806
807 /* Restart TX/RX to CPU port, enable CRC checking */
808 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
809
810 if (priv->family_id == RTL9300_FAMILY_ID)
811 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
812 else
813 sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
814
815 if (priv->family_id == RTL9300_FAMILY_ID)
816 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
817 else
818 sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
819 }
820
821 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
822 {
823 int i, j;
824
825 struct p_hdr *h;
826
827 for (i = 0; i < priv->rxrings; i++) {
828 for (j = 0; j < priv->rxringlen; j++) {
829 h = &ring->rx_header[i][j];
830 memset(h, 0, sizeof(struct p_hdr));
831 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
832 + i * priv->rxringlen * RING_BUFFER
833 + j * RING_BUFFER);
834 h->size = RING_BUFFER;
835 /* All rings owned by switch, last one wraps */
836 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
837 | (j == (priv->rxringlen - 1) ? WRAP : 0);
838 }
839 ring->c_rx[i] = 0;
840 }
841
842 for (i = 0; i < TXRINGS; i++) {
843 for (j = 0; j < TXRINGLEN; j++) {
844 h = &ring->tx_header[i][j];
845 memset(h, 0, sizeof(struct p_hdr));
846 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
847 + i * TXRINGLEN * RING_BUFFER
848 + j * RING_BUFFER);
849 h->size = RING_BUFFER;
850 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
851 }
852 /* Last header is wrapping around */
853 ring->tx_r[i][j-1] |= WRAP;
854 ring->c_tx[i] = 0;
855 }
856 }
857
858 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
859 {
860 int i;
861 struct notify_b *b = priv->membase + sizeof(struct ring_b);
862
863 for (i = 0; i < NOTIFY_BLOCKS; i++)
864 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
865
866 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
867 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
868
869 /* Setup notification events */
870 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
871 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
872
873 /* Enable Notification */
874 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
875 priv->lastEvent = 0;
876 }
877
878 static int rtl838x_eth_open(struct net_device *ndev)
879 {
880 unsigned long flags;
881 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
882 struct ring_b *ring = priv->membase;
883 int i;
884
885 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
886 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
887
888 spin_lock_irqsave(&priv->lock, flags);
889 rtl838x_hw_reset(priv);
890 rtl838x_setup_ring_buffer(priv, ring);
891 if (priv->family_id == RTL8390_FAMILY_ID) {
892 rtl839x_setup_notify_ring_buffer(priv);
893 /* Make sure the ring structure is visible to the ASIC */
894 mb();
895 flush_cache_all();
896 }
897
898 rtl838x_hw_ring_setup(priv);
899 phylink_start(priv->phylink);
900
901 for (i = 0; i < priv->rxrings; i++)
902 napi_enable(&priv->rx_qs[i].napi);
903
904 switch (priv->family_id) {
905 case RTL8380_FAMILY_ID:
906 rtl838x_hw_en_rxtx(priv);
907 /* Trap IGMP/MLD traffic to CPU-Port */
908 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
909 /* Flush learned FDB entries on link down of a port */
910 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
911 break;
912
913 case RTL8390_FAMILY_ID:
914 rtl839x_hw_en_rxtx(priv);
915 // Trap MLD and IGMP messages to CPU_PORT
916 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
917 /* Flush learned FDB entries on link down of a port */
918 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
919 break;
920
921 case RTL9300_FAMILY_ID:
922 rtl93xx_hw_en_rxtx(priv);
923 /* Flush learned FDB entries on link down of a port */
924 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
925 // Trap MLD and IGMP messages to CPU_PORT
926 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
927 break;
928
929 case RTL9310_FAMILY_ID:
930 rtl93xx_hw_en_rxtx(priv);
931
932 // Trap MLD and IGMP messages to CPU_PORT
933 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
934
935 // Disable External CPU access to switch, clear EXT_CPU_EN
936 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
937
938 // Set PCIE_PWR_DOWN
939 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
940 break;
941 }
942
943 netif_tx_start_all_queues(ndev);
944
945 spin_unlock_irqrestore(&priv->lock, flags);
946
947 return 0;
948 }
949
950 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
951 {
952 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
953 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
954 int i;
955
956 // Disable RX/TX from/to CPU-port
957 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
958
959 /* Disable traffic */
960 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
961 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
962 else
963 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
964 mdelay(200); // Test, whether this is needed
965
966 /* Block all ports */
967 if (priv->family_id == RTL8380_FAMILY_ID) {
968 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
969 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
970 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
971 }
972
973 /* Flush L2 address cache */
974 if (priv->family_id == RTL8380_FAMILY_ID) {
975 for (i = 0; i <= priv->cpu_port; i++) {
976 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
977 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
978 }
979 } else if (priv->family_id == RTL8390_FAMILY_ID) {
980 for (i = 0; i <= priv->cpu_port; i++) {
981 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
982 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
983 }
984 }
985 // TODO: L2 flush register is 64 bit on RTL931X and 930X
986
987 /* CPU-Port: Link down */
988 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
989 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
990 else if (priv->family_id == RTL9300_FAMILY_ID)
991 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
992 else if (priv->family_id == RTL9310_FAMILY_ID)
993 sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
994 mdelay(100);
995
996 /* Disable all TX/RX interrupts */
997 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
998 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
999 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
1000 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
1001 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
1002 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
1003 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
1004 } else {
1005 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
1006 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
1007 }
1008
1009 /* Disable TX/RX DMA */
1010 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1011 mdelay(200);
1012 }
1013
1014 static int rtl838x_eth_stop(struct net_device *ndev)
1015 {
1016 unsigned long flags;
1017 int i;
1018 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1019
1020 pr_info("in %s\n", __func__);
1021
1022 phylink_stop(priv->phylink);
1023 rtl838x_hw_stop(priv);
1024
1025 for (i = 0; i < priv->rxrings; i++)
1026 napi_disable(&priv->rx_qs[i].napi);
1027
1028 netif_tx_stop_all_queues(ndev);
1029
1030 return 0;
1031 }
1032
1033 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1034 {
1035 /*
1036 * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1037 * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF
1038 */
1039 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1040 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1041 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1042 }
1043 if (ndev->flags & IFF_ALLMULTI)
1044 sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0);
1045 if (ndev->flags & IFF_PROMISC) {
1046 sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0);
1047 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1048 }
1049 }
1050
1051 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1052 {
1053 /*
1054 * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1055 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1056 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
1057 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1058 */
1059 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1060 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1061 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1062 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1063 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1064 }
1065 if (ndev->flags & IFF_ALLMULTI) {
1066 sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0);
1067 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1);
1068 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2);
1069 }
1070 if (ndev->flags & IFF_PROMISC) {
1071 sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0);
1072 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1);
1073 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2);
1074 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1075 }
1076 }
1077
1078 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1079 {
1080 /*
1081 * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1082 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1083 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
1084 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1085 */
1086 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1087 sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0);
1088 sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1);
1089 sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2);
1090 } else {
1091 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1092 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1093 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1094 }
1095 }
1096
1097 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1098 {
1099 /*
1100 * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1101 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1102 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00.
1103 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1104 */
1105 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1106 sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0);
1107 sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1);
1108 sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2);
1109 } else {
1110 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1111 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1112 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1113 }
1114 }
1115
1116 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1117 {
1118 unsigned long flags;
1119 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1120
1121 pr_warn("%s\n", __func__);
1122 spin_lock_irqsave(&priv->lock, flags);
1123 rtl838x_hw_stop(priv);
1124 rtl838x_hw_ring_setup(priv);
1125 rtl838x_hw_en_rxtx(priv);
1126 netif_trans_update(ndev);
1127 netif_start_queue(ndev);
1128 spin_unlock_irqrestore(&priv->lock, flags);
1129 }
1130
1131 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1132 {
1133 int len, i;
1134 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1135 struct ring_b *ring = priv->membase;
1136 uint32_t val;
1137 int ret;
1138 unsigned long flags;
1139 struct p_hdr *h;
1140 int dest_port = -1;
1141 int q = skb_get_queue_mapping(skb) % TXRINGS;
1142
1143 if (q) // Check for high prio queue
1144 pr_debug("SKB priority: %d\n", skb->priority);
1145
1146 spin_lock_irqsave(&priv->lock, flags);
1147 len = skb->len;
1148
1149 /* Check for DSA tagging at the end of the buffer */
1150 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80
1151 && skb->data[len-3] < priv->cpu_port
1152 && skb->data[len-2] == 0x10
1153 && skb->data[len-1] == 0x00) {
1154 /* Reuse tag space for CRC if possible */
1155 dest_port = skb->data[len-3];
1156 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1157 len -= 4;
1158 }
1159
1160 len += 4; // Add space for CRC
1161
1162 if (skb_padto(skb, len)) {
1163 ret = NETDEV_TX_OK;
1164 goto txdone;
1165 }
1166
1167 /* We can send this packet if CPU owns the descriptor */
1168 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1169
1170 /* Set descriptor for tx */
1171 h = &ring->tx_header[q][ring->c_tx[q]];
1172 h->size = len;
1173 h->len = len;
1174 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1175 if (priv->family_id == RTL8380_FAMILY_ID) {
1176 if (len < ETH_ZLEN - 4)
1177 h->len -= 4;
1178 }
1179
1180 if (dest_port >= 0)
1181 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1182
1183 /* Copy packet data to tx buffer */
1184 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1185 /* Make sure packet data is visible to ASIC */
1186 wmb();
1187
1188 /* Hand over to switch */
1189 ring->tx_r[q][ring->c_tx[q]] |= 1;
1190
1191 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1192 if (priv->family_id == RTL8380_FAMILY_ID) {
1193 for (i = 0; i < 10; i++) {
1194 val = sw_r32(priv->r->dma_if_ctrl);
1195 if ((val & 0xc) == 0xc)
1196 break;
1197 }
1198 }
1199
1200 /* Tell switch to send data */
1201 if (priv->family_id == RTL9310_FAMILY_ID
1202 || priv->family_id == RTL9300_FAMILY_ID) {
1203 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1204 if (!q)
1205 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1206 else
1207 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1208 } else {
1209 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1210 }
1211
1212 dev->stats.tx_packets++;
1213 dev->stats.tx_bytes += len;
1214 dev_kfree_skb(skb);
1215 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1216 ret = NETDEV_TX_OK;
1217 } else {
1218 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1219 ret = NETDEV_TX_BUSY;
1220 }
1221 txdone:
1222 spin_unlock_irqrestore(&priv->lock, flags);
1223 return ret;
1224 }
1225
1226 /*
1227 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1228 * so we do round-robin
1229 */
1230 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1231 struct net_device *sb_dev)
1232 {
1233 static u8 last = 0;
1234
1235 last++;
1236 return last % TXRINGS;
1237 }
1238
1239 /*
1240 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1241 */
1242 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1243 struct net_device *sb_dev)
1244 {
1245 if (skb->priority >= TC_PRIO_CONTROL)
1246 return 1;
1247 return 0;
1248 }
1249
1250 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1251 {
1252 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1253 struct ring_b *ring = priv->membase;
1254 struct sk_buff *skb;
1255 unsigned long flags;
1256 int i, len, work_done = 0;
1257 u8 *data, *skb_data;
1258 unsigned int val;
1259 u32 *last;
1260 struct p_hdr *h;
1261 bool dsa = netdev_uses_dsa(dev);
1262 struct dsa_tag tag;
1263
1264 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1265 spin_lock_irqsave(&priv->lock, flags);
1266 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1267
1268 do {
1269 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1270 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1271 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1272 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1273 }
1274 break;
1275 }
1276
1277 h = &ring->rx_header[r][ring->c_rx[r]];
1278 data = (u8 *)KSEG1ADDR(h->buf);
1279 len = h->len;
1280 if (!len)
1281 break;
1282 work_done++;
1283
1284 len -= 4; /* strip the CRC */
1285 /* Add 4 bytes for cpu_tag */
1286 if (dsa)
1287 len += 4;
1288
1289 skb = netdev_alloc_skb(dev, len + 4);
1290 skb_reserve(skb, NET_IP_ALIGN);
1291
1292 if (likely(skb)) {
1293 /* BUG: Prevent bug on RTL838x SoCs*/
1294 if (priv->family_id == RTL8380_FAMILY_ID) {
1295 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1296 for (i = 0; i < priv->rxrings; i++) {
1297 /* Update each ring cnt */
1298 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1299 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1300 }
1301 }
1302
1303 skb_data = skb_put(skb, len);
1304 /* Make sure data is visible */
1305 mb();
1306 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1307 /* Overwrite CRC with cpu_tag */
1308 if (dsa) {
1309 priv->r->decode_tag(h, &tag);
1310 skb->data[len-4] = 0x80;
1311 skb->data[len-3] = tag.port;
1312 skb->data[len-2] = 0x10;
1313 skb->data[len-1] = 0x00;
1314 if (tag.l2_offloaded)
1315 skb->data[len-3] |= 0x40;
1316 }
1317
1318 if (tag.queue >= 0)
1319 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1320 tag.queue, len, tag.reason, tag.port);
1321
1322 skb->protocol = eth_type_trans(skb, dev);
1323 if (dev->features & NETIF_F_RXCSUM) {
1324 if (tag.crc_error)
1325 skb_checksum_none_assert(skb);
1326 else
1327 skb->ip_summed = CHECKSUM_UNNECESSARY;
1328 }
1329 dev->stats.rx_packets++;
1330 dev->stats.rx_bytes += len;
1331
1332 netif_receive_skb(skb);
1333 } else {
1334 if (net_ratelimit())
1335 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1336 dev->stats.rx_dropped++;
1337 }
1338
1339 /* Reset header structure */
1340 memset(h, 0, sizeof(struct p_hdr));
1341 h->buf = data;
1342 h->size = RING_BUFFER;
1343
1344 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1345 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1346 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1347 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1348 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1349
1350 // Update counters
1351 priv->r->update_cntr(r, 0);
1352
1353 spin_unlock_irqrestore(&priv->lock, flags);
1354
1355 return work_done;
1356 }
1357
1358 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1359 {
1360 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1361 struct rtl838x_eth_priv *priv = rx_q->priv;
1362 int work_done = 0;
1363 int r = rx_q->id;
1364 int work;
1365
1366 while (work_done < budget) {
1367 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1368 if (!work)
1369 break;
1370 work_done += work;
1371 }
1372
1373 if (work_done < budget) {
1374 napi_complete_done(napi, work_done);
1375
1376 /* Enable RX interrupt */
1377 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1378 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1379 else
1380 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1381 }
1382 return work_done;
1383 }
1384
1385
1386 static void rtl838x_validate(struct phylink_config *config,
1387 unsigned long *supported,
1388 struct phylink_link_state *state)
1389 {
1390 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1391
1392 pr_debug("In %s\n", __func__);
1393
1394 if (!phy_interface_mode_is_rgmii(state->interface) &&
1395 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1396 state->interface != PHY_INTERFACE_MODE_MII &&
1397 state->interface != PHY_INTERFACE_MODE_REVMII &&
1398 state->interface != PHY_INTERFACE_MODE_GMII &&
1399 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1400 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1401 state->interface != PHY_INTERFACE_MODE_SGMII) {
1402 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1403 pr_err("Unsupported interface: %d\n", state->interface);
1404 return;
1405 }
1406
1407 /* Allow all the expected bits */
1408 phylink_set(mask, Autoneg);
1409 phylink_set_port_modes(mask);
1410 phylink_set(mask, Pause);
1411 phylink_set(mask, Asym_Pause);
1412
1413 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1414 * including Half duplex
1415 */
1416 if (state->interface != PHY_INTERFACE_MODE_MII &&
1417 state->interface != PHY_INTERFACE_MODE_REVMII) {
1418 phylink_set(mask, 1000baseT_Full);
1419 phylink_set(mask, 1000baseT_Half);
1420 }
1421
1422 phylink_set(mask, 10baseT_Half);
1423 phylink_set(mask, 10baseT_Full);
1424 phylink_set(mask, 100baseT_Half);
1425 phylink_set(mask, 100baseT_Full);
1426
1427 bitmap_and(supported, supported, mask,
1428 __ETHTOOL_LINK_MODE_MASK_NBITS);
1429 bitmap_and(state->advertising, state->advertising, mask,
1430 __ETHTOOL_LINK_MODE_MASK_NBITS);
1431 }
1432
1433
1434 static void rtl838x_mac_config(struct phylink_config *config,
1435 unsigned int mode,
1436 const struct phylink_link_state *state)
1437 {
1438 /* This is only being called for the master device,
1439 * i.e. the CPU-Port. We don't need to do anything.
1440 */
1441
1442 pr_info("In %s, mode %x\n", __func__, mode);
1443 }
1444
1445 static void rtl838x_mac_an_restart(struct phylink_config *config)
1446 {
1447 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1448 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1449
1450 /* This works only on RTL838x chips */
1451 if (priv->family_id != RTL8380_FAMILY_ID)
1452 return;
1453
1454 pr_debug("In %s\n", __func__);
1455 /* Restart by disabling and re-enabling link */
1456 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1457 mdelay(20);
1458 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1459 }
1460
1461 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1462 struct phylink_link_state *state)
1463 {
1464 u32 speed;
1465 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1466 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1467 int port = priv->cpu_port;
1468
1469 pr_info("In %s\n", __func__);
1470
1471 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1472 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1473
1474 pr_info("%s link status is %d\n", __func__, state->link);
1475 speed = priv->r->get_mac_link_spd_sts(port);
1476 switch (speed) {
1477 case 0:
1478 state->speed = SPEED_10;
1479 break;
1480 case 1:
1481 state->speed = SPEED_100;
1482 break;
1483 case 2:
1484 state->speed = SPEED_1000;
1485 break;
1486 case 5:
1487 state->speed = SPEED_2500;
1488 break;
1489 case 6:
1490 state->speed = SPEED_5000;
1491 break;
1492 case 4:
1493 state->speed = SPEED_10000;
1494 break;
1495 default:
1496 state->speed = SPEED_UNKNOWN;
1497 break;
1498 }
1499
1500 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1501 if (priv->r->get_mac_rx_pause_sts(port))
1502 state->pause |= MLO_PAUSE_RX;
1503 if (priv->r->get_mac_tx_pause_sts(port))
1504 state->pause |= MLO_PAUSE_TX;
1505 }
1506
1507 static void rtl838x_mac_link_down(struct phylink_config *config,
1508 unsigned int mode,
1509 phy_interface_t interface)
1510 {
1511 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1512 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1513
1514 pr_debug("In %s\n", __func__);
1515 /* Stop TX/RX to port */
1516 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1517 }
1518
1519 static void rtl838x_mac_link_up(struct phylink_config *config,
1520 struct phy_device *phy, unsigned int mode,
1521 phy_interface_t interface, int speed, int duplex,
1522 bool tx_pause, bool rx_pause)
1523 {
1524 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1525 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1526
1527 pr_debug("In %s\n", __func__);
1528 /* Restart TX/RX to port */
1529 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1530 }
1531
1532 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1533 {
1534 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1535 unsigned long flags;
1536
1537 spin_lock_irqsave(&priv->lock, flags);
1538 pr_debug("In %s\n", __func__);
1539 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1540 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1541
1542 if (priv->family_id == RTL8380_FAMILY_ID) {
1543 /* 2 more registers, ALE/MAC block */
1544 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1545 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1546 (RTL838X_MAC_ALE + 4));
1547
1548 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1549 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1550 RTL838X_MAC2 + 4);
1551 }
1552 spin_unlock_irqrestore(&priv->lock, flags);
1553 }
1554
1555 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1556 {
1557 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1558 const struct sockaddr *addr = p;
1559 u8 *mac = (u8 *) (addr->sa_data);
1560
1561 if (!is_valid_ether_addr(addr->sa_data))
1562 return -EADDRNOTAVAIL;
1563
1564 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1565 rtl838x_set_mac_hw(dev, mac);
1566
1567 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1568 return 0;
1569 }
1570
1571 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1572 {
1573 // We will need to set-up EEE and the egress-rate limitation
1574 return 0;
1575 }
1576
1577 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1578 {
1579 int i;
1580
1581 if (priv->family_id == 0x8390)
1582 return rtl8390_init_mac(priv);
1583
1584 // At present we do not know how to set up EEE on any other SoC than RTL8380
1585 if (priv->family_id != 0x8380)
1586 return 0;
1587
1588 pr_info("%s\n", __func__);
1589 /* fix timer for EEE */
1590 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1591 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1592
1593 /* Init VLAN. TODO: Understand what is being done, here */
1594 if (priv->id == 0x8382) {
1595 for (i = 0; i <= 28; i++)
1596 sw_w32(0, 0xd57c + i * 0x80);
1597 }
1598 if (priv->id == 0x8380) {
1599 for (i = 8; i <= 28; i++)
1600 sw_w32(0, 0xd57c + i * 0x80);
1601 }
1602 return 0;
1603 }
1604
1605 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1606 struct ethtool_link_ksettings *cmd)
1607 {
1608 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1609
1610 pr_debug("%s called\n", __func__);
1611 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1612 }
1613
1614 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1615 const struct ethtool_link_ksettings *cmd)
1616 {
1617 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1618
1619 pr_debug("%s called\n", __func__);
1620 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1621 }
1622
1623 static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1624 {
1625 u32 val;
1626 int err;
1627 struct rtl838x_eth_priv *priv = bus->priv;
1628
1629 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1630 return rtl838x_read_sds_phy(mii_id, regnum);
1631
1632 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1633 err = rtl838x_read_mmd_phy(mii_id,
1634 mdiobus_c45_devad(regnum),
1635 regnum, &val);
1636 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1637 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1638 val, err);
1639 } else {
1640 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1641 err = rtl838x_read_phy(mii_id, page, regnum, &val);
1642 }
1643 if (err)
1644 return err;
1645 return val;
1646 }
1647
1648 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1649 {
1650 return rtl838x_mdio_read_paged(bus, mii_id, 0, regnum);
1651 }
1652
1653 static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1654 {
1655 u32 val;
1656 int err;
1657 struct rtl838x_eth_priv *priv = bus->priv;
1658
1659 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1660 return rtl839x_read_sds_phy(mii_id, regnum);
1661
1662 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1663 err = rtl839x_read_mmd_phy(mii_id,
1664 mdiobus_c45_devad(regnum),
1665 regnum, &val);
1666 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1667 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1668 val, err);
1669 } else {
1670 err = rtl839x_read_phy(mii_id, page, regnum, &val);
1671 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1672 }
1673 if (err)
1674 return err;
1675 return val;
1676 }
1677
1678 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1679 {
1680 return rtl839x_mdio_read_paged(bus, mii_id, 0, regnum);
1681 }
1682
1683 static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1684 {
1685 u32 val;
1686 int err;
1687 struct rtl838x_eth_priv *priv = bus->priv;
1688
1689 if (priv->phy_is_internal[mii_id])
1690 return rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1691
1692 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1693 err = rtl930x_read_mmd_phy(mii_id,
1694 mdiobus_c45_devad(regnum),
1695 regnum, &val);
1696 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1697 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1698 val, err);
1699 } else {
1700 err = rtl930x_read_phy(mii_id, page, regnum, &val);
1701 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1702 }
1703 if (err)
1704 return err;
1705 return val;
1706 }
1707
1708 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1709 {
1710 return rtl930x_mdio_read_paged(bus, mii_id, 0, regnum);
1711 }
1712
1713 static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1714 {
1715 u32 val;
1716 int err, v;
1717 struct rtl838x_eth_priv *priv = bus->priv;
1718
1719 pr_debug("%s: In here, port %d\n", __func__, mii_id);
1720 if (priv->phy_is_internal[mii_id]) {
1721 v = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1722 if (v < 0) {
1723 err = v;
1724 } else {
1725 err = 0;
1726 val = v;
1727 }
1728 } else {
1729 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1730 err = rtl931x_read_mmd_phy(mii_id,
1731 mdiobus_c45_devad(regnum),
1732 regnum, &val);
1733 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1734 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1735 val, err);
1736 } else {
1737 err = rtl931x_read_phy(mii_id, page, regnum, &val);
1738 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1739 }
1740 }
1741
1742 if (err)
1743 return err;
1744 return val;
1745 }
1746
1747 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1748 {
1749 return rtl931x_mdio_read_paged(bus, mii_id, 0, regnum);
1750 }
1751
1752 static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1753 int regnum, u16 value)
1754 {
1755 u32 offset = 0;
1756 struct rtl838x_eth_priv *priv = bus->priv;
1757 int err;
1758
1759 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1760 if (mii_id == 26)
1761 offset = 0x100;
1762 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1763 return 0;
1764 }
1765
1766 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1767 err = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1768 regnum, value);
1769 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1770 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1771 value, err);
1772
1773 return err;
1774 }
1775 err = rtl838x_write_phy(mii_id, page, regnum, value);
1776 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1777 return err;
1778 }
1779
1780 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1781 int regnum, u16 value)
1782 {
1783 return rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1784 }
1785
1786 static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1787 int regnum, u16 value)
1788 {
1789 struct rtl838x_eth_priv *priv = bus->priv;
1790 int err;
1791
1792 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1793 return rtl839x_write_sds_phy(mii_id, regnum, value);
1794
1795 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1796 err = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1797 regnum, value);
1798 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1799 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1800 value, err);
1801
1802 return err;
1803 }
1804
1805 err = rtl839x_write_phy(mii_id, page, regnum, value);
1806 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1807 return err;
1808 }
1809
1810 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1811 int regnum, u16 value)
1812 {
1813 return rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1814 }
1815
1816 static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1817 int regnum, u16 value)
1818 {
1819 struct rtl838x_eth_priv *priv = bus->priv;
1820 int err;
1821
1822 if (priv->phy_is_internal[mii_id])
1823 return rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1824
1825 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD))
1826 return rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1827 regnum, value);
1828
1829 err = rtl930x_write_phy(mii_id, page, regnum, value);
1830 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1831 return err;
1832 }
1833
1834 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1835 int regnum, u16 value)
1836 {
1837 return rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1838 }
1839
1840 static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1841 int regnum, u16 value)
1842 {
1843 struct rtl838x_eth_priv *priv = bus->priv;
1844 int err;
1845
1846 if (priv->phy_is_internal[mii_id])
1847 return rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1848
1849 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1850 err = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1851 regnum, value);
1852 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1853 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1854 value, err);
1855
1856 return err;
1857 }
1858
1859 err = rtl931x_write_phy(mii_id, page, regnum, value);
1860 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1861 return err;
1862 }
1863
1864 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1865 int regnum, u16 value)
1866 {
1867 return rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1868 }
1869
1870 static int rtl838x_mdio_reset(struct mii_bus *bus)
1871 {
1872 pr_debug("%s called\n", __func__);
1873 /* Disable MAC polling the PHY so that we can start configuration */
1874 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1875
1876 /* Enable PHY control via SoC */
1877 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1878
1879 // Probably should reset all PHYs here...
1880 return 0;
1881 }
1882
1883 static int rtl839x_mdio_reset(struct mii_bus *bus)
1884 {
1885 return 0;
1886
1887 pr_debug("%s called\n", __func__);
1888 /* BUG: The following does not work, but should! */
1889 /* Disable MAC polling the PHY so that we can start configuration */
1890 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1891 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1892 /* Disable PHY polling via SoC */
1893 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1894
1895 // Probably should reset all PHYs here...
1896 return 0;
1897 }
1898
1899 u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1900 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1901
1902 static int rtl930x_mdio_reset(struct mii_bus *bus)
1903 {
1904 int i;
1905 int pos;
1906 struct rtl838x_eth_priv *priv = bus->priv;
1907 u32 c45_mask = 0;
1908 u32 poll_sel[2];
1909 u32 poll_ctrl = 0;
1910 u32 private_poll_mask = 0;
1911 u32 v;
1912 bool uses_usxgmii = false; // For the Aquantia PHYs
1913 bool uses_hisgmii = false; // For the RTL8221/8226
1914
1915 // Mapping of port to phy-addresses on an SMI bus
1916 poll_sel[0] = poll_sel[1] = 0;
1917 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1918 if (priv->smi_bus[i] > 3)
1919 continue;
1920 pos = (i % 6) * 5;
1921 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1922 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1923
1924 pos = (i * 2) % 32;
1925 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1926 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1927 }
1928
1929 // Configure which SMI bus is behind which port number
1930 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1931 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1932
1933 // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+)
1934 sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
1935
1936 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1937 for (i = 0; i < 4; i++)
1938 if (priv->smi_bus_isc45[i])
1939 c45_mask |= BIT(i + 16);
1940
1941 pr_info("c45_mask: %08x\n", c45_mask);
1942 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1943
1944 // Set the MAC type of each port according to the PHY-interface
1945 // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0
1946 v = 0;
1947 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1948 switch (priv->interfaces[i]) {
1949 case PHY_INTERFACE_MODE_10GBASER:
1950 break; // Serdes: Value = 0
1951
1952 case PHY_INTERFACE_MODE_HSGMII:
1953 private_poll_mask |= BIT(i);
1954 // fallthrough
1955 case PHY_INTERFACE_MODE_USXGMII:
1956 v |= BIT(mac_type_bit[i]);
1957 uses_usxgmii = true;
1958 break;
1959
1960 case PHY_INTERFACE_MODE_QSGMII:
1961 private_poll_mask |= BIT(i);
1962 v |= 3 << mac_type_bit[i];
1963 break;
1964
1965 default:
1966 break;
1967 }
1968 }
1969 sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);
1970
1971 // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones)
1972 sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);
1973
1974 /* The following magic values are found in the port configuration, they seem to
1975 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1976 * the XGS1250 and the RTL8226 of the XGS1210 */
1977 if (uses_usxgmii) {
1978 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1979 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1980 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1981 }
1982 if (uses_hisgmii) {
1983 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1984 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1985 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1986 }
1987
1988 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__,
1989 sw_r32(RTL930X_SMI_GLB_CTRL));
1990 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__,
1991 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));
1992 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__,
1993 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
1994 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__,
1995 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));
1996 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__,
1997 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));
1998 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__,
1999 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));
2000 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__,
2001 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));
2002 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__,
2003 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));
2004 return 0;
2005 }
2006
2007 static int rtl931x_mdio_reset(struct mii_bus *bus)
2008 {
2009 int i;
2010 int pos;
2011 struct rtl838x_eth_priv *priv = bus->priv;
2012 u32 c45_mask = 0;
2013 u32 poll_sel[4];
2014 u32 poll_ctrl = 0;
2015 bool mdc_on[4];
2016
2017 pr_info("%s called\n", __func__);
2018 // Disable port polling for configuration purposes
2019 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
2020 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
2021 msleep(100);
2022
2023 mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
2024 // Mapping of port to phy-addresses on an SMI bus
2025 poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
2026 for (i = 0; i < 56; i++) {
2027 pos = (i % 6) * 5;
2028 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
2029 pos = (i * 2) % 32;
2030 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
2031 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
2032 mdc_on[priv->smi_bus[i]] = true;
2033 }
2034
2035 // Configure which SMI bus is behind which port number
2036 for (i = 0; i < 4; i++) {
2037 pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
2038 sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
2039 }
2040
2041 // Configure which SMI busses
2042 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2043 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2044 for (i = 0; i < 4; i++) {
2045 // bus is polled in c45
2046 if (priv->smi_bus_isc45[i])
2047 c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3
2048 // Enable bus access via MDC
2049 if (mdc_on[i])
2050 sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
2051 }
2052
2053 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2054 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2055
2056 /* We have a 10G PHY enable polling
2057 sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
2058 sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
2059 sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
2060 */
2061 sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
2062
2063 return 0;
2064 }
2065
2066 static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
2067 {
2068 pr_info("In %s\n", __func__);
2069
2070 // Initialize Encapsulation memory and wait until finished
2071 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
2072 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
2073 pr_info("%s: init ENCAP done\n", __func__);
2074
2075 // Initialize Managemen Information Base memory and wait until finished
2076 sw_w32(0x1, RTL931X_MEM_MIB_INIT);
2077 do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
2078 pr_info("%s: init MIB done\n", __func__);
2079
2080 // Initialize ACL (PIE) memory and wait until finished
2081 sw_w32(0x1, RTL931X_MEM_ACL_INIT);
2082 do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
2083 pr_info("%s: init ACL done\n", __func__);
2084
2085 // Initialize ALE memory and wait until finished
2086 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
2087 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
2088 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
2089 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
2090 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
2091 pr_info("%s: init ALE done\n", __func__);
2092
2093 // Enable ESD auto recovery
2094 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
2095
2096 // Init SPI, is this for thermal control or what?
2097 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
2098
2099 return 0;
2100 }
2101
2102 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
2103 {
2104 struct device_node *mii_np, *dn;
2105 u32 pn;
2106 int ret;
2107
2108 pr_debug("%s called\n", __func__);
2109 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
2110
2111 if (!mii_np) {
2112 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
2113 return -ENODEV;
2114 }
2115
2116 if (!of_device_is_available(mii_np)) {
2117 ret = -ENODEV;
2118 goto err_put_node;
2119 }
2120
2121 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
2122 if (!priv->mii_bus) {
2123 ret = -ENOMEM;
2124 goto err_put_node;
2125 }
2126
2127 switch(priv->family_id) {
2128 case RTL8380_FAMILY_ID:
2129 priv->mii_bus->name = "rtl838x-eth-mdio";
2130 priv->mii_bus->read = rtl838x_mdio_read;
2131 priv->mii_bus->read_paged = rtl838x_mdio_read_paged;
2132 priv->mii_bus->write = rtl838x_mdio_write;
2133 priv->mii_bus->write_paged = rtl838x_mdio_write_paged;
2134 priv->mii_bus->reset = rtl838x_mdio_reset;
2135 break;
2136 case RTL8390_FAMILY_ID:
2137 priv->mii_bus->name = "rtl839x-eth-mdio";
2138 priv->mii_bus->read = rtl839x_mdio_read;
2139 priv->mii_bus->read_paged = rtl839x_mdio_read_paged;
2140 priv->mii_bus->write = rtl839x_mdio_write;
2141 priv->mii_bus->write_paged = rtl839x_mdio_write_paged;
2142 priv->mii_bus->reset = rtl839x_mdio_reset;
2143 break;
2144 case RTL9300_FAMILY_ID:
2145 priv->mii_bus->name = "rtl930x-eth-mdio";
2146 priv->mii_bus->read = rtl930x_mdio_read;
2147 priv->mii_bus->read_paged = rtl930x_mdio_read_paged;
2148 priv->mii_bus->write = rtl930x_mdio_write;
2149 priv->mii_bus->write_paged = rtl930x_mdio_write_paged;
2150 priv->mii_bus->reset = rtl930x_mdio_reset;
2151 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2152 break;
2153 case RTL9310_FAMILY_ID:
2154 priv->mii_bus->name = "rtl931x-eth-mdio";
2155 priv->mii_bus->read = rtl931x_mdio_read;
2156 priv->mii_bus->read_paged = rtl931x_mdio_read_paged;
2157 priv->mii_bus->write = rtl931x_mdio_write;
2158 priv->mii_bus->write_paged = rtl931x_mdio_write_paged;
2159 priv->mii_bus->reset = rtl931x_mdio_reset;
2160 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2161 break;
2162 }
2163 priv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD;
2164 priv->mii_bus->priv = priv;
2165 priv->mii_bus->parent = &priv->pdev->dev;
2166
2167 for_each_node_by_name(dn, "ethernet-phy") {
2168 u32 smi_addr[2];
2169
2170 if (of_property_read_u32(dn, "reg", &pn))
2171 continue;
2172
2173 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
2174 smi_addr[0] = 0;
2175 smi_addr[1] = pn;
2176 }
2177
2178 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
2179 priv->sds_id[pn] = -1;
2180 else {
2181 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
2182 }
2183
2184 if (pn < MAX_PORTS) {
2185 priv->smi_bus[pn] = smi_addr[0];
2186 priv->smi_addr[pn] = smi_addr[1];
2187 } else {
2188 pr_err("%s: illegal port number %d\n", __func__, pn);
2189 }
2190
2191 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
2192 priv->smi_bus_isc45[smi_addr[0]] = true;
2193
2194 if (of_property_read_bool(dn, "phy-is-integrated")) {
2195 priv->phy_is_internal[pn] = true;
2196 }
2197 }
2198
2199 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
2200 if (!dn) {
2201 dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n");
2202 return -ENODEV;
2203 }
2204
2205 for_each_node_by_name(dn, "port") {
2206 if (of_property_read_u32(dn, "reg", &pn))
2207 continue;
2208 pr_debug("%s Looking at port %d\n", __func__, pn);
2209 if (pn > priv->cpu_port)
2210 continue;
2211 if (of_get_phy_mode(dn, &priv->interfaces[pn]))
2212 priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
2213 pr_debug("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn]));
2214 }
2215
2216 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
2217 ret = of_mdiobus_register(priv->mii_bus, mii_np);
2218
2219 err_put_node:
2220 of_node_put(mii_np);
2221 return ret;
2222 }
2223
2224 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
2225 {
2226 pr_debug("%s called\n", __func__);
2227 if (!priv->mii_bus)
2228 return 0;
2229
2230 mdiobus_unregister(priv->mii_bus);
2231 mdiobus_free(priv->mii_bus);
2232
2233 return 0;
2234 }
2235
2236 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
2237 netdev_features_t features)
2238 {
2239 return features;
2240 }
2241
2242 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
2243 {
2244 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2245
2246 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2247 if (!(features & NETIF_F_RXCSUM))
2248 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2249 else
2250 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
2251 }
2252
2253 return 0;
2254 }
2255
2256 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
2257 {
2258 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2259
2260 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2261 if (!(features & NETIF_F_RXCSUM))
2262 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2263 else
2264 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2265 }
2266
2267 return 0;
2268 }
2269
2270 static const struct net_device_ops rtl838x_eth_netdev_ops = {
2271 .ndo_open = rtl838x_eth_open,
2272 .ndo_stop = rtl838x_eth_stop,
2273 .ndo_start_xmit = rtl838x_eth_tx,
2274 .ndo_select_queue = rtl83xx_pick_tx_queue,
2275 .ndo_set_mac_address = rtl838x_set_mac_address,
2276 .ndo_validate_addr = eth_validate_addr,
2277 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
2278 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2279 .ndo_set_features = rtl83xx_set_features,
2280 .ndo_fix_features = rtl838x_fix_features,
2281 .ndo_setup_tc = rtl83xx_setup_tc,
2282 };
2283
2284 static const struct net_device_ops rtl839x_eth_netdev_ops = {
2285 .ndo_open = rtl838x_eth_open,
2286 .ndo_stop = rtl838x_eth_stop,
2287 .ndo_start_xmit = rtl838x_eth_tx,
2288 .ndo_select_queue = rtl83xx_pick_tx_queue,
2289 .ndo_set_mac_address = rtl838x_set_mac_address,
2290 .ndo_validate_addr = eth_validate_addr,
2291 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
2292 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2293 .ndo_set_features = rtl83xx_set_features,
2294 .ndo_fix_features = rtl838x_fix_features,
2295 .ndo_setup_tc = rtl83xx_setup_tc,
2296 };
2297
2298 static const struct net_device_ops rtl930x_eth_netdev_ops = {
2299 .ndo_open = rtl838x_eth_open,
2300 .ndo_stop = rtl838x_eth_stop,
2301 .ndo_start_xmit = rtl838x_eth_tx,
2302 .ndo_select_queue = rtl93xx_pick_tx_queue,
2303 .ndo_set_mac_address = rtl838x_set_mac_address,
2304 .ndo_validate_addr = eth_validate_addr,
2305 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
2306 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2307 .ndo_set_features = rtl93xx_set_features,
2308 .ndo_fix_features = rtl838x_fix_features,
2309 .ndo_setup_tc = rtl83xx_setup_tc,
2310 };
2311
2312 static const struct net_device_ops rtl931x_eth_netdev_ops = {
2313 .ndo_open = rtl838x_eth_open,
2314 .ndo_stop = rtl838x_eth_stop,
2315 .ndo_start_xmit = rtl838x_eth_tx,
2316 .ndo_select_queue = rtl93xx_pick_tx_queue,
2317 .ndo_set_mac_address = rtl838x_set_mac_address,
2318 .ndo_validate_addr = eth_validate_addr,
2319 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
2320 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2321 .ndo_set_features = rtl93xx_set_features,
2322 .ndo_fix_features = rtl838x_fix_features,
2323 };
2324
2325 static const struct phylink_mac_ops rtl838x_phylink_ops = {
2326 .validate = rtl838x_validate,
2327 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
2328 .mac_an_restart = rtl838x_mac_an_restart,
2329 .mac_config = rtl838x_mac_config,
2330 .mac_link_down = rtl838x_mac_link_down,
2331 .mac_link_up = rtl838x_mac_link_up,
2332 };
2333
2334 static const struct ethtool_ops rtl838x_ethtool_ops = {
2335 .get_link_ksettings = rtl838x_get_link_ksettings,
2336 .set_link_ksettings = rtl838x_set_link_ksettings,
2337 };
2338
2339 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2340 {
2341 struct net_device *dev;
2342 struct device_node *dn = pdev->dev.of_node;
2343 struct rtl838x_eth_priv *priv;
2344 struct resource *res, *mem;
2345 phy_interface_t phy_mode;
2346 struct phylink *phylink;
2347 int err = 0, i, rxrings, rxringlen;
2348 struct ring_b *ring;
2349
2350 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2351 (u32)pdev, (u32)(&(pdev->dev)));
2352
2353 if (!dn) {
2354 dev_err(&pdev->dev, "No DT found\n");
2355 return -EINVAL;
2356 }
2357
2358 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2359 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2360 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2361 rxringlen = MAX_ENTRIES / rxrings;
2362 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2363
2364 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2365 if (!dev) {
2366 err = -ENOMEM;
2367 goto err_free;
2368 }
2369 SET_NETDEV_DEV(dev, &pdev->dev);
2370 priv = netdev_priv(dev);
2371
2372 /* obtain buffer memory space */
2373 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2374 if (res) {
2375 mem = devm_request_mem_region(&pdev->dev, res->start,
2376 resource_size(res), res->name);
2377 if (!mem) {
2378 dev_err(&pdev->dev, "cannot request memory space\n");
2379 err = -ENXIO;
2380 goto err_free;
2381 }
2382
2383 dev->mem_start = mem->start;
2384 dev->mem_end = mem->end;
2385 } else {
2386 dev_err(&pdev->dev, "cannot request IO resource\n");
2387 err = -ENXIO;
2388 goto err_free;
2389 }
2390
2391 /* Allocate buffer memory */
2392 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2393 + sizeof(struct ring_b) + sizeof(struct notify_b),
2394 (void *)&dev->mem_start, GFP_KERNEL);
2395 if (!priv->membase) {
2396 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2397 err = -ENOMEM;
2398 goto err_free;
2399 }
2400
2401 // Allocate ring-buffer space at the end of the allocated memory
2402 ring = priv->membase;
2403 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2404
2405 spin_lock_init(&priv->lock);
2406
2407 dev->ethtool_ops = &rtl838x_ethtool_ops;
2408 dev->min_mtu = ETH_ZLEN;
2409 dev->max_mtu = 1536;
2410 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2411 dev->hw_features = NETIF_F_RXCSUM;
2412
2413 priv->id = soc_info.id;
2414 priv->family_id = soc_info.family;
2415 if (priv->id) {
2416 pr_info("Found SoC ID: %4x: %s, family %x\n",
2417 priv->id, soc_info.name, priv->family_id);
2418 } else {
2419 pr_err("Unknown chip id (%04x)\n", priv->id);
2420 return -ENODEV;
2421 }
2422
2423 switch (priv->family_id) {
2424 case RTL8380_FAMILY_ID:
2425 priv->cpu_port = RTL838X_CPU_PORT;
2426 priv->r = &rtl838x_reg;
2427 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2428 break;
2429 case RTL8390_FAMILY_ID:
2430 priv->cpu_port = RTL839X_CPU_PORT;
2431 priv->r = &rtl839x_reg;
2432 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2433 break;
2434 case RTL9300_FAMILY_ID:
2435 priv->cpu_port = RTL930X_CPU_PORT;
2436 priv->r = &rtl930x_reg;
2437 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2438 break;
2439 case RTL9310_FAMILY_ID:
2440 priv->cpu_port = RTL931X_CPU_PORT;
2441 priv->r = &rtl931x_reg;
2442 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2443 rtl931x_chip_init(priv);
2444 break;
2445 default:
2446 pr_err("Unknown SoC family\n");
2447 return -ENODEV;
2448 }
2449 priv->rxringlen = rxringlen;
2450 priv->rxrings = rxrings;
2451
2452 /* Obtain device IRQ number */
2453 dev->irq = platform_get_irq(pdev, 0);
2454 if (dev->irq < 0) {
2455 dev_err(&pdev->dev, "cannot obtain network-device IRQ\n");
2456 goto err_free;
2457 }
2458
2459 err = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq,
2460 IRQF_SHARED, dev->name, dev);
2461 if (err) {
2462 dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n",
2463 __func__, err);
2464 goto err_free;
2465 }
2466
2467 rtl8380_init_mac(priv);
2468
2469 /* try to get mac address in the following order:
2470 * 1) from device tree data
2471 * 2) from internal registers set by bootloader
2472 */
2473 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2474 if (is_valid_ether_addr(dev->dev_addr)) {
2475 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2476 } else {
2477 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2478 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2479 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2480 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2481 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2482 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2483 }
2484 /* if the address is invalid, use a random value */
2485 if (!is_valid_ether_addr(dev->dev_addr)) {
2486 struct sockaddr sa = { AF_UNSPEC };
2487
2488 netdev_warn(dev, "Invalid MAC address, using random\n");
2489 eth_hw_addr_random(dev);
2490 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2491 if (rtl838x_set_mac_address(dev, &sa))
2492 netdev_warn(dev, "Failed to set MAC address.\n");
2493 }
2494 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2495 sw_r32(priv->r->mac + 4));
2496 strcpy(dev->name, "eth%d");
2497 priv->pdev = pdev;
2498 priv->netdev = dev;
2499
2500 err = rtl838x_mdio_init(priv);
2501 if (err)
2502 goto err_free;
2503
2504 err = register_netdev(dev);
2505 if (err)
2506 goto err_free;
2507
2508 for (i = 0; i < priv->rxrings; i++) {
2509 priv->rx_qs[i].id = i;
2510 priv->rx_qs[i].priv = priv;
2511 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2512 }
2513
2514 platform_set_drvdata(pdev, dev);
2515
2516 phy_mode = PHY_INTERFACE_MODE_NA;
2517 err = of_get_phy_mode(dn, &phy_mode);
2518 if (err < 0) {
2519 dev_err(&pdev->dev, "incorrect phy-mode\n");
2520 err = -EINVAL;
2521 goto err_free;
2522 }
2523 priv->phylink_config.dev = &dev->dev;
2524 priv->phylink_config.type = PHYLINK_NETDEV;
2525
2526 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2527 phy_mode, &rtl838x_phylink_ops);
2528
2529 if (IS_ERR(phylink)) {
2530 err = PTR_ERR(phylink);
2531 goto err_free;
2532 }
2533 priv->phylink = phylink;
2534
2535 return 0;
2536
2537 err_free:
2538 pr_err("Error setting up netdev, freeing it again.\n");
2539 free_netdev(dev);
2540 return err;
2541 }
2542
2543 static int rtl838x_eth_remove(struct platform_device *pdev)
2544 {
2545 struct net_device *dev = platform_get_drvdata(pdev);
2546 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2547 int i;
2548
2549 if (dev) {
2550 pr_info("Removing platform driver for rtl838x-eth\n");
2551 rtl838x_mdio_remove(priv);
2552 rtl838x_hw_stop(priv);
2553
2554 netif_tx_stop_all_queues(dev);
2555
2556 for (i = 0; i < priv->rxrings; i++)
2557 netif_napi_del(&priv->rx_qs[i].napi);
2558
2559 unregister_netdev(dev);
2560 free_netdev(dev);
2561 }
2562 return 0;
2563 }
2564
2565 static const struct of_device_id rtl838x_eth_of_ids[] = {
2566 { .compatible = "realtek,rtl838x-eth"},
2567 { /* sentinel */ }
2568 };
2569 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2570
2571 static struct platform_driver rtl838x_eth_driver = {
2572 .probe = rtl838x_eth_probe,
2573 .remove = rtl838x_eth_remove,
2574 .driver = {
2575 .name = "rtl838x-eth",
2576 .pm = NULL,
2577 .of_match_table = rtl838x_eth_of_ids,
2578 },
2579 };
2580
2581 module_platform_driver(rtl838x_eth_driver);
2582
2583 MODULE_AUTHOR("B. Koblitz");
2584 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2585 MODULE_LICENSE("GPL");
Staging tree of Matthias Schiffer