1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
27 extern struct rtl83xx_soc_info soc_info
;
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
37 #define MAX_RXRINGS 32
39 #define MAX_ENTRIES (200 * 8)
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
51 #define MAX_SMI_BUSSES 4
53 #define RING_BUFFER 1600
58 uint16_t size
; /* buffer size */
60 uint16_t len
; /* pkt len */
62 } __packed
__aligned(1);
71 } __packed
__aligned(1);
74 uint32_t rx_r
[MAX_RXRINGS
][MAX_RXLEN
];
75 uint32_t tx_r
[TXRINGS
][TXRINGLEN
];
76 struct p_hdr rx_header
[MAX_RXRINGS
][MAX_RXLEN
];
77 struct p_hdr tx_header
[TXRINGS
][TXRINGLEN
];
78 uint32_t c_rx
[MAX_RXRINGS
];
79 uint32_t c_tx
[TXRINGS
];
80 uint8_t tx_space
[TXRINGS
* TXRINGLEN
* RING_BUFFER
];
85 struct n_event events
[NOTIFY_EVENTS
];
89 struct notify_block blocks
[NOTIFY_BLOCKS
];
91 u32 ring
[NOTIFY_BLOCKS
];
95 static void rtl838x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
100 // cpu_tag[0] is reserved on the RTL83XX SoCs
101 h
->cpu_tag
[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
102 h
->cpu_tag
[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
103 h
->cpu_tag
[3] = 0x0000;
104 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
105 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
106 // Set internal priority and AS_PRIO
108 h
->cpu_tag
[2] |= (prio
| 0x8) << 12;
112 static void rtl839x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
117 // cpu_tag[0] is reserved on the RTL83XX SoCs
118 h
->cpu_tag
[1] = 0x0100; // RTL8390_CPU_TAG marker
119 h
->cpu_tag
[2] = h
->cpu_tag
[3] = h
->cpu_tag
[4] = h
->cpu_tag
[5] = 0;
120 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
121 if (dest_port
>= 32) {
123 h
->cpu_tag
[2] = BIT(dest_port
) >> 16;
124 h
->cpu_tag
[3] = BIT(dest_port
) & 0xffff;
126 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
127 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
129 h
->cpu_tag
[2] |= BIT(20); // Enable destination port mask use
130 h
->cpu_tag
[2] |= BIT(23); // Enable L2 Learning
131 // Set internal priority and AS_PRIO
133 h
->cpu_tag
[1] |= prio
| BIT(3);
137 static void rtl930x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
139 h
->cpu_tag
[0] = 0x8000; // CPU tag marker
140 h
->cpu_tag
[1] = h
->cpu_tag
[2] = 0;
142 h
->cpu_tag
[2] = BIT(13) | prio
<< 8; // Enable and set Priority Queue
146 h
->cpu_tag
[6] = BIT(dest_port
) >> 16;
147 h
->cpu_tag
[7] = BIT(dest_port
) & 0xffff;
150 static void rtl931x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
152 h
->cpu_tag
[0] = 0x8000; // CPU tag marker
153 h
->cpu_tag
[1] = h
->cpu_tag
[2] = 0;
155 h
->cpu_tag
[2] = BIT(13) | prio
<< 8; // Enable and set Priority Queue
157 h
->cpu_tag
[4] = h
->cpu_tag
[5] = h
->cpu_tag
[6] = h
->cpu_tag
[7] = 0;
158 if (dest_port
>= 32) {
160 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
161 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
163 h
->cpu_tag
[6] = BIT(dest_port
) >> 16;
164 h
->cpu_tag
[7] = BIT(dest_port
) & 0xffff;
168 struct rtl838x_rx_q
{
170 struct rtl838x_eth_priv
*priv
;
171 struct napi_struct napi
;
174 struct rtl838x_eth_priv
{
175 struct net_device
*netdev
;
176 struct platform_device
*pdev
;
179 struct mii_bus
*mii_bus
;
180 struct rtl838x_rx_q rx_qs
[MAX_RXRINGS
];
181 struct phylink
*phylink
;
182 struct phylink_config phylink_config
;
185 const struct rtl838x_reg
*r
;
190 u8 smi_bus
[MAX_PORTS
];
191 u8 smi_addr
[MAX_PORTS
];
192 bool smi_bus_isc45
[MAX_SMI_BUSSES
];
193 bool phy_is_internal
[MAX_PORTS
];
196 extern int rtl838x_phy_init(struct rtl838x_eth_priv
*priv
);
197 extern int rtl838x_read_sds_phy(int phy_addr
, int phy_reg
);
198 extern int rtl839x_read_sds_phy(int phy_addr
, int phy_reg
);
199 extern int rtl839x_write_sds_phy(int phy_addr
, int phy_reg
, u16 v
);
200 extern int rtl930x_read_sds_phy(int phy_addr
, int page
, int phy_reg
);
201 extern int rtl930x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
);
202 extern int rtl930x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
203 extern int rtl930x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
);
206 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
207 * the rings. Writing x into these registers substracts x from its content.
208 * When the content reaches the ring size, the ASIC no longer adds
209 * packets to this receive queue.
211 void rtl838x_update_cntr(int r
, int released
)
213 // This feature is not available on RTL838x SoCs
216 void rtl839x_update_cntr(int r
, int released
)
218 // This feature is not available on RTL839x SoCs
221 void rtl930x_update_cntr(int r
, int released
)
223 int pos
= (r
% 3) * 10;
224 u32 reg
= RTL930X_DMA_IF_RX_RING_CNTR
+ ((r
/ 3) << 2);
227 v
= (v
>> pos
) & 0x3ff;
228 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released
, v
, pos
, reg
);
229 sw_w32_mask(0x3ff << pos
, released
<< pos
, reg
);
233 void rtl931x_update_cntr(int r
, int released
)
235 int pos
= (r
% 3) * 10;
236 u32 reg
= RTL931X_DMA_IF_RX_RING_CNTR
+ ((r
/ 3) << 2);
238 sw_w32_mask(0x3ff << pos
, released
<< pos
, reg
);
250 bool rtl838x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
252 t
->reason
= h
->cpu_tag
[3] & 0xf;
253 t
->queue
= (h
->cpu_tag
[0] & 0xe0) >> 5;
254 t
->port
= h
->cpu_tag
[1] & 0x1f;
255 t
->crc_error
= t
->reason
== 13;
257 pr_debug("Reason: %d\n", t
->reason
);
258 if (t
->reason
!= 4) // NIC_RX_REASON_SPECIAL_TRAP
263 return t
->l2_offloaded
;
266 bool rtl839x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
268 t
->reason
= h
->cpu_tag
[4] & 0x1f;
269 t
->queue
= (h
->cpu_tag
[3] & 0xe000) >> 13;
270 t
->port
= h
->cpu_tag
[1] & 0x3f;
271 t
->crc_error
= h
->cpu_tag
[3] & BIT(2);
273 pr_debug("Reason: %d\n", t
->reason
);
274 if ((t
->reason
!= 7) && (t
->reason
!= 8)) // NIC_RX_REASON_RMA_USR
279 return t
->l2_offloaded
;
282 bool rtl930x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
284 t
->reason
= h
->cpu_tag
[7] & 0x3f;
285 t
->queue
= (h
->cpu_tag
[2] >> 11) & 0x1f;
286 t
->port
= (h
->cpu_tag
[0] >> 8) & 0x1f;
287 t
->crc_error
= h
->cpu_tag
[1] & BIT(6);
289 pr_debug("Reason %d, port %d, queue %d\n", t
->reason
, t
->port
, t
->queue
);
290 if (t
->reason
>= 19 && t
->reason
<= 27)
295 return t
->l2_offloaded
;
298 bool rtl931x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
300 t
->reason
= h
->cpu_tag
[7] & 0x3f;
301 t
->queue
= (h
->cpu_tag
[2] >> 11) & 0x1f;
302 t
->port
= (h
->cpu_tag
[0] >> 8) & 0x3f;
303 t
->crc_error
= h
->cpu_tag
[1] & BIT(6);
305 pr_debug("Reason %d, port %d, queue %d\n", t
->reason
, t
->port
, t
->queue
);
306 if (t
->reason
>= 19 && t
->reason
<= 27)
311 return t
->l2_offloaded
;
315 * Discard the RX ring-buffers, called as part of the net-ISR
316 * when the buffer runs over
317 * Caller needs to hold priv->lock
319 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv
*priv
, int status
)
324 struct ring_b
*ring
= priv
->membase
;
326 for (r
= 0; r
< priv
->rxrings
; r
++) {
327 pr_debug("In %s working on r: %d\n", __func__
, r
);
328 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
330 if ((ring
->rx_r
[r
][ring
->c_rx
[r
]] & 0x1))
332 pr_debug("Got something: %d\n", ring
->c_rx
[r
]);
333 h
= &ring
->rx_header
[r
][ring
->c_rx
[r
]];
334 memset(h
, 0, sizeof(struct p_hdr
));
335 h
->buf
= (u8
*)KSEG1ADDR(ring
->rx_space
336 + r
* priv
->rxringlen
* RING_BUFFER
337 + ring
->c_rx
[r
] * RING_BUFFER
);
338 h
->size
= RING_BUFFER
;
339 /* make sure the header is visible to the ASIC */
342 ring
->rx_r
[r
][ring
->c_rx
[r
]] = KSEG1ADDR(h
) | 0x1
343 | (ring
->c_rx
[r
] == (priv
->rxringlen
- 1) ? WRAP
: 0x1);
344 ring
->c_rx
[r
] = (ring
->c_rx
[r
] + 1) % priv
->rxringlen
;
345 } while (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
);
349 struct fdb_update_work
{
350 struct work_struct work
;
351 struct net_device
*ndev
;
352 u64 macs
[NOTIFY_EVENTS
+ 1];
355 void rtl838x_fdb_sync(struct work_struct
*work
)
357 const struct fdb_update_work
*uw
=
358 container_of(work
, struct fdb_update_work
, work
);
359 struct switchdev_notifier_fdb_info info
;
364 while (uw
->macs
[i
]) {
365 action
= (uw
->macs
[i
] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
366 : SWITCHDEV_FDB_DEL_TO_BRIDGE
;
367 u64_to_ether_addr(uw
->macs
[i
] & 0xffffffffffffULL
, addr
);
368 info
.addr
= &addr
[0];
371 pr_debug("FDB entry %d: %llx, action %d\n", i
, uw
->macs
[0], action
);
372 call_switchdev_notifiers(action
, uw
->ndev
, &info
.info
, NULL
);
378 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv
*priv
)
380 struct notify_b
*nb
= priv
->membase
+ sizeof(struct ring_b
);
381 u32 e
= priv
->lastEvent
;
382 struct n_event
*event
;
385 struct fdb_update_work
*w
;
387 while (!(nb
->ring
[e
] & 1)) {
388 w
= kzalloc(sizeof(*w
), GFP_ATOMIC
);
390 pr_err("Out of memory: %s", __func__
);
393 INIT_WORK(&w
->work
, rtl838x_fdb_sync
);
395 for (i
= 0; i
< NOTIFY_EVENTS
; i
++) {
396 event
= &nb
->blocks
[e
].events
[i
];
402 w
->ndev
= priv
->netdev
;
406 /* Hand the ring entry back to the switch */
407 nb
->ring
[e
] = nb
->ring
[e
] | 1;
408 e
= (e
+ 1) % NOTIFY_BLOCKS
;
411 schedule_work(&w
->work
);
416 static irqreturn_t
rtl83xx_net_irq(int irq
, void *dev_id
)
418 struct net_device
*dev
= dev_id
;
419 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
420 u32 status
= sw_r32(priv
->r
->dma_if_intr_sts
);
423 pr_debug("IRQ: %08x\n", status
);
425 spin_lock(&priv
->lock
);
426 /* Ignore TX interrupt */
427 if ((status
& 0xf0000)) {
429 sw_w32(0x000f0000, priv
->r
->dma_if_intr_sts
);
433 if (status
& 0x0ff00) {
434 /* ACK and disable RX interrupt for this ring */
435 sw_w32_mask(0xff00 & status
, 0, priv
->r
->dma_if_intr_msk
);
436 sw_w32(0x0000ff00 & status
, priv
->r
->dma_if_intr_sts
);
437 for (i
= 0; i
< priv
->rxrings
; i
++) {
438 if (status
& BIT(i
+ 8)) {
439 pr_debug("Scheduling queue: %d\n", i
);
440 napi_schedule(&priv
->rx_qs
[i
].napi
);
445 /* RX buffer overrun */
446 if (status
& 0x000ff) {
447 pr_debug("RX buffer overrun: status %x, mask: %x\n",
448 status
, sw_r32(priv
->r
->dma_if_intr_msk
));
449 sw_w32(status
, priv
->r
->dma_if_intr_sts
);
450 rtl838x_rb_cleanup(priv
, status
& 0xff);
453 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00100000) {
454 sw_w32(0x00100000, priv
->r
->dma_if_intr_sts
);
455 rtl839x_l2_notification_handler(priv
);
458 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00200000) {
459 sw_w32(0x00200000, priv
->r
->dma_if_intr_sts
);
460 rtl839x_l2_notification_handler(priv
);
463 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00400000) {
464 sw_w32(0x00400000, priv
->r
->dma_if_intr_sts
);
465 rtl839x_l2_notification_handler(priv
);
468 spin_unlock(&priv
->lock
);
472 static irqreturn_t
rtl93xx_net_irq(int irq
, void *dev_id
)
474 struct net_device
*dev
= dev_id
;
475 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
476 u32 status_rx_r
= sw_r32(priv
->r
->dma_if_intr_rx_runout_sts
);
477 u32 status_rx
= sw_r32(priv
->r
->dma_if_intr_rx_done_sts
);
478 u32 status_tx
= sw_r32(priv
->r
->dma_if_intr_tx_done_sts
);
481 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
482 __func__
, status_tx
, status_rx
, status_rx_r
);
483 spin_lock(&priv
->lock
);
485 /* Ignore TX interrupt */
488 pr_debug("TX done\n");
489 sw_w32(status_tx
, priv
->r
->dma_if_intr_tx_done_sts
);
494 pr_debug("RX IRQ\n");
495 /* ACK and disable RX interrupt for given rings */
496 sw_w32(status_rx
, priv
->r
->dma_if_intr_rx_done_sts
);
497 sw_w32_mask(status_rx
, 0, priv
->r
->dma_if_intr_rx_done_msk
);
498 for (i
= 0; i
< priv
->rxrings
; i
++) {
499 if (status_rx
& BIT(i
)) {
500 pr_debug("Scheduling queue: %d\n", i
);
501 napi_schedule(&priv
->rx_qs
[i
].napi
);
506 /* RX buffer overrun */
508 pr_debug("RX buffer overrun: status %x, mask: %x\n",
509 status_rx_r
, sw_r32(priv
->r
->dma_if_intr_rx_runout_msk
));
510 sw_w32(status_rx_r
, priv
->r
->dma_if_intr_rx_runout_sts
);
511 rtl838x_rb_cleanup(priv
, status_rx_r
);
514 spin_unlock(&priv
->lock
);
518 static const struct rtl838x_reg rtl838x_reg
= {
519 .net_irq
= rtl83xx_net_irq
,
520 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
521 .dma_if_intr_sts
= RTL838X_DMA_IF_INTR_STS
,
522 .dma_if_intr_msk
= RTL838X_DMA_IF_INTR_MSK
,
523 .dma_if_ctrl
= RTL838X_DMA_IF_CTRL
,
524 .mac_force_mode_ctrl
= RTL838X_MAC_FORCE_MODE_CTRL
,
525 .dma_rx_base
= RTL838X_DMA_RX_BASE
,
526 .dma_tx_base
= RTL838X_DMA_TX_BASE
,
527 .dma_if_rx_ring_size
= rtl838x_dma_if_rx_ring_size
,
528 .dma_if_rx_ring_cntr
= rtl838x_dma_if_rx_ring_cntr
,
529 .dma_if_rx_cur
= RTL838X_DMA_IF_RX_CUR
,
530 .rst_glb_ctrl
= RTL838X_RST_GLB_CTRL_0
,
531 .get_mac_link_sts
= rtl838x_get_mac_link_sts
,
532 .get_mac_link_dup_sts
= rtl838x_get_mac_link_dup_sts
,
533 .get_mac_link_spd_sts
= rtl838x_get_mac_link_spd_sts
,
534 .get_mac_rx_pause_sts
= rtl838x_get_mac_rx_pause_sts
,
535 .get_mac_tx_pause_sts
= rtl838x_get_mac_tx_pause_sts
,
537 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
538 .update_cntr
= rtl838x_update_cntr
,
539 .create_tx_header
= rtl838x_create_tx_header
,
540 .decode_tag
= rtl838x_decode_tag
,
543 static const struct rtl838x_reg rtl839x_reg
= {
544 .net_irq
= rtl83xx_net_irq
,
545 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
546 .dma_if_intr_sts
= RTL839X_DMA_IF_INTR_STS
,
547 .dma_if_intr_msk
= RTL839X_DMA_IF_INTR_MSK
,
548 .dma_if_ctrl
= RTL839X_DMA_IF_CTRL
,
549 .mac_force_mode_ctrl
= RTL839X_MAC_FORCE_MODE_CTRL
,
550 .dma_rx_base
= RTL839X_DMA_RX_BASE
,
551 .dma_tx_base
= RTL839X_DMA_TX_BASE
,
552 .dma_if_rx_ring_size
= rtl839x_dma_if_rx_ring_size
,
553 .dma_if_rx_ring_cntr
= rtl839x_dma_if_rx_ring_cntr
,
554 .dma_if_rx_cur
= RTL839X_DMA_IF_RX_CUR
,
555 .rst_glb_ctrl
= RTL839X_RST_GLB_CTRL
,
556 .get_mac_link_sts
= rtl839x_get_mac_link_sts
,
557 .get_mac_link_dup_sts
= rtl839x_get_mac_link_dup_sts
,
558 .get_mac_link_spd_sts
= rtl839x_get_mac_link_spd_sts
,
559 .get_mac_rx_pause_sts
= rtl839x_get_mac_rx_pause_sts
,
560 .get_mac_tx_pause_sts
= rtl839x_get_mac_tx_pause_sts
,
562 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
563 .update_cntr
= rtl839x_update_cntr
,
564 .create_tx_header
= rtl839x_create_tx_header
,
565 .decode_tag
= rtl839x_decode_tag
,
568 static const struct rtl838x_reg rtl930x_reg
= {
569 .net_irq
= rtl93xx_net_irq
,
570 .mac_port_ctrl
= rtl930x_mac_port_ctrl
,
571 .dma_if_intr_rx_runout_sts
= RTL930X_DMA_IF_INTR_RX_RUNOUT_STS
,
572 .dma_if_intr_rx_done_sts
= RTL930X_DMA_IF_INTR_RX_DONE_STS
,
573 .dma_if_intr_tx_done_sts
= RTL930X_DMA_IF_INTR_TX_DONE_STS
,
574 .dma_if_intr_rx_runout_msk
= RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK
,
575 .dma_if_intr_rx_done_msk
= RTL930X_DMA_IF_INTR_RX_DONE_MSK
,
576 .dma_if_intr_tx_done_msk
= RTL930X_DMA_IF_INTR_TX_DONE_MSK
,
577 .l2_ntfy_if_intr_sts
= RTL930X_L2_NTFY_IF_INTR_STS
,
578 .l2_ntfy_if_intr_msk
= RTL930X_L2_NTFY_IF_INTR_MSK
,
579 .dma_if_ctrl
= RTL930X_DMA_IF_CTRL
,
580 .mac_force_mode_ctrl
= RTL930X_MAC_FORCE_MODE_CTRL
,
581 .dma_rx_base
= RTL930X_DMA_RX_BASE
,
582 .dma_tx_base
= RTL930X_DMA_TX_BASE
,
583 .dma_if_rx_ring_size
= rtl930x_dma_if_rx_ring_size
,
584 .dma_if_rx_ring_cntr
= rtl930x_dma_if_rx_ring_cntr
,
585 .dma_if_rx_cur
= RTL930X_DMA_IF_RX_CUR
,
586 .rst_glb_ctrl
= RTL930X_RST_GLB_CTRL_0
,
587 .get_mac_link_sts
= rtl930x_get_mac_link_sts
,
588 .get_mac_link_dup_sts
= rtl930x_get_mac_link_dup_sts
,
589 .get_mac_link_spd_sts
= rtl930x_get_mac_link_spd_sts
,
590 .get_mac_rx_pause_sts
= rtl930x_get_mac_rx_pause_sts
,
591 .get_mac_tx_pause_sts
= rtl930x_get_mac_tx_pause_sts
,
592 .mac
= RTL930X_MAC_L2_ADDR_CTRL
,
593 .l2_tbl_flush_ctrl
= RTL930X_L2_TBL_FLUSH_CTRL
,
594 .update_cntr
= rtl930x_update_cntr
,
595 .create_tx_header
= rtl930x_create_tx_header
,
596 .decode_tag
= rtl930x_decode_tag
,
599 static const struct rtl838x_reg rtl931x_reg
= {
600 .net_irq
= rtl93xx_net_irq
,
601 .mac_port_ctrl
= rtl931x_mac_port_ctrl
,
602 .dma_if_intr_rx_runout_sts
= RTL931X_DMA_IF_INTR_RX_RUNOUT_STS
,
603 .dma_if_intr_rx_done_sts
= RTL931X_DMA_IF_INTR_RX_DONE_STS
,
604 .dma_if_intr_tx_done_sts
= RTL931X_DMA_IF_INTR_TX_DONE_STS
,
605 .dma_if_intr_rx_runout_msk
= RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK
,
606 .dma_if_intr_rx_done_msk
= RTL931X_DMA_IF_INTR_RX_DONE_MSK
,
607 .dma_if_intr_tx_done_msk
= RTL931X_DMA_IF_INTR_TX_DONE_MSK
,
608 .l2_ntfy_if_intr_sts
= RTL931X_L2_NTFY_IF_INTR_STS
,
609 .l2_ntfy_if_intr_msk
= RTL931X_L2_NTFY_IF_INTR_MSK
,
610 .dma_if_ctrl
= RTL931X_DMA_IF_CTRL
,
611 .mac_force_mode_ctrl
= RTL931X_MAC_FORCE_MODE_CTRL
,
612 .dma_rx_base
= RTL931X_DMA_RX_BASE
,
613 .dma_tx_base
= RTL931X_DMA_TX_BASE
,
614 .dma_if_rx_ring_size
= rtl931x_dma_if_rx_ring_size
,
615 .dma_if_rx_ring_cntr
= rtl931x_dma_if_rx_ring_cntr
,
616 .dma_if_rx_cur
= RTL931X_DMA_IF_RX_CUR
,
617 .rst_glb_ctrl
= RTL931X_RST_GLB_CTRL
,
618 .get_mac_link_sts
= rtl931x_get_mac_link_sts
,
619 .get_mac_link_dup_sts
= rtl931x_get_mac_link_dup_sts
,
620 .get_mac_link_spd_sts
= rtl931x_get_mac_link_spd_sts
,
621 .get_mac_rx_pause_sts
= rtl931x_get_mac_rx_pause_sts
,
622 .get_mac_tx_pause_sts
= rtl931x_get_mac_tx_pause_sts
,
623 .mac
= RTL931X_MAC_L2_ADDR_CTRL
,
624 .l2_tbl_flush_ctrl
= RTL931X_L2_TBL_FLUSH_CTRL
,
625 .update_cntr
= rtl931x_update_cntr
,
626 .create_tx_header
= rtl931x_create_tx_header
,
627 .decode_tag
= rtl931x_decode_tag
,
630 static void rtl838x_hw_reset(struct rtl838x_eth_priv
*priv
)
635 pr_info("RESETTING %x, CPU_PORT %d\n", priv
->family_id
, priv
->cpu_port
);
636 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
639 /* Disable and clear interrupts */
640 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
641 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_runout_msk
);
642 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_sts
);
643 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_done_msk
);
644 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_sts
);
645 sw_w32(0x00000000, priv
->r
->dma_if_intr_tx_done_msk
);
646 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_sts
);
648 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
649 sw_w32(0xffffffff, priv
->r
->dma_if_intr_sts
);
652 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
653 /* Preserve L2 notification and NBUF settings */
654 int_saved
= sw_r32(priv
->r
->dma_if_intr_msk
);
655 nbuf
= sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
657 /* Disable link change interrupt on RTL839x */
658 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG
);
659 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG
+ 4);
661 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
662 sw_w32(0xffffffff, priv
->r
->dma_if_intr_sts
);
666 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
667 sw_w32(0x4, priv
->r
->rst_glb_ctrl
);
669 sw_w32(0x8, priv
->r
->rst_glb_ctrl
);
671 do { /* Wait for reset of NIC and Queues done */
673 } while (sw_r32(priv
->r
->rst_glb_ctrl
) & 0xc);
676 /* Setup Head of Line */
677 if (priv
->family_id
== RTL8380_FAMILY_ID
)
678 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE
); // Disabled on RTL8380
679 if (priv
->family_id
== RTL8390_FAMILY_ID
)
680 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR
);
681 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
682 for (i
= 0; i
< priv
->rxrings
; i
++) {
684 sw_w32_mask(0x3ff << pos
, 0, priv
->r
->dma_if_rx_ring_size(i
));
685 sw_w32_mask(0x3ff << pos
, priv
->rxringlen
,
686 priv
->r
->dma_if_rx_ring_cntr(i
));
690 /* Re-enable link change interrupt */
691 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
692 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG
);
693 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG
+ 4);
694 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG
);
695 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG
+ 4);
697 /* Restore notification settings: on RTL838x these bits are null */
698 sw_w32_mask(7 << 20, int_saved
& (7 << 20), priv
->r
->dma_if_intr_msk
);
699 sw_w32(nbuf
, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
703 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv
*priv
)
706 struct ring_b
*ring
= priv
->membase
;
708 for (i
= 0; i
< priv
->rxrings
; i
++)
709 sw_w32(KSEG1ADDR(&ring
->rx_r
[i
]), priv
->r
->dma_rx_base
+ i
* 4);
711 for (i
= 0; i
< TXRINGS
; i
++)
712 sw_w32(KSEG1ADDR(&ring
->tx_r
[i
]), priv
->r
->dma_tx_base
+ i
* 4);
715 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
717 /* Disable Head of Line features for all RX rings */
718 sw_w32(0xffffffff, priv
->r
->dma_if_rx_ring_size(0));
720 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
721 sw_w32(0x06400020, priv
->r
->dma_if_ctrl
);
723 /* Enable RX done, RX overflow and TX done interrupts */
724 sw_w32(0xfffff, priv
->r
->dma_if_intr_msk
);
726 /* Enable DMA, engine expects empty FCS field */
727 sw_w32_mask(0, RX_EN
| TX_EN
, priv
->r
->dma_if_ctrl
);
729 /* Restart TX/RX to CPU port */
730 sw_w32_mask(0x0, 0x3, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
731 /* Set Speed, duplex, flow control
732 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
733 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
736 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
738 /* Enable CRC checks on CPU-port */
739 sw_w32_mask(0, BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
742 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
744 /* Setup CPU-Port: RX Buffer */
745 sw_w32(0x0000c808, priv
->r
->dma_if_ctrl
);
747 /* Enable Notify, RX done, RX overflow and TX done interrupts */
748 sw_w32(0x007fffff, priv
->r
->dma_if_intr_msk
); // Notify IRQ!
751 sw_w32_mask(0, RX_EN
| TX_EN
, priv
->r
->dma_if_ctrl
);
753 /* Restart TX/RX to CPU port, enable CRC checking */
754 sw_w32_mask(0x0, 0x3 | BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
756 /* CPU port joins Lookup Miss Flooding Portmask */
757 // TODO: The code below should also work for the RTL838x
758 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL
);
759 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
760 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL
);
762 /* Force CPU port link up */
763 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
766 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
771 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
772 sw_w32(0x06400040, priv
->r
->dma_if_ctrl
);
774 for (i
= 0; i
< priv
->rxrings
; i
++) {
776 sw_w32_mask(0x3ff << pos
, priv
->rxringlen
<< pos
, priv
->r
->dma_if_rx_ring_size(i
));
778 // Some SoCs have issues with missing underflow protection
779 v
= (sw_r32(priv
->r
->dma_if_rx_ring_cntr(i
)) >> pos
) & 0x3ff;
780 sw_w32_mask(0x3ff << pos
, v
, priv
->r
->dma_if_rx_ring_cntr(i
));
783 /* Enable Notify, RX done, RX overflow and TX done interrupts */
784 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_msk
);
785 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_msk
);
786 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_msk
);
789 sw_w32_mask(0, RX_EN_93XX
| TX_EN_93XX
, priv
->r
->dma_if_ctrl
);
791 /* Restart TX/RX to CPU port, enable CRC checking */
792 sw_w32_mask(0x0, 0x3 | BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
794 sw_w32_mask(0, BIT(priv
->cpu_port
), RTL930X_L2_UNKN_UC_FLD_PMSK
);
795 sw_w32(0x217, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
798 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv
*priv
, struct ring_b
*ring
)
804 for (i
= 0; i
< priv
->rxrings
; i
++) {
805 for (j
= 0; j
< priv
->rxringlen
; j
++) {
806 h
= &ring
->rx_header
[i
][j
];
807 memset(h
, 0, sizeof(struct p_hdr
));
808 h
->buf
= (u8
*)KSEG1ADDR(ring
->rx_space
809 + i
* priv
->rxringlen
* RING_BUFFER
811 h
->size
= RING_BUFFER
;
812 /* All rings owned by switch, last one wraps */
813 ring
->rx_r
[i
][j
] = KSEG1ADDR(h
) | 1
814 | (j
== (priv
->rxringlen
- 1) ? WRAP
: 0);
819 for (i
= 0; i
< TXRINGS
; i
++) {
820 for (j
= 0; j
< TXRINGLEN
; j
++) {
821 h
= &ring
->tx_header
[i
][j
];
822 memset(h
, 0, sizeof(struct p_hdr
));
823 h
->buf
= (u8
*)KSEG1ADDR(ring
->tx_space
824 + i
* TXRINGLEN
* RING_BUFFER
826 h
->size
= RING_BUFFER
;
827 ring
->tx_r
[i
][j
] = KSEG1ADDR(&ring
->tx_header
[i
][j
]);
829 /* Last header is wrapping around */
830 ring
->tx_r
[i
][j
-1] |= WRAP
;
835 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv
*priv
)
838 struct notify_b
*b
= priv
->membase
+ sizeof(struct ring_b
);
840 for (i
= 0; i
< NOTIFY_BLOCKS
; i
++)
841 b
->ring
[i
] = KSEG1ADDR(&b
->blocks
[i
]) | 1 | (i
== (NOTIFY_BLOCKS
- 1) ? WRAP
: 0);
843 sw_w32((u32
) b
->ring
, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
844 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL
);
846 /* Setup notification events */
847 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0
); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
848 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL
); // SUSPEND_NOTIFICATION_EN
850 /* Enable Notification */
851 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL
);
855 static int rtl838x_eth_open(struct net_device
*ndev
)
858 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
859 struct ring_b
*ring
= priv
->membase
;
862 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
863 __func__
, priv
->rxrings
, priv
->rxringlen
, TXRINGS
, TXRINGLEN
);
865 spin_lock_irqsave(&priv
->lock
, flags
);
866 rtl838x_hw_reset(priv
);
867 rtl838x_setup_ring_buffer(priv
, ring
);
868 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
869 rtl839x_setup_notify_ring_buffer(priv
);
870 /* Make sure the ring structure is visible to the ASIC */
875 rtl838x_hw_ring_setup(priv
);
876 err
= request_irq(ndev
->irq
, priv
->r
->net_irq
, IRQF_SHARED
, ndev
->name
, ndev
);
878 netdev_err(ndev
, "%s: could not acquire interrupt: %d\n",
882 phylink_start(priv
->phylink
);
884 for (i
= 0; i
< priv
->rxrings
; i
++)
885 napi_enable(&priv
->rx_qs
[i
].napi
);
887 switch (priv
->family_id
) {
888 case RTL8380_FAMILY_ID
:
889 rtl838x_hw_en_rxtx(priv
);
890 /* Trap IGMP/MLD traffic to CPU-Port */
891 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL
);
892 /* Flush learned FDB entries on link down of a port */
893 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0
);
896 case RTL8390_FAMILY_ID
:
897 rtl839x_hw_en_rxtx(priv
);
898 // Trap MLD and IGMP messages to CPU_PORT
899 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL
);
900 /* Flush learned FDB entries on link down of a port */
901 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0
);
904 case RTL9300_FAMILY_ID
:
905 rtl93xx_hw_en_rxtx(priv
);
906 /* Flush learned FDB entries on link down of a port */
907 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL
);
908 // Trap MLD and IGMP messages to CPU_PORT
909 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL
);
912 case RTL9310_FAMILY_ID
:
913 rtl93xx_hw_en_rxtx(priv
);
917 netif_tx_start_all_queues(ndev
);
919 spin_unlock_irqrestore(&priv
->lock
, flags
);
924 static void rtl838x_hw_stop(struct rtl838x_eth_priv
*priv
)
926 u32 force_mac
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x6192C : 0x75;
927 u32 clear_irq
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x000fffff : 0x007fffff;
930 // Disable RX/TX from/to CPU-port
931 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
933 /* Disable traffic */
934 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
935 sw_w32_mask(RX_EN_93XX
| TX_EN_93XX
, 0, priv
->r
->dma_if_ctrl
);
937 sw_w32_mask(RX_EN
| TX_EN
, 0, priv
->r
->dma_if_ctrl
);
938 mdelay(200); // Test, whether this is needed
940 /* Block all ports */
941 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
942 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
943 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
944 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0
);
947 /* Flush L2 address cache */
948 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
949 for (i
= 0; i
<= priv
->cpu_port
; i
++) {
950 sw_w32(1 << 26 | 1 << 23 | i
<< 5, priv
->r
->l2_tbl_flush_ctrl
);
951 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << 26));
953 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
954 for (i
= 0; i
<= priv
->cpu_port
; i
++) {
955 sw_w32(1 << 28 | 1 << 25 | i
<< 5, priv
->r
->l2_tbl_flush_ctrl
);
956 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << 28));
959 // TODO: L2 flush register is 64 bit on RTL931X and 930X
961 /* CPU-Port: Link down */
962 if (priv
->family_id
== RTL8380_FAMILY_ID
|| priv
->family_id
== RTL8390_FAMILY_ID
)
963 sw_w32(force_mac
, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
965 sw_w32_mask(0x3, 0, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
*4);
968 /* Disable all TX/RX interrupts */
969 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
970 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_runout_msk
);
971 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_sts
);
972 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_done_msk
);
973 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_sts
);
974 sw_w32(0x00000000, priv
->r
->dma_if_intr_tx_done_msk
);
975 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_sts
);
977 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
978 sw_w32(clear_irq
, priv
->r
->dma_if_intr_sts
);
981 /* Disable TX/RX DMA */
982 sw_w32(0x00000000, priv
->r
->dma_if_ctrl
);
986 static int rtl838x_eth_stop(struct net_device
*ndev
)
990 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
992 pr_info("in %s\n", __func__
);
994 spin_lock_irqsave(&priv
->lock
, flags
);
995 phylink_stop(priv
->phylink
);
996 rtl838x_hw_stop(priv
);
997 free_irq(ndev
->irq
, ndev
);
999 for (i
= 0; i
< priv
->rxrings
; i
++)
1000 napi_disable(&priv
->rx_qs
[i
].napi
);
1002 netif_tx_stop_all_queues(ndev
);
1004 spin_unlock_irqrestore(&priv
->lock
, flags
);
1009 static void rtl839x_eth_set_multicast_list(struct net_device
*ndev
)
1011 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1012 sw_w32(0x0, RTL839X_RMA_CTRL_0
);
1013 sw_w32(0x0, RTL839X_RMA_CTRL_1
);
1014 sw_w32(0x0, RTL839X_RMA_CTRL_2
);
1015 sw_w32(0x0, RTL839X_RMA_CTRL_3
);
1017 if (ndev
->flags
& IFF_ALLMULTI
) {
1018 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0
);
1019 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1
);
1020 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2
);
1022 if (ndev
->flags
& IFF_PROMISC
) {
1023 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0
);
1024 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1
);
1025 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2
);
1026 sw_w32(0x3ff, RTL839X_RMA_CTRL_3
);
1030 static void rtl838x_eth_set_multicast_list(struct net_device
*ndev
)
1032 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1034 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1035 return rtl839x_eth_set_multicast_list(ndev
);
1037 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1038 sw_w32(0x0, RTL838X_RMA_CTRL_0
);
1039 sw_w32(0x0, RTL838X_RMA_CTRL_1
);
1041 if (ndev
->flags
& IFF_ALLMULTI
)
1042 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0
);
1043 if (ndev
->flags
& IFF_PROMISC
) {
1044 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0
);
1045 sw_w32(0x7fff, RTL838X_RMA_CTRL_1
);
1049 static void rtl930x_eth_set_multicast_list(struct net_device
*ndev
)
1051 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1052 sw_w32(0x0, RTL930X_RMA_CTRL_0
);
1053 sw_w32(0x0, RTL930X_RMA_CTRL_1
);
1054 sw_w32(0x0, RTL930X_RMA_CTRL_2
);
1056 if (ndev
->flags
& IFF_ALLMULTI
) {
1057 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0
);
1058 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1
);
1059 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2
);
1061 if (ndev
->flags
& IFF_PROMISC
) {
1062 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0
);
1063 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1
);
1064 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2
);
1068 static void rtl931x_eth_set_multicast_list(struct net_device
*ndev
)
1070 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1071 sw_w32(0x0, RTL931X_RMA_CTRL_0
);
1072 sw_w32(0x0, RTL931X_RMA_CTRL_1
);
1073 sw_w32(0x0, RTL931X_RMA_CTRL_2
);
1075 if (ndev
->flags
& IFF_ALLMULTI
) {
1076 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0
);
1077 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1
);
1078 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2
);
1080 if (ndev
->flags
& IFF_PROMISC
) {
1081 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0
);
1082 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1
);
1083 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2
);
1087 static void rtl838x_eth_tx_timeout(struct net_device
*ndev
, unsigned int txqueue
)
1089 unsigned long flags
;
1090 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1092 pr_warn("%s\n", __func__
);
1093 spin_lock_irqsave(&priv
->lock
, flags
);
1094 rtl838x_hw_stop(priv
);
1095 rtl838x_hw_ring_setup(priv
);
1096 rtl838x_hw_en_rxtx(priv
);
1097 netif_trans_update(ndev
);
1098 netif_start_queue(ndev
);
1099 spin_unlock_irqrestore(&priv
->lock
, flags
);
1102 static int rtl838x_eth_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1105 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1106 struct ring_b
*ring
= priv
->membase
;
1109 unsigned long flags
;
1112 int q
= skb_get_queue_mapping(skb
) % TXRINGS
;
1114 if (q
) // Check for high prio queue
1115 pr_debug("SKB priority: %d\n", skb
->priority
);
1117 spin_lock_irqsave(&priv
->lock
, flags
);
1120 /* Check for DSA tagging at the end of the buffer */
1121 if (netdev_uses_dsa(dev
) && skb
->data
[len
-4] == 0x80 && skb
->data
[len
-3] > 0
1122 && skb
->data
[len
-3] < priv
->cpu_port
&& skb
->data
[len
-2] == 0x10
1123 && skb
->data
[len
-1] == 0x00) {
1124 /* Reuse tag space for CRC if possible */
1125 dest_port
= skb
->data
[len
-3];
1126 skb
->data
[len
-4] = skb
->data
[len
-3] = skb
->data
[len
-2] = skb
->data
[len
-1] = 0x00;
1130 len
+= 4; // Add space for CRC
1132 if (skb_padto(skb
, len
)) {
1137 /* We can send this packet if CPU owns the descriptor */
1138 if (!(ring
->tx_r
[q
][ring
->c_tx
[q
]] & 0x1)) {
1140 /* Set descriptor for tx */
1141 h
= &ring
->tx_header
[q
][ring
->c_tx
[q
]];
1144 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1145 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1146 if (len
< ETH_ZLEN
- 4)
1150 priv
->r
->create_tx_header(h
, dest_port
, skb
->priority
>> 1);
1152 /* Copy packet data to tx buffer */
1153 memcpy((void *)KSEG1ADDR(h
->buf
), skb
->data
, len
);
1154 /* Make sure packet data is visible to ASIC */
1157 /* Hand over to switch */
1158 ring
->tx_r
[q
][ring
->c_tx
[q
]] |= 1;
1160 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1161 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1162 for (i
= 0; i
< 10; i
++) {
1163 val
= sw_r32(priv
->r
->dma_if_ctrl
);
1164 if ((val
& 0xc) == 0xc)
1169 /* Tell switch to send data */
1170 if (priv
->family_id
== RTL9310_FAMILY_ID
1171 || priv
->family_id
== RTL9300_FAMILY_ID
) {
1172 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1174 sw_w32_mask(0, BIT(2), priv
->r
->dma_if_ctrl
);
1176 sw_w32_mask(0, BIT(3), priv
->r
->dma_if_ctrl
);
1178 sw_w32_mask(0, TX_DO
, priv
->r
->dma_if_ctrl
);
1181 dev
->stats
.tx_packets
++;
1182 dev
->stats
.tx_bytes
+= len
;
1184 ring
->c_tx
[q
] = (ring
->c_tx
[q
] + 1) % TXRINGLEN
;
1187 dev_warn(&priv
->pdev
->dev
, "Data is owned by switch\n");
1188 ret
= NETDEV_TX_BUSY
;
1191 spin_unlock_irqrestore(&priv
->lock
, flags
);
1196 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1197 * so we do round-robin
1199 u16
rtl83xx_pick_tx_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1200 struct net_device
*sb_dev
)
1205 return last
% TXRINGS
;
1209 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1211 u16
rtl93xx_pick_tx_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1212 struct net_device
*sb_dev
)
1214 if (skb
->priority
>= TC_PRIO_CONTROL
)
1219 static int rtl838x_hw_receive(struct net_device
*dev
, int r
, int budget
)
1221 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1222 struct ring_b
*ring
= priv
->membase
;
1223 struct sk_buff
*skb
;
1224 unsigned long flags
;
1225 int i
, len
, work_done
= 0;
1226 u8
*data
, *skb_data
;
1230 bool dsa
= netdev_uses_dsa(dev
);
1233 spin_lock_irqsave(&priv
->lock
, flags
);
1234 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
1235 pr_debug("---------------------------------------------------------- RX - %d\n", r
);
1238 if ((ring
->rx_r
[r
][ring
->c_rx
[r
]] & 0x1)) {
1239 if (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
) {
1240 netdev_warn(dev
, "Ring contention: r: %x, last %x, cur %x\n",
1241 r
, (uint32_t)last
, (u32
) &ring
->rx_r
[r
][ring
->c_rx
[r
]]);
1246 h
= &ring
->rx_header
[r
][ring
->c_rx
[r
]];
1247 data
= (u8
*)KSEG1ADDR(h
->buf
);
1253 len
-= 4; /* strip the CRC */
1254 /* Add 4 bytes for cpu_tag */
1258 skb
= alloc_skb(len
+ 4, GFP_KERNEL
);
1259 skb_reserve(skb
, NET_IP_ALIGN
);
1262 /* BUG: Prevent bug on RTL838x SoCs*/
1263 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1264 sw_w32(0xffffffff, priv
->r
->dma_if_rx_ring_size(0));
1265 for (i
= 0; i
< priv
->rxrings
; i
++) {
1266 /* Update each ring cnt */
1267 val
= sw_r32(priv
->r
->dma_if_rx_ring_cntr(i
));
1268 sw_w32(val
, priv
->r
->dma_if_rx_ring_cntr(i
));
1272 skb_data
= skb_put(skb
, len
);
1273 /* Make sure data is visible */
1275 memcpy(skb
->data
, (u8
*)KSEG1ADDR(data
), len
);
1276 /* Overwrite CRC with cpu_tag */
1278 priv
->r
->decode_tag(h
, &tag
);
1279 skb
->data
[len
-4] = 0x80;
1280 skb
->data
[len
-3] = tag
.port
;
1281 skb
->data
[len
-2] = 0x10;
1282 skb
->data
[len
-1] = 0x00;
1283 if (tag
.l2_offloaded
)
1284 skb
->data
[len
-3] |= 0x40;
1288 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1289 tag
.queue
, len
, tag
.reason
, tag
.port
);
1291 skb
->protocol
= eth_type_trans(skb
, dev
);
1292 if (dev
->features
& NETIF_F_RXCSUM
) {
1294 skb_checksum_none_assert(skb
);
1296 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1298 dev
->stats
.rx_packets
++;
1299 dev
->stats
.rx_bytes
+= len
;
1301 netif_receive_skb(skb
);
1303 if (net_ratelimit())
1304 dev_warn(&dev
->dev
, "low on memory - packet dropped\n");
1305 dev
->stats
.rx_dropped
++;
1308 /* Reset header structure */
1309 memset(h
, 0, sizeof(struct p_hdr
));
1311 h
->size
= RING_BUFFER
;
1313 ring
->rx_r
[r
][ring
->c_rx
[r
]] = KSEG1ADDR(h
) | 0x1
1314 | (ring
->c_rx
[r
] == (priv
->rxringlen
- 1) ? WRAP
: 0x1);
1315 ring
->c_rx
[r
] = (ring
->c_rx
[r
] + 1) % priv
->rxringlen
;
1316 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
1317 } while (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
&& work_done
< budget
);
1320 priv
->r
->update_cntr(r
, 0);
1322 spin_unlock_irqrestore(&priv
->lock
, flags
);
1326 static int rtl838x_poll_rx(struct napi_struct
*napi
, int budget
)
1328 struct rtl838x_rx_q
*rx_q
= container_of(napi
, struct rtl838x_rx_q
, napi
);
1329 struct rtl838x_eth_priv
*priv
= rx_q
->priv
;
1334 while (work_done
< budget
) {
1335 work
= rtl838x_hw_receive(priv
->netdev
, r
, budget
- work_done
);
1341 if (work_done
< budget
) {
1342 napi_complete_done(napi
, work_done
);
1344 /* Enable RX interrupt */
1345 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
1346 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_msk
);
1348 sw_w32_mask(0, 0xf00ff | BIT(r
+ 8), priv
->r
->dma_if_intr_msk
);
1354 static void rtl838x_validate(struct phylink_config
*config
,
1355 unsigned long *supported
,
1356 struct phylink_link_state
*state
)
1358 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1360 pr_debug("In %s\n", __func__
);
1362 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1363 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
1364 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1365 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
1366 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
1367 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
1368 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
1369 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
1370 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1371 pr_err("Unsupported interface: %d\n", state
->interface
);
1375 /* Allow all the expected bits */
1376 phylink_set(mask
, Autoneg
);
1377 phylink_set_port_modes(mask
);
1378 phylink_set(mask
, Pause
);
1379 phylink_set(mask
, Asym_Pause
);
1381 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1382 * including Half duplex
1384 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1385 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
1386 phylink_set(mask
, 1000baseT_Full
);
1387 phylink_set(mask
, 1000baseT_Half
);
1390 phylink_set(mask
, 10baseT_Half
);
1391 phylink_set(mask
, 10baseT_Full
);
1392 phylink_set(mask
, 100baseT_Half
);
1393 phylink_set(mask
, 100baseT_Full
);
1395 bitmap_and(supported
, supported
, mask
,
1396 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1397 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1398 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1402 static void rtl838x_mac_config(struct phylink_config
*config
,
1404 const struct phylink_link_state
*state
)
1406 /* This is only being called for the master device,
1407 * i.e. the CPU-Port. We don't need to do anything.
1410 pr_info("In %s, mode %x\n", __func__
, mode
);
1413 static void rtl838x_mac_an_restart(struct phylink_config
*config
)
1415 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1416 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1418 /* This works only on RTL838x chips */
1419 if (priv
->family_id
!= RTL8380_FAMILY_ID
)
1422 pr_debug("In %s\n", __func__
);
1423 /* Restart by disabling and re-enabling link */
1424 sw_w32(0x6192D, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
1426 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
1429 static void rtl838x_mac_pcs_get_state(struct phylink_config
*config
,
1430 struct phylink_link_state
*state
)
1433 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1434 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1435 int port
= priv
->cpu_port
;
1437 pr_debug("In %s\n", __func__
);
1439 state
->link
= priv
->r
->get_mac_link_sts(port
) ? 1 : 0;
1440 state
->duplex
= priv
->r
->get_mac_link_dup_sts(port
) ? 1 : 0;
1442 speed
= priv
->r
->get_mac_link_spd_sts(port
);
1445 state
->speed
= SPEED_10
;
1448 state
->speed
= SPEED_100
;
1451 state
->speed
= SPEED_1000
;
1454 state
->speed
= SPEED_UNKNOWN
;
1458 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
1459 if (priv
->r
->get_mac_rx_pause_sts(port
))
1460 state
->pause
|= MLO_PAUSE_RX
;
1461 if (priv
->r
->get_mac_tx_pause_sts(port
))
1462 state
->pause
|= MLO_PAUSE_TX
;
1465 static void rtl838x_mac_link_down(struct phylink_config
*config
,
1467 phy_interface_t interface
)
1469 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1470 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1472 pr_debug("In %s\n", __func__
);
1473 /* Stop TX/RX to port */
1474 sw_w32_mask(0x03, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1477 static void rtl838x_mac_link_up(struct phylink_config
*config
,
1478 struct phy_device
*phy
, unsigned int mode
,
1479 phy_interface_t interface
, int speed
, int duplex
,
1480 bool tx_pause
, bool rx_pause
)
1482 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1483 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1485 pr_debug("In %s\n", __func__
);
1486 /* Restart TX/RX to port */
1487 sw_w32_mask(0, 0x03, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1490 static void rtl838x_set_mac_hw(struct net_device
*dev
, u8
*mac
)
1492 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1493 unsigned long flags
;
1495 spin_lock_irqsave(&priv
->lock
, flags
);
1496 pr_debug("In %s\n", __func__
);
1497 sw_w32((mac
[0] << 8) | mac
[1], priv
->r
->mac
);
1498 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5], priv
->r
->mac
+ 4);
1500 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1501 /* 2 more registers, ALE/MAC block */
1502 sw_w32((mac
[0] << 8) | mac
[1], RTL838X_MAC_ALE
);
1503 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
1504 (RTL838X_MAC_ALE
+ 4));
1506 sw_w32((mac
[0] << 8) | mac
[1], RTL838X_MAC2
);
1507 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
1510 spin_unlock_irqrestore(&priv
->lock
, flags
);
1513 static int rtl838x_set_mac_address(struct net_device
*dev
, void *p
)
1515 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1516 const struct sockaddr
*addr
= p
;
1517 u8
*mac
= (u8
*) (addr
->sa_data
);
1519 if (!is_valid_ether_addr(addr
->sa_data
))
1520 return -EADDRNOTAVAIL
;
1522 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
1523 rtl838x_set_mac_hw(dev
, mac
);
1525 pr_info("Using MAC %08x%08x\n", sw_r32(priv
->r
->mac
), sw_r32(priv
->r
->mac
+ 4));
1529 static int rtl8390_init_mac(struct rtl838x_eth_priv
*priv
)
1531 // We will need to set-up EEE and the egress-rate limitation
1535 static int rtl8380_init_mac(struct rtl838x_eth_priv
*priv
)
1539 if (priv
->family_id
== 0x8390)
1540 return rtl8390_init_mac(priv
);
1542 pr_info("%s\n", __func__
);
1543 /* fix timer for EEE */
1544 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
1545 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
1548 if (priv
->id
== 0x8382) {
1549 for (i
= 0; i
<= 28; i
++)
1550 sw_w32(0, 0xd57c + i
* 0x80);
1552 if (priv
->id
== 0x8380) {
1553 for (i
= 8; i
<= 28; i
++)
1554 sw_w32(0, 0xd57c + i
* 0x80);
1559 static int rtl838x_get_link_ksettings(struct net_device
*ndev
,
1560 struct ethtool_link_ksettings
*cmd
)
1562 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1564 pr_debug("%s called\n", __func__
);
1565 return phylink_ethtool_ksettings_get(priv
->phylink
, cmd
);
1568 static int rtl838x_set_link_ksettings(struct net_device
*ndev
,
1569 const struct ethtool_link_ksettings
*cmd
)
1571 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1573 pr_debug("%s called\n", __func__
);
1574 return phylink_ethtool_ksettings_set(priv
->phylink
, cmd
);
1577 static int rtl838x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1581 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1583 if (mii_id
>= 24 && mii_id
<= 27 && priv
->id
== 0x8380)
1584 return rtl838x_read_sds_phy(mii_id
, regnum
);
1585 err
= rtl838x_read_phy(mii_id
, 0, regnum
, &val
);
1591 static int rtl839x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1595 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1597 if (mii_id
>= 48 && mii_id
<= 49 && priv
->id
== 0x8393)
1598 return rtl839x_read_sds_phy(mii_id
, regnum
);
1600 err
= rtl839x_read_phy(mii_id
, 0, regnum
, &val
);
1606 static int rtl930x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1611 // TODO: These are hard-coded for the 2 Fibre Ports of the XGS1210
1612 if (mii_id
>= 26 && mii_id
<= 27)
1613 return rtl930x_read_sds_phy(mii_id
- 18, 0, regnum
);
1615 if (regnum
& MII_ADDR_C45
) {
1616 regnum
&= ~MII_ADDR_C45
;
1617 err
= rtl930x_read_mmd_phy(mii_id
, regnum
>> 16, regnum
& 0xffff, &val
);
1619 err
= rtl930x_read_phy(mii_id
, 0, regnum
, &val
);
1626 static int rtl931x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1630 // struct rtl838x_eth_priv *priv = bus->priv;
1632 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1633 // return rtl839x_read_sds_phy(mii_id, regnum);
1635 err
= rtl931x_read_phy(mii_id
, 0, regnum
, &val
);
1641 static int rtl838x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1642 int regnum
, u16 value
)
1645 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1647 if (mii_id
>= 24 && mii_id
<= 27 && priv
->id
== 0x8380) {
1650 sw_w32(value
, RTL838X_SDS4_FIB_REG0
+ offset
+ (regnum
<< 2));
1653 return rtl838x_write_phy(mii_id
, 0, regnum
, value
);
1656 static int rtl839x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1657 int regnum
, u16 value
)
1659 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1661 if (mii_id
>= 48 && mii_id
<= 49 && priv
->id
== 0x8393)
1662 return rtl839x_write_sds_phy(mii_id
, regnum
, value
);
1664 return rtl839x_write_phy(mii_id
, 0, regnum
, value
);
1667 static int rtl930x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1668 int regnum
, u16 value
)
1670 // struct rtl838x_eth_priv *priv = bus->priv;
1672 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1673 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1674 if (regnum
& MII_ADDR_C45
) {
1675 regnum
&= ~MII_ADDR_C45
;
1676 return rtl930x_write_mmd_phy(mii_id
, regnum
>> 16, regnum
& 0xffff, value
);
1679 return rtl930x_write_phy(mii_id
, 0, regnum
, value
);
1682 static int rtl931x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1683 int regnum
, u16 value
)
1685 // struct rtl838x_eth_priv *priv = bus->priv;
1687 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1688 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1690 return rtl931x_write_phy(mii_id
, 0, regnum
, value
);
1693 static int rtl838x_mdio_reset(struct mii_bus
*bus
)
1695 pr_debug("%s called\n", __func__
);
1696 /* Disable MAC polling the PHY so that we can start configuration */
1697 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL
);
1699 /* Enable PHY control via SoC */
1700 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL
);
1702 // Probably should reset all PHYs here...
1706 static int rtl839x_mdio_reset(struct mii_bus
*bus
)
1710 pr_debug("%s called\n", __func__
);
1711 /* BUG: The following does not work, but should! */
1712 /* Disable MAC polling the PHY so that we can start configuration */
1713 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL
);
1714 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
1715 /* Disable PHY polling via SoC */
1716 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL
);
1718 // Probably should reset all PHYs here...
1722 static int rtl931x_mdio_reset(struct mii_bus
*bus
)
1724 sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL
);
1725 sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
1727 pr_debug("%s called\n", __func__
);
1732 static int rtl930x_mdio_reset(struct mii_bus
*bus
)
1736 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1741 // Mapping of port to phy-addresses on an SMI bus
1742 poll_sel
[0] = poll_sel
[1] = 0;
1743 for (i
= 0; i
< 28; i
++) {
1745 sw_w32_mask(0x1f << pos
, priv
->smi_addr
[i
] << pos
,
1746 RTL930X_SMI_PORT0_5_ADDR
+ (i
/ 6) * 4);
1749 poll_sel
[i
/ 16] |= priv
->smi_bus
[i
] << pos
;
1750 poll_ctrl
|= BIT(20 + priv
->smi_bus
[i
]);
1753 // Configure which SMI bus is behind which port number
1754 sw_w32(poll_sel
[0], RTL930X_SMI_PORT0_15_POLLING_SEL
);
1755 sw_w32(poll_sel
[1], RTL930X_SMI_PORT16_27_POLLING_SEL
);
1757 // Enable polling on the respective SMI busses
1758 sw_w32_mask(0, poll_ctrl
, RTL930X_SMI_GLB_CTRL
);
1760 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1761 for (i
= 0; i
< 4; i
++)
1762 if (priv
->smi_bus_isc45
[i
])
1763 c45_mask
|= BIT(i
+ 16);
1765 pr_info("c45_mask: %08x\n", c45_mask
);
1766 sw_w32_mask(0, c45_mask
, RTL930X_SMI_GLB_CTRL
);
1768 // Ports 24 to 27 are 2.5 or 10Gig, set this type (1) or (0) for internal SerDes
1769 for (i
= 24; i
< 28; i
++) {
1770 pos
= (i
- 24) * 3 + 12;
1771 if (priv
->phy_is_internal
[i
])
1772 sw_w32_mask(0x7 << pos
, 0 << pos
, RTL930X_SMI_MAC_TYPE_CTRL
);
1774 sw_w32_mask(0x7 << pos
, 1 << pos
, RTL930X_SMI_MAC_TYPE_CTRL
);
1777 // TODO: Set up RTL9300_SMI_10GPHY_POLLING_SEL_0 for Aquantia PHYs on e.g. XGS 1250
1782 static int rtl838x_mdio_init(struct rtl838x_eth_priv
*priv
)
1784 struct device_node
*mii_np
, *dn
;
1788 pr_debug("%s called\n", __func__
);
1789 mii_np
= of_get_child_by_name(priv
->pdev
->dev
.of_node
, "mdio-bus");
1792 dev_err(&priv
->pdev
->dev
, "no %s child node found", "mdio-bus");
1796 if (!of_device_is_available(mii_np
)) {
1801 priv
->mii_bus
= devm_mdiobus_alloc(&priv
->pdev
->dev
);
1802 if (!priv
->mii_bus
) {
1807 switch(priv
->family_id
) {
1808 case RTL8380_FAMILY_ID
:
1809 priv
->mii_bus
->name
= "rtl838x-eth-mdio";
1810 priv
->mii_bus
->read
= rtl838x_mdio_read
;
1811 priv
->mii_bus
->write
= rtl838x_mdio_write
;
1812 priv
->mii_bus
->reset
= rtl838x_mdio_reset
;
1814 case RTL8390_FAMILY_ID
:
1815 priv
->mii_bus
->name
= "rtl839x-eth-mdio";
1816 priv
->mii_bus
->read
= rtl839x_mdio_read
;
1817 priv
->mii_bus
->write
= rtl839x_mdio_write
;
1818 priv
->mii_bus
->reset
= rtl839x_mdio_reset
;
1820 case RTL9300_FAMILY_ID
:
1821 priv
->mii_bus
->name
= "rtl930x-eth-mdio";
1822 priv
->mii_bus
->read
= rtl930x_mdio_read
;
1823 priv
->mii_bus
->write
= rtl930x_mdio_write
;
1824 priv
->mii_bus
->reset
= rtl930x_mdio_reset
;
1825 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1827 case RTL9310_FAMILY_ID
:
1828 priv
->mii_bus
->name
= "rtl931x-eth-mdio";
1829 priv
->mii_bus
->read
= rtl931x_mdio_read
;
1830 priv
->mii_bus
->write
= rtl931x_mdio_write
;
1831 priv
->mii_bus
->reset
= rtl931x_mdio_reset
;
1832 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1835 priv
->mii_bus
->priv
= priv
;
1836 priv
->mii_bus
->parent
= &priv
->pdev
->dev
;
1838 for_each_node_by_name(dn
, "ethernet-phy") {
1841 if (of_property_read_u32(dn
, "reg", &pn
))
1844 if (of_property_read_u32_array(dn
, "rtl9300,smi-address", &smi_addr
[0], 2)) {
1849 if (pn
< MAX_PORTS
) {
1850 priv
->smi_bus
[pn
] = smi_addr
[0];
1851 priv
->smi_addr
[pn
] = smi_addr
[1];
1853 pr_err("%s: illegal port number %d\n", __func__
, pn
);
1856 if (of_device_is_compatible(dn
, "ethernet-phy-ieee802.3-c45"))
1857 priv
->smi_bus_isc45
[smi_addr
[0]] = true;
1859 if (of_property_read_bool(dn
, "phy-is-integrated")) {
1860 priv
->phy_is_internal
[pn
] = true;
1865 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%pOFn", mii_np
);
1866 ret
= of_mdiobus_register(priv
->mii_bus
, mii_np
);
1869 of_node_put(mii_np
);
1873 static int rtl838x_mdio_remove(struct rtl838x_eth_priv
*priv
)
1875 pr_debug("%s called\n", __func__
);
1879 mdiobus_unregister(priv
->mii_bus
);
1880 mdiobus_free(priv
->mii_bus
);
1885 static netdev_features_t
rtl838x_fix_features(struct net_device
*dev
,
1886 netdev_features_t features
)
1891 static int rtl83xx_set_features(struct net_device
*dev
, netdev_features_t features
)
1893 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1895 if ((features
^ dev
->features
) & NETIF_F_RXCSUM
) {
1896 if (!(features
& NETIF_F_RXCSUM
))
1897 sw_w32_mask(BIT(3), 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1899 sw_w32_mask(0, BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1905 static int rtl93xx_set_features(struct net_device
*dev
, netdev_features_t features
)
1907 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1909 if ((features
^ dev
->features
) & NETIF_F_RXCSUM
) {
1910 if (!(features
& NETIF_F_RXCSUM
))
1911 sw_w32_mask(BIT(4), 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1913 sw_w32_mask(0, BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1919 static const struct net_device_ops rtl838x_eth_netdev_ops
= {
1920 .ndo_open
= rtl838x_eth_open
,
1921 .ndo_stop
= rtl838x_eth_stop
,
1922 .ndo_start_xmit
= rtl838x_eth_tx
,
1923 .ndo_select_queue
= rtl83xx_pick_tx_queue
,
1924 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1925 .ndo_validate_addr
= eth_validate_addr
,
1926 .ndo_set_rx_mode
= rtl838x_eth_set_multicast_list
,
1927 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1928 .ndo_set_features
= rtl83xx_set_features
,
1929 .ndo_fix_features
= rtl838x_fix_features
,
1930 .ndo_setup_tc
= rtl83xx_setup_tc
,
1933 static const struct net_device_ops rtl839x_eth_netdev_ops
= {
1934 .ndo_open
= rtl838x_eth_open
,
1935 .ndo_stop
= rtl838x_eth_stop
,
1936 .ndo_start_xmit
= rtl838x_eth_tx
,
1937 .ndo_select_queue
= rtl83xx_pick_tx_queue
,
1938 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1939 .ndo_validate_addr
= eth_validate_addr
,
1940 .ndo_set_rx_mode
= rtl839x_eth_set_multicast_list
,
1941 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1942 .ndo_set_features
= rtl83xx_set_features
,
1943 .ndo_fix_features
= rtl838x_fix_features
,
1944 .ndo_setup_tc
= rtl83xx_setup_tc
,
1947 static const struct net_device_ops rtl930x_eth_netdev_ops
= {
1948 .ndo_open
= rtl838x_eth_open
,
1949 .ndo_stop
= rtl838x_eth_stop
,
1950 .ndo_start_xmit
= rtl838x_eth_tx
,
1951 .ndo_select_queue
= rtl93xx_pick_tx_queue
,
1952 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1953 .ndo_validate_addr
= eth_validate_addr
,
1954 .ndo_set_rx_mode
= rtl930x_eth_set_multicast_list
,
1955 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1956 .ndo_set_features
= rtl93xx_set_features
,
1957 .ndo_fix_features
= rtl838x_fix_features
,
1958 .ndo_setup_tc
= rtl83xx_setup_tc
,
1961 static const struct net_device_ops rtl931x_eth_netdev_ops
= {
1962 .ndo_open
= rtl838x_eth_open
,
1963 .ndo_stop
= rtl838x_eth_stop
,
1964 .ndo_start_xmit
= rtl838x_eth_tx
,
1965 .ndo_select_queue
= rtl93xx_pick_tx_queue
,
1966 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1967 .ndo_validate_addr
= eth_validate_addr
,
1968 .ndo_set_rx_mode
= rtl931x_eth_set_multicast_list
,
1969 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1970 .ndo_set_features
= rtl93xx_set_features
,
1971 .ndo_fix_features
= rtl838x_fix_features
,
1974 static const struct phylink_mac_ops rtl838x_phylink_ops
= {
1975 .validate
= rtl838x_validate
,
1976 .mac_pcs_get_state
= rtl838x_mac_pcs_get_state
,
1977 .mac_an_restart
= rtl838x_mac_an_restart
,
1978 .mac_config
= rtl838x_mac_config
,
1979 .mac_link_down
= rtl838x_mac_link_down
,
1980 .mac_link_up
= rtl838x_mac_link_up
,
1983 static const struct ethtool_ops rtl838x_ethtool_ops
= {
1984 .get_link_ksettings
= rtl838x_get_link_ksettings
,
1985 .set_link_ksettings
= rtl838x_set_link_ksettings
,
1988 static int __init
rtl838x_eth_probe(struct platform_device
*pdev
)
1990 struct net_device
*dev
;
1991 struct device_node
*dn
= pdev
->dev
.of_node
;
1992 struct rtl838x_eth_priv
*priv
;
1993 struct resource
*res
, *mem
;
1994 phy_interface_t phy_mode
;
1995 struct phylink
*phylink
;
1996 int err
= 0, i
, rxrings
, rxringlen
;
1997 struct ring_b
*ring
;
1999 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2000 (u32
)pdev
, (u32
)(&(pdev
->dev
)));
2003 dev_err(&pdev
->dev
, "No DT found\n");
2007 rxrings
= (soc_info
.family
== RTL8380_FAMILY_ID
2008 || soc_info
.family
== RTL8390_FAMILY_ID
) ? 8 : 32;
2009 rxrings
= rxrings
> MAX_RXRINGS
? MAX_RXRINGS
: rxrings
;
2010 rxringlen
= MAX_ENTRIES
/ rxrings
;
2011 rxringlen
= rxringlen
> MAX_RXLEN
? MAX_RXLEN
: rxringlen
;
2013 dev
= alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv
), TXRINGS
, rxrings
);
2018 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2019 priv
= netdev_priv(dev
);
2021 /* obtain buffer memory space */
2022 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2024 mem
= devm_request_mem_region(&pdev
->dev
, res
->start
,
2025 resource_size(res
), res
->name
);
2027 dev_err(&pdev
->dev
, "cannot request memory space\n");
2032 dev
->mem_start
= mem
->start
;
2033 dev
->mem_end
= mem
->end
;
2035 dev_err(&pdev
->dev
, "cannot request IO resource\n");
2040 /* Allocate buffer memory */
2041 priv
->membase
= dmam_alloc_coherent(&pdev
->dev
, rxrings
* rxringlen
* RING_BUFFER
2042 + sizeof(struct ring_b
) + sizeof(struct notify_b
),
2043 (void *)&dev
->mem_start
, GFP_KERNEL
);
2044 if (!priv
->membase
) {
2045 dev_err(&pdev
->dev
, "cannot allocate DMA buffer\n");
2050 // Allocate ring-buffer space at the end of the allocated memory
2051 ring
= priv
->membase
;
2052 ring
->rx_space
= priv
->membase
+ sizeof(struct ring_b
) + sizeof(struct notify_b
);
2054 spin_lock_init(&priv
->lock
);
2056 /* obtain device IRQ number */
2057 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2059 dev_err(&pdev
->dev
, "cannot obtain IRQ, using default 24\n");
2062 dev
->irq
= res
->start
;
2064 dev
->ethtool_ops
= &rtl838x_ethtool_ops
;
2065 dev
->min_mtu
= ETH_ZLEN
;
2066 dev
->max_mtu
= 1536;
2067 dev
->features
= NETIF_F_RXCSUM
| NETIF_F_HW_CSUM
;
2068 dev
->hw_features
= NETIF_F_RXCSUM
;
2070 priv
->id
= soc_info
.id
;
2071 priv
->family_id
= soc_info
.family
;
2073 pr_info("Found SoC ID: %4x: %s, family %x\n",
2074 priv
->id
, soc_info
.name
, priv
->family_id
);
2076 pr_err("Unknown chip id (%04x)\n", priv
->id
);
2080 switch (priv
->family_id
) {
2081 case RTL8380_FAMILY_ID
:
2082 priv
->cpu_port
= RTL838X_CPU_PORT
;
2083 priv
->r
= &rtl838x_reg
;
2084 dev
->netdev_ops
= &rtl838x_eth_netdev_ops
;
2086 case RTL8390_FAMILY_ID
:
2087 priv
->cpu_port
= RTL839X_CPU_PORT
;
2088 priv
->r
= &rtl839x_reg
;
2089 dev
->netdev_ops
= &rtl839x_eth_netdev_ops
;
2091 case RTL9300_FAMILY_ID
:
2092 priv
->cpu_port
= RTL930X_CPU_PORT
;
2093 priv
->r
= &rtl930x_reg
;
2094 dev
->netdev_ops
= &rtl930x_eth_netdev_ops
;
2096 case RTL9310_FAMILY_ID
:
2097 priv
->cpu_port
= RTL931X_CPU_PORT
;
2098 priv
->r
= &rtl931x_reg
;
2099 dev
->netdev_ops
= &rtl931x_eth_netdev_ops
;
2102 pr_err("Unknown SoC family\n");
2105 priv
->rxringlen
= rxringlen
;
2106 priv
->rxrings
= rxrings
;
2108 rtl8380_init_mac(priv
);
2110 /* try to get mac address in the following order:
2111 * 1) from device tree data
2112 * 2) from internal registers set by bootloader
2114 of_get_mac_address(pdev
->dev
.of_node
, dev
->dev_addr
);
2115 if (is_valid_ether_addr(dev
->dev_addr
)) {
2116 rtl838x_set_mac_hw(dev
, (u8
*)dev
->dev_addr
);
2118 dev
->dev_addr
[0] = (sw_r32(priv
->r
->mac
) >> 8) & 0xff;
2119 dev
->dev_addr
[1] = sw_r32(priv
->r
->mac
) & 0xff;
2120 dev
->dev_addr
[2] = (sw_r32(priv
->r
->mac
+ 4) >> 24) & 0xff;
2121 dev
->dev_addr
[3] = (sw_r32(priv
->r
->mac
+ 4) >> 16) & 0xff;
2122 dev
->dev_addr
[4] = (sw_r32(priv
->r
->mac
+ 4) >> 8) & 0xff;
2123 dev
->dev_addr
[5] = sw_r32(priv
->r
->mac
+ 4) & 0xff;
2125 /* if the address is invalid, use a random value */
2126 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2127 struct sockaddr sa
= { AF_UNSPEC
};
2129 netdev_warn(dev
, "Invalid MAC address, using random\n");
2130 eth_hw_addr_random(dev
);
2131 memcpy(sa
.sa_data
, dev
->dev_addr
, ETH_ALEN
);
2132 if (rtl838x_set_mac_address(dev
, &sa
))
2133 netdev_warn(dev
, "Failed to set MAC address.\n");
2135 pr_info("Using MAC %08x%08x\n", sw_r32(priv
->r
->mac
),
2136 sw_r32(priv
->r
->mac
+ 4));
2137 strcpy(dev
->name
, "eth%d");
2141 err
= rtl838x_mdio_init(priv
);
2145 err
= register_netdev(dev
);
2149 for (i
= 0; i
< priv
->rxrings
; i
++) {
2150 priv
->rx_qs
[i
].id
= i
;
2151 priv
->rx_qs
[i
].priv
= priv
;
2152 netif_napi_add(dev
, &priv
->rx_qs
[i
].napi
, rtl838x_poll_rx
, 64);
2155 platform_set_drvdata(pdev
, dev
);
2157 phy_mode
= PHY_INTERFACE_MODE_NA
;
2158 err
= of_get_phy_mode(dn
, &phy_mode
);
2160 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
2164 priv
->phylink_config
.dev
= &dev
->dev
;
2165 priv
->phylink_config
.type
= PHYLINK_NETDEV
;
2167 phylink
= phylink_create(&priv
->phylink_config
, pdev
->dev
.fwnode
,
2168 phy_mode
, &rtl838x_phylink_ops
);
2169 if (IS_ERR(phylink
)) {
2170 err
= PTR_ERR(phylink
);
2173 priv
->phylink
= phylink
;
2178 pr_err("Error setting up netdev, freeing it again.\n");
2183 static int rtl838x_eth_remove(struct platform_device
*pdev
)
2185 struct net_device
*dev
= platform_get_drvdata(pdev
);
2186 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
2190 pr_info("Removing platform driver for rtl838x-eth\n");
2191 rtl838x_mdio_remove(priv
);
2192 rtl838x_hw_stop(priv
);
2194 netif_tx_stop_all_queues(dev
);
2196 for (i
= 0; i
< priv
->rxrings
; i
++)
2197 netif_napi_del(&priv
->rx_qs
[i
].napi
);
2199 unregister_netdev(dev
);
2205 static const struct of_device_id rtl838x_eth_of_ids
[] = {
2206 { .compatible
= "realtek,rtl838x-eth"},
2209 MODULE_DEVICE_TABLE(of
, rtl838x_eth_of_ids
);
2211 static struct platform_driver rtl838x_eth_driver
= {
2212 .probe
= rtl838x_eth_probe
,
2213 .remove
= rtl838x_eth_remove
,
2215 .name
= "rtl838x-eth",
2217 .of_match_table
= rtl838x_eth_of_ids
,
2221 module_platform_driver(rtl838x_eth_driver
);
2223 MODULE_AUTHOR("B. Koblitz");
2224 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2225 MODULE_LICENSE("GPL");