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realtek: fix RTL839x egress tag for ports >= 32
[openwrt/staging/jow.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 /* cpu_tag[0] is a reserved uint16_t on RTL83xx */
62 uint16_t cpu_tag[10];
63 } __packed __aligned(1);
64
65 struct n_event {
66 uint32_t type:2;
67 uint32_t fidVid:12;
68 uint64_t mac:48;
69 uint32_t slp:6;
70 uint32_t valid:1;
71 uint32_t reserved:27;
72 } __packed __aligned(1);
73
74 struct ring_b {
75 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
76 uint32_t tx_r[TXRINGS][TXRINGLEN];
77 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
78 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
79 uint32_t c_rx[MAX_RXRINGS];
80 uint32_t c_tx[TXRINGS];
81 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
82 uint8_t *rx_space;
83 };
84
85 struct notify_block {
86 struct n_event events[NOTIFY_EVENTS];
87 };
88
89 struct notify_b {
90 struct notify_block blocks[NOTIFY_BLOCKS];
91 u32 reserved1[8];
92 u32 ring[NOTIFY_BLOCKS];
93 u32 reserved2[8];
94 };
95
96 static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
97 {
98 // cpu_tag[0] is reserved on the RTL83XX SoCs
99 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
100 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
101 h->cpu_tag[3] = 0x0000;
102 h->cpu_tag[4] = BIT(dest_port) >> 16;
103 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
104
105 /* Set internal priority (PRI) and enable (AS_PRI) */
106 if (prio >= 0)
107 h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
108 }
109
110 static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
111 {
112 // cpu_tag[0] is reserved on the RTL83XX SoCs
113 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
114 h->cpu_tag[2] = BIT(4) | BIT(7); /* AS_DPM (4) and L2LEARNING (7) flags */
115 h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
116 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
117 if (dest_port >= 32) {
118 dest_port -= 32;
119 h->cpu_tag[2] |= (BIT(dest_port) >> 16) & 0xf;
120 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
121 } else {
122 h->cpu_tag[4] = BIT(dest_port) >> 16;
123 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
124 }
125
126 /* Set internal priority (PRI) and enable (AS_PRI) */
127 if (prio >= 0)
128 h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
129 }
130
131 static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
132 {
133 h->cpu_tag[0] = 0x8000; // CPU tag marker
134 h->cpu_tag[1] = h->cpu_tag[2] = 0;
135 h->cpu_tag[3] = 0;
136 h->cpu_tag[4] = 0;
137 h->cpu_tag[5] = 0;
138 h->cpu_tag[6] = BIT(dest_port) >> 16;
139 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
140
141 /* Enable (AS_QID) and set priority queue (QID) */
142 if (prio >= 0)
143 h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
144 }
145
146 static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
147 {
148 h->cpu_tag[0] = 0x8000; // CPU tag marker
149 h->cpu_tag[1] = h->cpu_tag[2] = 0;
150 h->cpu_tag[3] = 0;
151 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
152 if (dest_port >= 32) {
153 dest_port -= 32;
154 h->cpu_tag[4] = BIT(dest_port) >> 16;
155 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
156 } else {
157 h->cpu_tag[6] = BIT(dest_port) >> 16;
158 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
159 }
160
161 /* Enable (AS_QID) and set priority queue (QID) */
162 if (prio >= 0)
163 h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
164 }
165
166 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
167 {
168 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
169 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
170 h->cpu_tag[3] |= (vlan & 0xff) << 8;
171 }
172
173 struct rtl838x_rx_q {
174 int id;
175 struct rtl838x_eth_priv *priv;
176 struct napi_struct napi;
177 };
178
179 struct rtl838x_eth_priv {
180 struct net_device *netdev;
181 struct platform_device *pdev;
182 void *membase;
183 spinlock_t lock;
184 struct mii_bus *mii_bus;
185 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
186 struct phylink *phylink;
187 struct phylink_config phylink_config;
188 u16 id;
189 u16 family_id;
190 const struct rtl838x_eth_reg *r;
191 u8 cpu_port;
192 u32 lastEvent;
193 u16 rxrings;
194 u16 rxringlen;
195 u8 smi_bus[MAX_PORTS];
196 u8 smi_addr[MAX_PORTS];
197 u32 sds_id[MAX_PORTS];
198 bool smi_bus_isc45[MAX_SMI_BUSSES];
199 bool phy_is_internal[MAX_PORTS];
200 phy_interface_t interfaces[MAX_PORTS];
201 };
202
203 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
204 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
205 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
206 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
207 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
208 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
209 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
210 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
211 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
212 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
213 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
214 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
215
216 /*
217 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
218 * the rings. Writing x into these registers substracts x from its content.
219 * When the content reaches the ring size, the ASIC no longer adds
220 * packets to this receive queue.
221 */
222 void rtl838x_update_cntr(int r, int released)
223 {
224 // This feature is not available on RTL838x SoCs
225 }
226
227 void rtl839x_update_cntr(int r, int released)
228 {
229 // This feature is not available on RTL839x SoCs
230 }
231
232 void rtl930x_update_cntr(int r, int released)
233 {
234 int pos = (r % 3) * 10;
235 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
236 u32 v = sw_r32(reg);
237
238 v = (v >> pos) & 0x3ff;
239 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
240 sw_w32_mask(0x3ff << pos, released << pos, reg);
241 sw_w32(v, reg);
242 }
243
244 void rtl931x_update_cntr(int r, int released)
245 {
246 int pos = (r % 3) * 10;
247 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
248 u32 v = sw_r32(reg);
249
250 v = (v >> pos) & 0x3ff;
251 sw_w32_mask(0x3ff << pos, released << pos, reg);
252 sw_w32(v, reg);
253 }
254
255 struct dsa_tag {
256 u8 reason;
257 u8 queue;
258 u16 port;
259 u8 l2_offloaded;
260 u8 prio;
261 bool crc_error;
262 };
263
264 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
265 {
266 /* cpu_tag[0] is reserved. Fields are off-by-one */
267 t->reason = h->cpu_tag[4] & 0xf;
268 t->queue = (h->cpu_tag[1] & 0xe0) >> 5;
269 t->port = h->cpu_tag[1] & 0x1f;
270 t->crc_error = t->reason == 13;
271
272 pr_debug("Reason: %d\n", t->reason);
273 if (t->reason != 6) // NIC_RX_REASON_SPECIAL_TRAP
274 t->l2_offloaded = 1;
275 else
276 t->l2_offloaded = 0;
277
278 return t->l2_offloaded;
279 }
280
281 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
282 {
283 /* cpu_tag[0] is reserved. Fields are off-by-one */
284 t->reason = h->cpu_tag[5] & 0x1f;
285 t->queue = (h->cpu_tag[4] & 0xe000) >> 13;
286 t->port = h->cpu_tag[1] & 0x3f;
287 t->crc_error = h->cpu_tag[4] & BIT(6);
288
289 pr_debug("Reason: %d\n", t->reason);
290 if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA
291 (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP
292 t->l2_offloaded = 0;
293 else
294 t->l2_offloaded = 1;
295
296 return t->l2_offloaded;
297 }
298
299 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
300 {
301 t->reason = h->cpu_tag[7] & 0x3f;
302 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
303 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
304 t->crc_error = h->cpu_tag[1] & BIT(6);
305
306 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
307 if (t->reason >= 19 && t->reason <= 27)
308 t->l2_offloaded = 0;
309 else
310 t->l2_offloaded = 1;
311
312 return t->l2_offloaded;
313 }
314
315 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
316 {
317 t->reason = h->cpu_tag[7] & 0x3f;
318 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
319 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
320 t->crc_error = h->cpu_tag[1] & BIT(6);
321
322 if (t->reason != 63)
323 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
324 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
325 t->l2_offloaded = 0;
326 else
327 t->l2_offloaded = 1;
328
329 return t->l2_offloaded;
330 }
331
332 /*
333 * Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
335 */
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
337 {
338 int r;
339 u32 *last;
340 struct p_hdr *h;
341 struct ring_b *ring = priv->membase;
342
343 for (r = 0; r < priv->rxrings; r++) {
344 pr_debug("In %s working on r: %d\n", __func__, r);
345 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
346 do {
347 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
348 break;
349 pr_debug("Got something: %d\n", ring->c_rx[r]);
350 h = &ring->rx_header[r][ring->c_rx[r]];
351 memset(h, 0, sizeof(struct p_hdr));
352 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
353 + r * priv->rxringlen * RING_BUFFER
354 + ring->c_rx[r] * RING_BUFFER);
355 h->size = RING_BUFFER;
356 /* make sure the header is visible to the ASIC */
357 mb();
358
359 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
360 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
361 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
362 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
363 }
364 }
365
366 struct fdb_update_work {
367 struct work_struct work;
368 struct net_device *ndev;
369 u64 macs[NOTIFY_EVENTS + 1];
370 };
371
372 void rtl838x_fdb_sync(struct work_struct *work)
373 {
374 const struct fdb_update_work *uw =
375 container_of(work, struct fdb_update_work, work);
376 struct switchdev_notifier_fdb_info info;
377 u8 addr[ETH_ALEN];
378 int i = 0;
379 int action;
380
381 while (uw->macs[i]) {
382 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
383 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
384 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
385 info.addr = &addr[0];
386 info.vid = 0;
387 info.offloaded = 1;
388 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
389 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
390 i++;
391 }
392 kfree(work);
393 }
394
395 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
396 {
397 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
398 u32 e = priv->lastEvent;
399 struct n_event *event;
400 int i;
401 u64 mac;
402 struct fdb_update_work *w;
403
404 while (!(nb->ring[e] & 1)) {
405 w = kzalloc(sizeof(*w), GFP_ATOMIC);
406 if (!w) {
407 pr_err("Out of memory: %s", __func__);
408 return;
409 }
410 INIT_WORK(&w->work, rtl838x_fdb_sync);
411
412 for (i = 0; i < NOTIFY_EVENTS; i++) {
413 event = &nb->blocks[e].events[i];
414 if (!event->valid)
415 continue;
416 mac = event->mac;
417 if (event->type)
418 mac |= 1ULL << 63;
419 w->ndev = priv->netdev;
420 w->macs[i] = mac;
421 }
422
423 /* Hand the ring entry back to the switch */
424 nb->ring[e] = nb->ring[e] | 1;
425 e = (e + 1) % NOTIFY_BLOCKS;
426
427 w->macs[i] = 0ULL;
428 schedule_work(&w->work);
429 }
430 priv->lastEvent = e;
431 }
432
433 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct rtl838x_eth_priv *priv = netdev_priv(dev);
437 u32 status = sw_r32(priv->r->dma_if_intr_sts);
438 int i;
439
440 pr_debug("IRQ: %08x\n", status);
441
442 /* Ignore TX interrupt */
443 if ((status & 0xf0000)) {
444 /* Clear ISR */
445 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
446 }
447
448 /* RX interrupt */
449 if (status & 0x0ff00) {
450 /* ACK and disable RX interrupt for this ring */
451 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
452 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
453 for (i = 0; i < priv->rxrings; i++) {
454 if (status & BIT(i + 8)) {
455 pr_debug("Scheduling queue: %d\n", i);
456 napi_schedule(&priv->rx_qs[i].napi);
457 }
458 }
459 }
460
461 /* RX buffer overrun */
462 if (status & 0x000ff) {
463 pr_debug("RX buffer overrun: status %x, mask: %x\n",
464 status, sw_r32(priv->r->dma_if_intr_msk));
465 sw_w32(status, priv->r->dma_if_intr_sts);
466 rtl838x_rb_cleanup(priv, status & 0xff);
467 }
468
469 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
470 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
471 rtl839x_l2_notification_handler(priv);
472 }
473
474 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
475 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
476 rtl839x_l2_notification_handler(priv);
477 }
478
479 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
480 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
481 rtl839x_l2_notification_handler(priv);
482 }
483
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
488 {
489 struct net_device *dev = dev_id;
490 struct rtl838x_eth_priv *priv = netdev_priv(dev);
491 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
492 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
493 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
494 int i;
495
496 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
497 __func__, status_tx, status_rx, status_rx_r);
498
499 /* Ignore TX interrupt */
500 if (status_tx) {
501 /* Clear ISR */
502 pr_debug("TX done\n");
503 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
504 }
505
506 /* RX interrupt */
507 if (status_rx) {
508 pr_debug("RX IRQ\n");
509 /* ACK and disable RX interrupt for given rings */
510 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
511 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
512 for (i = 0; i < priv->rxrings; i++) {
513 if (status_rx & BIT(i)) {
514 pr_debug("Scheduling queue: %d\n", i);
515 napi_schedule(&priv->rx_qs[i].napi);
516 }
517 }
518 }
519
520 /* RX buffer overrun */
521 if (status_rx_r) {
522 pr_debug("RX buffer overrun: status %x, mask: %x\n",
523 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
524 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
525 rtl838x_rb_cleanup(priv, status_rx_r);
526 }
527
528 return IRQ_HANDLED;
529 }
530
531 static const struct rtl838x_eth_reg rtl838x_reg = {
532 .net_irq = rtl83xx_net_irq,
533 .mac_port_ctrl = rtl838x_mac_port_ctrl,
534 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
535 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
536 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
537 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
538 .dma_rx_base = RTL838X_DMA_RX_BASE,
539 .dma_tx_base = RTL838X_DMA_TX_BASE,
540 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
541 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
542 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
543 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
544 .get_mac_link_sts = rtl838x_get_mac_link_sts,
545 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
546 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
547 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
548 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
549 .mac = RTL838X_MAC,
550 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
551 .update_cntr = rtl838x_update_cntr,
552 .create_tx_header = rtl838x_create_tx_header,
553 .decode_tag = rtl838x_decode_tag,
554 };
555
556 static const struct rtl838x_eth_reg rtl839x_reg = {
557 .net_irq = rtl83xx_net_irq,
558 .mac_port_ctrl = rtl839x_mac_port_ctrl,
559 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
560 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
561 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
562 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
563 .dma_rx_base = RTL839X_DMA_RX_BASE,
564 .dma_tx_base = RTL839X_DMA_TX_BASE,
565 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
566 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
567 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
568 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
569 .get_mac_link_sts = rtl839x_get_mac_link_sts,
570 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
571 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
572 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
573 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
574 .mac = RTL839X_MAC,
575 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
576 .update_cntr = rtl839x_update_cntr,
577 .create_tx_header = rtl839x_create_tx_header,
578 .decode_tag = rtl839x_decode_tag,
579 };
580
581 static const struct rtl838x_eth_reg rtl930x_reg = {
582 .net_irq = rtl93xx_net_irq,
583 .mac_port_ctrl = rtl930x_mac_port_ctrl,
584 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
585 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
586 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
587 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
588 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
589 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
590 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
591 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
592 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
593 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
594 .dma_rx_base = RTL930X_DMA_RX_BASE,
595 .dma_tx_base = RTL930X_DMA_TX_BASE,
596 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
597 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
598 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
599 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
600 .get_mac_link_sts = rtl930x_get_mac_link_sts,
601 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
602 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
603 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
604 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
605 .mac = RTL930X_MAC_L2_ADDR_CTRL,
606 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
607 .update_cntr = rtl930x_update_cntr,
608 .create_tx_header = rtl930x_create_tx_header,
609 .decode_tag = rtl930x_decode_tag,
610 };
611
612 static const struct rtl838x_eth_reg rtl931x_reg = {
613 .net_irq = rtl93xx_net_irq,
614 .mac_port_ctrl = rtl931x_mac_port_ctrl,
615 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
616 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
617 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
618 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
619 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
620 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
621 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
622 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
623 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
624 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
625 .dma_rx_base = RTL931X_DMA_RX_BASE,
626 .dma_tx_base = RTL931X_DMA_TX_BASE,
627 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
628 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
629 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
630 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
631 .get_mac_link_sts = rtl931x_get_mac_link_sts,
632 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
633 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
634 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
635 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
636 .mac = RTL931X_MAC_L2_ADDR_CTRL,
637 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
638 .update_cntr = rtl931x_update_cntr,
639 .create_tx_header = rtl931x_create_tx_header,
640 .decode_tag = rtl931x_decode_tag,
641 };
642
643 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
644 {
645 u32 int_saved, nbuf;
646 u32 reset_mask;
647 int i, pos;
648
649 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
650 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
651 mdelay(100);
652
653 /* Disable and clear interrupts */
654 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
655 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
656 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
657 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
658 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
659 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
660 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
661 } else {
662 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
663 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
664 }
665
666 if (priv->family_id == RTL8390_FAMILY_ID) {
667 /* Preserve L2 notification and NBUF settings */
668 int_saved = sw_r32(priv->r->dma_if_intr_msk);
669 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
670
671 /* Disable link change interrupt on RTL839x */
672 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
673 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
674
675 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
676 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
677 }
678
679 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
680 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
681 reset_mask = 0x6;
682 else
683 reset_mask = 0xc;
684
685 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
686
687 do { /* Wait for reset of NIC and Queues done */
688 udelay(20);
689 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
690 mdelay(100);
691
692 /* Setup Head of Line */
693 if (priv->family_id == RTL8380_FAMILY_ID)
694 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
695 if (priv->family_id == RTL8390_FAMILY_ID)
696 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
697 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
698 for (i = 0; i < priv->rxrings; i++) {
699 pos = (i % 3) * 10;
700 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
701 sw_w32_mask(0x3ff << pos, priv->rxringlen,
702 priv->r->dma_if_rx_ring_cntr(i));
703 }
704 }
705
706 /* Re-enable link change interrupt */
707 if (priv->family_id == RTL8390_FAMILY_ID) {
708 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
709 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
710 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
711 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
712
713 /* Restore notification settings: on RTL838x these bits are null */
714 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
715 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
716 }
717 }
718
719 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
720 {
721 int i;
722 struct ring_b *ring = priv->membase;
723
724 for (i = 0; i < priv->rxrings; i++)
725 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
726
727 for (i = 0; i < TXRINGS; i++)
728 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
729 }
730
731 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
732 {
733 /* Disable Head of Line features for all RX rings */
734 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
735
736 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
737 sw_w32(0x06400020, priv->r->dma_if_ctrl);
738
739 /* Enable RX done, RX overflow and TX done interrupts */
740 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
741
742 /* Enable DMA, engine expects empty FCS field */
743 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
744
745 /* Restart TX/RX to CPU port */
746 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
747 /* Set Speed, duplex, flow control
748 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
749 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
750 * | MEDIA_SEL
751 */
752 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
753
754 /* Enable CRC checks on CPU-port */
755 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
756 }
757
758 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
759 {
760 /* Setup CPU-Port: RX Buffer */
761 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
762
763 /* Enable Notify, RX done, RX overflow and TX done interrupts */
764 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
765
766 /* Enable DMA */
767 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
768
769 /* Restart TX/RX to CPU port, enable CRC checking */
770 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
771
772 /* CPU port joins Lookup Miss Flooding Portmask */
773 // TODO: The code below should also work for the RTL838x
774 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
775 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
776 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
777
778 /* Force CPU port link up */
779 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
780 }
781
782 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
783 {
784 int i, pos;
785 u32 v;
786
787 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
788 sw_w32(0x06400040, priv->r->dma_if_ctrl);
789
790 for (i = 0; i < priv->rxrings; i++) {
791 pos = (i % 3) * 10;
792 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
793
794 // Some SoCs have issues with missing underflow protection
795 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
796 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
797 }
798
799 /* Enable Notify, RX done, RX overflow and TX done interrupts */
800 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
801 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
802 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
803
804 /* Enable DMA */
805 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
806
807 /* Restart TX/RX to CPU port, enable CRC checking */
808 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
809
810 if (priv->family_id == RTL9300_FAMILY_ID)
811 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
812 else
813 sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
814
815 if (priv->family_id == RTL9300_FAMILY_ID)
816 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
817 else
818 sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
819 }
820
821 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
822 {
823 int i, j;
824
825 struct p_hdr *h;
826
827 for (i = 0; i < priv->rxrings; i++) {
828 for (j = 0; j < priv->rxringlen; j++) {
829 h = &ring->rx_header[i][j];
830 memset(h, 0, sizeof(struct p_hdr));
831 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
832 + i * priv->rxringlen * RING_BUFFER
833 + j * RING_BUFFER);
834 h->size = RING_BUFFER;
835 /* All rings owned by switch, last one wraps */
836 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
837 | (j == (priv->rxringlen - 1) ? WRAP : 0);
838 }
839 ring->c_rx[i] = 0;
840 }
841
842 for (i = 0; i < TXRINGS; i++) {
843 for (j = 0; j < TXRINGLEN; j++) {
844 h = &ring->tx_header[i][j];
845 memset(h, 0, sizeof(struct p_hdr));
846 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
847 + i * TXRINGLEN * RING_BUFFER
848 + j * RING_BUFFER);
849 h->size = RING_BUFFER;
850 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
851 }
852 /* Last header is wrapping around */
853 ring->tx_r[i][j-1] |= WRAP;
854 ring->c_tx[i] = 0;
855 }
856 }
857
858 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
859 {
860 int i;
861 struct notify_b *b = priv->membase + sizeof(struct ring_b);
862
863 for (i = 0; i < NOTIFY_BLOCKS; i++)
864 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
865
866 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
867 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
868
869 /* Setup notification events */
870 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
871 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
872
873 /* Enable Notification */
874 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
875 priv->lastEvent = 0;
876 }
877
878 static int rtl838x_eth_open(struct net_device *ndev)
879 {
880 unsigned long flags;
881 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
882 struct ring_b *ring = priv->membase;
883 int i;
884
885 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
886 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
887
888 spin_lock_irqsave(&priv->lock, flags);
889 rtl838x_hw_reset(priv);
890 rtl838x_setup_ring_buffer(priv, ring);
891 if (priv->family_id == RTL8390_FAMILY_ID) {
892 rtl839x_setup_notify_ring_buffer(priv);
893 /* Make sure the ring structure is visible to the ASIC */
894 mb();
895 flush_cache_all();
896 }
897
898 rtl838x_hw_ring_setup(priv);
899 phylink_start(priv->phylink);
900
901 for (i = 0; i < priv->rxrings; i++)
902 napi_enable(&priv->rx_qs[i].napi);
903
904 switch (priv->family_id) {
905 case RTL8380_FAMILY_ID:
906 rtl838x_hw_en_rxtx(priv);
907 /* Trap IGMP/MLD traffic to CPU-Port */
908 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
909 /* Flush learned FDB entries on link down of a port */
910 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
911 break;
912
913 case RTL8390_FAMILY_ID:
914 rtl839x_hw_en_rxtx(priv);
915 // Trap MLD and IGMP messages to CPU_PORT
916 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
917 /* Flush learned FDB entries on link down of a port */
918 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
919 break;
920
921 case RTL9300_FAMILY_ID:
922 rtl93xx_hw_en_rxtx(priv);
923 /* Flush learned FDB entries on link down of a port */
924 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
925 // Trap MLD and IGMP messages to CPU_PORT
926 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
927 break;
928
929 case RTL9310_FAMILY_ID:
930 rtl93xx_hw_en_rxtx(priv);
931
932 // Trap MLD and IGMP messages to CPU_PORT
933 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
934
935 // Disable External CPU access to switch, clear EXT_CPU_EN
936 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
937
938 // Set PCIE_PWR_DOWN
939 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
940 break;
941 }
942
943 netif_tx_start_all_queues(ndev);
944
945 spin_unlock_irqrestore(&priv->lock, flags);
946
947 return 0;
948 }
949
950 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
951 {
952 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
953 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
954 int i;
955
956 // Disable RX/TX from/to CPU-port
957 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
958
959 /* Disable traffic */
960 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
961 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
962 else
963 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
964 mdelay(200); // Test, whether this is needed
965
966 /* Block all ports */
967 if (priv->family_id == RTL8380_FAMILY_ID) {
968 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
969 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
970 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
971 }
972
973 /* Flush L2 address cache */
974 if (priv->family_id == RTL8380_FAMILY_ID) {
975 for (i = 0; i <= priv->cpu_port; i++) {
976 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
977 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
978 }
979 } else if (priv->family_id == RTL8390_FAMILY_ID) {
980 for (i = 0; i <= priv->cpu_port; i++) {
981 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
982 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
983 }
984 }
985 // TODO: L2 flush register is 64 bit on RTL931X and 930X
986
987 /* CPU-Port: Link down */
988 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
989 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
990 else if (priv->family_id == RTL9300_FAMILY_ID)
991 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
992 else if (priv->family_id == RTL9310_FAMILY_ID)
993 sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
994 mdelay(100);
995
996 /* Disable all TX/RX interrupts */
997 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
998 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
999 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
1000 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
1001 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
1002 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
1003 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
1004 } else {
1005 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
1006 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
1007 }
1008
1009 /* Disable TX/RX DMA */
1010 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1011 mdelay(200);
1012 }
1013
1014 static int rtl838x_eth_stop(struct net_device *ndev)
1015 {
1016 unsigned long flags;
1017 int i;
1018 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1019
1020 pr_info("in %s\n", __func__);
1021
1022 phylink_stop(priv->phylink);
1023 rtl838x_hw_stop(priv);
1024
1025 for (i = 0; i < priv->rxrings; i++)
1026 napi_disable(&priv->rx_qs[i].napi);
1027
1028 netif_tx_stop_all_queues(ndev);
1029
1030 return 0;
1031 }
1032
1033 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1034 {
1035 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1036 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1037 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1038 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1039 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1040 }
1041 if (ndev->flags & IFF_ALLMULTI) {
1042 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1043 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1044 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1045 }
1046 if (ndev->flags & IFF_PROMISC) {
1047 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1048 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1049 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1050 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1051 }
1052 }
1053
1054 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1055 {
1056 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1057
1058 if (priv->family_id == RTL8390_FAMILY_ID)
1059 return rtl839x_eth_set_multicast_list(ndev);
1060
1061 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1062 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1063 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1064 }
1065 if (ndev->flags & IFF_ALLMULTI)
1066 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1067 if (ndev->flags & IFF_PROMISC) {
1068 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1069 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1070 }
1071 }
1072
1073 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1074 {
1075 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1076 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1077 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1078 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1079 }
1080 if (ndev->flags & IFF_ALLMULTI) {
1081 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1082 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1083 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1084 }
1085 if (ndev->flags & IFF_PROMISC) {
1086 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1087 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1088 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1089 }
1090 }
1091
1092 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1093 {
1094 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1095 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1096 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1097 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1098 }
1099 if (ndev->flags & IFF_ALLMULTI) {
1100 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1101 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1102 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1103 }
1104 if (ndev->flags & IFF_PROMISC) {
1105 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1106 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1107 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1108 }
1109 }
1110
1111 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1112 {
1113 unsigned long flags;
1114 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1115
1116 pr_warn("%s\n", __func__);
1117 spin_lock_irqsave(&priv->lock, flags);
1118 rtl838x_hw_stop(priv);
1119 rtl838x_hw_ring_setup(priv);
1120 rtl838x_hw_en_rxtx(priv);
1121 netif_trans_update(ndev);
1122 netif_start_queue(ndev);
1123 spin_unlock_irqrestore(&priv->lock, flags);
1124 }
1125
1126 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1127 {
1128 int len, i;
1129 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1130 struct ring_b *ring = priv->membase;
1131 uint32_t val;
1132 int ret;
1133 unsigned long flags;
1134 struct p_hdr *h;
1135 int dest_port = -1;
1136 int q = skb_get_queue_mapping(skb) % TXRINGS;
1137
1138 if (q) // Check for high prio queue
1139 pr_debug("SKB priority: %d\n", skb->priority);
1140
1141 spin_lock_irqsave(&priv->lock, flags);
1142 len = skb->len;
1143
1144 /* Check for DSA tagging at the end of the buffer */
1145 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80
1146 && skb->data[len-3] < priv->cpu_port
1147 && skb->data[len-2] == 0x10
1148 && skb->data[len-1] == 0x00) {
1149 /* Reuse tag space for CRC if possible */
1150 dest_port = skb->data[len-3];
1151 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1152 len -= 4;
1153 }
1154
1155 len += 4; // Add space for CRC
1156
1157 if (skb_padto(skb, len)) {
1158 ret = NETDEV_TX_OK;
1159 goto txdone;
1160 }
1161
1162 /* We can send this packet if CPU owns the descriptor */
1163 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1164
1165 /* Set descriptor for tx */
1166 h = &ring->tx_header[q][ring->c_tx[q]];
1167 h->size = len;
1168 h->len = len;
1169 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1170 if (priv->family_id == RTL8380_FAMILY_ID) {
1171 if (len < ETH_ZLEN - 4)
1172 h->len -= 4;
1173 }
1174
1175 if (dest_port >= 0)
1176 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1177
1178 /* Copy packet data to tx buffer */
1179 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1180 /* Make sure packet data is visible to ASIC */
1181 wmb();
1182
1183 /* Hand over to switch */
1184 ring->tx_r[q][ring->c_tx[q]] |= 1;
1185
1186 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1187 if (priv->family_id == RTL8380_FAMILY_ID) {
1188 for (i = 0; i < 10; i++) {
1189 val = sw_r32(priv->r->dma_if_ctrl);
1190 if ((val & 0xc) == 0xc)
1191 break;
1192 }
1193 }
1194
1195 /* Tell switch to send data */
1196 if (priv->family_id == RTL9310_FAMILY_ID
1197 || priv->family_id == RTL9300_FAMILY_ID) {
1198 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1199 if (!q)
1200 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1201 else
1202 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1203 } else {
1204 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1205 }
1206
1207 dev->stats.tx_packets++;
1208 dev->stats.tx_bytes += len;
1209 dev_kfree_skb(skb);
1210 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1211 ret = NETDEV_TX_OK;
1212 } else {
1213 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1214 ret = NETDEV_TX_BUSY;
1215 }
1216 txdone:
1217 spin_unlock_irqrestore(&priv->lock, flags);
1218 return ret;
1219 }
1220
1221 /*
1222 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1223 * so we do round-robin
1224 */
1225 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1226 struct net_device *sb_dev)
1227 {
1228 static u8 last = 0;
1229
1230 last++;
1231 return last % TXRINGS;
1232 }
1233
1234 /*
1235 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1236 */
1237 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1238 struct net_device *sb_dev)
1239 {
1240 if (skb->priority >= TC_PRIO_CONTROL)
1241 return 1;
1242 return 0;
1243 }
1244
1245 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1246 {
1247 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1248 struct ring_b *ring = priv->membase;
1249 struct sk_buff *skb;
1250 unsigned long flags;
1251 int i, len, work_done = 0;
1252 u8 *data, *skb_data;
1253 unsigned int val;
1254 u32 *last;
1255 struct p_hdr *h;
1256 bool dsa = netdev_uses_dsa(dev);
1257 struct dsa_tag tag;
1258
1259 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1260 spin_lock_irqsave(&priv->lock, flags);
1261 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1262
1263 do {
1264 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1265 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1266 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1267 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1268 }
1269 break;
1270 }
1271
1272 h = &ring->rx_header[r][ring->c_rx[r]];
1273 data = (u8 *)KSEG1ADDR(h->buf);
1274 len = h->len;
1275 if (!len)
1276 break;
1277 work_done++;
1278
1279 len -= 4; /* strip the CRC */
1280 /* Add 4 bytes for cpu_tag */
1281 if (dsa)
1282 len += 4;
1283
1284 skb = netdev_alloc_skb(dev, len + 4);
1285 skb_reserve(skb, NET_IP_ALIGN);
1286
1287 if (likely(skb)) {
1288 /* BUG: Prevent bug on RTL838x SoCs*/
1289 if (priv->family_id == RTL8380_FAMILY_ID) {
1290 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1291 for (i = 0; i < priv->rxrings; i++) {
1292 /* Update each ring cnt */
1293 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1294 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1295 }
1296 }
1297
1298 skb_data = skb_put(skb, len);
1299 /* Make sure data is visible */
1300 mb();
1301 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1302 /* Overwrite CRC with cpu_tag */
1303 if (dsa) {
1304 priv->r->decode_tag(h, &tag);
1305 skb->data[len-4] = 0x80;
1306 skb->data[len-3] = tag.port;
1307 skb->data[len-2] = 0x10;
1308 skb->data[len-1] = 0x00;
1309 if (tag.l2_offloaded)
1310 skb->data[len-3] |= 0x40;
1311 }
1312
1313 if (tag.queue >= 0)
1314 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1315 tag.queue, len, tag.reason, tag.port);
1316
1317 skb->protocol = eth_type_trans(skb, dev);
1318 if (dev->features & NETIF_F_RXCSUM) {
1319 if (tag.crc_error)
1320 skb_checksum_none_assert(skb);
1321 else
1322 skb->ip_summed = CHECKSUM_UNNECESSARY;
1323 }
1324 dev->stats.rx_packets++;
1325 dev->stats.rx_bytes += len;
1326
1327 netif_receive_skb(skb);
1328 } else {
1329 if (net_ratelimit())
1330 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1331 dev->stats.rx_dropped++;
1332 }
1333
1334 /* Reset header structure */
1335 memset(h, 0, sizeof(struct p_hdr));
1336 h->buf = data;
1337 h->size = RING_BUFFER;
1338
1339 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1340 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1341 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1342 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1343 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1344
1345 // Update counters
1346 priv->r->update_cntr(r, 0);
1347
1348 spin_unlock_irqrestore(&priv->lock, flags);
1349
1350 return work_done;
1351 }
1352
1353 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1354 {
1355 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1356 struct rtl838x_eth_priv *priv = rx_q->priv;
1357 int work_done = 0;
1358 int r = rx_q->id;
1359 int work;
1360
1361 while (work_done < budget) {
1362 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1363 if (!work)
1364 break;
1365 work_done += work;
1366 }
1367
1368 if (work_done < budget) {
1369 napi_complete_done(napi, work_done);
1370
1371 /* Enable RX interrupt */
1372 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1373 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1374 else
1375 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1376 }
1377 return work_done;
1378 }
1379
1380
1381 static void rtl838x_validate(struct phylink_config *config,
1382 unsigned long *supported,
1383 struct phylink_link_state *state)
1384 {
1385 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1386
1387 pr_debug("In %s\n", __func__);
1388
1389 if (!phy_interface_mode_is_rgmii(state->interface) &&
1390 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1391 state->interface != PHY_INTERFACE_MODE_MII &&
1392 state->interface != PHY_INTERFACE_MODE_REVMII &&
1393 state->interface != PHY_INTERFACE_MODE_GMII &&
1394 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1395 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1396 state->interface != PHY_INTERFACE_MODE_SGMII) {
1397 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1398 pr_err("Unsupported interface: %d\n", state->interface);
1399 return;
1400 }
1401
1402 /* Allow all the expected bits */
1403 phylink_set(mask, Autoneg);
1404 phylink_set_port_modes(mask);
1405 phylink_set(mask, Pause);
1406 phylink_set(mask, Asym_Pause);
1407
1408 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1409 * including Half duplex
1410 */
1411 if (state->interface != PHY_INTERFACE_MODE_MII &&
1412 state->interface != PHY_INTERFACE_MODE_REVMII) {
1413 phylink_set(mask, 1000baseT_Full);
1414 phylink_set(mask, 1000baseT_Half);
1415 }
1416
1417 phylink_set(mask, 10baseT_Half);
1418 phylink_set(mask, 10baseT_Full);
1419 phylink_set(mask, 100baseT_Half);
1420 phylink_set(mask, 100baseT_Full);
1421
1422 bitmap_and(supported, supported, mask,
1423 __ETHTOOL_LINK_MODE_MASK_NBITS);
1424 bitmap_and(state->advertising, state->advertising, mask,
1425 __ETHTOOL_LINK_MODE_MASK_NBITS);
1426 }
1427
1428
1429 static void rtl838x_mac_config(struct phylink_config *config,
1430 unsigned int mode,
1431 const struct phylink_link_state *state)
1432 {
1433 /* This is only being called for the master device,
1434 * i.e. the CPU-Port. We don't need to do anything.
1435 */
1436
1437 pr_info("In %s, mode %x\n", __func__, mode);
1438 }
1439
1440 static void rtl838x_mac_an_restart(struct phylink_config *config)
1441 {
1442 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1443 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1444
1445 /* This works only on RTL838x chips */
1446 if (priv->family_id != RTL8380_FAMILY_ID)
1447 return;
1448
1449 pr_debug("In %s\n", __func__);
1450 /* Restart by disabling and re-enabling link */
1451 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1452 mdelay(20);
1453 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1454 }
1455
1456 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1457 struct phylink_link_state *state)
1458 {
1459 u32 speed;
1460 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1461 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1462 int port = priv->cpu_port;
1463
1464 pr_info("In %s\n", __func__);
1465
1466 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1467 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1468
1469 pr_info("%s link status is %d\n", __func__, state->link);
1470 speed = priv->r->get_mac_link_spd_sts(port);
1471 switch (speed) {
1472 case 0:
1473 state->speed = SPEED_10;
1474 break;
1475 case 1:
1476 state->speed = SPEED_100;
1477 break;
1478 case 2:
1479 state->speed = SPEED_1000;
1480 break;
1481 case 5:
1482 state->speed = SPEED_2500;
1483 break;
1484 case 6:
1485 state->speed = SPEED_5000;
1486 break;
1487 case 4:
1488 state->speed = SPEED_10000;
1489 break;
1490 default:
1491 state->speed = SPEED_UNKNOWN;
1492 break;
1493 }
1494
1495 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1496 if (priv->r->get_mac_rx_pause_sts(port))
1497 state->pause |= MLO_PAUSE_RX;
1498 if (priv->r->get_mac_tx_pause_sts(port))
1499 state->pause |= MLO_PAUSE_TX;
1500 }
1501
1502 static void rtl838x_mac_link_down(struct phylink_config *config,
1503 unsigned int mode,
1504 phy_interface_t interface)
1505 {
1506 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1507 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1508
1509 pr_debug("In %s\n", __func__);
1510 /* Stop TX/RX to port */
1511 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1512 }
1513
1514 static void rtl838x_mac_link_up(struct phylink_config *config,
1515 struct phy_device *phy, unsigned int mode,
1516 phy_interface_t interface, int speed, int duplex,
1517 bool tx_pause, bool rx_pause)
1518 {
1519 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1520 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1521
1522 pr_debug("In %s\n", __func__);
1523 /* Restart TX/RX to port */
1524 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1525 }
1526
1527 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1528 {
1529 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1530 unsigned long flags;
1531
1532 spin_lock_irqsave(&priv->lock, flags);
1533 pr_debug("In %s\n", __func__);
1534 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1535 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1536
1537 if (priv->family_id == RTL8380_FAMILY_ID) {
1538 /* 2 more registers, ALE/MAC block */
1539 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1540 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1541 (RTL838X_MAC_ALE + 4));
1542
1543 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1544 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1545 RTL838X_MAC2 + 4);
1546 }
1547 spin_unlock_irqrestore(&priv->lock, flags);
1548 }
1549
1550 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1551 {
1552 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1553 const struct sockaddr *addr = p;
1554 u8 *mac = (u8 *) (addr->sa_data);
1555
1556 if (!is_valid_ether_addr(addr->sa_data))
1557 return -EADDRNOTAVAIL;
1558
1559 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1560 rtl838x_set_mac_hw(dev, mac);
1561
1562 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1563 return 0;
1564 }
1565
1566 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1567 {
1568 // We will need to set-up EEE and the egress-rate limitation
1569 return 0;
1570 }
1571
1572 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1573 {
1574 int i;
1575
1576 if (priv->family_id == 0x8390)
1577 return rtl8390_init_mac(priv);
1578
1579 // At present we do not know how to set up EEE on any other SoC than RTL8380
1580 if (priv->family_id != 0x8380)
1581 return 0;
1582
1583 pr_info("%s\n", __func__);
1584 /* fix timer for EEE */
1585 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1586 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1587
1588 /* Init VLAN. TODO: Understand what is being done, here */
1589 if (priv->id == 0x8382) {
1590 for (i = 0; i <= 28; i++)
1591 sw_w32(0, 0xd57c + i * 0x80);
1592 }
1593 if (priv->id == 0x8380) {
1594 for (i = 8; i <= 28; i++)
1595 sw_w32(0, 0xd57c + i * 0x80);
1596 }
1597 return 0;
1598 }
1599
1600 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1601 struct ethtool_link_ksettings *cmd)
1602 {
1603 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1604
1605 pr_debug("%s called\n", __func__);
1606 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1607 }
1608
1609 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1610 const struct ethtool_link_ksettings *cmd)
1611 {
1612 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1613
1614 pr_debug("%s called\n", __func__);
1615 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1616 }
1617
1618 static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1619 {
1620 u32 val;
1621 int err;
1622 struct rtl838x_eth_priv *priv = bus->priv;
1623
1624 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1625 return rtl838x_read_sds_phy(mii_id, regnum);
1626
1627 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1628 err = rtl838x_read_mmd_phy(mii_id,
1629 mdiobus_c45_devad(regnum),
1630 regnum, &val);
1631 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1632 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1633 val, err);
1634 } else {
1635 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1636 err = rtl838x_read_phy(mii_id, page, regnum, &val);
1637 }
1638 if (err)
1639 return err;
1640 return val;
1641 }
1642
1643 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1644 {
1645 return rtl838x_mdio_read_paged(bus, mii_id, 0, regnum);
1646 }
1647
1648 static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1649 {
1650 u32 val;
1651 int err;
1652 struct rtl838x_eth_priv *priv = bus->priv;
1653
1654 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1655 return rtl839x_read_sds_phy(mii_id, regnum);
1656
1657 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1658 err = rtl839x_read_mmd_phy(mii_id,
1659 mdiobus_c45_devad(regnum),
1660 regnum, &val);
1661 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1662 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1663 val, err);
1664 } else {
1665 err = rtl839x_read_phy(mii_id, page, regnum, &val);
1666 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1667 }
1668 if (err)
1669 return err;
1670 return val;
1671 }
1672
1673 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1674 {
1675 return rtl839x_mdio_read_paged(bus, mii_id, 0, regnum);
1676 }
1677
1678 static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1679 {
1680 u32 val;
1681 int err;
1682 struct rtl838x_eth_priv *priv = bus->priv;
1683
1684 if (priv->phy_is_internal[mii_id])
1685 return rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1686
1687 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1688 err = rtl930x_read_mmd_phy(mii_id,
1689 mdiobus_c45_devad(regnum),
1690 regnum, &val);
1691 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1692 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1693 val, err);
1694 } else {
1695 err = rtl930x_read_phy(mii_id, page, regnum, &val);
1696 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1697 }
1698 if (err)
1699 return err;
1700 return val;
1701 }
1702
1703 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1704 {
1705 return rtl930x_mdio_read_paged(bus, mii_id, 0, regnum);
1706 }
1707
1708 static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1709 {
1710 u32 val;
1711 int err, v;
1712 struct rtl838x_eth_priv *priv = bus->priv;
1713
1714 pr_debug("%s: In here, port %d\n", __func__, mii_id);
1715 if (priv->phy_is_internal[mii_id]) {
1716 v = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1717 if (v < 0) {
1718 err = v;
1719 } else {
1720 err = 0;
1721 val = v;
1722 }
1723 } else {
1724 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1725 err = rtl931x_read_mmd_phy(mii_id,
1726 mdiobus_c45_devad(regnum),
1727 regnum, &val);
1728 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1729 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1730 val, err);
1731 } else {
1732 err = rtl931x_read_phy(mii_id, page, regnum, &val);
1733 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1734 }
1735 }
1736
1737 if (err)
1738 return err;
1739 return val;
1740 }
1741
1742 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1743 {
1744 return rtl931x_mdio_read_paged(bus, mii_id, 0, regnum);
1745 }
1746
1747 static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1748 int regnum, u16 value)
1749 {
1750 u32 offset = 0;
1751 struct rtl838x_eth_priv *priv = bus->priv;
1752 int err;
1753
1754 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1755 if (mii_id == 26)
1756 offset = 0x100;
1757 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1758 return 0;
1759 }
1760
1761 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1762 err = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1763 regnum, value);
1764 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1765 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1766 value, err);
1767
1768 return err;
1769 }
1770 err = rtl838x_write_phy(mii_id, page, regnum, value);
1771 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1772 return err;
1773 }
1774
1775 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1776 int regnum, u16 value)
1777 {
1778 return rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1779 }
1780
1781 static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1782 int regnum, u16 value)
1783 {
1784 struct rtl838x_eth_priv *priv = bus->priv;
1785 int err;
1786
1787 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1788 return rtl839x_write_sds_phy(mii_id, regnum, value);
1789
1790 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1791 err = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1792 regnum, value);
1793 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1794 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1795 value, err);
1796
1797 return err;
1798 }
1799
1800 err = rtl839x_write_phy(mii_id, page, regnum, value);
1801 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1802 return err;
1803 }
1804
1805 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1806 int regnum, u16 value)
1807 {
1808 return rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1809 }
1810
1811 static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1812 int regnum, u16 value)
1813 {
1814 struct rtl838x_eth_priv *priv = bus->priv;
1815 int err;
1816
1817 if (priv->phy_is_internal[mii_id])
1818 return rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1819
1820 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD))
1821 return rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1822 regnum, value);
1823
1824 err = rtl930x_write_phy(mii_id, page, regnum, value);
1825 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1826 return err;
1827 }
1828
1829 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1830 int regnum, u16 value)
1831 {
1832 return rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1833 }
1834
1835 static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1836 int regnum, u16 value)
1837 {
1838 struct rtl838x_eth_priv *priv = bus->priv;
1839 int err;
1840
1841 if (priv->phy_is_internal[mii_id])
1842 return rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1843
1844 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1845 err = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1846 regnum, value);
1847 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1848 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1849 value, err);
1850
1851 return err;
1852 }
1853
1854 err = rtl931x_write_phy(mii_id, page, regnum, value);
1855 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1856 return err;
1857 }
1858
1859 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1860 int regnum, u16 value)
1861 {
1862 return rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1863 }
1864
1865 static int rtl838x_mdio_reset(struct mii_bus *bus)
1866 {
1867 pr_debug("%s called\n", __func__);
1868 /* Disable MAC polling the PHY so that we can start configuration */
1869 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1870
1871 /* Enable PHY control via SoC */
1872 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1873
1874 // Probably should reset all PHYs here...
1875 return 0;
1876 }
1877
1878 static int rtl839x_mdio_reset(struct mii_bus *bus)
1879 {
1880 return 0;
1881
1882 pr_debug("%s called\n", __func__);
1883 /* BUG: The following does not work, but should! */
1884 /* Disable MAC polling the PHY so that we can start configuration */
1885 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1886 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1887 /* Disable PHY polling via SoC */
1888 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1889
1890 // Probably should reset all PHYs here...
1891 return 0;
1892 }
1893
1894 u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1895 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1896
1897 static int rtl930x_mdio_reset(struct mii_bus *bus)
1898 {
1899 int i;
1900 int pos;
1901 struct rtl838x_eth_priv *priv = bus->priv;
1902 u32 c45_mask = 0;
1903 u32 poll_sel[2];
1904 u32 poll_ctrl = 0;
1905 u32 private_poll_mask = 0;
1906 u32 v;
1907 bool uses_usxgmii = false; // For the Aquantia PHYs
1908 bool uses_hisgmii = false; // For the RTL8221/8226
1909
1910 // Mapping of port to phy-addresses on an SMI bus
1911 poll_sel[0] = poll_sel[1] = 0;
1912 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1913 if (priv->smi_bus[i] > 3)
1914 continue;
1915 pos = (i % 6) * 5;
1916 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1917 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1918
1919 pos = (i * 2) % 32;
1920 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1921 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1922 }
1923
1924 // Configure which SMI bus is behind which port number
1925 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1926 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1927
1928 // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+)
1929 sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
1930
1931 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1932 for (i = 0; i < 4; i++)
1933 if (priv->smi_bus_isc45[i])
1934 c45_mask |= BIT(i + 16);
1935
1936 pr_info("c45_mask: %08x\n", c45_mask);
1937 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1938
1939 // Set the MAC type of each port according to the PHY-interface
1940 // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0
1941 v = 0;
1942 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1943 switch (priv->interfaces[i]) {
1944 case PHY_INTERFACE_MODE_10GBASER:
1945 break; // Serdes: Value = 0
1946
1947 case PHY_INTERFACE_MODE_HSGMII:
1948 private_poll_mask |= BIT(i);
1949 // fallthrough
1950 case PHY_INTERFACE_MODE_USXGMII:
1951 v |= BIT(mac_type_bit[i]);
1952 uses_usxgmii = true;
1953 break;
1954
1955 case PHY_INTERFACE_MODE_QSGMII:
1956 private_poll_mask |= BIT(i);
1957 v |= 3 << mac_type_bit[i];
1958 break;
1959
1960 default:
1961 break;
1962 }
1963 }
1964 sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);
1965
1966 // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones)
1967 sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);
1968
1969 /* The following magic values are found in the port configuration, they seem to
1970 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1971 * the XGS1250 and the RTL8226 of the XGS1210 */
1972 if (uses_usxgmii) {
1973 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1974 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1975 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1976 }
1977 if (uses_hisgmii) {
1978 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1979 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1980 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1981 }
1982
1983 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__,
1984 sw_r32(RTL930X_SMI_GLB_CTRL));
1985 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__,
1986 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));
1987 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__,
1988 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
1989 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__,
1990 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));
1991 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__,
1992 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));
1993 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__,
1994 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));
1995 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__,
1996 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));
1997 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__,
1998 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));
1999 return 0;
2000 }
2001
2002 static int rtl931x_mdio_reset(struct mii_bus *bus)
2003 {
2004 int i;
2005 int pos;
2006 struct rtl838x_eth_priv *priv = bus->priv;
2007 u32 c45_mask = 0;
2008 u32 poll_sel[4];
2009 u32 poll_ctrl = 0;
2010 bool mdc_on[4];
2011
2012 pr_info("%s called\n", __func__);
2013 // Disable port polling for configuration purposes
2014 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
2015 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
2016 msleep(100);
2017
2018 mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
2019 // Mapping of port to phy-addresses on an SMI bus
2020 poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
2021 for (i = 0; i < 56; i++) {
2022 pos = (i % 6) * 5;
2023 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
2024 pos = (i * 2) % 32;
2025 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
2026 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
2027 mdc_on[priv->smi_bus[i]] = true;
2028 }
2029
2030 // Configure which SMI bus is behind which port number
2031 for (i = 0; i < 4; i++) {
2032 pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
2033 sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
2034 }
2035
2036 // Configure which SMI busses
2037 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2038 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2039 for (i = 0; i < 4; i++) {
2040 // bus is polled in c45
2041 if (priv->smi_bus_isc45[i])
2042 c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3
2043 // Enable bus access via MDC
2044 if (mdc_on[i])
2045 sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
2046 }
2047
2048 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2049 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2050
2051 /* We have a 10G PHY enable polling
2052 sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
2053 sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
2054 sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
2055 */
2056 sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
2057
2058 return 0;
2059 }
2060
2061 static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
2062 {
2063 pr_info("In %s\n", __func__);
2064
2065 // Initialize Encapsulation memory and wait until finished
2066 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
2067 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
2068 pr_info("%s: init ENCAP done\n", __func__);
2069
2070 // Initialize Managemen Information Base memory and wait until finished
2071 sw_w32(0x1, RTL931X_MEM_MIB_INIT);
2072 do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
2073 pr_info("%s: init MIB done\n", __func__);
2074
2075 // Initialize ACL (PIE) memory and wait until finished
2076 sw_w32(0x1, RTL931X_MEM_ACL_INIT);
2077 do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
2078 pr_info("%s: init ACL done\n", __func__);
2079
2080 // Initialize ALE memory and wait until finished
2081 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
2082 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
2083 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
2084 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
2085 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
2086 pr_info("%s: init ALE done\n", __func__);
2087
2088 // Enable ESD auto recovery
2089 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
2090
2091 // Init SPI, is this for thermal control or what?
2092 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
2093
2094 return 0;
2095 }
2096
2097 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
2098 {
2099 struct device_node *mii_np, *dn;
2100 u32 pn;
2101 int ret;
2102
2103 pr_debug("%s called\n", __func__);
2104 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
2105
2106 if (!mii_np) {
2107 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
2108 return -ENODEV;
2109 }
2110
2111 if (!of_device_is_available(mii_np)) {
2112 ret = -ENODEV;
2113 goto err_put_node;
2114 }
2115
2116 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
2117 if (!priv->mii_bus) {
2118 ret = -ENOMEM;
2119 goto err_put_node;
2120 }
2121
2122 switch(priv->family_id) {
2123 case RTL8380_FAMILY_ID:
2124 priv->mii_bus->name = "rtl838x-eth-mdio";
2125 priv->mii_bus->read = rtl838x_mdio_read;
2126 priv->mii_bus->read_paged = rtl838x_mdio_read_paged;
2127 priv->mii_bus->write = rtl838x_mdio_write;
2128 priv->mii_bus->write_paged = rtl838x_mdio_write_paged;
2129 priv->mii_bus->reset = rtl838x_mdio_reset;
2130 break;
2131 case RTL8390_FAMILY_ID:
2132 priv->mii_bus->name = "rtl839x-eth-mdio";
2133 priv->mii_bus->read = rtl839x_mdio_read;
2134 priv->mii_bus->read_paged = rtl839x_mdio_read_paged;
2135 priv->mii_bus->write = rtl839x_mdio_write;
2136 priv->mii_bus->write_paged = rtl839x_mdio_write_paged;
2137 priv->mii_bus->reset = rtl839x_mdio_reset;
2138 break;
2139 case RTL9300_FAMILY_ID:
2140 priv->mii_bus->name = "rtl930x-eth-mdio";
2141 priv->mii_bus->read = rtl930x_mdio_read;
2142 priv->mii_bus->read_paged = rtl930x_mdio_read_paged;
2143 priv->mii_bus->write = rtl930x_mdio_write;
2144 priv->mii_bus->write_paged = rtl930x_mdio_write_paged;
2145 priv->mii_bus->reset = rtl930x_mdio_reset;
2146 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2147 break;
2148 case RTL9310_FAMILY_ID:
2149 priv->mii_bus->name = "rtl931x-eth-mdio";
2150 priv->mii_bus->read = rtl931x_mdio_read;
2151 priv->mii_bus->read_paged = rtl931x_mdio_read_paged;
2152 priv->mii_bus->write = rtl931x_mdio_write;
2153 priv->mii_bus->write_paged = rtl931x_mdio_write_paged;
2154 priv->mii_bus->reset = rtl931x_mdio_reset;
2155 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2156 break;
2157 }
2158 priv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD;
2159 priv->mii_bus->priv = priv;
2160 priv->mii_bus->parent = &priv->pdev->dev;
2161
2162 for_each_node_by_name(dn, "ethernet-phy") {
2163 u32 smi_addr[2];
2164
2165 if (of_property_read_u32(dn, "reg", &pn))
2166 continue;
2167
2168 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
2169 smi_addr[0] = 0;
2170 smi_addr[1] = pn;
2171 }
2172
2173 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
2174 priv->sds_id[pn] = -1;
2175 else {
2176 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
2177 }
2178
2179 if (pn < MAX_PORTS) {
2180 priv->smi_bus[pn] = smi_addr[0];
2181 priv->smi_addr[pn] = smi_addr[1];
2182 } else {
2183 pr_err("%s: illegal port number %d\n", __func__, pn);
2184 }
2185
2186 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
2187 priv->smi_bus_isc45[smi_addr[0]] = true;
2188
2189 if (of_property_read_bool(dn, "phy-is-integrated")) {
2190 priv->phy_is_internal[pn] = true;
2191 }
2192 }
2193
2194 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
2195 if (!dn) {
2196 dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n");
2197 return -ENODEV;
2198 }
2199
2200 for_each_node_by_name(dn, "port") {
2201 if (of_property_read_u32(dn, "reg", &pn))
2202 continue;
2203 pr_debug("%s Looking at port %d\n", __func__, pn);
2204 if (pn > priv->cpu_port)
2205 continue;
2206 if (of_get_phy_mode(dn, &priv->interfaces[pn]))
2207 priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
2208 pr_debug("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn]));
2209 }
2210
2211 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
2212 ret = of_mdiobus_register(priv->mii_bus, mii_np);
2213
2214 err_put_node:
2215 of_node_put(mii_np);
2216 return ret;
2217 }
2218
2219 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
2220 {
2221 pr_debug("%s called\n", __func__);
2222 if (!priv->mii_bus)
2223 return 0;
2224
2225 mdiobus_unregister(priv->mii_bus);
2226 mdiobus_free(priv->mii_bus);
2227
2228 return 0;
2229 }
2230
2231 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
2232 netdev_features_t features)
2233 {
2234 return features;
2235 }
2236
2237 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
2238 {
2239 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2240
2241 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2242 if (!(features & NETIF_F_RXCSUM))
2243 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2244 else
2245 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2246 }
2247
2248 return 0;
2249 }
2250
2251 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
2252 {
2253 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2254
2255 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2256 if (!(features & NETIF_F_RXCSUM))
2257 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2258 else
2259 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2260 }
2261
2262 return 0;
2263 }
2264
2265 static const struct net_device_ops rtl838x_eth_netdev_ops = {
2266 .ndo_open = rtl838x_eth_open,
2267 .ndo_stop = rtl838x_eth_stop,
2268 .ndo_start_xmit = rtl838x_eth_tx,
2269 .ndo_select_queue = rtl83xx_pick_tx_queue,
2270 .ndo_set_mac_address = rtl838x_set_mac_address,
2271 .ndo_validate_addr = eth_validate_addr,
2272 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
2273 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2274 .ndo_set_features = rtl83xx_set_features,
2275 .ndo_fix_features = rtl838x_fix_features,
2276 .ndo_setup_tc = rtl83xx_setup_tc,
2277 };
2278
2279 static const struct net_device_ops rtl839x_eth_netdev_ops = {
2280 .ndo_open = rtl838x_eth_open,
2281 .ndo_stop = rtl838x_eth_stop,
2282 .ndo_start_xmit = rtl838x_eth_tx,
2283 .ndo_select_queue = rtl83xx_pick_tx_queue,
2284 .ndo_set_mac_address = rtl838x_set_mac_address,
2285 .ndo_validate_addr = eth_validate_addr,
2286 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
2287 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2288 .ndo_set_features = rtl83xx_set_features,
2289 .ndo_fix_features = rtl838x_fix_features,
2290 .ndo_setup_tc = rtl83xx_setup_tc,
2291 };
2292
2293 static const struct net_device_ops rtl930x_eth_netdev_ops = {
2294 .ndo_open = rtl838x_eth_open,
2295 .ndo_stop = rtl838x_eth_stop,
2296 .ndo_start_xmit = rtl838x_eth_tx,
2297 .ndo_select_queue = rtl93xx_pick_tx_queue,
2298 .ndo_set_mac_address = rtl838x_set_mac_address,
2299 .ndo_validate_addr = eth_validate_addr,
2300 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
2301 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2302 .ndo_set_features = rtl93xx_set_features,
2303 .ndo_fix_features = rtl838x_fix_features,
2304 .ndo_setup_tc = rtl83xx_setup_tc,
2305 };
2306
2307 static const struct net_device_ops rtl931x_eth_netdev_ops = {
2308 .ndo_open = rtl838x_eth_open,
2309 .ndo_stop = rtl838x_eth_stop,
2310 .ndo_start_xmit = rtl838x_eth_tx,
2311 .ndo_select_queue = rtl93xx_pick_tx_queue,
2312 .ndo_set_mac_address = rtl838x_set_mac_address,
2313 .ndo_validate_addr = eth_validate_addr,
2314 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
2315 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2316 .ndo_set_features = rtl93xx_set_features,
2317 .ndo_fix_features = rtl838x_fix_features,
2318 };
2319
2320 static const struct phylink_mac_ops rtl838x_phylink_ops = {
2321 .validate = rtl838x_validate,
2322 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
2323 .mac_an_restart = rtl838x_mac_an_restart,
2324 .mac_config = rtl838x_mac_config,
2325 .mac_link_down = rtl838x_mac_link_down,
2326 .mac_link_up = rtl838x_mac_link_up,
2327 };
2328
2329 static const struct ethtool_ops rtl838x_ethtool_ops = {
2330 .get_link_ksettings = rtl838x_get_link_ksettings,
2331 .set_link_ksettings = rtl838x_set_link_ksettings,
2332 };
2333
2334 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2335 {
2336 struct net_device *dev;
2337 struct device_node *dn = pdev->dev.of_node;
2338 struct rtl838x_eth_priv *priv;
2339 struct resource *res, *mem;
2340 phy_interface_t phy_mode;
2341 struct phylink *phylink;
2342 int err = 0, i, rxrings, rxringlen;
2343 struct ring_b *ring;
2344
2345 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2346 (u32)pdev, (u32)(&(pdev->dev)));
2347
2348 if (!dn) {
2349 dev_err(&pdev->dev, "No DT found\n");
2350 return -EINVAL;
2351 }
2352
2353 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2354 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2355 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2356 rxringlen = MAX_ENTRIES / rxrings;
2357 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2358
2359 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2360 if (!dev) {
2361 err = -ENOMEM;
2362 goto err_free;
2363 }
2364 SET_NETDEV_DEV(dev, &pdev->dev);
2365 priv = netdev_priv(dev);
2366
2367 /* obtain buffer memory space */
2368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2369 if (res) {
2370 mem = devm_request_mem_region(&pdev->dev, res->start,
2371 resource_size(res), res->name);
2372 if (!mem) {
2373 dev_err(&pdev->dev, "cannot request memory space\n");
2374 err = -ENXIO;
2375 goto err_free;
2376 }
2377
2378 dev->mem_start = mem->start;
2379 dev->mem_end = mem->end;
2380 } else {
2381 dev_err(&pdev->dev, "cannot request IO resource\n");
2382 err = -ENXIO;
2383 goto err_free;
2384 }
2385
2386 /* Allocate buffer memory */
2387 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2388 + sizeof(struct ring_b) + sizeof(struct notify_b),
2389 (void *)&dev->mem_start, GFP_KERNEL);
2390 if (!priv->membase) {
2391 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2392 err = -ENOMEM;
2393 goto err_free;
2394 }
2395
2396 // Allocate ring-buffer space at the end of the allocated memory
2397 ring = priv->membase;
2398 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2399
2400 spin_lock_init(&priv->lock);
2401
2402 dev->ethtool_ops = &rtl838x_ethtool_ops;
2403 dev->min_mtu = ETH_ZLEN;
2404 dev->max_mtu = 1536;
2405 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2406 dev->hw_features = NETIF_F_RXCSUM;
2407
2408 priv->id = soc_info.id;
2409 priv->family_id = soc_info.family;
2410 if (priv->id) {
2411 pr_info("Found SoC ID: %4x: %s, family %x\n",
2412 priv->id, soc_info.name, priv->family_id);
2413 } else {
2414 pr_err("Unknown chip id (%04x)\n", priv->id);
2415 return -ENODEV;
2416 }
2417
2418 switch (priv->family_id) {
2419 case RTL8380_FAMILY_ID:
2420 priv->cpu_port = RTL838X_CPU_PORT;
2421 priv->r = &rtl838x_reg;
2422 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2423 break;
2424 case RTL8390_FAMILY_ID:
2425 priv->cpu_port = RTL839X_CPU_PORT;
2426 priv->r = &rtl839x_reg;
2427 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2428 break;
2429 case RTL9300_FAMILY_ID:
2430 priv->cpu_port = RTL930X_CPU_PORT;
2431 priv->r = &rtl930x_reg;
2432 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2433 break;
2434 case RTL9310_FAMILY_ID:
2435 priv->cpu_port = RTL931X_CPU_PORT;
2436 priv->r = &rtl931x_reg;
2437 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2438 rtl931x_chip_init(priv);
2439 break;
2440 default:
2441 pr_err("Unknown SoC family\n");
2442 return -ENODEV;
2443 }
2444 priv->rxringlen = rxringlen;
2445 priv->rxrings = rxrings;
2446
2447 /* Obtain device IRQ number */
2448 dev->irq = platform_get_irq(pdev, 0);
2449 if (dev->irq < 0) {
2450 dev_err(&pdev->dev, "cannot obtain network-device IRQ\n");
2451 goto err_free;
2452 }
2453
2454 err = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq,
2455 IRQF_SHARED, dev->name, dev);
2456 if (err) {
2457 dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n",
2458 __func__, err);
2459 goto err_free;
2460 }
2461
2462 rtl8380_init_mac(priv);
2463
2464 /* try to get mac address in the following order:
2465 * 1) from device tree data
2466 * 2) from internal registers set by bootloader
2467 */
2468 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2469 if (is_valid_ether_addr(dev->dev_addr)) {
2470 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2471 } else {
2472 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2473 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2474 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2475 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2476 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2477 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2478 }
2479 /* if the address is invalid, use a random value */
2480 if (!is_valid_ether_addr(dev->dev_addr)) {
2481 struct sockaddr sa = { AF_UNSPEC };
2482
2483 netdev_warn(dev, "Invalid MAC address, using random\n");
2484 eth_hw_addr_random(dev);
2485 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2486 if (rtl838x_set_mac_address(dev, &sa))
2487 netdev_warn(dev, "Failed to set MAC address.\n");
2488 }
2489 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2490 sw_r32(priv->r->mac + 4));
2491 strcpy(dev->name, "eth%d");
2492 priv->pdev = pdev;
2493 priv->netdev = dev;
2494
2495 err = rtl838x_mdio_init(priv);
2496 if (err)
2497 goto err_free;
2498
2499 err = register_netdev(dev);
2500 if (err)
2501 goto err_free;
2502
2503 for (i = 0; i < priv->rxrings; i++) {
2504 priv->rx_qs[i].id = i;
2505 priv->rx_qs[i].priv = priv;
2506 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2507 }
2508
2509 platform_set_drvdata(pdev, dev);
2510
2511 phy_mode = PHY_INTERFACE_MODE_NA;
2512 err = of_get_phy_mode(dn, &phy_mode);
2513 if (err < 0) {
2514 dev_err(&pdev->dev, "incorrect phy-mode\n");
2515 err = -EINVAL;
2516 goto err_free;
2517 }
2518 priv->phylink_config.dev = &dev->dev;
2519 priv->phylink_config.type = PHYLINK_NETDEV;
2520
2521 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2522 phy_mode, &rtl838x_phylink_ops);
2523
2524 if (IS_ERR(phylink)) {
2525 err = PTR_ERR(phylink);
2526 goto err_free;
2527 }
2528 priv->phylink = phylink;
2529
2530 return 0;
2531
2532 err_free:
2533 pr_err("Error setting up netdev, freeing it again.\n");
2534 free_netdev(dev);
2535 return err;
2536 }
2537
2538 static int rtl838x_eth_remove(struct platform_device *pdev)
2539 {
2540 struct net_device *dev = platform_get_drvdata(pdev);
2541 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2542 int i;
2543
2544 if (dev) {
2545 pr_info("Removing platform driver for rtl838x-eth\n");
2546 rtl838x_mdio_remove(priv);
2547 rtl838x_hw_stop(priv);
2548
2549 netif_tx_stop_all_queues(dev);
2550
2551 for (i = 0; i < priv->rxrings; i++)
2552 netif_napi_del(&priv->rx_qs[i].napi);
2553
2554 unregister_netdev(dev);
2555 free_netdev(dev);
2556 }
2557 return 0;
2558 }
2559
2560 static const struct of_device_id rtl838x_eth_of_ids[] = {
2561 { .compatible = "realtek,rtl838x-eth"},
2562 { /* sentinel */ }
2563 };
2564 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2565
2566 static struct platform_driver rtl838x_eth_driver = {
2567 .probe = rtl838x_eth_probe,
2568 .remove = rtl838x_eth_remove,
2569 .driver = {
2570 .name = "rtl838x-eth",
2571 .pm = NULL,
2572 .of_match_table = rtl838x_eth_of_ids,
2573 },
2574 };
2575
2576 module_platform_driver(rtl838x_eth_driver);
2577
2578 MODULE_AUTHOR("B. Koblitz");
2579 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2580 MODULE_LICENSE("GPL");
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