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realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210
[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 uint16_t cpu_tag[10];
62 } __packed __aligned(1);
63
64 struct n_event {
65 uint32_t type:2;
66 uint32_t fidVid:12;
67 uint64_t mac:48;
68 uint32_t slp:6;
69 uint32_t valid:1;
70 uint32_t reserved:27;
71 } __packed __aligned(1);
72
73 struct ring_b {
74 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
75 uint32_t tx_r[TXRINGS][TXRINGLEN];
76 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
77 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
78 uint32_t c_rx[MAX_RXRINGS];
79 uint32_t c_tx[TXRINGS];
80 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
81 uint8_t *rx_space;
82 };
83
84 struct notify_block {
85 struct n_event events[NOTIFY_EVENTS];
86 };
87
88 struct notify_b {
89 struct notify_block blocks[NOTIFY_BLOCKS];
90 u32 reserved1[8];
91 u32 ring[NOTIFY_BLOCKS];
92 u32 reserved2[8];
93 };
94
95 static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
96 {
97 prio &= 0x7;
98
99 if (dest_port > 0) {
100 // cpu_tag[0] is reserved on the RTL83XX SoCs
101 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
102 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
103 h->cpu_tag[3] = 0x0000;
104 h->cpu_tag[4] = BIT(dest_port) >> 16;
105 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
106 // Set internal priority and AS_PRIO
107 if (prio >= 0)
108 h->cpu_tag[2] |= (prio | 0x8) << 12;
109 }
110 }
111
112 static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
113 {
114 prio &= 0x7;
115
116 if (dest_port > 0) {
117 // cpu_tag[0] is reserved on the RTL83XX SoCs
118 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
119 h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
120 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
121 if (dest_port >= 32) {
122 dest_port -= 32;
123 h->cpu_tag[2] = BIT(dest_port) >> 16;
124 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
125 } else {
126 h->cpu_tag[4] = BIT(dest_port) >> 16;
127 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
128 }
129 h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
130 h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
131 // Set internal priority and AS_PRIO
132 if (prio >= 0)
133 h->cpu_tag[1] |= prio | BIT(3);
134 }
135 }
136
137 static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
138 {
139 h->cpu_tag[0] = 0x8000; // CPU tag marker
140 h->cpu_tag[1] = h->cpu_tag[2] = 0;
141 if (prio >= 0)
142 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
143 h->cpu_tag[3] = 0;
144 h->cpu_tag[4] = 0;
145 h->cpu_tag[5] = 0;
146 h->cpu_tag[6] = BIT(dest_port) >> 16;
147 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
148 }
149
150 static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
151 {
152 h->cpu_tag[0] = 0x8000; // CPU tag marker
153 h->cpu_tag[1] = h->cpu_tag[2] = 0;
154 if (prio >= 0)
155 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
156 h->cpu_tag[3] = 0;
157 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
158 if (dest_port >= 32) {
159 dest_port -= 32;
160 h->cpu_tag[4] = BIT(dest_port) >> 16;
161 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
162 } else {
163 h->cpu_tag[6] = BIT(dest_port) >> 16;
164 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
165 }
166 }
167
168 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
169 {
170 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
171 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 h->cpu_tag[3] |= (vlan & 0xff) << 8;
173 }
174
175 struct rtl838x_rx_q {
176 int id;
177 struct rtl838x_eth_priv *priv;
178 struct napi_struct napi;
179 };
180
181 struct rtl838x_eth_priv {
182 struct net_device *netdev;
183 struct platform_device *pdev;
184 void *membase;
185 spinlock_t lock;
186 struct mii_bus *mii_bus;
187 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
188 struct phylink *phylink;
189 struct phylink_config phylink_config;
190 u16 id;
191 u16 family_id;
192 const struct rtl838x_eth_reg *r;
193 u8 cpu_port;
194 u32 lastEvent;
195 u16 rxrings;
196 u16 rxringlen;
197 u8 smi_bus[MAX_PORTS];
198 u8 smi_addr[MAX_PORTS];
199 u32 sds_id[MAX_PORTS];
200 bool smi_bus_isc45[MAX_SMI_BUSSES];
201 bool phy_is_internal[MAX_PORTS];
202 phy_interface_t interfaces[MAX_PORTS];
203 };
204
205 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
206 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
207 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
208 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
209 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
210 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
211 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
212 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
213 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
214 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
215 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
216 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
217
218 /*
219 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
220 * the rings. Writing x into these registers substracts x from its content.
221 * When the content reaches the ring size, the ASIC no longer adds
222 * packets to this receive queue.
223 */
224 void rtl838x_update_cntr(int r, int released)
225 {
226 // This feature is not available on RTL838x SoCs
227 }
228
229 void rtl839x_update_cntr(int r, int released)
230 {
231 // This feature is not available on RTL839x SoCs
232 }
233
234 void rtl930x_update_cntr(int r, int released)
235 {
236 int pos = (r % 3) * 10;
237 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
238 u32 v = sw_r32(reg);
239
240 v = (v >> pos) & 0x3ff;
241 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
242 sw_w32_mask(0x3ff << pos, released << pos, reg);
243 sw_w32(v, reg);
244 }
245
246 void rtl931x_update_cntr(int r, int released)
247 {
248 int pos = (r % 3) * 10;
249 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
250 u32 v = sw_r32(reg);
251
252 v = (v >> pos) & 0x3ff;
253 sw_w32_mask(0x3ff << pos, released << pos, reg);
254 sw_w32(v, reg);
255 }
256
257 struct dsa_tag {
258 u8 reason;
259 u8 queue;
260 u16 port;
261 u8 l2_offloaded;
262 u8 prio;
263 bool crc_error;
264 };
265
266 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
267 {
268 t->reason = h->cpu_tag[3] & 0xf;
269 t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
270 t->port = h->cpu_tag[1] & 0x1f;
271 t->crc_error = t->reason == 13;
272
273 pr_debug("Reason: %d\n", t->reason);
274 if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
275 t->l2_offloaded = 1;
276 else
277 t->l2_offloaded = 0;
278
279 return t->l2_offloaded;
280 }
281
282 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
283 {
284 t->reason = h->cpu_tag[5] & 0x1f;
285 t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
286 t->port = h->cpu_tag[1] & 0x3f;
287 t->crc_error = h->cpu_tag[3] & BIT(2);
288
289 pr_debug("Reason: %d\n", t->reason);
290 if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA
291 (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP
292 t->l2_offloaded = 0;
293 else
294 t->l2_offloaded = 1;
295
296 return t->l2_offloaded;
297 }
298
299 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
300 {
301 t->reason = h->cpu_tag[7] & 0x3f;
302 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
303 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
304 t->crc_error = h->cpu_tag[1] & BIT(6);
305
306 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
307 if (t->reason >= 19 && t->reason <= 27)
308 t->l2_offloaded = 0;
309 else
310 t->l2_offloaded = 1;
311
312 return t->l2_offloaded;
313 }
314
315 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
316 {
317 t->reason = h->cpu_tag[7] & 0x3f;
318 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
319 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
320 t->crc_error = h->cpu_tag[1] & BIT(6);
321
322 if (t->reason != 63)
323 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
324 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
325 t->l2_offloaded = 0;
326 else
327 t->l2_offloaded = 1;
328
329 return t->l2_offloaded;
330 }
331
332 /*
333 * Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
335 */
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
337 {
338 int r;
339 u32 *last;
340 struct p_hdr *h;
341 struct ring_b *ring = priv->membase;
342
343 for (r = 0; r < priv->rxrings; r++) {
344 pr_debug("In %s working on r: %d\n", __func__, r);
345 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
346 do {
347 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
348 break;
349 pr_debug("Got something: %d\n", ring->c_rx[r]);
350 h = &ring->rx_header[r][ring->c_rx[r]];
351 memset(h, 0, sizeof(struct p_hdr));
352 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
353 + r * priv->rxringlen * RING_BUFFER
354 + ring->c_rx[r] * RING_BUFFER);
355 h->size = RING_BUFFER;
356 /* make sure the header is visible to the ASIC */
357 mb();
358
359 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
360 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
361 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
362 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
363 }
364 }
365
366 struct fdb_update_work {
367 struct work_struct work;
368 struct net_device *ndev;
369 u64 macs[NOTIFY_EVENTS + 1];
370 };
371
372 void rtl838x_fdb_sync(struct work_struct *work)
373 {
374 const struct fdb_update_work *uw =
375 container_of(work, struct fdb_update_work, work);
376 struct switchdev_notifier_fdb_info info;
377 u8 addr[ETH_ALEN];
378 int i = 0;
379 int action;
380
381 while (uw->macs[i]) {
382 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
383 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
384 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
385 info.addr = &addr[0];
386 info.vid = 0;
387 info.offloaded = 1;
388 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
389 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
390 i++;
391 }
392 kfree(work);
393 }
394
395 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
396 {
397 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
398 u32 e = priv->lastEvent;
399 struct n_event *event;
400 int i;
401 u64 mac;
402 struct fdb_update_work *w;
403
404 while (!(nb->ring[e] & 1)) {
405 w = kzalloc(sizeof(*w), GFP_ATOMIC);
406 if (!w) {
407 pr_err("Out of memory: %s", __func__);
408 return;
409 }
410 INIT_WORK(&w->work, rtl838x_fdb_sync);
411
412 for (i = 0; i < NOTIFY_EVENTS; i++) {
413 event = &nb->blocks[e].events[i];
414 if (!event->valid)
415 continue;
416 mac = event->mac;
417 if (event->type)
418 mac |= 1ULL << 63;
419 w->ndev = priv->netdev;
420 w->macs[i] = mac;
421 }
422
423 /* Hand the ring entry back to the switch */
424 nb->ring[e] = nb->ring[e] | 1;
425 e = (e + 1) % NOTIFY_BLOCKS;
426
427 w->macs[i] = 0ULL;
428 schedule_work(&w->work);
429 }
430 priv->lastEvent = e;
431 }
432
433 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct rtl838x_eth_priv *priv = netdev_priv(dev);
437 u32 status = sw_r32(priv->r->dma_if_intr_sts);
438 int i;
439
440 pr_debug("IRQ: %08x\n", status);
441
442 /* Ignore TX interrupt */
443 if ((status & 0xf0000)) {
444 /* Clear ISR */
445 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
446 }
447
448 /* RX interrupt */
449 if (status & 0x0ff00) {
450 /* ACK and disable RX interrupt for this ring */
451 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
452 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
453 for (i = 0; i < priv->rxrings; i++) {
454 if (status & BIT(i + 8)) {
455 pr_debug("Scheduling queue: %d\n", i);
456 napi_schedule(&priv->rx_qs[i].napi);
457 }
458 }
459 }
460
461 /* RX buffer overrun */
462 if (status & 0x000ff) {
463 pr_debug("RX buffer overrun: status %x, mask: %x\n",
464 status, sw_r32(priv->r->dma_if_intr_msk));
465 sw_w32(status, priv->r->dma_if_intr_sts);
466 rtl838x_rb_cleanup(priv, status & 0xff);
467 }
468
469 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
470 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
471 rtl839x_l2_notification_handler(priv);
472 }
473
474 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
475 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
476 rtl839x_l2_notification_handler(priv);
477 }
478
479 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
480 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
481 rtl839x_l2_notification_handler(priv);
482 }
483
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
488 {
489 struct net_device *dev = dev_id;
490 struct rtl838x_eth_priv *priv = netdev_priv(dev);
491 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
492 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
493 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
494 int i;
495
496 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
497 __func__, status_tx, status_rx, status_rx_r);
498
499 /* Ignore TX interrupt */
500 if (status_tx) {
501 /* Clear ISR */
502 pr_debug("TX done\n");
503 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
504 }
505
506 /* RX interrupt */
507 if (status_rx) {
508 pr_debug("RX IRQ\n");
509 /* ACK and disable RX interrupt for given rings */
510 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
511 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
512 for (i = 0; i < priv->rxrings; i++) {
513 if (status_rx & BIT(i)) {
514 pr_debug("Scheduling queue: %d\n", i);
515 napi_schedule(&priv->rx_qs[i].napi);
516 }
517 }
518 }
519
520 /* RX buffer overrun */
521 if (status_rx_r) {
522 pr_debug("RX buffer overrun: status %x, mask: %x\n",
523 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
524 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
525 rtl838x_rb_cleanup(priv, status_rx_r);
526 }
527
528 return IRQ_HANDLED;
529 }
530
531 static const struct rtl838x_eth_reg rtl838x_reg = {
532 .net_irq = rtl83xx_net_irq,
533 .mac_port_ctrl = rtl838x_mac_port_ctrl,
534 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
535 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
536 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
537 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
538 .dma_rx_base = RTL838X_DMA_RX_BASE,
539 .dma_tx_base = RTL838X_DMA_TX_BASE,
540 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
541 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
542 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
543 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
544 .get_mac_link_sts = rtl838x_get_mac_link_sts,
545 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
546 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
547 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
548 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
549 .mac = RTL838X_MAC,
550 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
551 .update_cntr = rtl838x_update_cntr,
552 .create_tx_header = rtl838x_create_tx_header,
553 .decode_tag = rtl838x_decode_tag,
554 };
555
556 static const struct rtl838x_eth_reg rtl839x_reg = {
557 .net_irq = rtl83xx_net_irq,
558 .mac_port_ctrl = rtl839x_mac_port_ctrl,
559 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
560 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
561 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
562 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
563 .dma_rx_base = RTL839X_DMA_RX_BASE,
564 .dma_tx_base = RTL839X_DMA_TX_BASE,
565 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
566 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
567 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
568 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
569 .get_mac_link_sts = rtl839x_get_mac_link_sts,
570 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
571 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
572 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
573 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
574 .mac = RTL839X_MAC,
575 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
576 .update_cntr = rtl839x_update_cntr,
577 .create_tx_header = rtl839x_create_tx_header,
578 .decode_tag = rtl839x_decode_tag,
579 };
580
581 static const struct rtl838x_eth_reg rtl930x_reg = {
582 .net_irq = rtl93xx_net_irq,
583 .mac_port_ctrl = rtl930x_mac_port_ctrl,
584 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
585 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
586 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
587 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
588 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
589 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
590 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
591 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
592 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
593 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
594 .dma_rx_base = RTL930X_DMA_RX_BASE,
595 .dma_tx_base = RTL930X_DMA_TX_BASE,
596 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
597 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
598 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
599 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
600 .get_mac_link_sts = rtl930x_get_mac_link_sts,
601 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
602 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
603 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
604 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
605 .mac = RTL930X_MAC_L2_ADDR_CTRL,
606 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
607 .update_cntr = rtl930x_update_cntr,
608 .create_tx_header = rtl930x_create_tx_header,
609 .decode_tag = rtl930x_decode_tag,
610 };
611
612 static const struct rtl838x_eth_reg rtl931x_reg = {
613 .net_irq = rtl93xx_net_irq,
614 .mac_port_ctrl = rtl931x_mac_port_ctrl,
615 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
616 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
617 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
618 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
619 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
620 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
621 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
622 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
623 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
624 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
625 .dma_rx_base = RTL931X_DMA_RX_BASE,
626 .dma_tx_base = RTL931X_DMA_TX_BASE,
627 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
628 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
629 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
630 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
631 .get_mac_link_sts = rtl931x_get_mac_link_sts,
632 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
633 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
634 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
635 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
636 .mac = RTL931X_MAC_L2_ADDR_CTRL,
637 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
638 .update_cntr = rtl931x_update_cntr,
639 .create_tx_header = rtl931x_create_tx_header,
640 .decode_tag = rtl931x_decode_tag,
641 };
642
643 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
644 {
645 u32 int_saved, nbuf;
646 u32 reset_mask;
647 int i, pos;
648
649 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
650 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
651 mdelay(100);
652
653 /* Disable and clear interrupts */
654 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
655 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
656 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
657 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
658 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
659 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
660 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
661 } else {
662 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
663 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
664 }
665
666 if (priv->family_id == RTL8390_FAMILY_ID) {
667 /* Preserve L2 notification and NBUF settings */
668 int_saved = sw_r32(priv->r->dma_if_intr_msk);
669 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
670
671 /* Disable link change interrupt on RTL839x */
672 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
673 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
674
675 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
676 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
677 }
678
679 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
680 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
681 reset_mask = 0x6;
682 else
683 reset_mask = 0xc;
684
685 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
686
687 do { /* Wait for reset of NIC and Queues done */
688 udelay(20);
689 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
690 mdelay(100);
691
692 /* Setup Head of Line */
693 if (priv->family_id == RTL8380_FAMILY_ID)
694 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
695 if (priv->family_id == RTL8390_FAMILY_ID)
696 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
697 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
698 for (i = 0; i < priv->rxrings; i++) {
699 pos = (i % 3) * 10;
700 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
701 sw_w32_mask(0x3ff << pos, priv->rxringlen,
702 priv->r->dma_if_rx_ring_cntr(i));
703 }
704 }
705
706 /* Re-enable link change interrupt */
707 if (priv->family_id == RTL8390_FAMILY_ID) {
708 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
709 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
710 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
711 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
712
713 /* Restore notification settings: on RTL838x these bits are null */
714 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
715 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
716 }
717 }
718
719 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
720 {
721 int i;
722 struct ring_b *ring = priv->membase;
723
724 for (i = 0; i < priv->rxrings; i++)
725 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
726
727 for (i = 0; i < TXRINGS; i++)
728 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
729 }
730
731 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
732 {
733 /* Disable Head of Line features for all RX rings */
734 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
735
736 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
737 sw_w32(0x06400020, priv->r->dma_if_ctrl);
738
739 /* Enable RX done, RX overflow and TX done interrupts */
740 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
741
742 /* Enable DMA, engine expects empty FCS field */
743 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
744
745 /* Restart TX/RX to CPU port */
746 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
747 /* Set Speed, duplex, flow control
748 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
749 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
750 * | MEDIA_SEL
751 */
752 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
753
754 /* Enable CRC checks on CPU-port */
755 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
756 }
757
758 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
759 {
760 /* Setup CPU-Port: RX Buffer */
761 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
762
763 /* Enable Notify, RX done, RX overflow and TX done interrupts */
764 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
765
766 /* Enable DMA */
767 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
768
769 /* Restart TX/RX to CPU port, enable CRC checking */
770 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
771
772 /* CPU port joins Lookup Miss Flooding Portmask */
773 // TODO: The code below should also work for the RTL838x
774 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
775 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
776 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
777
778 /* Force CPU port link up */
779 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
780 }
781
782 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
783 {
784 int i, pos;
785 u32 v;
786
787 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
788 sw_w32(0x06400040, priv->r->dma_if_ctrl);
789
790 for (i = 0; i < priv->rxrings; i++) {
791 pos = (i % 3) * 10;
792 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
793
794 // Some SoCs have issues with missing underflow protection
795 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
796 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
797 }
798
799 /* Enable Notify, RX done, RX overflow and TX done interrupts */
800 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
801 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
802 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
803
804 /* Enable DMA */
805 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
806
807 /* Restart TX/RX to CPU port, enable CRC checking */
808 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
809
810 if (priv->family_id == RTL9300_FAMILY_ID)
811 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
812 else
813 sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
814
815 if (priv->family_id == RTL9300_FAMILY_ID)
816 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
817 else
818 sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
819 }
820
821 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
822 {
823 int i, j;
824
825 struct p_hdr *h;
826
827 for (i = 0; i < priv->rxrings; i++) {
828 for (j = 0; j < priv->rxringlen; j++) {
829 h = &ring->rx_header[i][j];
830 memset(h, 0, sizeof(struct p_hdr));
831 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
832 + i * priv->rxringlen * RING_BUFFER
833 + j * RING_BUFFER);
834 h->size = RING_BUFFER;
835 /* All rings owned by switch, last one wraps */
836 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
837 | (j == (priv->rxringlen - 1) ? WRAP : 0);
838 }
839 ring->c_rx[i] = 0;
840 }
841
842 for (i = 0; i < TXRINGS; i++) {
843 for (j = 0; j < TXRINGLEN; j++) {
844 h = &ring->tx_header[i][j];
845 memset(h, 0, sizeof(struct p_hdr));
846 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
847 + i * TXRINGLEN * RING_BUFFER
848 + j * RING_BUFFER);
849 h->size = RING_BUFFER;
850 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
851 }
852 /* Last header is wrapping around */
853 ring->tx_r[i][j-1] |= WRAP;
854 ring->c_tx[i] = 0;
855 }
856 }
857
858 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
859 {
860 int i;
861 struct notify_b *b = priv->membase + sizeof(struct ring_b);
862
863 for (i = 0; i < NOTIFY_BLOCKS; i++)
864 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
865
866 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
867 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
868
869 /* Setup notification events */
870 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
871 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
872
873 /* Enable Notification */
874 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
875 priv->lastEvent = 0;
876 }
877
878 static int rtl838x_eth_open(struct net_device *ndev)
879 {
880 unsigned long flags;
881 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
882 struct ring_b *ring = priv->membase;
883 int i, err;
884
885 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
886 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
887
888 spin_lock_irqsave(&priv->lock, flags);
889 rtl838x_hw_reset(priv);
890 rtl838x_setup_ring_buffer(priv, ring);
891 if (priv->family_id == RTL8390_FAMILY_ID) {
892 rtl839x_setup_notify_ring_buffer(priv);
893 /* Make sure the ring structure is visible to the ASIC */
894 mb();
895 flush_cache_all();
896 }
897
898 rtl838x_hw_ring_setup(priv);
899 err = request_irq(ndev->irq, priv->r->net_irq, IRQF_SHARED, ndev->name, ndev);
900 if (err) {
901 netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
902 __func__, err);
903 return err;
904 }
905 phylink_start(priv->phylink);
906
907 for (i = 0; i < priv->rxrings; i++)
908 napi_enable(&priv->rx_qs[i].napi);
909
910 switch (priv->family_id) {
911 case RTL8380_FAMILY_ID:
912 rtl838x_hw_en_rxtx(priv);
913 /* Trap IGMP/MLD traffic to CPU-Port */
914 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
915 /* Flush learned FDB entries on link down of a port */
916 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
917 break;
918
919 case RTL8390_FAMILY_ID:
920 rtl839x_hw_en_rxtx(priv);
921 // Trap MLD and IGMP messages to CPU_PORT
922 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
923 /* Flush learned FDB entries on link down of a port */
924 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
925 break;
926
927 case RTL9300_FAMILY_ID:
928 rtl93xx_hw_en_rxtx(priv);
929 /* Flush learned FDB entries on link down of a port */
930 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
931 // Trap MLD and IGMP messages to CPU_PORT
932 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
933 break;
934
935
936 case RTL9310_FAMILY_ID:
937 rtl93xx_hw_en_rxtx(priv);
938
939 // Trap MLD and IGMP messages to CPU_PORT
940 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
941
942 // Disable External CPU access to switch, clear EXT_CPU_EN
943 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
944
945 // Set PCIE_PWR_DOWN
946 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
947 break;
948 }
949
950 netif_tx_start_all_queues(ndev);
951
952 spin_unlock_irqrestore(&priv->lock, flags);
953
954 return 0;
955 }
956
957 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
958 {
959 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
960 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
961 int i;
962
963 // Disable RX/TX from/to CPU-port
964 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
965
966 /* Disable traffic */
967 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
968 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
969 else
970 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
971 mdelay(200); // Test, whether this is needed
972
973 /* Block all ports */
974 if (priv->family_id == RTL8380_FAMILY_ID) {
975 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
976 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
977 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
978 }
979
980 /* Flush L2 address cache */
981 if (priv->family_id == RTL8380_FAMILY_ID) {
982 for (i = 0; i <= priv->cpu_port; i++) {
983 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
984 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
985 }
986 } else if (priv->family_id == RTL8390_FAMILY_ID) {
987 for (i = 0; i <= priv->cpu_port; i++) {
988 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
989 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
990 }
991 }
992 // TODO: L2 flush register is 64 bit on RTL931X and 930X
993
994 /* CPU-Port: Link down */
995 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
996 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
997 else if (priv->family_id == RTL9300_FAMILY_ID)
998 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
999 else if (priv->family_id == RTL9310_FAMILY_ID)
1000 sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
1001 mdelay(100);
1002
1003 /* Disable all TX/RX interrupts */
1004 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
1005 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
1006 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
1007 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
1008 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
1009 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
1010 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
1011 } else {
1012 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
1013 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
1014 }
1015
1016 /* Disable TX/RX DMA */
1017 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1018 mdelay(200);
1019 }
1020
1021 static int rtl838x_eth_stop(struct net_device *ndev)
1022 {
1023 unsigned long flags;
1024 int i;
1025 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1026
1027 pr_info("in %s\n", __func__);
1028
1029 spin_lock_irqsave(&priv->lock, flags);
1030 phylink_stop(priv->phylink);
1031 rtl838x_hw_stop(priv);
1032 free_irq(ndev->irq, ndev);
1033
1034 for (i = 0; i < priv->rxrings; i++)
1035 napi_disable(&priv->rx_qs[i].napi);
1036
1037 netif_tx_stop_all_queues(ndev);
1038
1039 spin_unlock_irqrestore(&priv->lock, flags);
1040
1041 return 0;
1042 }
1043
1044 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1045 {
1046 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1047 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1048 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1049 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1050 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1051 }
1052 if (ndev->flags & IFF_ALLMULTI) {
1053 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1054 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1055 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1056 }
1057 if (ndev->flags & IFF_PROMISC) {
1058 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1059 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1060 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1061 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1062 }
1063 }
1064
1065 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1066 {
1067 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1068
1069 if (priv->family_id == RTL8390_FAMILY_ID)
1070 return rtl839x_eth_set_multicast_list(ndev);
1071
1072 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1073 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1074 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1075 }
1076 if (ndev->flags & IFF_ALLMULTI)
1077 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1078 if (ndev->flags & IFF_PROMISC) {
1079 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1080 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1081 }
1082 }
1083
1084 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1085 {
1086 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1087 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1088 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1089 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1090 }
1091 if (ndev->flags & IFF_ALLMULTI) {
1092 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1093 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1094 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1095 }
1096 if (ndev->flags & IFF_PROMISC) {
1097 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1098 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1099 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1100 }
1101 }
1102
1103 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1104 {
1105 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1106 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1107 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1108 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1109 }
1110 if (ndev->flags & IFF_ALLMULTI) {
1111 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1112 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1113 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1114 }
1115 if (ndev->flags & IFF_PROMISC) {
1116 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1117 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1118 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1119 }
1120 }
1121
1122 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1123 {
1124 unsigned long flags;
1125 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1126
1127 pr_warn("%s\n", __func__);
1128 spin_lock_irqsave(&priv->lock, flags);
1129 rtl838x_hw_stop(priv);
1130 rtl838x_hw_ring_setup(priv);
1131 rtl838x_hw_en_rxtx(priv);
1132 netif_trans_update(ndev);
1133 netif_start_queue(ndev);
1134 spin_unlock_irqrestore(&priv->lock, flags);
1135 }
1136
1137 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1138 {
1139 int len, i;
1140 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1141 struct ring_b *ring = priv->membase;
1142 uint32_t val;
1143 int ret;
1144 unsigned long flags;
1145 struct p_hdr *h;
1146 int dest_port = -1;
1147 int q = skb_get_queue_mapping(skb) % TXRINGS;
1148
1149 if (q) // Check for high prio queue
1150 pr_debug("SKB priority: %d\n", skb->priority);
1151
1152 spin_lock_irqsave(&priv->lock, flags);
1153 len = skb->len;
1154
1155 /* Check for DSA tagging at the end of the buffer */
1156 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
1157 && skb->data[len-3] < priv->cpu_port && skb->data[len-2] == 0x10
1158 && skb->data[len-1] == 0x00) {
1159 /* Reuse tag space for CRC if possible */
1160 dest_port = skb->data[len-3];
1161 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1162 len -= 4;
1163 }
1164
1165 len += 4; // Add space for CRC
1166
1167 if (skb_padto(skb, len)) {
1168 ret = NETDEV_TX_OK;
1169 goto txdone;
1170 }
1171
1172 /* We can send this packet if CPU owns the descriptor */
1173 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1174
1175 /* Set descriptor for tx */
1176 h = &ring->tx_header[q][ring->c_tx[q]];
1177 h->size = len;
1178 h->len = len;
1179 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1180 if (priv->family_id == RTL8380_FAMILY_ID) {
1181 if (len < ETH_ZLEN - 4)
1182 h->len -= 4;
1183 }
1184
1185 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1186
1187 /* Copy packet data to tx buffer */
1188 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1189 /* Make sure packet data is visible to ASIC */
1190 wmb();
1191
1192 /* Hand over to switch */
1193 ring->tx_r[q][ring->c_tx[q]] |= 1;
1194
1195 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1196 if (priv->family_id == RTL8380_FAMILY_ID) {
1197 for (i = 0; i < 10; i++) {
1198 val = sw_r32(priv->r->dma_if_ctrl);
1199 if ((val & 0xc) == 0xc)
1200 break;
1201 }
1202 }
1203
1204 /* Tell switch to send data */
1205 if (priv->family_id == RTL9310_FAMILY_ID
1206 || priv->family_id == RTL9300_FAMILY_ID) {
1207 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1208 if (!q)
1209 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1210 else
1211 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1212 } else {
1213 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1214 }
1215
1216 dev->stats.tx_packets++;
1217 dev->stats.tx_bytes += len;
1218 dev_kfree_skb(skb);
1219 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1220 ret = NETDEV_TX_OK;
1221 } else {
1222 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1223 ret = NETDEV_TX_BUSY;
1224 }
1225 txdone:
1226 spin_unlock_irqrestore(&priv->lock, flags);
1227 return ret;
1228 }
1229
1230 /*
1231 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1232 * so we do round-robin
1233 */
1234 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1235 struct net_device *sb_dev)
1236 {
1237 static u8 last = 0;
1238
1239 last++;
1240 return last % TXRINGS;
1241 }
1242
1243 /*
1244 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1245 */
1246 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1247 struct net_device *sb_dev)
1248 {
1249 if (skb->priority >= TC_PRIO_CONTROL)
1250 return 1;
1251 return 0;
1252 }
1253
1254 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1255 {
1256 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1257 struct ring_b *ring = priv->membase;
1258 struct sk_buff *skb;
1259 unsigned long flags;
1260 int i, len, work_done = 0;
1261 u8 *data, *skb_data;
1262 unsigned int val;
1263 u32 *last;
1264 struct p_hdr *h;
1265 bool dsa = netdev_uses_dsa(dev);
1266 struct dsa_tag tag;
1267
1268 spin_lock_irqsave(&priv->lock, flags);
1269 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1270 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1271
1272 do {
1273 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1274 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1275 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1276 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1277 }
1278 break;
1279 }
1280
1281 h = &ring->rx_header[r][ring->c_rx[r]];
1282 data = (u8 *)KSEG1ADDR(h->buf);
1283 len = h->len;
1284 if (!len)
1285 break;
1286 work_done++;
1287
1288 len -= 4; /* strip the CRC */
1289 /* Add 4 bytes for cpu_tag */
1290 if (dsa)
1291 len += 4;
1292
1293 skb = alloc_skb(len + 4, GFP_KERNEL);
1294 skb_reserve(skb, NET_IP_ALIGN);
1295
1296 if (likely(skb)) {
1297 /* BUG: Prevent bug on RTL838x SoCs*/
1298 if (priv->family_id == RTL8380_FAMILY_ID) {
1299 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1300 for (i = 0; i < priv->rxrings; i++) {
1301 /* Update each ring cnt */
1302 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1303 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1304 }
1305 }
1306
1307 skb_data = skb_put(skb, len);
1308 /* Make sure data is visible */
1309 mb();
1310 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1311 /* Overwrite CRC with cpu_tag */
1312 if (dsa) {
1313 priv->r->decode_tag(h, &tag);
1314 skb->data[len-4] = 0x80;
1315 skb->data[len-3] = tag.port;
1316 skb->data[len-2] = 0x10;
1317 skb->data[len-1] = 0x00;
1318 if (tag.l2_offloaded)
1319 skb->data[len-3] |= 0x40;
1320 }
1321
1322 if (tag.queue >= 0)
1323 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1324 tag.queue, len, tag.reason, tag.port);
1325
1326 skb->protocol = eth_type_trans(skb, dev);
1327 if (dev->features & NETIF_F_RXCSUM) {
1328 if (tag.crc_error)
1329 skb_checksum_none_assert(skb);
1330 else
1331 skb->ip_summed = CHECKSUM_UNNECESSARY;
1332 }
1333 dev->stats.rx_packets++;
1334 dev->stats.rx_bytes += len;
1335
1336 netif_receive_skb(skb);
1337 } else {
1338 if (net_ratelimit())
1339 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1340 dev->stats.rx_dropped++;
1341 }
1342
1343 /* Reset header structure */
1344 memset(h, 0, sizeof(struct p_hdr));
1345 h->buf = data;
1346 h->size = RING_BUFFER;
1347
1348 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1349 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1350 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1351 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1352 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1353
1354 // Update counters
1355 priv->r->update_cntr(r, 0);
1356
1357 spin_unlock_irqrestore(&priv->lock, flags);
1358 return work_done;
1359 }
1360
1361 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1362 {
1363 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1364 struct rtl838x_eth_priv *priv = rx_q->priv;
1365 int work_done = 0;
1366 int r = rx_q->id;
1367 int work;
1368
1369 while (work_done < budget) {
1370 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1371 if (!work)
1372 break;
1373 work_done += work;
1374 }
1375
1376 if (work_done < budget) {
1377 napi_complete_done(napi, work_done);
1378
1379 /* Enable RX interrupt */
1380 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1381 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1382 else
1383 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1384 }
1385 return work_done;
1386 }
1387
1388
1389 static void rtl838x_validate(struct phylink_config *config,
1390 unsigned long *supported,
1391 struct phylink_link_state *state)
1392 {
1393 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1394
1395 pr_debug("In %s\n", __func__);
1396
1397 if (!phy_interface_mode_is_rgmii(state->interface) &&
1398 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1399 state->interface != PHY_INTERFACE_MODE_MII &&
1400 state->interface != PHY_INTERFACE_MODE_REVMII &&
1401 state->interface != PHY_INTERFACE_MODE_GMII &&
1402 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1403 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1404 state->interface != PHY_INTERFACE_MODE_SGMII) {
1405 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1406 pr_err("Unsupported interface: %d\n", state->interface);
1407 return;
1408 }
1409
1410 /* Allow all the expected bits */
1411 phylink_set(mask, Autoneg);
1412 phylink_set_port_modes(mask);
1413 phylink_set(mask, Pause);
1414 phylink_set(mask, Asym_Pause);
1415
1416 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1417 * including Half duplex
1418 */
1419 if (state->interface != PHY_INTERFACE_MODE_MII &&
1420 state->interface != PHY_INTERFACE_MODE_REVMII) {
1421 phylink_set(mask, 1000baseT_Full);
1422 phylink_set(mask, 1000baseT_Half);
1423 }
1424
1425 phylink_set(mask, 10baseT_Half);
1426 phylink_set(mask, 10baseT_Full);
1427 phylink_set(mask, 100baseT_Half);
1428 phylink_set(mask, 100baseT_Full);
1429
1430 bitmap_and(supported, supported, mask,
1431 __ETHTOOL_LINK_MODE_MASK_NBITS);
1432 bitmap_and(state->advertising, state->advertising, mask,
1433 __ETHTOOL_LINK_MODE_MASK_NBITS);
1434 }
1435
1436
1437 static void rtl838x_mac_config(struct phylink_config *config,
1438 unsigned int mode,
1439 const struct phylink_link_state *state)
1440 {
1441 /* This is only being called for the master device,
1442 * i.e. the CPU-Port. We don't need to do anything.
1443 */
1444
1445 pr_info("In %s, mode %x\n", __func__, mode);
1446 }
1447
1448 static void rtl838x_mac_an_restart(struct phylink_config *config)
1449 {
1450 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1451 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1452
1453 /* This works only on RTL838x chips */
1454 if (priv->family_id != RTL8380_FAMILY_ID)
1455 return;
1456
1457 pr_debug("In %s\n", __func__);
1458 /* Restart by disabling and re-enabling link */
1459 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1460 mdelay(20);
1461 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1462 }
1463
1464 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1465 struct phylink_link_state *state)
1466 {
1467 u32 speed;
1468 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1469 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1470 int port = priv->cpu_port;
1471
1472 pr_info("In %s\n", __func__);
1473
1474 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1475 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1476
1477 pr_info("%s link status is %d\n", __func__, state->link);
1478 speed = priv->r->get_mac_link_spd_sts(port);
1479 switch (speed) {
1480 case 0:
1481 state->speed = SPEED_10;
1482 break;
1483 case 1:
1484 state->speed = SPEED_100;
1485 break;
1486 case 2:
1487 state->speed = SPEED_1000;
1488 break;
1489 case 5:
1490 state->speed = SPEED_2500;
1491 break;
1492 case 6:
1493 state->speed = SPEED_5000;
1494 break;
1495 case 4:
1496 state->speed = SPEED_10000;
1497 break;
1498 default:
1499 state->speed = SPEED_UNKNOWN;
1500 break;
1501 }
1502
1503 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1504 if (priv->r->get_mac_rx_pause_sts(port))
1505 state->pause |= MLO_PAUSE_RX;
1506 if (priv->r->get_mac_tx_pause_sts(port))
1507 state->pause |= MLO_PAUSE_TX;
1508 }
1509
1510 static void rtl838x_mac_link_down(struct phylink_config *config,
1511 unsigned int mode,
1512 phy_interface_t interface)
1513 {
1514 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1515 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1516
1517 pr_debug("In %s\n", __func__);
1518 /* Stop TX/RX to port */
1519 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1520 }
1521
1522 static void rtl838x_mac_link_up(struct phylink_config *config,
1523 struct phy_device *phy, unsigned int mode,
1524 phy_interface_t interface, int speed, int duplex,
1525 bool tx_pause, bool rx_pause)
1526 {
1527 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1528 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1529
1530 pr_debug("In %s\n", __func__);
1531 /* Restart TX/RX to port */
1532 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1533 }
1534
1535 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1536 {
1537 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1538 unsigned long flags;
1539
1540 spin_lock_irqsave(&priv->lock, flags);
1541 pr_debug("In %s\n", __func__);
1542 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1543 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1544
1545 if (priv->family_id == RTL8380_FAMILY_ID) {
1546 /* 2 more registers, ALE/MAC block */
1547 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1548 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1549 (RTL838X_MAC_ALE + 4));
1550
1551 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1552 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1553 RTL838X_MAC2 + 4);
1554 }
1555 spin_unlock_irqrestore(&priv->lock, flags);
1556 }
1557
1558 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1559 {
1560 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1561 const struct sockaddr *addr = p;
1562 u8 *mac = (u8 *) (addr->sa_data);
1563
1564 if (!is_valid_ether_addr(addr->sa_data))
1565 return -EADDRNOTAVAIL;
1566
1567 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1568 rtl838x_set_mac_hw(dev, mac);
1569
1570 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1571 return 0;
1572 }
1573
1574 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1575 {
1576 // We will need to set-up EEE and the egress-rate limitation
1577 return 0;
1578 }
1579
1580 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1581 {
1582 int i;
1583
1584 if (priv->family_id == 0x8390)
1585 return rtl8390_init_mac(priv);
1586
1587 // At present we do not know how to set up EEE on any other SoC than RTL8380
1588 if (priv->family_id != 0x8380)
1589 return 0;
1590
1591 pr_info("%s\n", __func__);
1592 /* fix timer for EEE */
1593 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1594 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1595
1596 /* Init VLAN. TODO: Understand what is being done, here */
1597 if (priv->id == 0x8382) {
1598 for (i = 0; i <= 28; i++)
1599 sw_w32(0, 0xd57c + i * 0x80);
1600 }
1601 if (priv->id == 0x8380) {
1602 for (i = 8; i <= 28; i++)
1603 sw_w32(0, 0xd57c + i * 0x80);
1604 }
1605 return 0;
1606 }
1607
1608 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1609 struct ethtool_link_ksettings *cmd)
1610 {
1611 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1612
1613 pr_debug("%s called\n", __func__);
1614 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1615 }
1616
1617 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1618 const struct ethtool_link_ksettings *cmd)
1619 {
1620 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1621
1622 pr_debug("%s called\n", __func__);
1623 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1624 }
1625
1626 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1627 {
1628 u32 val;
1629 int err;
1630 struct rtl838x_eth_priv *priv = bus->priv;
1631
1632 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1633 return rtl838x_read_sds_phy(mii_id, regnum);
1634 err = rtl838x_read_phy(mii_id, 0, regnum, &val);
1635 if (err)
1636 return err;
1637 return val;
1638 }
1639
1640 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1641 {
1642 u32 val;
1643 int err;
1644 struct rtl838x_eth_priv *priv = bus->priv;
1645
1646 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1647 return rtl839x_read_sds_phy(mii_id, regnum);
1648
1649 err = rtl839x_read_phy(mii_id, 0, regnum, &val);
1650 if (err)
1651 return err;
1652 return val;
1653 }
1654
1655 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1656 {
1657 u32 val;
1658 int err;
1659 struct rtl838x_eth_priv *priv = bus->priv;
1660
1661 if (priv->phy_is_internal[mii_id])
1662 return rtl930x_read_sds_phy(priv->sds_id[mii_id], 0, regnum);
1663
1664 if (regnum & MII_ADDR_C45) {
1665 regnum &= ~MII_ADDR_C45;
1666 err = rtl930x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
1667 pr_debug("MMD: %d register %d read %x, err %d\n", mii_id, regnum & 0xffff, val, err);
1668 } else {
1669 err = rtl930x_read_phy(mii_id, 0, regnum, &val);
1670 pr_debug("PHY: %d register %d read %x, err %d\n", mii_id, regnum, val, err);
1671 }
1672 if (err)
1673 return err;
1674 return val;
1675 }
1676
1677
1678 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1679 {
1680 u32 val;
1681 int err, v;
1682 struct rtl838x_eth_priv *priv = bus->priv;
1683
1684 pr_debug("%s: In here, port %d\n", __func__, mii_id);
1685 if (priv->sds_id[mii_id] >= 0 && mii_id >= 52) {
1686 v = rtl931x_read_sds_phy(priv->sds_id[mii_id], 0, regnum);
1687 if (v < 0) {
1688 err = v;
1689 } else {
1690 err = 0;
1691 val = v;
1692 }
1693 } else {
1694 if (regnum & MII_ADDR_C45) {
1695 regnum &= ~MII_ADDR_C45;
1696 err = rtl931x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
1697 } else {
1698 err = rtl931x_read_phy(mii_id, 0, regnum, &val);
1699 }
1700 pr_debug("%s: phy %d, register %d value %x\n", __func__, mii_id, regnum, val);
1701 }
1702
1703 if (err)
1704 return err;
1705 return val;
1706 }
1707
1708 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1709 int regnum, u16 value)
1710 {
1711 u32 offset = 0;
1712 struct rtl838x_eth_priv *priv = bus->priv;
1713
1714 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1715 if (mii_id == 26)
1716 offset = 0x100;
1717 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1718 return 0;
1719 }
1720 return rtl838x_write_phy(mii_id, 0, regnum, value);
1721 }
1722
1723 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1724 int regnum, u16 value)
1725 {
1726 struct rtl838x_eth_priv *priv = bus->priv;
1727
1728 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1729 return rtl839x_write_sds_phy(mii_id, regnum, value);
1730
1731 return rtl839x_write_phy(mii_id, 0, regnum, value);
1732 }
1733
1734 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1735 int regnum, u16 value)
1736 {
1737 struct rtl838x_eth_priv *priv = bus->priv;
1738
1739 if (priv->sds_id[mii_id] >= 0)
1740 return rtl930x_write_sds_phy(priv->sds_id[mii_id], 0, regnum, value);
1741
1742 if (regnum & MII_ADDR_C45) {
1743 regnum &= ~MII_ADDR_C45;
1744 return rtl930x_write_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, value);
1745 }
1746
1747 return rtl930x_write_phy(mii_id, 0, regnum, value);
1748 }
1749
1750 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1751 int regnum, u16 value)
1752 {
1753 struct rtl838x_eth_priv *priv = bus->priv;
1754
1755 if (priv->sds_id[mii_id] >= 0)
1756 return rtl931x_write_sds_phy(priv->sds_id[mii_id], 0, regnum, value);
1757
1758 return rtl931x_write_phy(mii_id, 0, regnum, value);
1759 }
1760
1761 static int rtl838x_mdio_reset(struct mii_bus *bus)
1762 {
1763 pr_debug("%s called\n", __func__);
1764 /* Disable MAC polling the PHY so that we can start configuration */
1765 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1766
1767 /* Enable PHY control via SoC */
1768 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1769
1770 // Probably should reset all PHYs here...
1771 return 0;
1772 }
1773
1774 static int rtl839x_mdio_reset(struct mii_bus *bus)
1775 {
1776 return 0;
1777
1778 pr_debug("%s called\n", __func__);
1779 /* BUG: The following does not work, but should! */
1780 /* Disable MAC polling the PHY so that we can start configuration */
1781 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1782 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1783 /* Disable PHY polling via SoC */
1784 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1785
1786 // Probably should reset all PHYs here...
1787 return 0;
1788 }
1789
1790 u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1791 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1792
1793 static int rtl930x_mdio_reset(struct mii_bus *bus)
1794 {
1795 int i;
1796 int pos;
1797 struct rtl838x_eth_priv *priv = bus->priv;
1798 u32 c45_mask = 0;
1799 u32 poll_sel[2];
1800 u32 poll_ctrl = 0;
1801 u32 private_poll_mask = 0;
1802 u32 v;
1803 bool uses_usxgmii = false; // For the Aquantia PHYs
1804 bool uses_hisgmii = false; // For the RTL8221/8226
1805
1806 // Mapping of port to phy-addresses on an SMI bus
1807 poll_sel[0] = poll_sel[1] = 0;
1808 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1809 if (priv->smi_bus[i] > 3)
1810 continue;
1811 pos = (i % 6) * 5;
1812 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1813 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1814
1815 pos = (i * 2) % 32;
1816 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1817 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1818 }
1819
1820 // Configure which SMI bus is behind which port number
1821 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1822 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1823
1824 // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+)
1825 sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
1826
1827 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1828 for (i = 0; i < 4; i++)
1829 if (priv->smi_bus_isc45[i])
1830 c45_mask |= BIT(i + 16);
1831
1832 pr_info("c45_mask: %08x\n", c45_mask);
1833 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1834
1835 // Set the MAC type of each port according to the PHY-interface
1836 // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0
1837 v = 0;
1838 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1839 switch (priv->interfaces[i]) {
1840 case PHY_INTERFACE_MODE_10GBASER:
1841 break; // Serdes: Value = 0
1842
1843 case PHY_INTERFACE_MODE_HSGMII:
1844 private_poll_mask |= BIT(i);
1845 // fallthrough
1846 case PHY_INTERFACE_MODE_USXGMII:
1847 v |= BIT(mac_type_bit[i]);
1848 uses_usxgmii = true;
1849 break;
1850
1851 case PHY_INTERFACE_MODE_QSGMII:
1852 private_poll_mask |= BIT(i);
1853 v |= 3 << mac_type_bit[i];
1854 break;
1855
1856 default:
1857 break;
1858 }
1859 }
1860 sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);
1861
1862 // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones)
1863 sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);
1864
1865 /* The following magic values are found in the port configuration, they seem to
1866 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1867 * the XGS1250 and the RTL8226 of the XGS1210 */
1868 if (uses_usxgmii) {
1869 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1870 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1871 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1872 }
1873 if (uses_hisgmii) {
1874 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1875 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1876 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1877 }
1878
1879 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__,
1880 sw_r32(RTL930X_SMI_GLB_CTRL));
1881 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__,
1882 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));
1883 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__,
1884 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
1885 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__,
1886 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));
1887 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__,
1888 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));
1889 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__,
1890 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));
1891 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__,
1892 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));
1893 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__,
1894 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));
1895 return 0;
1896 }
1897
1898 static int rtl931x_mdio_reset(struct mii_bus *bus)
1899 {
1900 int i;
1901 int pos;
1902 struct rtl838x_eth_priv *priv = bus->priv;
1903 u32 c45_mask = 0;
1904 u32 poll_sel[4];
1905 u32 poll_ctrl = 0;
1906 bool mdc_on[4];
1907
1908 pr_info("%s called\n", __func__);
1909 // Disable port polling for configuration purposes
1910 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
1911 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
1912 msleep(100);
1913
1914 mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
1915 // Mapping of port to phy-addresses on an SMI bus
1916 poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
1917 for (i = 0; i < 56; i++) {
1918 pos = (i % 6) * 5;
1919 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
1920 pos = (i * 2) % 32;
1921 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1922 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1923 mdc_on[priv->smi_bus[i]] = true;
1924 }
1925
1926 // Configure which SMI bus is behind which port number
1927 for (i = 0; i < 4; i++) {
1928 pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
1929 sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
1930 }
1931
1932 // Configure which SMI busses
1933 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
1934 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
1935 for (i = 0; i < 4; i++) {
1936 // bus is polled in c45
1937 if (priv->smi_bus_isc45[i])
1938 c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3
1939 // Enable bus access via MDC
1940 if (mdc_on[i])
1941 sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
1942 }
1943
1944 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
1945 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
1946
1947 /* We have a 10G PHY enable polling
1948 sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
1949 sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
1950 sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
1951 */
1952 sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
1953
1954 return 0;
1955 }
1956
1957 static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
1958 {
1959 pr_info("In %s\n", __func__);
1960
1961 // Initialize Encapsulation memory and wait until finished
1962 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
1963 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
1964 pr_info("%s: init ENCAP done\n", __func__);
1965
1966 // Initialize Managemen Information Base memory and wait until finished
1967 sw_w32(0x1, RTL931X_MEM_MIB_INIT);
1968 do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
1969 pr_info("%s: init MIB done\n", __func__);
1970
1971 // Initialize ACL (PIE) memory and wait until finished
1972 sw_w32(0x1, RTL931X_MEM_ACL_INIT);
1973 do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
1974 pr_info("%s: init ACL done\n", __func__);
1975
1976 // Initialize ALE memory and wait until finished
1977 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
1978 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
1979 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
1980 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
1981 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
1982 pr_info("%s: init ALE done\n", __func__);
1983
1984 // Enable ESD auto recovery
1985 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
1986
1987 // Init SPI, is this for thermal control or what?
1988 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
1989
1990 return 0;
1991 }
1992
1993 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
1994 {
1995 struct device_node *mii_np, *dn;
1996 u32 pn;
1997 int ret;
1998
1999 pr_debug("%s called\n", __func__);
2000 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
2001
2002 if (!mii_np) {
2003 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
2004 return -ENODEV;
2005 }
2006
2007 if (!of_device_is_available(mii_np)) {
2008 ret = -ENODEV;
2009 goto err_put_node;
2010 }
2011
2012 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
2013 if (!priv->mii_bus) {
2014 ret = -ENOMEM;
2015 goto err_put_node;
2016 }
2017
2018 switch(priv->family_id) {
2019 case RTL8380_FAMILY_ID:
2020 priv->mii_bus->name = "rtl838x-eth-mdio";
2021 priv->mii_bus->read = rtl838x_mdio_read;
2022 priv->mii_bus->write = rtl838x_mdio_write;
2023 priv->mii_bus->reset = rtl838x_mdio_reset;
2024 break;
2025 case RTL8390_FAMILY_ID:
2026 priv->mii_bus->name = "rtl839x-eth-mdio";
2027 priv->mii_bus->read = rtl839x_mdio_read;
2028 priv->mii_bus->write = rtl839x_mdio_write;
2029 priv->mii_bus->reset = rtl839x_mdio_reset;
2030 break;
2031 case RTL9300_FAMILY_ID:
2032 priv->mii_bus->name = "rtl930x-eth-mdio";
2033 priv->mii_bus->read = rtl930x_mdio_read;
2034 priv->mii_bus->write = rtl930x_mdio_write;
2035 priv->mii_bus->reset = rtl930x_mdio_reset;
2036 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
2037 break;
2038 case RTL9310_FAMILY_ID:
2039 priv->mii_bus->name = "rtl931x-eth-mdio";
2040 priv->mii_bus->read = rtl931x_mdio_read;
2041 priv->mii_bus->write = rtl931x_mdio_write;
2042 priv->mii_bus->reset = rtl931x_mdio_reset;
2043 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
2044 break;
2045 }
2046 priv->mii_bus->priv = priv;
2047 priv->mii_bus->parent = &priv->pdev->dev;
2048
2049 for_each_node_by_name(dn, "ethernet-phy") {
2050 u32 smi_addr[2];
2051
2052 if (of_property_read_u32(dn, "reg", &pn))
2053 continue;
2054
2055 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
2056 smi_addr[0] = 0;
2057 smi_addr[1] = pn;
2058 }
2059
2060 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
2061 priv->sds_id[pn] = -1;
2062 else {
2063 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
2064 }
2065
2066 if (pn < MAX_PORTS) {
2067 priv->smi_bus[pn] = smi_addr[0];
2068 priv->smi_addr[pn] = smi_addr[1];
2069 } else {
2070 pr_err("%s: illegal port number %d\n", __func__, pn);
2071 }
2072
2073 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
2074 priv->smi_bus_isc45[smi_addr[0]] = true;
2075
2076 if (of_property_read_bool(dn, "phy-is-integrated")) {
2077 priv->phy_is_internal[pn] = true;
2078 }
2079 }
2080
2081 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
2082 if (!dn) {
2083 dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n");
2084 return -ENODEV;
2085 }
2086
2087 for_each_node_by_name(dn, "port") {
2088 if (of_property_read_u32(dn, "reg", &pn))
2089 continue;
2090 pr_info("%s Looking at port %d\n", __func__, pn);
2091 if (pn > priv->cpu_port)
2092 continue;
2093 if (of_get_phy_mode(dn, &priv->interfaces[pn]))
2094 priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
2095 pr_info("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn]));
2096 }
2097
2098 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
2099 ret = of_mdiobus_register(priv->mii_bus, mii_np);
2100
2101 err_put_node:
2102 of_node_put(mii_np);
2103 return ret;
2104 }
2105
2106 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
2107 {
2108 pr_debug("%s called\n", __func__);
2109 if (!priv->mii_bus)
2110 return 0;
2111
2112 mdiobus_unregister(priv->mii_bus);
2113 mdiobus_free(priv->mii_bus);
2114
2115 return 0;
2116 }
2117
2118 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
2119 netdev_features_t features)
2120 {
2121 return features;
2122 }
2123
2124 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
2125 {
2126 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2127
2128 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2129 if (!(features & NETIF_F_RXCSUM))
2130 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2131 else
2132 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2133 }
2134
2135 return 0;
2136 }
2137
2138 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
2139 {
2140 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2141
2142 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2143 if (!(features & NETIF_F_RXCSUM))
2144 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2145 else
2146 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2147 }
2148
2149 return 0;
2150 }
2151
2152 static const struct net_device_ops rtl838x_eth_netdev_ops = {
2153 .ndo_open = rtl838x_eth_open,
2154 .ndo_stop = rtl838x_eth_stop,
2155 .ndo_start_xmit = rtl838x_eth_tx,
2156 .ndo_select_queue = rtl83xx_pick_tx_queue,
2157 .ndo_set_mac_address = rtl838x_set_mac_address,
2158 .ndo_validate_addr = eth_validate_addr,
2159 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
2160 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2161 .ndo_set_features = rtl83xx_set_features,
2162 .ndo_fix_features = rtl838x_fix_features,
2163 .ndo_setup_tc = rtl83xx_setup_tc,
2164 };
2165
2166 static const struct net_device_ops rtl839x_eth_netdev_ops = {
2167 .ndo_open = rtl838x_eth_open,
2168 .ndo_stop = rtl838x_eth_stop,
2169 .ndo_start_xmit = rtl838x_eth_tx,
2170 .ndo_select_queue = rtl83xx_pick_tx_queue,
2171 .ndo_set_mac_address = rtl838x_set_mac_address,
2172 .ndo_validate_addr = eth_validate_addr,
2173 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
2174 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2175 .ndo_set_features = rtl83xx_set_features,
2176 .ndo_fix_features = rtl838x_fix_features,
2177 .ndo_setup_tc = rtl83xx_setup_tc,
2178 };
2179
2180 static const struct net_device_ops rtl930x_eth_netdev_ops = {
2181 .ndo_open = rtl838x_eth_open,
2182 .ndo_stop = rtl838x_eth_stop,
2183 .ndo_start_xmit = rtl838x_eth_tx,
2184 .ndo_select_queue = rtl93xx_pick_tx_queue,
2185 .ndo_set_mac_address = rtl838x_set_mac_address,
2186 .ndo_validate_addr = eth_validate_addr,
2187 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
2188 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2189 .ndo_set_features = rtl93xx_set_features,
2190 .ndo_fix_features = rtl838x_fix_features,
2191 .ndo_setup_tc = rtl83xx_setup_tc,
2192 };
2193
2194 static const struct net_device_ops rtl931x_eth_netdev_ops = {
2195 .ndo_open = rtl838x_eth_open,
2196 .ndo_stop = rtl838x_eth_stop,
2197 .ndo_start_xmit = rtl838x_eth_tx,
2198 .ndo_select_queue = rtl93xx_pick_tx_queue,
2199 .ndo_set_mac_address = rtl838x_set_mac_address,
2200 .ndo_validate_addr = eth_validate_addr,
2201 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
2202 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2203 .ndo_set_features = rtl93xx_set_features,
2204 .ndo_fix_features = rtl838x_fix_features,
2205 };
2206
2207 static const struct phylink_mac_ops rtl838x_phylink_ops = {
2208 .validate = rtl838x_validate,
2209 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
2210 .mac_an_restart = rtl838x_mac_an_restart,
2211 .mac_config = rtl838x_mac_config,
2212 .mac_link_down = rtl838x_mac_link_down,
2213 .mac_link_up = rtl838x_mac_link_up,
2214 };
2215
2216 static const struct ethtool_ops rtl838x_ethtool_ops = {
2217 .get_link_ksettings = rtl838x_get_link_ksettings,
2218 .set_link_ksettings = rtl838x_set_link_ksettings,
2219 };
2220
2221 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2222 {
2223 struct net_device *dev;
2224 struct device_node *dn = pdev->dev.of_node;
2225 struct rtl838x_eth_priv *priv;
2226 struct resource *res, *mem;
2227 phy_interface_t phy_mode;
2228 struct phylink *phylink;
2229 int err = 0, i, rxrings, rxringlen;
2230 struct ring_b *ring;
2231
2232 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2233 (u32)pdev, (u32)(&(pdev->dev)));
2234
2235 if (!dn) {
2236 dev_err(&pdev->dev, "No DT found\n");
2237 return -EINVAL;
2238 }
2239
2240 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2241 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2242 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2243 rxringlen = MAX_ENTRIES / rxrings;
2244 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2245
2246 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2247 if (!dev) {
2248 err = -ENOMEM;
2249 goto err_free;
2250 }
2251 SET_NETDEV_DEV(dev, &pdev->dev);
2252 priv = netdev_priv(dev);
2253
2254 /* obtain buffer memory space */
2255 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2256 if (res) {
2257 mem = devm_request_mem_region(&pdev->dev, res->start,
2258 resource_size(res), res->name);
2259 if (!mem) {
2260 dev_err(&pdev->dev, "cannot request memory space\n");
2261 err = -ENXIO;
2262 goto err_free;
2263 }
2264
2265 dev->mem_start = mem->start;
2266 dev->mem_end = mem->end;
2267 } else {
2268 dev_err(&pdev->dev, "cannot request IO resource\n");
2269 err = -ENXIO;
2270 goto err_free;
2271 }
2272
2273 /* Allocate buffer memory */
2274 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2275 + sizeof(struct ring_b) + sizeof(struct notify_b),
2276 (void *)&dev->mem_start, GFP_KERNEL);
2277 if (!priv->membase) {
2278 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2279 err = -ENOMEM;
2280 goto err_free;
2281 }
2282
2283 // Allocate ring-buffer space at the end of the allocated memory
2284 ring = priv->membase;
2285 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2286
2287 spin_lock_init(&priv->lock);
2288
2289 /* Obtain device IRQ number */
2290 dev->irq = platform_get_irq(pdev, 0);
2291 if (dev->irq < 0) {
2292 dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n");
2293 dev->irq = 24;
2294 }
2295
2296 dev->ethtool_ops = &rtl838x_ethtool_ops;
2297 dev->min_mtu = ETH_ZLEN;
2298 dev->max_mtu = 1536;
2299 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2300 dev->hw_features = NETIF_F_RXCSUM;
2301
2302 priv->id = soc_info.id;
2303 priv->family_id = soc_info.family;
2304 if (priv->id) {
2305 pr_info("Found SoC ID: %4x: %s, family %x\n",
2306 priv->id, soc_info.name, priv->family_id);
2307 } else {
2308 pr_err("Unknown chip id (%04x)\n", priv->id);
2309 return -ENODEV;
2310 }
2311
2312 switch (priv->family_id) {
2313 case RTL8380_FAMILY_ID:
2314 priv->cpu_port = RTL838X_CPU_PORT;
2315 priv->r = &rtl838x_reg;
2316 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2317 break;
2318 case RTL8390_FAMILY_ID:
2319 priv->cpu_port = RTL839X_CPU_PORT;
2320 priv->r = &rtl839x_reg;
2321 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2322 break;
2323 case RTL9300_FAMILY_ID:
2324 priv->cpu_port = RTL930X_CPU_PORT;
2325 priv->r = &rtl930x_reg;
2326 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2327 break;
2328 case RTL9310_FAMILY_ID:
2329 priv->cpu_port = RTL931X_CPU_PORT;
2330 priv->r = &rtl931x_reg;
2331 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2332 rtl931x_chip_init(priv);
2333 break;
2334 default:
2335 pr_err("Unknown SoC family\n");
2336 return -ENODEV;
2337 }
2338 priv->rxringlen = rxringlen;
2339 priv->rxrings = rxrings;
2340
2341 rtl8380_init_mac(priv);
2342
2343 /* try to get mac address in the following order:
2344 * 1) from device tree data
2345 * 2) from internal registers set by bootloader
2346 */
2347 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2348 if (is_valid_ether_addr(dev->dev_addr)) {
2349 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2350 } else {
2351 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2352 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2353 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2354 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2355 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2356 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2357 }
2358 /* if the address is invalid, use a random value */
2359 if (!is_valid_ether_addr(dev->dev_addr)) {
2360 struct sockaddr sa = { AF_UNSPEC };
2361
2362 netdev_warn(dev, "Invalid MAC address, using random\n");
2363 eth_hw_addr_random(dev);
2364 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2365 if (rtl838x_set_mac_address(dev, &sa))
2366 netdev_warn(dev, "Failed to set MAC address.\n");
2367 }
2368 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2369 sw_r32(priv->r->mac + 4));
2370 strcpy(dev->name, "eth%d");
2371 priv->pdev = pdev;
2372 priv->netdev = dev;
2373
2374 err = rtl838x_mdio_init(priv);
2375 if (err)
2376 goto err_free;
2377
2378 err = register_netdev(dev);
2379 if (err)
2380 goto err_free;
2381
2382 for (i = 0; i < priv->rxrings; i++) {
2383 priv->rx_qs[i].id = i;
2384 priv->rx_qs[i].priv = priv;
2385 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2386 }
2387
2388 platform_set_drvdata(pdev, dev);
2389
2390 phy_mode = PHY_INTERFACE_MODE_NA;
2391 err = of_get_phy_mode(dn, &phy_mode);
2392 if (err < 0) {
2393 dev_err(&pdev->dev, "incorrect phy-mode\n");
2394 err = -EINVAL;
2395 goto err_free;
2396 }
2397 priv->phylink_config.dev = &dev->dev;
2398 priv->phylink_config.type = PHYLINK_NETDEV;
2399
2400 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2401 phy_mode, &rtl838x_phylink_ops);
2402
2403 if (IS_ERR(phylink)) {
2404 err = PTR_ERR(phylink);
2405 goto err_free;
2406 }
2407 priv->phylink = phylink;
2408
2409 return 0;
2410
2411 err_free:
2412 pr_err("Error setting up netdev, freeing it again.\n");
2413 free_netdev(dev);
2414 return err;
2415 }
2416
2417 static int rtl838x_eth_remove(struct platform_device *pdev)
2418 {
2419 struct net_device *dev = platform_get_drvdata(pdev);
2420 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2421 int i;
2422
2423 if (dev) {
2424 pr_info("Removing platform driver for rtl838x-eth\n");
2425 rtl838x_mdio_remove(priv);
2426 rtl838x_hw_stop(priv);
2427
2428 netif_tx_stop_all_queues(dev);
2429
2430 for (i = 0; i < priv->rxrings; i++)
2431 netif_napi_del(&priv->rx_qs[i].napi);
2432
2433 unregister_netdev(dev);
2434 free_netdev(dev);
2435 }
2436 return 0;
2437 }
2438
2439 static const struct of_device_id rtl838x_eth_of_ids[] = {
2440 { .compatible = "realtek,rtl838x-eth"},
2441 { /* sentinel */ }
2442 };
2443 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2444
2445 static struct platform_driver rtl838x_eth_driver = {
2446 .probe = rtl838x_eth_probe,
2447 .remove = rtl838x_eth_remove,
2448 .driver = {
2449 .name = "rtl838x-eth",
2450 .pm = NULL,
2451 .of_match_table = rtl838x_eth_of_ids,
2452 },
2453 };
2454
2455 module_platform_driver(rtl838x_eth_driver);
2456
2457 MODULE_AUTHOR("B. Koblitz");
2458 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2459 MODULE_LICENSE("GPL");
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