1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
4 * Copyright (C) 2020 B. Koblitz
7 #include <linux/module.h>
8 #include <linux/delay.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13 #include <linux/sfp.h>
15 #include <asm/mach-rtl838x/mach-rtl83xx.h>
16 #include "rtl83xx-phy.h"
18 extern struct rtl83xx_soc_info soc_info
;
19 extern struct mutex smi_lock
;
21 #define PHY_CTRL_REG 0
22 #define PHY_POWER_BIT 11
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
39 * Using the special page 0xfff with the MDIO controller found in
40 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
41 * the cache and paging engine of the MDIO controller.
43 #define RTL83XX_PAGE_RAW 0x0fff
45 /* internal RTL821X PHY uses register 0x1d to select media page */
46 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
47 /* external RTL821X PHY uses register 0x1e to select media page */
48 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
50 #define RTL821X_MEDIA_PAGE_AUTO 0
51 #define RTL821X_MEDIA_PAGE_COPPER 1
52 #define RTL821X_MEDIA_PAGE_FIBRE 3
53 #define RTL821X_MEDIA_PAGE_INTERNAL 8
55 #define RTL9300_PHY_ID_MASK 0xf0ffffff
58 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
59 * bus to detect e.g. link and media changes. For operations on the PHYs such as
60 * patching or other configuration changes such as EEE, polling needs to be disabled
61 * since otherwise these operations may fails or lead to unpredictable results.
63 DEFINE_MUTEX(poll_lock
);
65 static const struct firmware rtl838x_8380_fw
;
66 static const struct firmware rtl838x_8214fc_fw
;
67 static const struct firmware rtl838x_8218b_fw
;
69 static u64
disable_polling(int port
)
73 mutex_lock(&poll_lock
);
75 switch (soc_info
.family
) {
76 case RTL8380_FAMILY_ID
:
77 saved_state
= sw_r32(RTL838X_SMI_POLL_CTRL
);
78 sw_w32_mask(BIT(port
), 0, RTL838X_SMI_POLL_CTRL
);
80 case RTL8390_FAMILY_ID
:
81 saved_state
= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
83 saved_state
|= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL
);
84 sw_w32_mask(BIT(port
% 32), 0,
85 RTL839X_SMI_PORT_POLLING_CTRL
+ ((port
>> 5) << 2));
87 case RTL9300_FAMILY_ID
:
88 saved_state
= sw_r32(RTL930X_SMI_POLL_CTRL
);
89 sw_w32_mask(BIT(port
), 0, RTL930X_SMI_POLL_CTRL
);
91 case RTL9310_FAMILY_ID
:
92 pr_warn("%s not implemented for RTL931X\n", __func__
);
96 mutex_unlock(&poll_lock
);
101 static int resume_polling(u64 saved_state
)
103 mutex_lock(&poll_lock
);
105 switch (soc_info
.family
) {
106 case RTL8380_FAMILY_ID
:
107 sw_w32(saved_state
, RTL838X_SMI_POLL_CTRL
);
109 case RTL8390_FAMILY_ID
:
110 sw_w32(saved_state
>> 32, RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
111 sw_w32(saved_state
, RTL839X_SMI_PORT_POLLING_CTRL
);
113 case RTL9300_FAMILY_ID
:
114 sw_w32(saved_state
, RTL930X_SMI_POLL_CTRL
);
116 case RTL9310_FAMILY_ID
:
117 pr_warn("%s not implemented for RTL931X\n", __func__
);
121 mutex_unlock(&poll_lock
);
126 static void rtl8380_int_phy_on_off(struct phy_device
*phydev
, bool on
)
128 phy_modify(phydev
, 0, BIT(11), on
?0:BIT(11));
131 static void rtl8380_rtl8214fc_on_off(struct phy_device
*phydev
, bool on
)
134 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_FIBRE
);
135 phy_modify(phydev
, 0x10, BIT(11), on
?0:BIT(11));
138 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
139 phy_modify_paged(phydev
, RTL821X_PAGE_POWER
, 0x10, BIT(11), on
?0:BIT(11));
142 static void rtl8380_phy_reset(struct phy_device
*phydev
)
144 phy_modify(phydev
, 0, BIT(15), BIT(15));
147 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
148 u16 rtl9300_sds_regs
[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
149 0x02A4, 0x02A4, 0x0198, 0x0198 };
150 u8 rtl9300_sds_lsb
[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
153 * Reset the SerDes by powering it off and set a new operations mode
154 * of the SerDes. 0x1f is off. Other modes are
155 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
156 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
157 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
158 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
159 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
161 void rtl9300_sds_rst(int sds_num
, u32 mode
)
163 pr_info("%s %d\n", __func__
, mode
);
164 if (sds_num
< 0 || sds_num
> 11) {
165 pr_err("Wrong SerDes number: %d\n", sds_num
);
169 sw_w32_mask(0x1f << rtl9300_sds_lsb
[sds_num
], 0x1f << rtl9300_sds_lsb
[sds_num
],
170 rtl9300_sds_regs
[sds_num
]);
173 sw_w32_mask(0x1f << rtl9300_sds_lsb
[sds_num
], mode
<< rtl9300_sds_lsb
[sds_num
],
174 rtl9300_sds_regs
[sds_num
]);
177 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__
,
178 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
181 void rtl9300_sds_set(int sds_num
, u32 mode
)
183 pr_info("%s %d\n", __func__
, mode
);
184 if (sds_num
< 0 || sds_num
> 11) {
185 pr_err("Wrong SerDes number: %d\n", sds_num
);
189 sw_w32_mask(0x1f << rtl9300_sds_lsb
[sds_num
], mode
<< rtl9300_sds_lsb
[sds_num
],
190 rtl9300_sds_regs
[sds_num
]);
193 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__
,
194 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
197 u32
rtl9300_sds_mode_get(int sds_num
)
201 if (sds_num
< 0 || sds_num
> 11) {
202 pr_err("Wrong SerDes number: %d\n", sds_num
);
206 v
= sw_r32(rtl9300_sds_regs
[sds_num
]);
207 v
>>= rtl9300_sds_lsb
[sds_num
];
213 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
214 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
216 int rtl839x_read_sds_phy(int phy_addr
, int phy_reg
)
226 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
227 * which would otherwise read as 0.
229 if (soc_info
.id
== 0x8393) {
237 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
238 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
239 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
240 * one 32 bit register.
242 reg
= (phy_reg
<< 1) & 0xfc;
243 val
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
246 val
= (val
>> 16) & 0xffff;
253 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
254 * register which simulates commands to an internal MDIO bus.
256 int rtl930x_read_sds_phy(int phy_addr
, int page
, int phy_reg
)
259 u32 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 1;
261 sw_w32(cmd
, RTL930X_SDS_INDACS_CMD
);
263 for (i
= 0; i
< 100; i
++) {
264 if (!(sw_r32(RTL930X_SDS_INDACS_CMD
) & 0x1))
272 return sw_r32(RTL930X_SDS_INDACS_DATA
) & 0xffff;
275 int rtl930x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
)
280 sw_w32(v
, RTL930X_SDS_INDACS_DATA
);
281 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 0x3;
283 for (i
= 0; i
< 100; i
++) {
284 if (!(sw_r32(RTL930X_SDS_INDACS_CMD
) & 0x1))
291 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__
);
298 int rtl931x_read_sds_phy(int phy_addr
, int page
, int phy_reg
)
301 u32 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 1;
303 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__
, phy_addr
, phy_reg
);
304 sw_w32(cmd
, RTL931X_SERDES_INDRT_ACCESS_CTRL
);
306 for (i
= 0; i
< 100; i
++) {
307 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL
) & 0x1))
315 pr_debug("%s: returning %04x\n", __func__
, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL
) & 0xffff);
316 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL
) & 0xffff;
319 int rtl931x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
)
324 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13;
325 sw_w32(cmd
, RTL931X_SERDES_INDRT_ACCESS_CTRL
);
327 sw_w32(v
, RTL931X_SERDES_INDRT_DATA_CTRL
);
329 cmd
= sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL
) | 0x3;
330 sw_w32(cmd
, RTL931X_SERDES_INDRT_ACCESS_CTRL
);
332 for (i
= 0; i
< 100; i
++) {
333 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL
) & 0x1))
345 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
346 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
347 * in a standard page 0 of a PHY
349 int rtl838x_read_sds_phy(int phy_addr
, int phy_reg
)
356 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
361 int rtl839x_write_sds_phy(int phy_addr
, int phy_reg
, u16 v
)
370 reg
= (phy_reg
<< 1) & 0xfc;
374 sw_w32_mask(0xffff0000, val
,
375 RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
377 sw_w32_mask(0xffff, val
,
378 RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
384 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
385 * ports of the RTL838x SoCs
387 static int rtl8380_read_status(struct phy_device
*phydev
)
391 err
= genphy_read_status(phydev
);
394 phydev
->speed
= SPEED_1000
;
395 phydev
->duplex
= DUPLEX_FULL
;
401 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
402 * ports of the RTL8393 SoC
404 static int rtl8393_read_status(struct phy_device
*phydev
)
408 int phy_addr
= phydev
->mdio
.addr
;
411 err
= genphy_read_status(phydev
);
416 phydev
->speed
= SPEED_100
;
417 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
420 v
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80);
421 if (!(v
& (1 << 13)) && (v
& (1 << 6)))
422 phydev
->speed
= SPEED_1000
;
423 phydev
->duplex
= DUPLEX_FULL
;
429 static int rtl8226_read_page(struct phy_device
*phydev
)
431 return __phy_read(phydev
, RTL8XXX_PAGE_SELECT
);
434 static int rtl8226_write_page(struct phy_device
*phydev
, int page
)
436 return __phy_write(phydev
, RTL8XXX_PAGE_SELECT
, page
);
439 static int rtl8226_read_status(struct phy_device
*phydev
)
444 // TODO: ret = genphy_read_status(phydev);
446 // pr_info("%s: genphy_read_status failed\n", __func__);
450 // Link status must be read twice
451 for (i
= 0; i
< 2; i
++) {
452 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA402);
454 phydev
->link
= val
& BIT(2) ? 1 : 0;
458 // Read duplex status
459 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA434);
462 phydev
->duplex
= !!(val
& BIT(3));
465 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA434);
466 switch (val
& 0x0630) {
468 phydev
->speed
= SPEED_10
;
471 phydev
->speed
= SPEED_100
;
474 phydev
->speed
= SPEED_1000
;
477 phydev
->speed
= SPEED_10000
;
480 phydev
->speed
= SPEED_2500
;
483 phydev
->speed
= SPEED_5000
;
492 static int rtl8226_advertise_aneg(struct phy_device
*phydev
)
497 pr_info("In %s\n", __func__
);
499 v
= phy_read_mmd(phydev
, MMD_AN
, 16);
503 v
|= BIT(5); // HD 10M
504 v
|= BIT(6); // FD 10M
505 v
|= BIT(7); // HD 100M
506 v
|= BIT(8); // FD 100M
508 ret
= phy_write_mmd(phydev
, MMD_AN
, 16, v
);
511 v
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA412);
514 v
|= BIT(9); // FD 1000M
516 ret
= phy_write_mmd(phydev
, MMD_VEND2
, 0xA412, v
);
521 v
= phy_read_mmd(phydev
, MMD_AN
, 32);
526 ret
= phy_write_mmd(phydev
, MMD_AN
, 32, v
);
532 static int rtl8226_config_aneg(struct phy_device
*phydev
)
537 pr_debug("In %s\n", __func__
);
538 if (phydev
->autoneg
== AUTONEG_ENABLE
) {
539 ret
= rtl8226_advertise_aneg(phydev
);
542 // AutoNegotiationEnable
543 v
= phy_read_mmd(phydev
, MMD_AN
, 0);
547 v
|= BIT(12); // Enable AN
548 ret
= phy_write_mmd(phydev
, MMD_AN
, 0, v
);
552 // RestartAutoNegotiation
553 v
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA400);
558 ret
= phy_write_mmd(phydev
, MMD_VEND2
, 0xA400, v
);
561 // TODO: ret = __genphy_config_aneg(phydev, ret);
567 static int rtl8226_get_eee(struct phy_device
*phydev
,
568 struct ethtool_eee
*e
)
571 int addr
= phydev
->mdio
.addr
;
573 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
575 val
= phy_read_mmd(phydev
, MMD_AN
, 60);
576 if (e
->eee_enabled
) {
577 e
->eee_enabled
= !!(val
& BIT(1));
578 if (!e
->eee_enabled
) {
579 val
= phy_read_mmd(phydev
, MMD_AN
, 62);
580 e
->eee_enabled
= !!(val
& BIT(0));
583 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
588 static int rtl8226_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
590 int port
= phydev
->mdio
.addr
;
595 pr_info("In %s, port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
597 poll_state
= disable_polling(port
);
599 // Remember aneg state
600 val
= phy_read_mmd(phydev
, MMD_AN
, 0);
601 an_enabled
= !!(val
& BIT(12));
603 // Setup 100/1000MBit
604 val
= phy_read_mmd(phydev
, MMD_AN
, 60);
609 phy_write_mmd(phydev
, MMD_AN
, 60, val
);
612 val
= phy_read_mmd(phydev
, MMD_AN
, 62);
617 phy_write_mmd(phydev
, MMD_AN
, 62, val
);
619 // RestartAutoNegotiation
620 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA400);
622 phy_write_mmd(phydev
, MMD_VEND2
, 0xA400, val
);
624 resume_polling(poll_state
);
629 static struct fw_header
*rtl838x_request_fw(struct phy_device
*phydev
,
630 const struct firmware
*fw
,
633 struct device
*dev
= &phydev
->mdio
.dev
;
636 uint32_t checksum
, my_checksum
;
638 err
= request_firmware(&fw
, name
, dev
);
642 if (fw
->size
< sizeof(struct fw_header
)) {
643 pr_err("Firmware size too small.\n");
648 h
= (struct fw_header
*) fw
->data
;
649 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw
->size
, h
->magic
);
651 if (h
->magic
!= 0x83808380) {
652 pr_err("Wrong firmware file: MAGIC mismatch.\n");
656 checksum
= h
->checksum
;
658 my_checksum
= ~crc32(0xFFFFFFFFU
, fw
->data
, fw
->size
);
659 if (checksum
!= my_checksum
) {
660 pr_err("Firmware checksum mismatch.\n");
664 h
->checksum
= checksum
;
668 dev_err(dev
, "Unable to load firmware %s (%d)\n", name
, err
);
672 static void rtl821x_phy_setup_package_broadcast(struct phy_device
*phydev
, bool enable
)
674 int mac
= phydev
->mdio
.addr
;
676 /* select main page 0 */
677 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
678 /* write to 0x8 to register 0x1d on main page 0 */
679 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
680 /* select page 0x266 */
681 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PORT
);
682 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
683 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 0x16, (enable
?0xff00:0x00) | mac
);
684 /* return to main page 0 */
685 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
686 /* write to 0x0 to register 0x1d on main page 0 */
687 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
691 static int rtl8390_configure_generic(struct phy_device
*phydev
)
693 int mac
= phydev
->mdio
.addr
;
696 val
= phy_read(phydev
, 2);
698 val
= phy_read(phydev
, 3);
700 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
702 /* Read internal PHY ID */
703 phy_write_paged(phydev
, 31, 27, 0x0002);
704 val
= phy_read_paged(phydev
, 31, 28);
706 /* Internal RTL8218B, version 2 */
707 phydev_info(phydev
, "Detected unknown %x\n", val
);
711 static int rtl8380_configure_int_rtl8218b(struct phy_device
*phydev
)
715 int mac
= phydev
->mdio
.addr
;
717 u32
*rtl838x_6275B_intPhy_perport
;
718 u32
*rtl8218b_6276B_hwEsd_perport
;
720 val
= phy_read(phydev
, 2);
722 val
= phy_read(phydev
, 3);
724 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
726 /* Read internal PHY ID */
727 phy_write_paged(phydev
, 31, 27, 0x0002);
728 val
= phy_read_paged(phydev
, 31, 28);
730 phydev_err(phydev
, "Expected internal RTL8218B, found PHY-ID %x\n", val
);
734 /* Internal RTL8218B, version 2 */
735 phydev_info(phydev
, "Detected internal RTL8218B\n");
737 h
= rtl838x_request_fw(phydev
, &rtl838x_8380_fw
, FIRMWARE_838X_8380_1
);
741 if (h
->phy
!= 0x83800000) {
742 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
746 rtl838x_6275B_intPhy_perport
= (void *)h
+ sizeof(struct fw_header
)
749 rtl8218b_6276B_hwEsd_perport
= (void *)h
+ sizeof(struct fw_header
)
752 if (sw_r32(RTL838X_DMY_REG31
) == 0x1)
755 val
= phy_read(phydev
, 0);
757 rtl8380_int_phy_on_off(phydev
, true);
759 rtl8380_phy_reset(phydev
);
762 /* Ready PHY for patch */
763 for (p
= 0; p
< 8; p
++) {
764 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PATCH
);
765 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
, 0x10, 0x0010);
768 for (p
= 0; p
< 8; p
++) {
769 for (i
= 0; i
< 100 ; i
++) {
770 val
= phy_package_port_read_paged(phydev
, p
, RTL821X_PAGE_STATE
, 0x10);
776 "ERROR: Port %d not ready for patch.\n",
781 for (p
= 0; p
< 8; p
++) {
783 while (rtl838x_6275B_intPhy_perport
[i
* 2]) {
784 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
,
785 rtl838x_6275B_intPhy_perport
[i
* 2],
786 rtl838x_6275B_intPhy_perport
[i
* 2 + 1]);
790 while (rtl8218b_6276B_hwEsd_perport
[i
* 2]) {
791 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
,
792 rtl8218b_6276B_hwEsd_perport
[i
* 2],
793 rtl8218b_6276B_hwEsd_perport
[i
* 2 + 1]);
800 static int rtl8380_configure_ext_rtl8218b(struct phy_device
*phydev
)
802 u32 val
, ipd
, phy_id
;
804 int mac
= phydev
->mdio
.addr
;
806 u32
*rtl8380_rtl8218b_perchip
;
807 u32
*rtl8218B_6276B_rtl8380_perport
;
808 u32
*rtl8380_rtl8218b_perport
;
810 if (soc_info
.family
== RTL8380_FAMILY_ID
&& mac
!= 0 && mac
!= 16) {
811 phydev_err(phydev
, "External RTL8218B must have PHY-IDs 0 or 16!\n");
814 val
= phy_read(phydev
, 2);
816 val
= phy_read(phydev
, 3);
818 pr_info("Phy on MAC %d: %x\n", mac
, phy_id
);
820 /* Read internal PHY ID */
821 phy_write_paged(phydev
, 31, 27, 0x0002);
822 val
= phy_read_paged(phydev
, 31, 28);
824 phydev_err(phydev
, "Expected external RTL8218B, found PHY-ID %x\n", val
);
827 phydev_info(phydev
, "Detected external RTL8218B\n");
829 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8218b_1
);
833 if (h
->phy
!= 0x8218b000) {
834 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
838 rtl8380_rtl8218b_perchip
= (void *)h
+ sizeof(struct fw_header
)
841 rtl8218B_6276B_rtl8380_perport
= (void *)h
+ sizeof(struct fw_header
)
844 rtl8380_rtl8218b_perport
= (void *)h
+ sizeof(struct fw_header
)
847 val
= phy_read(phydev
, 0);
849 rtl8380_int_phy_on_off(phydev
, true);
851 rtl8380_phy_reset(phydev
);
855 /* Get Chip revision */
856 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
857 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 0x1b, 0x4);
858 val
= phy_read_paged(phydev
, RTL83XX_PAGE_RAW
, 0x1c);
860 phydev_info(phydev
, "Detected chip revision %04x\n", val
);
863 while (rtl8380_rtl8218b_perchip
[i
* 3]
864 && rtl8380_rtl8218b_perchip
[i
* 3 + 1]) {
865 phy_package_port_write_paged(phydev
, rtl8380_rtl8218b_perchip
[i
* 3],
866 RTL83XX_PAGE_RAW
, rtl8380_rtl8218b_perchip
[i
* 3 + 1],
867 rtl8380_rtl8218b_perchip
[i
* 3 + 2]);
872 for (i
= 0; i
< 8; i
++) {
873 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
874 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x00, 0x1140);
879 for (i
= 0; i
< 8; i
++) {
880 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PATCH
);
881 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x10, 0x0010);
886 /* Verify patch readiness */
887 for (i
= 0; i
< 8; i
++) {
888 for (l
= 0; l
< 100; l
++) {
889 val
= phy_package_port_read_paged(phydev
, i
, RTL821X_PAGE_STATE
, 0x10);
894 phydev_err(phydev
, "Could not patch PHY\n");
899 /* Use Broadcast ID method for patching */
900 rtl821x_phy_setup_package_broadcast(phydev
, true);
902 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 30, 8);
903 phy_write_paged(phydev
, 0x26e, 17, 0xb);
904 phy_write_paged(phydev
, 0x26e, 16, 0x2);
906 ipd
= phy_read_paged(phydev
, 0x26e, 19);
907 phy_write_paged(phydev
, 0, 30, 0);
908 ipd
= (ipd
>> 4) & 0xf; /* unused ? */
911 while (rtl8218B_6276B_rtl8380_perport
[i
* 2]) {
912 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, rtl8218B_6276B_rtl8380_perport
[i
* 2],
913 rtl8218B_6276B_rtl8380_perport
[i
* 2 + 1]);
917 /*Disable broadcast ID*/
918 rtl821x_phy_setup_package_broadcast(phydev
, false);
923 static int rtl8218b_ext_match_phy_device(struct phy_device
*phydev
)
925 int addr
= phydev
->mdio
.addr
;
927 /* Both the RTL8214FC and the external RTL8218B have the same
928 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
929 * at PHY IDs 0-7, while the RTL8214FC must be attached via
930 * the pair of SGMII/1000Base-X with higher PHY-IDs
932 if (soc_info
.family
== RTL8380_FAMILY_ID
)
933 return phydev
->phy_id
== PHY_ID_RTL8218B_E
&& addr
< 8;
935 return phydev
->phy_id
== PHY_ID_RTL8218B_E
;
938 static bool rtl8214fc_media_is_fibre(struct phy_device
*phydev
)
940 int mac
= phydev
->mdio
.addr
;
942 static int reg
[] = {16, 19, 20, 21};
945 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
946 val
= phy_package_read_paged(phydev
, RTL821X_PAGE_PORT
, reg
[mac
% 4]);
947 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
955 static void rtl8214fc_power_set(struct phy_device
*phydev
, int port
, bool on
)
957 char *state
= on
? "on" : "off";
959 if (port
== PORT_FIBRE
) {
960 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__
, state
, phydev
->mdio
.addr
);
961 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_FIBRE
);
963 pr_info("%s: Powering %s COPPER (port %d)\n", __func__
, state
, phydev
->mdio
.addr
);
964 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
968 phy_modify_paged(phydev
, RTL821X_PAGE_POWER
, 0x10, BIT(11), 0);
970 phy_modify_paged(phydev
, RTL821X_PAGE_POWER
, 0x10, 0, BIT(11));
973 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
976 static int rtl8214fc_suspend(struct phy_device
*phydev
)
978 rtl8214fc_power_set(phydev
, PORT_MII
, false);
979 rtl8214fc_power_set(phydev
, PORT_FIBRE
, false);
984 static int rtl8214fc_resume(struct phy_device
*phydev
)
986 if (rtl8214fc_media_is_fibre(phydev
)) {
987 rtl8214fc_power_set(phydev
, PORT_MII
, false);
988 rtl8214fc_power_set(phydev
, PORT_FIBRE
, true);
990 rtl8214fc_power_set(phydev
, PORT_FIBRE
, false);
991 rtl8214fc_power_set(phydev
, PORT_MII
, true);
997 static void rtl8214fc_media_set(struct phy_device
*phydev
, bool set_fibre
)
999 int mac
= phydev
->mdio
.addr
;
1001 static int reg
[] = {16, 19, 20, 21};
1004 pr_info("%s: port %d, set_fibre: %d\n", __func__
, mac
, set_fibre
);
1005 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
1006 val
= phy_package_read_paged(phydev
, RTL821X_PAGE_PORT
, reg
[mac
% 4]);
1015 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
1016 phy_package_write_paged(phydev
, RTL821X_PAGE_PORT
, reg
[mac
% 4], val
);
1017 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1019 if (!phydev
->suspended
) {
1021 rtl8214fc_power_set(phydev
, PORT_MII
, false);
1022 rtl8214fc_power_set(phydev
, PORT_FIBRE
, true);
1024 rtl8214fc_power_set(phydev
, PORT_FIBRE
, false);
1025 rtl8214fc_power_set(phydev
, PORT_MII
, true);
1030 static int rtl8214fc_set_port(struct phy_device
*phydev
, int port
)
1032 bool is_fibre
= (port
== PORT_FIBRE
? true : false);
1033 int addr
= phydev
->mdio
.addr
;
1035 pr_debug("%s port %d to %d\n", __func__
, addr
, port
);
1037 rtl8214fc_media_set(phydev
, is_fibre
);
1041 static int rtl8214fc_get_port(struct phy_device
*phydev
)
1043 int addr
= phydev
->mdio
.addr
;
1045 pr_debug("%s: port %d\n", __func__
, addr
);
1046 if (rtl8214fc_media_is_fibre(phydev
))
1052 * Enable EEE on the RTL8218B PHYs
1053 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1054 * but the only way that works since the kernel first enables EEE in the MAC
1055 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1057 void rtl8218d_eee_set(struct phy_device
*phydev
, bool enable
)
1062 pr_debug("In %s %d, enable %d\n", __func__
, phydev
->mdio
.addr
, enable
);
1063 /* Set GPHY page to copper */
1064 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1066 val
= phy_read(phydev
, 0);
1067 an_enabled
= val
& BIT(12);
1069 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1070 val
= phy_read_mmd(phydev
, 7, 60);
1071 val
|= BIT(2) | BIT(1);
1072 phy_write_mmd(phydev
, 7, 60, enable
? 0x6 : 0);
1074 /* 500M EEE ability */
1075 val
= phy_read_paged(phydev
, RTL821X_PAGE_GPHY
, 20);
1080 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, 20, val
);
1082 /* Restart AN if enabled */
1084 val
= phy_read(phydev
, 0);
1086 phy_write(phydev
, 0, val
);
1089 /* GPHY page back to auto*/
1090 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1093 static int rtl8218b_get_eee(struct phy_device
*phydev
,
1094 struct ethtool_eee
*e
)
1097 int addr
= phydev
->mdio
.addr
;
1099 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
1101 /* Set GPHY page to copper */
1102 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1104 val
= phy_read_paged(phydev
, 7, 60);
1105 if (e
->eee_enabled
) {
1106 // Verify vs MAC-based EEE
1107 e
->eee_enabled
= !!(val
& BIT(7));
1108 if (!e
->eee_enabled
) {
1109 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1110 e
->eee_enabled
= !!(val
& BIT(4));
1113 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
1115 /* GPHY page to auto */
1116 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1121 static int rtl8218d_get_eee(struct phy_device
*phydev
,
1122 struct ethtool_eee
*e
)
1125 int addr
= phydev
->mdio
.addr
;
1127 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
1129 /* Set GPHY page to copper */
1130 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1132 val
= phy_read_paged(phydev
, 7, 60);
1134 e
->eee_enabled
= !!(val
& BIT(7));
1135 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
1137 /* GPHY page to auto */
1138 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1143 static int rtl8214fc_set_eee(struct phy_device
*phydev
,
1144 struct ethtool_eee
*e
)
1147 int port
= phydev
->mdio
.addr
;
1151 pr_debug("In %s port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
1153 if (rtl8214fc_media_is_fibre(phydev
)) {
1154 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", port
);
1158 poll_state
= disable_polling(port
);
1160 /* Set GPHY page to copper */
1161 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1163 // Get auto-negotiation status
1164 val
= phy_read(phydev
, 0);
1165 an_enabled
= val
& BIT(12);
1167 pr_info("%s: aneg: %d\n", __func__
, an_enabled
);
1168 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1169 val
&= ~BIT(5); // Use MAC-based EEE
1170 phy_write_paged(phydev
, RTL821X_PAGE_MAC
, 25, val
);
1172 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1173 phy_write_paged(phydev
, 7, 60, e
->eee_enabled
? 0x6 : 0);
1175 /* 500M EEE ability */
1176 val
= phy_read_paged(phydev
, RTL821X_PAGE_GPHY
, 20);
1182 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, 20, val
);
1184 /* Restart AN if enabled */
1186 pr_info("%s: doing aneg\n", __func__
);
1187 val
= phy_read(phydev
, 0);
1189 phy_write(phydev
, 0, val
);
1192 /* GPHY page back to auto*/
1193 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1195 resume_polling(poll_state
);
1200 static int rtl8214fc_get_eee(struct phy_device
*phydev
,
1201 struct ethtool_eee
*e
)
1203 int addr
= phydev
->mdio
.addr
;
1205 pr_debug("In %s port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
1206 if (rtl8214fc_media_is_fibre(phydev
)) {
1207 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", addr
);
1211 return rtl8218b_get_eee(phydev
, e
);
1214 static int rtl8218b_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
1216 int port
= phydev
->mdio
.addr
;
1221 pr_info("In %s, port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
1223 poll_state
= disable_polling(port
);
1225 /* Set GPHY page to copper */
1226 phy_write(phydev
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1227 val
= phy_read(phydev
, 0);
1228 an_enabled
= val
& BIT(12);
1230 if (e
->eee_enabled
) {
1231 /* 100/1000M EEE Capability */
1232 phy_write(phydev
, 13, 0x0007);
1233 phy_write(phydev
, 14, 0x003C);
1234 phy_write(phydev
, 13, 0x4007);
1235 phy_write(phydev
, 14, 0x0006);
1237 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1239 phy_write_paged(phydev
, RTL821X_PAGE_MAC
, 25, val
);
1241 /* 100/1000M EEE Capability */
1242 phy_write(phydev
, 13, 0x0007);
1243 phy_write(phydev
, 14, 0x003C);
1244 phy_write(phydev
, 13, 0x0007);
1245 phy_write(phydev
, 14, 0x0000);
1247 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1249 phy_write_paged(phydev
, RTL821X_PAGE_MAC
, 25, val
);
1252 /* Restart AN if enabled */
1254 val
= phy_read(phydev
, 0);
1256 phy_write(phydev
, 0, val
);
1259 /* GPHY page back to auto*/
1260 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1262 pr_info("%s done\n", __func__
);
1263 resume_polling(poll_state
);
1268 static int rtl8218d_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
1270 int addr
= phydev
->mdio
.addr
;
1273 pr_info("In %s, port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
1275 poll_state
= disable_polling(addr
);
1277 rtl8218d_eee_set(phydev
, (bool) e
->eee_enabled
);
1279 resume_polling(poll_state
);
1284 static int rtl8214c_match_phy_device(struct phy_device
*phydev
)
1286 return phydev
->phy_id
== PHY_ID_RTL8214C
;
1289 static int rtl8380_configure_rtl8214c(struct phy_device
*phydev
)
1292 int mac
= phydev
->mdio
.addr
;
1294 val
= phy_read(phydev
, 2);
1296 val
= phy_read(phydev
, 3);
1298 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
1300 phydev_info(phydev
, "Detected external RTL8214C\n");
1302 /* GPHY auto conf */
1303 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1307 static int rtl8380_configure_rtl8214fc(struct phy_device
*phydev
)
1309 u32 phy_id
, val
, page
= 0;
1311 int mac
= phydev
->mdio
.addr
;
1312 struct fw_header
*h
;
1313 u32
*rtl8380_rtl8214fc_perchip
;
1314 u32
*rtl8380_rtl8214fc_perport
;
1316 val
= phy_read(phydev
, 2);
1318 val
= phy_read(phydev
, 3);
1320 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
1322 /* Read internal PHY id */
1323 phy_write_paged(phydev
, 0, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1324 phy_write_paged(phydev
, 0x1f, 0x1b, 0x0002);
1325 val
= phy_read_paged(phydev
, 0x1f, 0x1c);
1326 if (val
!= 0x6276) {
1327 phydev_err(phydev
, "Expected external RTL8214FC, found PHY-ID %x\n", val
);
1330 phydev_info(phydev
, "Detected external RTL8214FC\n");
1332 h
= rtl838x_request_fw(phydev
, &rtl838x_8214fc_fw
, FIRMWARE_838X_8214FC_1
);
1336 if (h
->phy
!= 0x8214fc00) {
1337 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
1341 rtl8380_rtl8214fc_perchip
= (void *)h
+ sizeof(struct fw_header
)
1342 + h
->parts
[0].start
;
1344 rtl8380_rtl8214fc_perport
= (void *)h
+ sizeof(struct fw_header
)
1345 + h
->parts
[1].start
;
1347 /* detect phy version */
1348 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 27, 0x0004);
1349 val
= phy_read_paged(phydev
, RTL83XX_PAGE_RAW
, 28);
1351 val
= phy_read(phydev
, 16);
1352 if (val
& (1 << 11))
1353 rtl8380_rtl8214fc_on_off(phydev
, true);
1355 rtl8380_phy_reset(phydev
);
1358 phy_write_paged(phydev
, 0, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1361 while (rtl8380_rtl8214fc_perchip
[i
* 3]
1362 && rtl8380_rtl8214fc_perchip
[i
* 3 + 1]) {
1363 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x1f)
1364 page
= rtl8380_rtl8214fc_perchip
[i
* 3 + 2];
1365 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x13 && page
== 0x260) {
1366 val
= phy_read_paged(phydev
, 0x260, 13);
1367 val
= (val
& 0x1f00) | (rtl8380_rtl8214fc_perchip
[i
* 3 + 2]
1369 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
,
1370 rtl8380_rtl8214fc_perchip
[i
* 3 + 1], val
);
1372 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
,
1373 rtl8380_rtl8214fc_perchip
[i
* 3 + 1],
1374 rtl8380_rtl8214fc_perchip
[i
* 3 + 2]);
1379 /* Force copper medium */
1380 for (i
= 0; i
< 4; i
++) {
1381 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
1382 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1386 for (i
= 0; i
< 4; i
++) {
1387 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
1388 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x00, 0x1140);
1392 /* Disable Autosensing */
1393 for (i
= 0; i
< 4; i
++) {
1394 for (l
= 0; l
< 100; l
++) {
1395 val
= phy_package_port_read_paged(phydev
, i
, RTL821X_PAGE_GPHY
, 0x10);
1396 if ((val
& 0x7) >= 3)
1400 phydev_err(phydev
, "Could not disable autosensing\n");
1406 for (i
= 0; i
< 4; i
++) {
1407 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PATCH
);
1408 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x10, 0x0010);
1412 /* Verify patch readiness */
1413 for (i
= 0; i
< 4; i
++) {
1414 for (l
= 0; l
< 100; l
++) {
1415 val
= phy_package_port_read_paged(phydev
, i
, RTL821X_PAGE_STATE
, 0x10);
1420 phydev_err(phydev
, "Could not patch PHY\n");
1424 /* Use Broadcast ID method for patching */
1425 rtl821x_phy_setup_package_broadcast(phydev
, true);
1428 while (rtl8380_rtl8214fc_perport
[i
* 2]) {
1429 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, rtl8380_rtl8214fc_perport
[i
* 2],
1430 rtl8380_rtl8214fc_perport
[i
* 2 + 1]);
1434 /*Disable broadcast ID*/
1435 rtl821x_phy_setup_package_broadcast(phydev
, false);
1437 /* Auto medium selection */
1438 for (i
= 0; i
< 4; i
++) {
1439 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
1440 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1446 static int rtl8214fc_match_phy_device(struct phy_device
*phydev
)
1448 int addr
= phydev
->mdio
.addr
;
1450 return phydev
->phy_id
== PHY_ID_RTL8214FC
&& addr
>= 24;
1453 static int rtl8380_configure_serdes(struct phy_device
*phydev
)
1458 struct fw_header
*h
;
1459 u32
*rtl8380_sds_take_reset
;
1460 u32
*rtl8380_sds_common
;
1461 u32
*rtl8380_sds01_qsgmii_6275b
;
1462 u32
*rtl8380_sds23_qsgmii_6275b
;
1463 u32
*rtl8380_sds4_fiber_6275b
;
1464 u32
*rtl8380_sds5_fiber_6275b
;
1465 u32
*rtl8380_sds_reset
;
1466 u32
*rtl8380_sds_release_reset
;
1468 phydev_info(phydev
, "Detected internal RTL8380 SERDES\n");
1470 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8380_1
);
1474 if (h
->magic
!= 0x83808380) {
1475 phydev_err(phydev
, "Wrong firmware file: magic number mismatch.\n");
1479 rtl8380_sds_take_reset
= (void *)h
+ sizeof(struct fw_header
)
1480 + h
->parts
[0].start
;
1482 rtl8380_sds_common
= (void *)h
+ sizeof(struct fw_header
)
1483 + h
->parts
[1].start
;
1485 rtl8380_sds01_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
)
1486 + h
->parts
[2].start
;
1488 rtl8380_sds23_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
)
1489 + h
->parts
[3].start
;
1491 rtl8380_sds4_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
)
1492 + h
->parts
[4].start
;
1494 rtl8380_sds5_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
)
1495 + h
->parts
[5].start
;
1497 rtl8380_sds_reset
= (void *)h
+ sizeof(struct fw_header
)
1498 + h
->parts
[6].start
;
1500 rtl8380_sds_release_reset
= (void *)h
+ sizeof(struct fw_header
)
1501 + h
->parts
[7].start
;
1503 /* Back up serdes power off value */
1504 sds_conf_value
= sw_r32(RTL838X_SDS_CFG_REG
);
1505 pr_info("SDS power down value: %x\n", sds_conf_value
);
1507 /* take serdes into reset */
1509 while (rtl8380_sds_take_reset
[2 * i
]) {
1510 sw_w32(rtl8380_sds_take_reset
[2 * i
+ 1], rtl8380_sds_take_reset
[2 * i
]);
1515 /* apply common serdes patch */
1517 while (rtl8380_sds_common
[2 * i
]) {
1518 sw_w32(rtl8380_sds_common
[2 * i
+ 1], rtl8380_sds_common
[2 * i
]);
1523 /* internal R/W enable */
1524 sw_w32(3, RTL838X_INT_RW_CTRL
);
1526 /* SerDes ports 4 and 5 are FIBRE ports */
1527 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL
);
1529 /* SerDes module settings, SerDes 0-3 are QSGMII */
1530 v
= 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1531 /* SerDes 4 and 5 are 1000BX FIBRE */
1532 v
|= 0x4 << 5 | 0x4;
1533 sw_w32(v
, RTL838X_SDS_MODE_SEL
);
1535 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL
));
1536 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL
);
1538 while (rtl8380_sds01_qsgmii_6275b
[2 * i
]) {
1539 sw_w32(rtl8380_sds01_qsgmii_6275b
[2 * i
+ 1],
1540 rtl8380_sds01_qsgmii_6275b
[2 * i
]);
1545 while (rtl8380_sds23_qsgmii_6275b
[2 * i
]) {
1546 sw_w32(rtl8380_sds23_qsgmii_6275b
[2 * i
+ 1], rtl8380_sds23_qsgmii_6275b
[2 * i
]);
1551 while (rtl8380_sds4_fiber_6275b
[2 * i
]) {
1552 sw_w32(rtl8380_sds4_fiber_6275b
[2 * i
+ 1], rtl8380_sds4_fiber_6275b
[2 * i
]);
1557 while (rtl8380_sds5_fiber_6275b
[2 * i
]) {
1558 sw_w32(rtl8380_sds5_fiber_6275b
[2 * i
+ 1], rtl8380_sds5_fiber_6275b
[2 * i
]);
1563 while (rtl8380_sds_reset
[2 * i
]) {
1564 sw_w32(rtl8380_sds_reset
[2 * i
+ 1], rtl8380_sds_reset
[2 * i
]);
1569 while (rtl8380_sds_release_reset
[2 * i
]) {
1570 sw_w32(rtl8380_sds_release_reset
[2 * i
+ 1], rtl8380_sds_release_reset
[2 * i
]);
1574 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG
));
1575 sw_w32(sds_conf_value
, RTL838X_SDS_CFG_REG
);
1577 pr_info("Configuration of SERDES done\n");
1581 static int rtl8390_configure_serdes(struct phy_device
*phydev
)
1583 phydev_info(phydev
, "Detected internal RTL8390 SERDES\n");
1585 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1586 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0
+ 0x0a);
1588 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1589 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1590 * and FRE16_EEE_QUIET_FIB1G
1592 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0
+ 0xe0);
1597 void rtl9300_sds_field_w(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
, u32 v
)
1599 int l
= end_bit
- start_bit
+ 1;
1603 u32 mask
= BIT(l
) - 1;
1605 data
= rtl930x_read_sds_phy(sds
, page
, reg
);
1606 data
&= ~(mask
<< start_bit
);
1607 data
|= (v
& mask
) << start_bit
;
1610 rtl930x_write_sds_phy(sds
, page
, reg
, data
);
1613 u32
rtl9300_sds_field_r(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
)
1615 int l
= end_bit
- start_bit
+ 1;
1616 u32 v
= rtl930x_read_sds_phy(sds
, page
, reg
);
1621 return (v
>> start_bit
) & (BIT(l
) - 1);
1624 /* Read the link and speed status of the internal SerDes of the RTL9300
1626 static int rtl9300_read_status(struct phy_device
*phydev
)
1628 struct device
*dev
= &phydev
->mdio
.dev
;
1629 int phy_addr
= phydev
->mdio
.addr
;
1630 struct device_node
*dn
;
1631 u32 sds_num
= 0, status
, latch_status
, mode
;
1636 if (of_property_read_u32(dn
, "sds", &sds_num
))
1638 pr_info("%s: Port %d, SerDes is %d\n", __func__
, phy_addr
, sds_num
);
1640 dev_err(dev
, "No DT node.\n");
1647 mode
= rtl9300_sds_mode_get(sds_num
);
1648 pr_info("%s got SDS mode %02x\n", __func__
, mode
);
1649 if (mode
== 0x1a) { // 10GR mode
1650 status
= rtl9300_sds_field_r(sds_num
, 0x5, 0, 12, 12);
1651 latch_status
= rtl9300_sds_field_r(sds_num
, 0x4, 1, 2, 2);
1652 status
|= rtl9300_sds_field_r(sds_num
, 0x5, 0, 12, 12);
1653 latch_status
|= rtl9300_sds_field_r(sds_num
, 0x4, 1, 2, 2);
1655 status
= rtl9300_sds_field_r(sds_num
, 0x1, 29, 8, 0);
1656 latch_status
= rtl9300_sds_field_r(sds_num
, 0x1, 30, 8, 0);
1657 status
|= rtl9300_sds_field_r(sds_num
, 0x1, 29, 8, 0);
1658 latch_status
|= rtl9300_sds_field_r(sds_num
, 0x1, 30, 8, 0);
1661 pr_info("%s link status: status: %d, latch %d\n", __func__
, status
, latch_status
);
1664 phydev
->link
= true;
1666 phydev
->speed
= SPEED_10000
;
1668 phydev
->speed
= SPEED_1000
;
1670 phydev
->duplex
= DUPLEX_FULL
;
1676 void rtl930x_sds_rx_rst(int sds_num
, phy_interface_t phy_if
)
1678 int page
= 0x2e; // 10GR and USXGMII
1680 if (phy_if
== PHY_INTERFACE_MODE_1000BASEX
)
1683 rtl9300_sds_field_w(sds_num
, page
, 0x15, 4, 4, 0x1);
1685 rtl9300_sds_field_w(sds_num
, page
, 0x15, 4, 4, 0x0);
1689 * Force PHY modes on 10GBit Serdes
1691 void rtl9300_force_sds_mode(int sds
, phy_interface_t phy_if
)
1696 int lane_0
= (sds
% 2) ? sds
- 1 : sds
;
1697 u32 v
, cr_0
, cr_1
, cr_2
;
1700 pr_info("%s: SDS: %d, mode %d\n", __func__
, sds
, phy_if
);
1702 case PHY_INTERFACE_MODE_SGMII
:
1708 case PHY_INTERFACE_MODE_HSGMII
:
1714 case PHY_INTERFACE_MODE_1000BASEX
:
1719 case PHY_INTERFACE_MODE_2500BASEX
:
1725 case PHY_INTERFACE_MODE_10GBASER
:
1731 case PHY_INTERFACE_MODE_NA
:
1732 // This will disable SerDes
1737 pr_err("%s: unknown serdes mode: %s\n",
1738 __func__
, phy_modes(phy_if
));
1742 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__
, sds
, sds_mode
);
1743 // Power down SerDes
1744 rtl9300_sds_field_w(sds
, 0x20, 0, 7, 6, 0x3);
1745 if (sds
== 5) pr_info("%s after %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x20, 0));
1747 if (sds
== 5) pr_info("%s a %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x1f, 9));
1748 // Force mode enable
1749 rtl9300_sds_field_w(sds
, 0x1f, 9, 6, 6, 0x1);
1750 if (sds
== 5) pr_info("%s b %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x1f, 9));
1753 rtl9300_sds_field_w(sds
, 0x1f, 9, 11, 7, 0x1f);
1755 if (phy_if
== PHY_INTERFACE_MODE_NA
)
1758 if (sds
== 5) pr_info("%s c %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x20, 18));
1759 // Enable LC and ring
1760 rtl9300_sds_field_w(lane_0
, 0x20, 18, 3, 0, 0xf);
1763 rtl9300_sds_field_w(lane_0
, 0x20, 18, 5, 4, 0x1);
1765 rtl9300_sds_field_w(lane_0
, 0x20, 18, 7, 6, 0x1);
1767 rtl9300_sds_field_w(sds
, 0x20, 0, 5, 4, 0x3);
1770 rtl9300_sds_field_w(lane_0
, 0x20, 18, 11, 8, lc_value
);
1772 rtl9300_sds_field_w(lane_0
, 0x20, 18, 15, 12, lc_value
);
1774 // Force analog LC & ring on
1775 rtl9300_sds_field_w(lane_0
, 0x21, 11, 3, 0, 0xf);
1777 v
= lc_on
? 0x3 : 0x1;
1780 rtl9300_sds_field_w(lane_0
, 0x20, 18, 5, 4, v
);
1782 rtl9300_sds_field_w(lane_0
, 0x20, 18, 7, 6, v
);
1784 // Force SerDes mode
1785 rtl9300_sds_field_w(sds
, 0x1f, 9, 6, 6, 1);
1786 rtl9300_sds_field_w(sds
, 0x1f, 9, 11, 7, sds_mode
);
1788 // Toggle LC or Ring
1789 for (i
= 0; i
< 20; i
++) {
1792 rtl930x_write_sds_phy(lane_0
, 0x1f, 2, 53);
1794 m_bit
= (lane_0
== sds
) ? (4) : (5);
1795 l_bit
= (lane_0
== sds
) ? (4) : (5);
1797 cr_0
= rtl9300_sds_field_r(lane_0
, 0x1f, 20, m_bit
, l_bit
);
1799 cr_1
= rtl9300_sds_field_r(lane_0
, 0x1f, 20, m_bit
, l_bit
);
1801 cr_2
= rtl9300_sds_field_r(lane_0
, 0x1f, 20, m_bit
, l_bit
);
1803 if (cr_0
&& cr_1
&& cr_2
) {
1805 if (phy_if
!= PHY_INTERFACE_MODE_10GBASER
)
1808 t
= rtl9300_sds_field_r(sds
, 0x6, 0x1, 2, 2);
1809 rtl9300_sds_field_w(sds
, 0x6, 0x1, 2, 2, 0x1);
1812 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x1);
1814 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x0);
1817 // Need to read this twice
1818 v
= rtl9300_sds_field_r(sds
, 0x5, 0, 12, 12);
1819 v
= rtl9300_sds_field_r(sds
, 0x5, 0, 12, 12);
1821 rtl9300_sds_field_w(sds
, 0x6, 0x1, 2, 2, t
);
1824 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x1);
1826 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x0);
1833 m_bit
= (phy_if
== PHY_INTERFACE_MODE_10GBASER
) ? 3 : 1;
1834 l_bit
= (phy_if
== PHY_INTERFACE_MODE_10GBASER
) ? 2 : 0;
1836 rtl9300_sds_field_w(lane_0
, 0x21, 11, m_bit
, l_bit
, 0x2);
1838 rtl9300_sds_field_w(lane_0
, 0x21, 11, m_bit
, l_bit
, 0x3);
1841 rtl930x_sds_rx_rst(sds
, phy_if
);
1844 rtl9300_sds_field_w(sds
, 0x20, 0, 7, 6, 0);
1846 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__
, sds
, sds_mode
);
1849 void rtl9300_sds_tx_config(int sds
, phy_interface_t phy_if
)
1851 // parameters: rtl9303_80G_txParam_s2
1852 int impedance
= 0x8;
1861 case PHY_INTERFACE_MODE_1000BASEX
:
1864 case PHY_INTERFACE_MODE_HSGMII
:
1865 case PHY_INTERFACE_MODE_2500BASEX
:
1868 case PHY_INTERFACE_MODE_10GBASER
:
1872 pr_err("%s: unsupported PHY mode\n", __func__
);
1876 rtl9300_sds_field_w(sds
, page
, 0x1, 15, 11, pre_amp
);
1877 rtl9300_sds_field_w(sds
, page
, 0x7, 0, 0, pre_en
);
1878 rtl9300_sds_field_w(sds
, page
, 0x7, 8, 4, main_amp
);
1879 rtl9300_sds_field_w(sds
, page
, 0x6, 4, 0, post_amp
);
1880 rtl9300_sds_field_w(sds
, page
, 0x7, 3, 3, post_en
);
1881 rtl9300_sds_field_w(sds
, page
, 0x18, 15, 12, impedance
);
1885 * Wait for clock ready, this assumes the SerDes is in XGMII mode
1888 int rtl9300_sds_clock_wait(int timeout
)
1891 unsigned long start
= jiffies
;
1894 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1895 v
= rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1898 } while (jiffies
< start
+ (HZ
/ 1000) * timeout
);
1903 void rtl9300_serdes_mac_link_config(int sds
, bool tx_normal
, bool rx_normal
)
1907 v10
= rtl930x_read_sds_phy(sds
, 6, 2); // 10GBit, page 6, reg 2
1908 v1
= rtl930x_read_sds_phy(sds
, 0, 0); // 1GBit, page 0, reg 0
1909 pr_info("%s: registers before %08x %08x\n", __func__
, v10
, v1
);
1911 v10
&= ~(BIT(13) | BIT(14));
1912 v1
&= ~(BIT(8) | BIT(9));
1914 v10
|= rx_normal
? 0 : BIT(13);
1915 v1
|= rx_normal
? 0 : BIT(9);
1917 v10
|= tx_normal
? 0 : BIT(14);
1918 v1
|= tx_normal
? 0 : BIT(8);
1920 rtl930x_write_sds_phy(sds
, 6, 2, v10
);
1921 rtl930x_write_sds_phy(sds
, 0, 0, v1
);
1923 v10
= rtl930x_read_sds_phy(sds
, 6, 2);
1924 v1
= rtl930x_read_sds_phy(sds
, 0, 0);
1925 pr_info("%s: registers after %08x %08x\n", __func__
, v10
, v1
);
1928 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num
, u32 dcvs_id
, bool manual
, u32 dvcs_list
[])
1933 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 14, 14, 0x1);
1934 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 5, 5, dvcs_list
[0]);
1935 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 4, 0, dvcs_list
[1]);
1938 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 13, 13, 0x1);
1939 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 15, 15, dvcs_list
[0]);
1940 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 14, 11, dvcs_list
[1]);
1943 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 12, 12, 0x1);
1944 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 10, 10, dvcs_list
[0]);
1945 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 9, 6, dvcs_list
[1]);
1948 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 11, 11, 0x1);
1949 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 5, 5, dvcs_list
[0]);
1950 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 4, 1, dvcs_list
[1]);
1953 rtl9300_sds_field_w(sds_num
, 0x2e, 0x01, 15, 15, 0x1);
1954 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 10, 10, dvcs_list
[0]);
1955 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 9, 6, dvcs_list
[1]);
1958 rtl9300_sds_field_w(sds_num
, 0x2e, 0x02, 11, 11, 0x1);
1959 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 4, 4, dvcs_list
[0]);
1960 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 3, 0, dvcs_list
[1]);
1968 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 14, 14, 0x0);
1971 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 13, 13, 0x0);
1974 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 12, 12, 0x0);
1977 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 11, 11, 0x0);
1980 rtl9300_sds_field_w(sds_num
, 0x2e, 0x01, 15, 15, 0x0);
1983 rtl9300_sds_field_w(sds_num
, 0x2e, 0x02, 11, 11, 0x0);
1992 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num
, u32 dcvs_id
, u32 dcvs_list
[])
1994 u32 dcvs_sign_out
= 0, dcvs_coef_bin
= 0;
1998 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2000 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2002 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2003 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2005 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2006 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2010 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x22);
2014 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2015 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2016 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 14, 14);
2020 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x23);
2024 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2025 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2026 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 13, 13);
2030 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x24);
2034 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2035 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2036 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 12, 12);
2039 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x25);
2043 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2044 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2045 dcvs_manual
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 11, 11);
2049 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x2c);
2053 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2054 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2055 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x01, 15, 15);
2059 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x2d);
2063 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2064 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2065 dcvs_manual
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x02, 11, 11);
2073 pr_info("%s DCVS %u Sign: -", __func__
, dcvs_id
);
2075 pr_info("%s DCVS %u Sign: +", __func__
, dcvs_id
);
2077 pr_info("DCVS %u even coefficient = %u", dcvs_id
, dcvs_coef_bin
);
2078 pr_info("DCVS %u manual = %u", dcvs_id
, dcvs_manual
);
2080 dcvs_list
[0] = dcvs_sign_out
;
2081 dcvs_list
[1] = dcvs_coef_bin
;
2084 void rtl9300_sds_rxcal_leq_manual(u32 sds_num
, bool manual
, u32 leq_gray
)
2087 rtl9300_sds_field_w(sds_num
, 0x2e, 0x18, 15, 15, 0x1);
2088 rtl9300_sds_field_w(sds_num
, 0x2e, 0x16, 14, 10, leq_gray
);
2090 rtl9300_sds_field_w(sds_num
, 0x2e, 0x18, 15, 15, 0x0);
2095 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num
, bool manual
, u32 offset
)
2098 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 6, 2, offset
);
2100 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 6, 2, offset
);
2106 u32
rtl9300_sds_rxcal_gray_to_binary(u32 gray_code
)
2113 for(i
= 0; i
< GRAY_BITS
; i
++)
2114 g
[i
] = (gray_code
& BIT(i
)) >> i
;
2120 for(i
= 0; i
< m
; i
++) {
2122 for(j
= i
+ 1; j
< GRAY_BITS
; j
++)
2126 for(i
= 0; i
< GRAY_BITS
; i
++)
2127 leq_binary
+= c
[i
] << i
;
2132 u32
rtl9300_sds_rxcal_leq_read(int sds_num
)
2134 u32 leq_gray
, leq_bin
;
2138 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2140 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2142 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2143 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2145 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]
2146 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x10);
2150 leq_gray
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 7, 3);
2151 leq_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x18, 15, 15);
2152 leq_bin
= rtl9300_sds_rxcal_gray_to_binary(leq_gray
);
2154 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray
, leq_bin
);
2155 pr_info("LEQ manual: %u", leq_manual
);
2160 void rtl9300_sds_rxcal_vth_manual(u32 sds_num
, bool manual
, u32 vth_list
[])
2163 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, 13, 13, 0x1);
2164 rtl9300_sds_field_w(sds_num
, 0x2e, 0x13, 5, 3, vth_list
[0]);
2165 rtl9300_sds_field_w(sds_num
, 0x2e, 0x13, 2, 0, vth_list
[1]);
2167 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, 13, 13, 0x0);
2172 void rtl9300_sds_rxcal_vth_get(u32 sds_num
, u32 vth_list
[])
2176 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0
2177 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1
2179 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2181 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2183 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2184 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2185 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2186 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2187 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]
2188 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0xc);
2192 //##VthP & VthN Read Out
2193 vth_list
[0] = rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 2, 0); // v_thp set bin
2194 vth_list
[1] = rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 3); // v_thn set bin
2196 pr_info("vth_set_bin = %d", vth_list
[0]);
2197 pr_info("vth_set_bin = %d", vth_list
[1]);
2199 vth_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x0f, 13, 13);
2200 pr_info("Vth Maunal = %d", vth_manual
);
2203 void rtl9300_sds_rxcal_tap_manual(u32 sds_num
, int tap_id
, bool manual
, u32 tap_list
[])
2208 //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value
2209 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2210 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 5, 5, tap_list
[0]);
2211 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 4, 0, tap_list
[1]);
2214 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2215 rtl9300_sds_field_w(sds_num
, 0x21, 0x07, 6, 6, tap_list
[0]);
2216 rtl9300_sds_field_w(sds_num
, 0x2e, 0x09, 11, 6, tap_list
[1]);
2217 rtl9300_sds_field_w(sds_num
, 0x21, 0x07, 5, 5, tap_list
[2]);
2218 rtl9300_sds_field_w(sds_num
, 0x2f, 0x12, 5, 0, tap_list
[3]);
2221 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2222 rtl9300_sds_field_w(sds_num
, 0x2e, 0x09, 5, 5, tap_list
[0]);
2223 rtl9300_sds_field_w(sds_num
, 0x2e, 0x09, 4, 0, tap_list
[1]);
2224 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 11, 11, tap_list
[2]);
2225 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 10, 6, tap_list
[3]);
2228 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2229 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 5, 5, tap_list
[0]);
2230 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 4, 0, tap_list
[1]);
2231 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 5, 5, tap_list
[2]);
2232 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 4, 0, tap_list
[3]);
2235 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2236 rtl9300_sds_field_w(sds_num
, 0x2f, 0x01, 5, 5, tap_list
[0]);
2237 rtl9300_sds_field_w(sds_num
, 0x2f, 0x01, 4, 0, tap_list
[1]);
2238 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 11, 11, tap_list
[2]);
2239 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 10, 6, tap_list
[3]);
2245 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x0);
2250 void rtl9300_sds_rxcal_tap_get(u32 sds_num
, u32 tap_id
, u32 tap_list
[])
2254 u32 tap_sign_out_even
;
2255 u32 tap_coef_bin_even
;
2256 u32 tap_sign_out_odd
;
2257 u32 tap_coef_bin_odd
;
2261 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2263 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2265 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2266 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2267 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2268 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2271 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2272 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0);
2273 //##Tap1 Even Read Out
2275 tap0_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 5);
2276 tap0_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 0);
2278 if (tap0_sign_out
== 1)
2279 pr_info("Tap0 Sign : -");
2281 pr_info("Tap0 Sign : +");
2283 pr_info("tap0_coef_bin = %d", tap0_coef_bin
);
2285 tap_list
[0] = tap0_sign_out
;
2286 tap_list
[1] = tap0_coef_bin
;
2288 tap_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x0f, 7, 7);
2289 pr_info("tap0 manual = %u",tap_manual
);
2291 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2292 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, tap_id
);
2294 //##Tap1 Even Read Out
2295 tap_sign_out_even
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 5);
2296 tap_coef_bin_even
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 0);
2298 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]
2299 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, (tap_id
+ 5));
2300 //##Tap1 Odd Read Out
2301 tap_sign_out_odd
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 5);
2302 tap_coef_bin_odd
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 0);
2304 if (tap_sign_out_even
== 1)
2305 pr_info("Tap %u even sign: -", tap_id
);
2307 pr_info("Tap %u even sign: +", tap_id
);
2309 pr_info("Tap %u even coefficient = %u", tap_id
, tap_coef_bin_even
);
2311 if (tap_sign_out_odd
== 1)
2312 pr_info("Tap %u odd sign: -", tap_id
);
2314 pr_info("Tap %u odd sign: +", tap_id
);
2316 pr_info("Tap %u odd coefficient = %u", tap_id
,tap_coef_bin_odd
);
2318 tap_list
[0] = tap_sign_out_even
;
2319 tap_list
[1] = tap_coef_bin_even
;
2320 tap_list
[2] = tap_sign_out_odd
;
2321 tap_list
[3] = tap_coef_bin_odd
;
2323 tap_manual
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7);
2324 pr_info("tap %u manual = %d",tap_id
, tap_manual
);
2328 void rtl9300_do_rx_calibration_1(int sds
, phy_interface_t phy_mode
)
2330 // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam
2331 int tap0_init_val
= 0x1f; // Initial Decision Fed Equalizer 0 tap
2334 pr_info("start_1.1.1 initial value for sds %d\n", sds
);
2335 rtl930x_write_sds_phy(sds
, 6, 0, 0);
2338 rtl9300_sds_field_w(sds
, 0x2e, 0x01, 14, 14, 0x0);
2339 rtl9300_sds_field_w(sds
, 0x2e, 0x1c, 10, 5, 0x20);
2340 rtl9300_sds_field_w(sds
, 0x2f, 0x02, 0, 0, 0x1);
2343 rtl9300_sds_field_w(sds
, 0x2e, 0x1e, 14, 11, 0x0);
2344 rtl9300_sds_field_w(sds
, 0x2e, 0x01, 15, 15, 0x0);
2345 rtl9300_sds_field_w(sds
, 0x2e, 0x02, 11, 11, 0x0);
2346 rtl9300_sds_field_w(sds
, 0x2e, 0x1c, 4, 0, 0x0);
2347 rtl9300_sds_field_w(sds
, 0x2e, 0x1d, 15, 11, 0x0);
2348 rtl9300_sds_field_w(sds
, 0x2e, 0x1d, 10, 6, 0x0);
2349 rtl9300_sds_field_w(sds
, 0x2e, 0x1d, 5, 1, 0x0);
2350 rtl9300_sds_field_w(sds
, 0x2e, 0x02, 10, 6, 0x0);
2351 rtl9300_sds_field_w(sds
, 0x2e, 0x11, 4, 0, 0x0);
2352 rtl9300_sds_field_w(sds
, 0x2f, 0x00, 3, 0, 0xf);
2353 rtl9300_sds_field_w(sds
, 0x2e, 0x04, 6, 6, 0x1);
2354 rtl9300_sds_field_w(sds
, 0x2e, 0x04, 7, 7, 0x1);
2356 // LEQ (Long Term Equivalent signal level)
2357 rtl9300_sds_field_w(sds
, 0x2e, 0x16, 14, 8, 0x0);
2359 // DFE (Decision Fed Equalizer)
2360 rtl9300_sds_field_w(sds
, 0x2f, 0x03, 5, 0, tap0_init_val
);
2361 rtl9300_sds_field_w(sds
, 0x2e, 0x09, 11, 6, 0x0);
2362 rtl9300_sds_field_w(sds
, 0x2e, 0x09, 5, 0, 0x0);
2363 rtl9300_sds_field_w(sds
, 0x2e, 0x0a, 5, 0, 0x0);
2364 rtl9300_sds_field_w(sds
, 0x2f, 0x01, 5, 0, 0x0);
2365 rtl9300_sds_field_w(sds
, 0x2f, 0x12, 5, 0, 0x0);
2366 rtl9300_sds_field_w(sds
, 0x2e, 0x0a, 11, 6, 0x0);
2367 rtl9300_sds_field_w(sds
, 0x2e, 0x06, 5, 0, 0x0);
2368 rtl9300_sds_field_w(sds
, 0x2f, 0x01, 5, 0, 0x0);
2371 rtl9300_sds_field_w(sds
, 0x2e, 0x13, 5, 3, 0x7);
2372 rtl9300_sds_field_w(sds
, 0x2e, 0x13, 2, 0, 0x7);
2373 rtl9300_sds_field_w(sds
, 0x2f, 0x0b, 5, 3, vth_min
);
2375 pr_info("end_1.1.1 --\n");
2377 pr_info("start_1.1.2 Load DFE init. value\n");
2379 rtl9300_sds_field_w(sds
, 0x2e, 0x0f, 13, 7, 0x7f);
2381 pr_info("end_1.1.2\n");
2383 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2385 rtl9300_sds_field_w(sds
, 0x2e, 0x17, 7, 7, 0x0);
2386 rtl9300_sds_field_w(sds
, 0x2e, 0x17, 6, 2, 0x0);
2387 rtl9300_sds_field_w(sds
, 0x2e, 0x0c, 8, 8, 0x0);
2388 rtl9300_sds_field_w(sds
, 0x2e, 0x0b, 4, 4, 0x1);
2389 rtl9300_sds_field_w(sds
, 0x2e, 0x12, 14, 14, 0x0);
2390 rtl9300_sds_field_w(sds
, 0x2f, 0x02, 15, 15, 0x0);
2392 pr_info("end_1.1.3 --\n");
2394 pr_info("start_1.1.4 offset cali setting\n");
2396 rtl9300_sds_field_w(sds
, 0x2e, 0x0f, 15, 14, 0x3);
2398 pr_info("end_1.1.4\n");
2400 pr_info("start_1.1.5 LEQ and DFE setting\n");
2402 // TODO: make this work for DAC cables of different lengths
2403 // For a 10GBit serdes wit Fibre, SDS 8 or 9
2404 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| PHY_INTERFACE_MODE_1000BASEX
)
2405 rtl9300_sds_field_w(sds
, 0x2e, 0x16, 3, 2, 0x2);
2407 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__
);
2409 // No serdes, check for Aquantia PHYs
2410 rtl9300_sds_field_w(sds
, 0x2e, 0x16, 3, 2, 0x2);
2412 rtl9300_sds_field_w(sds
, 0x2e, 0x0f, 6, 0, 0x5f);
2413 rtl9300_sds_field_w(sds
, 0x2f, 0x05, 7, 2, 0x1f);
2414 rtl9300_sds_field_w(sds
, 0x2e, 0x19, 9, 5, 0x1f);
2415 rtl9300_sds_field_w(sds
, 0x2f, 0x0b, 15, 9, 0x3c);
2416 rtl9300_sds_field_w(sds
, 0x2e, 0x0b, 1, 0, 0x3);
2418 pr_info("end_1.1.5\n");
2421 void rtl9300_do_rx_calibration_2_1(u32 sds_num
)
2423 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2425 // Gray config endis to 1
2426 rtl9300_sds_field_w(sds_num
, 0x2f, 0x02, 2, 2, 0x1);
2428 // ForegroundOffsetCal_Manual(auto mode)
2429 rtl9300_sds_field_w(sds_num
, 0x2e, 0x01, 14, 14, 0x0);
2431 pr_info("end_1.2.1");
2434 void rtl9300_do_rx_calibration_2_2(int sds_num
)
2437 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 8, 8, 0x0);
2439 rtl930x_sds_rx_rst(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
2442 void rtl9300_do_rx_calibration_2_3(int sds_num
)
2444 u32 fgcal_binary
, fgcal_gray
;
2447 pr_info("start_1.2.3 Foreground Calibration\n");
2451 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2453 rtl930x_write_sds_phy(sds_num
-1 , 0x1f, 0x2, 0x31);
2455 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2456 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2457 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2458 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2459 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]
2460 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0xf);
2461 // ##FGCAL read gray
2462 fgcal_gray
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 0);
2463 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]
2464 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0xe);
2465 // ##FGCAL read binary
2466 fgcal_binary
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 0);
2468 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2469 __func__
, fgcal_gray
, fgcal_binary
);
2471 offset_range
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x15, 15, 14);
2473 if (fgcal_binary
> 60 || fgcal_binary
< 3) {
2474 if (offset_range
== 3) {
2475 pr_info("%s: Foreground Calibration result marginal!", __func__
);
2479 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 15, 14, offset_range
);
2480 rtl9300_do_rx_calibration_2_2(sds_num
);
2486 pr_info("%s: end_1.2.3\n", __func__
);
2489 void rtl9300_do_rx_calibration_2(int sds
)
2491 rtl930x_sds_rx_rst(sds
, PHY_INTERFACE_MODE_10GBASER
);
2492 rtl9300_do_rx_calibration_2_1(sds
);
2493 rtl9300_do_rx_calibration_2_2(sds
);
2494 rtl9300_do_rx_calibration_2_3(sds
);
2497 void rtl9300_sds_rxcal_3_1(int sds_num
, phy_interface_t phy_mode
)
2499 pr_info("start_1.3.1");
2502 if (phy_mode
!= PHY_INTERFACE_MODE_10GBASER
&& phy_mode
!= PHY_INTERFACE_MODE_1000BASEX
)
2503 rtl9300_sds_field_w(sds_num
, 0x2e, 0xc, 8, 8, 0);
2505 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, 0x0);
2506 rtl9300_sds_rxcal_leq_manual(sds_num
, false, 0);
2508 pr_info("end_1.3.1");
2511 void rtl9300_sds_rxcal_3_2(int sds_num
, phy_interface_t phy_mode
)
2513 u32 sum10
= 0, avg10
, int10
;
2514 int dac_long_cable_offset
;
2515 bool eq_hold_enabled
;
2518 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| phy_mode
== PHY_INTERFACE_MODE_1000BASEX
) {
2519 // rtl9300_rxCaliConf_serdes_myParam
2520 dac_long_cable_offset
= 3;
2521 eq_hold_enabled
= true;
2523 // rtl9300_rxCaliConf_phy_myParam
2524 dac_long_cable_offset
= 0;
2525 eq_hold_enabled
= false;
2528 if (phy_mode
== PHY_INTERFACE_MODE_1000BASEX
)
2529 pr_warn("%s: LEQ only valid for 10GR!\n", __func__
);
2531 pr_info("start_1.3.2");
2533 for(i
= 0; i
< 10; i
++) {
2534 sum10
+= rtl9300_sds_rxcal_leq_read(sds_num
);
2538 avg10
= (sum10
/ 10) + (((sum10
% 10) >= 5) ? 1 : 0);
2541 pr_info("sum10:%u, avg10:%u, int10:%u", sum10
, avg10
, int10
);
2543 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| phy_mode
== PHY_INTERFACE_MODE_1000BASEX
) {
2544 if (dac_long_cable_offset
) {
2545 rtl9300_sds_rxcal_leq_offset_manual(sds_num
, 1, dac_long_cable_offset
);
2546 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, eq_hold_enabled
);
2547 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
)
2548 rtl9300_sds_rxcal_leq_manual(sds_num
, true, avg10
);
2551 rtl9300_sds_rxcal_leq_offset_manual(sds_num
, 1, 3);
2552 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, 0x1);
2553 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
)
2554 rtl9300_sds_rxcal_leq_manual(sds_num
, true, avg10
);
2556 rtl9300_sds_rxcal_leq_offset_manual(sds_num
, 1, 0);
2557 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, 0x1);
2558 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
)
2559 rtl9300_sds_rxcal_leq_manual(sds_num
, true, avg10
);
2564 pr_info("Sds:%u LEQ = %u",sds_num
, rtl9300_sds_rxcal_leq_read(sds_num
));
2566 pr_info("end_1.3.2");
2569 void rtl9300_do_rx_calibration_3(int sds_num
, phy_interface_t phy_mode
)
2571 rtl9300_sds_rxcal_3_1(sds_num
, phy_mode
);
2573 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| phy_mode
== PHY_INTERFACE_MODE_1000BASEX
)
2574 rtl9300_sds_rxcal_3_2(sds_num
, phy_mode
);
2577 void rtl9300_do_rx_calibration_4_1(int sds_num
)
2579 u32 vth_list
[2] = {0, 0};
2580 u32 tap0_list
[4] = {0, 0, 0, 0};
2582 pr_info("start_1.4.1");
2585 rtl9300_sds_rxcal_vth_manual(sds_num
, false, vth_list
);
2586 rtl9300_sds_rxcal_tap_manual(sds_num
, 0, false, tap0_list
);
2589 pr_info("end_1.4.1");
2592 void rtl9300_do_rx_calibration_4_2(u32 sds_num
)
2597 pr_info("start_1.4.2");
2599 rtl9300_sds_rxcal_vth_get(sds_num
, vth_list
);
2600 rtl9300_sds_rxcal_vth_manual(sds_num
, true, vth_list
);
2604 rtl9300_sds_rxcal_tap_get(sds_num
, 0, tap_list
);
2605 rtl9300_sds_rxcal_tap_manual(sds_num
, 0, true, tap_list
);
2607 pr_info("end_1.4.2");
2610 void rtl9300_do_rx_calibration_4(u32 sds_num
)
2612 rtl9300_do_rx_calibration_4_1(sds_num
);
2613 rtl9300_do_rx_calibration_4_2(sds_num
);
2616 void rtl9300_do_rx_calibration_5_2(u32 sds_num
)
2618 u32 tap1_list
[4] = {0};
2619 u32 tap2_list
[4] = {0};
2620 u32 tap3_list
[4] = {0};
2621 u32 tap4_list
[4] = {0};
2623 pr_info("start_1.5.2");
2625 rtl9300_sds_rxcal_tap_manual(sds_num
, 1, false, tap1_list
);
2626 rtl9300_sds_rxcal_tap_manual(sds_num
, 2, false, tap2_list
);
2627 rtl9300_sds_rxcal_tap_manual(sds_num
, 3, false, tap3_list
);
2628 rtl9300_sds_rxcal_tap_manual(sds_num
, 4, false, tap4_list
);
2632 pr_info("end_1.5.2");
2635 void rtl9300_do_rx_calibration_5(u32 sds_num
, phy_interface_t phy_mode
)
2637 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
) // dfeTap1_4Enable true
2638 rtl9300_do_rx_calibration_5_2(sds_num
);
2642 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num
)
2644 u32 tap1_list
[4] = {0};
2645 u32 tap2_list
[4] = {0};
2646 u32 tap3_list
[4] = {0};
2647 u32 tap4_list
[4] = {0};
2649 rtl9300_sds_rxcal_tap_manual(sds_num
, 1, true, tap1_list
);
2650 rtl9300_sds_rxcal_tap_manual(sds_num
, 2, true, tap2_list
);
2651 rtl9300_sds_rxcal_tap_manual(sds_num
, 3, true, tap3_list
);
2652 rtl9300_sds_rxcal_tap_manual(sds_num
, 4, true, tap4_list
);
2657 void rtl9300_do_rx_calibration(int sds
, phy_interface_t phy_mode
)
2661 rtl9300_do_rx_calibration_1(sds
, phy_mode
);
2662 rtl9300_do_rx_calibration_2(sds
);
2663 rtl9300_do_rx_calibration_4(sds
);
2664 rtl9300_do_rx_calibration_5(sds
, phy_mode
);
2667 // Do this only for 10GR mode, SDS active in mode 0x1a
2668 if (rtl9300_sds_field_r(sds
, 0x1f, 9, 11, 7) == 0x1a) {
2669 pr_info("%s: SDS enabled\n", __func__
);
2670 latch_sts
= rtl9300_sds_field_r(sds
, 0x4, 1, 2, 2);
2672 latch_sts
= rtl9300_sds_field_r(sds
, 0x4, 1, 2, 2);
2674 rtl9300_do_rx_calibration_dfe_disable(sds
);
2675 rtl9300_do_rx_calibration_4(sds
);
2676 rtl9300_do_rx_calibration_5(sds
, phy_mode
);
2681 int rtl9300_sds_sym_err_reset(int sds_num
, phy_interface_t phy_mode
)
2684 case PHY_INTERFACE_MODE_XGMII
:
2687 case PHY_INTERFACE_MODE_10GBASER
:
2688 // Read twice to clear
2689 rtl930x_read_sds_phy(sds_num
, 5, 1);
2690 rtl930x_read_sds_phy(sds_num
, 5, 1);
2693 case PHY_INTERFACE_MODE_1000BASEX
:
2694 rtl9300_sds_field_w(sds_num
, 0x1, 24, 2, 0, 0);
2695 rtl9300_sds_field_w(sds_num
, 0x1, 3, 15, 8, 0);
2696 rtl9300_sds_field_w(sds_num
, 0x1, 2, 15, 0, 0);
2700 pr_info("%s unsupported phy mode\n", __func__
);
2707 u32
rtl9300_sds_sym_err_get(int sds_num
, phy_interface_t phy_mode
)
2712 case PHY_INTERFACE_MODE_XGMII
:
2715 case PHY_INTERFACE_MODE_10GBASER
:
2716 v
= rtl930x_read_sds_phy(sds_num
, 5, 1);
2720 pr_info("%s unsupported PHY-mode\n", __func__
);
2726 int rtl9300_sds_check_calibration(int sds_num
, phy_interface_t phy_mode
)
2728 u32 errors1
, errors2
;
2730 rtl9300_sds_sym_err_reset(sds_num
, phy_mode
);
2731 rtl9300_sds_sym_err_reset(sds_num
, phy_mode
);
2733 // Count errors during 1ms
2734 errors1
= rtl9300_sds_sym_err_get(sds_num
, phy_mode
);
2736 errors2
= rtl9300_sds_sym_err_get(sds_num
, phy_mode
);
2739 case PHY_INTERFACE_MODE_XGMII
:
2741 if ((errors2
- errors1
> 100)
2742 || (errors1
>= 0xffff00) || (errors2
>= 0xffff00)) {
2743 pr_info("%s XSGMII error rate too high\n", __func__
);
2747 case PHY_INTERFACE_MODE_10GBASER
:
2749 pr_info("%s 10GBASER error rate too high\n", __func__
);
2759 void rtl9300_phy_enable_10g_1g(int sds_num
)
2764 v
= rtl930x_read_sds_phy(sds_num
, PHY_PAGE_2
, PHY_CTRL_REG
);
2765 pr_info("%s 1gbit phy: %08x\n", __func__
, v
);
2766 v
&= ~BIT(PHY_POWER_BIT
);
2767 rtl930x_write_sds_phy(sds_num
, PHY_PAGE_2
, PHY_CTRL_REG
, v
);
2768 pr_info("%s 1gbit phy enabled: %08x\n", __func__
, v
);
2770 // Enable 10GBit PHY
2771 v
= rtl930x_read_sds_phy(sds_num
, PHY_PAGE_4
, PHY_CTRL_REG
);
2772 pr_info("%s 10gbit phy: %08x\n", __func__
, v
);
2773 v
&= ~BIT(PHY_POWER_BIT
);
2774 rtl930x_write_sds_phy(sds_num
, PHY_PAGE_4
, PHY_CTRL_REG
, v
);
2775 pr_info("%s 10gbit phy after: %08x\n", __func__
, v
);
2777 // dal_longan_construct_mac_default_10gmedia_fiber
2778 v
= rtl930x_read_sds_phy(sds_num
, 0x1f, 11);
2779 pr_info("%s set medium: %08x\n", __func__
, v
);
2781 rtl930x_write_sds_phy(sds_num
, 0x1f, 11, v
);
2782 pr_info("%s set medium after: %08x\n", __func__
, v
);
2785 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2786 // phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a
2787 int rtl9300_serdes_setup(int sds_num
, phy_interface_t phy_mode
)
2790 int calib_tries
= 0;
2793 case PHY_INTERFACE_MODE_HSGMII
:
2796 case PHY_INTERFACE_MODE_1000BASEX
:
2799 case PHY_INTERFACE_MODE_XGMII
:
2802 case PHY_INTERFACE_MODE_10GBASER
:
2805 case PHY_INTERFACE_MODE_USXGMII
:
2809 pr_err("%s: unknown serdes mode: %s\n", __func__
, phy_modes(phy_mode
));
2813 // Maybe use dal_longan_sds_init
2815 // dal_longan_construct_serdesConfig_init // Serdes Construct
2816 rtl9300_phy_enable_10g_1g(sds_num
);
2819 rtl9300_sds_set(sds_num
, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO
2821 // Do RX calibration
2823 rtl9300_do_rx_calibration(sds_num
, phy_mode
);
2826 } while (rtl9300_sds_check_calibration(sds_num
, phy_mode
) && calib_tries
< 3);
2838 sds_config rtl9300_a_sds_10gr_lane0
[] =
2841 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2842 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2843 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2844 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2845 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2846 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2847 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2848 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2849 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2850 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2851 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2852 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2853 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2854 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2855 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2856 {0x2F, 0x1D, 0x66E1},
2858 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2859 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2860 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2861 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2862 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2863 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2864 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2865 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2867 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2868 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2869 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2870 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2871 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2872 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2873 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2874 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2875 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2876 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2877 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2878 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2879 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2880 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2881 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2882 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2883 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2886 sds_config rtl9300_a_sds_10gr_lane1
[] =
2889 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2890 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2891 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2892 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2893 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2894 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2895 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2896 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2897 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2898 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2899 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2900 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2901 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2902 {0x2D, 0x14, 0x1808},
2904 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2905 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2906 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2907 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2908 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2909 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2910 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2911 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2913 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2914 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2915 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2916 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2917 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2918 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2919 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2920 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2921 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2922 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2923 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2924 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2925 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2926 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2929 int rtl9300_sds_cmu_band_get(int sds
)
2935 // page = rtl9300_sds_cmu_page_get(sds);
2936 page
= 0x25; // 10GR and 1000BX
2937 sds
= (sds
% 2) ? (sds
- 1) : (sds
);
2939 rtl9300_sds_field_w(sds
, page
, 0x1c, 15, 15, 1);
2940 rtl9300_sds_field_w(sds
+ 1, page
, 0x1c, 15, 15, 1);
2942 en
= rtl9300_sds_field_r(sds
, page
, 27, 1, 1);
2943 if(!en
) { // Auto mode
2944 rtl930x_write_sds_phy(sds
, 0x1f, 0x02, 31);
2946 cmu_band
= rtl9300_sds_field_r(sds
, 0x1f, 0x15, 5, 1);
2948 cmu_band
= rtl9300_sds_field_r(sds
, page
, 30, 4, 0);
2954 int rtl9300_configure_serdes(struct phy_device
*phydev
)
2956 struct device
*dev
= &phydev
->mdio
.dev
;
2957 int phy_addr
= phydev
->mdio
.addr
;
2958 struct device_node
*dn
;
2960 int sds_mode
, calib_tries
= 0, phy_mode
= PHY_INTERFACE_MODE_10GBASER
, i
;
2965 if (of_property_read_u32(dn
, "sds", &sds_num
))
2967 pr_info("%s: Port %d, SerDes is %d\n", __func__
, phy_addr
, sds_num
);
2969 dev_err(dev
, "No DT node.\n");
2976 if (phy_mode
!= PHY_INTERFACE_MODE_10GBASER
) // TODO: for now we only patch 10GR SerDes
2980 case PHY_INTERFACE_MODE_HSGMII
:
2983 case PHY_INTERFACE_MODE_1000BASEX
:
2986 case PHY_INTERFACE_MODE_XGMII
:
2989 case PHY_INTERFACE_MODE_10GBASER
:
2992 case PHY_INTERFACE_MODE_USXGMII
:
2996 pr_err("%s: unknown serdes mode: %s\n", __func__
, phy_modes(phy_mode
));
3000 pr_info("%s CMU BAND is %d\n", __func__
, rtl9300_sds_cmu_band_get(sds_num
));
3003 rtl9300_sds_rst(sds_num
, 0x1f);
3005 pr_info("%s PATCHING SerDes %d\n", __func__
, sds_num
);
3007 for (i
= 0; i
< sizeof(rtl9300_a_sds_10gr_lane1
) / sizeof(sds_config
); ++i
) {
3008 rtl930x_write_sds_phy(sds_num
, rtl9300_a_sds_10gr_lane1
[i
].page
,
3009 rtl9300_a_sds_10gr_lane1
[i
].reg
,
3010 rtl9300_a_sds_10gr_lane1
[i
].data
);
3013 for (i
= 0; i
< sizeof(rtl9300_a_sds_10gr_lane0
) / sizeof(sds_config
); ++i
) {
3014 rtl930x_write_sds_phy(sds_num
, rtl9300_a_sds_10gr_lane0
[i
].page
,
3015 rtl9300_a_sds_10gr_lane0
[i
].reg
,
3016 rtl9300_a_sds_10gr_lane0
[i
].data
);
3020 rtl9300_phy_enable_10g_1g(sds_num
);
3023 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL
);
3026 // ----> dal_longan_sds_mode_set
3027 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__
, sds_num
, sds_mode
);
3029 // Configure link to MAC
3030 rtl9300_serdes_mac_link_config(sds_num
, true, true); // MAC Construct
3033 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL
);
3036 rtl9300_force_sds_mode(sds_num
, PHY_INTERFACE_MODE_NA
);
3039 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL
);
3041 rtl9300_force_sds_mode(sds_num
, phy_mode
);
3043 // Do RX calibration
3045 rtl9300_do_rx_calibration(sds_num
, phy_mode
);
3048 } while (rtl9300_sds_check_calibration(sds_num
, phy_mode
) && calib_tries
< 3);
3050 if (calib_tries
>= 3)
3051 pr_err("%s CALIBTRATION FAILED\n", __func__
);
3053 rtl9300_sds_tx_config(sds_num
, phy_mode
);
3055 // The clock needs only to be configured on the FPGA implementation
3060 void rtl9310_sds_field_w(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
, u32 v
)
3062 int l
= end_bit
- start_bit
+ 1;
3066 u32 mask
= BIT(l
) - 1;
3068 data
= rtl930x_read_sds_phy(sds
, page
, reg
);
3069 data
&= ~(mask
<< start_bit
);
3070 data
|= (v
& mask
) << start_bit
;
3073 rtl931x_write_sds_phy(sds
, page
, reg
, data
);
3077 u32
rtl9310_sds_field_r(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
)
3079 int l
= end_bit
- start_bit
+ 1;
3080 u32 v
= rtl931x_read_sds_phy(sds
, page
, reg
);
3085 return (v
>> start_bit
) & (BIT(l
) - 1);
3088 static void rtl931x_sds_rst(u32 sds
)
3091 int shift
= ((sds
& 0x3) << 3);
3093 // TODO: We need to lock this!
3095 o
= sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3097 sw_w32(v
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3099 o_mode
= sw_r32(RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3101 sw_w32_mask(0xff << shift
, v
<< shift
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3102 sw_w32(o_mode
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3104 sw_w32(o
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3107 static void rtl931x_symerr_clear(u32 sds
, phy_interface_t mode
)
3110 u32 xsg_sdsid_0
, xsg_sdsid_1
;
3113 case PHY_INTERFACE_MODE_NA
:
3115 case PHY_INTERFACE_MODE_XGMII
:
3119 xsg_sdsid_0
= (sds
- 1) * 2;
3120 xsg_sdsid_1
= xsg_sdsid_0
+ 1;
3122 for (i
= 0; i
< 4; ++i
) {
3123 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 24, 2, 0, i
);
3124 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 3, 15, 8, 0x0);
3125 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 2, 15, 0, 0x0);
3128 for (i
= 0; i
< 4; ++i
) {
3129 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 24, 2, 0, i
);
3130 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 3, 15, 8, 0x0);
3131 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 2, 15, 0, 0x0);
3134 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 0, 15, 0, 0x0);
3135 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 1, 15, 8, 0x0);
3136 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 0, 15, 0, 0x0);
3137 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 1, 15, 8, 0x0);
3146 static u32
rtl931x_get_analog_sds(u32 sds
)
3148 u32 sds_map
[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3151 return sds_map
[sds
];
3155 void rtl931x_sds_fiber_disable(u32 sds
)
3158 u32 asds
= rtl931x_get_analog_sds(sds
);
3160 rtl9310_sds_field_w(asds
, 0x1F, 0x9, 11, 6, v
);
3163 static void rtl931x_sds_fiber_mode_set(u32 sds
, phy_interface_t mode
)
3165 u32 val
, asds
= rtl931x_get_analog_sds(sds
);
3167 /* clear symbol error count before changing mode */
3168 rtl931x_symerr_clear(sds
, mode
);
3171 sw_w32(val
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3174 case PHY_INTERFACE_MODE_SGMII
:
3178 case PHY_INTERFACE_MODE_1000BASEX
:
3179 /* serdes mode FIBER1G */
3183 case PHY_INTERFACE_MODE_10GBASER
:
3184 case PHY_INTERFACE_MODE_10GKR
:
3187 /* case MII_10GR1000BX_AUTO:
3192 case PHY_INTERFACE_MODE_USXGMII
:
3199 pr_info("%s writing analog SerDes Mode value %02x\n", __func__
, val
);
3200 rtl9310_sds_field_w(asds
, 0x1F, 0x9, 11, 6, val
);
3205 static int rtl931x_sds_cmu_page_get(phy_interface_t mode
)
3208 case PHY_INTERFACE_MODE_SGMII
:
3209 case PHY_INTERFACE_MODE_1000BASEX
: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO
3211 case PHY_INTERFACE_MODE_HSGMII
:
3212 case PHY_INTERFACE_MODE_2500BASEX
: // MII_2500Base_X:
3214 // case MII_HISGMII_5G:
3216 case PHY_INTERFACE_MODE_QSGMII
:
3217 return 0x2a; // Code also has 0x34
3218 case PHY_INTERFACE_MODE_XAUI
: // MII_RXAUI_LITE:
3220 case PHY_INTERFACE_MODE_XGMII
: // MII_XSGMII
3221 case PHY_INTERFACE_MODE_10GKR
:
3222 case PHY_INTERFACE_MODE_10GBASER
: // MII_10GR
3230 static void rtl931x_cmu_type_set(u32 asds
, phy_interface_t mode
, int chiptype
)
3232 int cmu_type
= 0; // Clock Management Unit
3236 u32 lane
, frc_lc_mode_bitnum
, frc_lc_mode_val_bitnum
;
3239 case PHY_INTERFACE_MODE_NA
:
3240 case PHY_INTERFACE_MODE_10GKR
:
3241 case PHY_INTERFACE_MODE_XGMII
:
3242 case PHY_INTERFACE_MODE_10GBASER
:
3243 case PHY_INTERFACE_MODE_USXGMII
:
3246 /* case MII_10GR1000BX_AUTO:
3248 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3251 case PHY_INTERFACE_MODE_QSGMII
:
3256 case PHY_INTERFACE_MODE_HSGMII
:
3261 case PHY_INTERFACE_MODE_1000BASEX
:
3266 /* case MII_1000BX100BX_AUTO:
3271 case PHY_INTERFACE_MODE_SGMII
:
3276 case PHY_INTERFACE_MODE_2500BASEX
:
3282 pr_info("SerDes %d mode is invalid\n", asds
);
3287 cmu_page
= rtl931x_sds_cmu_page_get(mode
);
3292 frc_lc_mode_bitnum
= 4;
3293 frc_lc_mode_val_bitnum
= 5;
3295 frc_lc_mode_bitnum
= 6;
3296 frc_lc_mode_val_bitnum
= 7;
3299 evenSds
= asds
- lane
;
3301 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3302 __func__
, cmu_type
, cmu_page
, frc_cmu_spd
, lane
, asds
);
3304 if (cmu_type
== 1) {
3305 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3306 rtl9310_sds_field_w(asds
, cmu_page
, 0x7, 15, 15, 0);
3307 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3309 rtl9310_sds_field_w(asds
, cmu_page
, 0xd, 14, 14, 0);
3312 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, 3, 2, 0x3);
3313 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, frc_lc_mode_bitnum
, frc_lc_mode_bitnum
, 1);
3314 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, frc_lc_mode_val_bitnum
, frc_lc_mode_val_bitnum
, 0);
3315 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, 12, 12, 1);
3316 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, 15, 13, frc_cmu_spd
);
3319 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3323 static void rtl931x_sds_rx_rst(u32 sds
)
3325 u32 asds
= rtl931x_get_analog_sds(sds
);
3330 rtl931x_write_sds_phy(asds
, 0x2e, 0x12, 0x2740);
3331 rtl931x_write_sds_phy(asds
, 0x2f, 0x0, 0x0);
3332 rtl931x_write_sds_phy(asds
, 0x2f, 0x2, 0x2010);
3333 rtl931x_write_sds_phy(asds
, 0x20, 0x0, 0xc10);
3335 rtl931x_write_sds_phy(asds
, 0x2e, 0x12, 0x27c0);
3336 rtl931x_write_sds_phy(asds
, 0x2f, 0x0, 0xc000);
3337 rtl931x_write_sds_phy(asds
, 0x2f, 0x2, 0x6010);
3338 rtl931x_write_sds_phy(asds
, 0x20, 0x0, 0xc30);
3343 static void rtl931x_sds_disable(u32 sds
)
3348 sw_w32(v
, RTL931X_SERDES_MODE_CTRL
+ (sds
>> 2) * 4);
3351 static void rtl931x_sds_mii_mode_set(u32 sds
, phy_interface_t mode
)
3356 case PHY_INTERFACE_MODE_QSGMII
:
3359 case PHY_INTERFACE_MODE_XGMII
:
3360 val
= 0x10; // serdes mode XSGMII
3362 case PHY_INTERFACE_MODE_USXGMII
:
3363 case PHY_INTERFACE_MODE_2500BASEX
:
3366 case PHY_INTERFACE_MODE_HSGMII
:
3369 case PHY_INTERFACE_MODE_SGMII
:
3378 sw_w32(val
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3381 static sds_config sds_config_10p3125g_type1
[] = {
3382 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3383 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3384 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3385 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3386 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3387 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3388 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3389 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3390 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3391 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3392 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3393 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3394 { 0x2F, 0x13, 0x0000 }
3397 static sds_config sds_config_10p3125g_cmu_type1
[] = {
3398 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3399 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3400 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3401 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3402 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3405 void rtl931x_sds_init(u32 sds
, phy_interface_t mode
)
3408 u32 board_sds_tx_type1
[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3,
3409 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163
3412 u32 board_sds_tx
[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200,
3413 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3
3416 u32 board_sds_tx2
[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160,
3417 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3
3420 u32 asds
, dSds
, ori
, model_info
, val
;
3423 asds
= rtl931x_get_analog_sds(sds
);
3428 pr_info("%s: set sds %d to mode %d\n", __func__
, sds
, mode
);
3429 val
= rtl9310_sds_field_r(asds
, 0x1F, 0x9, 11, 6);
3431 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__
,
3432 rtl931x_read_sds_phy(asds
, 0x1f, 0x9), val
, asds
);
3433 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__
,
3434 rtl931x_read_sds_phy(asds
, 0x24, 0x9), asds
);
3435 pr_info("%s: CMU mode %08X stored even SDS %d", __func__
,
3436 rtl931x_read_sds_phy(asds
& ~1, 0x20, 0x12), asds
& ~1);
3437 pr_info("%s: serdes_mode_ctrl %08X", __func__
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3438 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x24, 0x7));
3439 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x26, 0x7));
3440 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3441 pr_info("%s XSG page 0x0 0xe %08x\n", __func__
, rtl931x_read_sds_phy(dSds
, 0x0, 0xe));
3442 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__
, rtl931x_read_sds_phy(dSds
+ 1, 0x0, 0xe));
3444 model_info
= sw_r32(RTL93XX_MODEL_NAME_INFO
);
3445 if ((model_info
>> 4) & 0x1) {
3446 pr_info("detected chiptype 1\n");
3449 pr_info("detected chiptype 0\n");
3455 dSds
= (sds
- 1) * 2;
3457 pr_info("%s: 2.5gbit %08X dsds %d", __func__
,
3458 rtl931x_read_sds_phy(dSds
, 0x1, 0x14), dSds
);
3460 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__
, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
));
3461 ori
= sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3462 val
= ori
| (1 << sds
);
3463 sw_w32(val
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3466 case PHY_INTERFACE_MODE_NA
:
3469 case PHY_INTERFACE_MODE_XGMII
: // MII_XSGMII
3473 xsg_sdsid_1
= dSds
+ 1;
3475 rtl9310_sds_field_w(dSds
, 0x1, 0x1, 7, 4, 0xf);
3476 rtl9310_sds_field_w(dSds
, 0x1, 0x1, 3, 0, 0xf);
3478 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 0x1, 7, 4, 0xf);
3479 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 0x1, 3, 0, 0xf);
3483 rtl9310_sds_field_w(dSds
, 0x0, 0xE, 12, 12, 1);
3484 rtl9310_sds_field_w(dSds
+ 1, 0x0, 0xE, 12, 12, 1);
3487 case PHY_INTERFACE_MODE_USXGMII
: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:
3489 u32 op_code
= 0x6003;
3492 rtl9310_sds_field_w(asds
, 0x6, 0x2, 12, 12, 1);
3494 for (i
= 0; i
< sizeof(sds_config_10p3125g_type1
) / sizeof(sds_config
); ++i
) {
3495 rtl931x_write_sds_phy(asds
, sds_config_10p3125g_type1
[i
].page
- 0x4, sds_config_10p3125g_type1
[i
].reg
, sds_config_10p3125g_type1
[i
].data
);
3498 evenSds
= asds
- (asds
% 2);
3500 for (i
= 0; i
< sizeof(sds_config_10p3125g_cmu_type1
) / sizeof(sds_config
); ++i
) {
3501 rtl931x_write_sds_phy(evenSds
,
3502 sds_config_10p3125g_cmu_type1
[i
].page
- 0x4, sds_config_10p3125g_cmu_type1
[i
].reg
, sds_config_10p3125g_cmu_type1
[i
].data
);
3505 rtl9310_sds_field_w(asds
, 0x6, 0x2, 12, 12, 0);
3508 rtl9310_sds_field_w(asds
, 0x2e, 0xd, 6, 0, 0x0);
3509 rtl9310_sds_field_w(asds
, 0x2e, 0xd, 7, 7, 0x1);
3511 rtl9310_sds_field_w(asds
, 0x2e, 0x1c, 5, 0, 0x1E);
3512 rtl9310_sds_field_w(asds
, 0x2e, 0x1d, 11, 0, 0x00);
3513 rtl9310_sds_field_w(asds
, 0x2e, 0x1f, 11, 0, 0x00);
3514 rtl9310_sds_field_w(asds
, 0x2f, 0x0, 11, 0, 0x00);
3515 rtl9310_sds_field_w(asds
, 0x2f, 0x1, 11, 0, 0x00);
3517 rtl9310_sds_field_w(asds
, 0x2e, 0xf, 12, 6, 0x7F);
3518 rtl931x_write_sds_phy(asds
, 0x2f, 0x12, 0xaaa);
3520 rtl931x_sds_rx_rst(sds
);
3522 rtl931x_write_sds_phy(asds
, 0x7, 0x10, op_code
);
3523 rtl931x_write_sds_phy(asds
, 0x6, 0x1d, 0x0480);
3524 rtl931x_write_sds_phy(asds
, 0x6, 0xe, 0x0400);
3528 case PHY_INTERFACE_MODE_10GBASER
: // MII_10GR / MII_10GR1000BX_AUTO:
3529 // configure 10GR fiber mode=1
3530 rtl9310_sds_field_w(asds
, 0x1f, 0xb, 1, 1, 1);
3533 rtl9310_sds_field_w(dSds
, 0x3, 0x13, 15, 14, 0);
3535 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 12, 12, 1);
3536 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 6, 6, 1);
3537 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 13, 13, 0);
3540 rtl9310_sds_field_w(asds
, 0x1f, 13, 15, 0, 0x109e);
3541 rtl9310_sds_field_w(asds
, 0x1f, 0x6, 14, 10, 0x8);
3542 rtl9310_sds_field_w(asds
, 0x1f, 0x7, 10, 4, 0x7f);
3545 case PHY_INTERFACE_MODE_HSGMII
:
3546 rtl9310_sds_field_w(dSds
, 0x1, 0x14, 8, 8, 1);
3549 case PHY_INTERFACE_MODE_1000BASEX
: // MII_1000BX_FIBER
3550 rtl9310_sds_field_w(dSds
, 0x3, 0x13, 15, 14, 0);
3552 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 12, 12, 1);
3553 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 6, 6, 1);
3554 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 13, 13, 0);
3557 case PHY_INTERFACE_MODE_SGMII
:
3558 rtl9310_sds_field_w(asds
, 0x24, 0x9, 15, 15, 0);
3561 case PHY_INTERFACE_MODE_2500BASEX
:
3562 rtl9310_sds_field_w(dSds
, 0x1, 0x14, 8, 8, 1);
3565 case PHY_INTERFACE_MODE_QSGMII
:
3567 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3568 __func__
, phy_modes(mode
), sds
);
3572 rtl931x_cmu_type_set(asds
, mode
, chiptype
);
3574 if (sds
>= 2 && sds
<= 13) {
3576 rtl931x_write_sds_phy(asds
, 0x2E, 0x1, board_sds_tx_type1
[sds
- 2]);
3579 sw_w32(val
, RTL931X_CHIP_INFO_ADDR
);
3580 val
= sw_r32(RTL931X_CHIP_INFO_ADDR
);
3581 if (val
& BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))
3583 rtl931x_write_sds_phy(asds
, 0x2E, 0x1, board_sds_tx2
[sds
- 2]);
3585 rtl931x_write_sds_phy(asds
, 0x2E, 0x1, board_sds_tx
[sds
- 2]);
3588 sw_w32(val
, RTL931X_CHIP_INFO_ADDR
);
3592 val
= ori
& ~BIT(sds
);
3593 sw_w32(val
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3594 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__
, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
));
3596 if (mode
== PHY_INTERFACE_MODE_XGMII
|| mode
== PHY_INTERFACE_MODE_QSGMII
3597 || mode
== PHY_INTERFACE_MODE_HSGMII
|| mode
== PHY_INTERFACE_MODE_SGMII
3598 || mode
== PHY_INTERFACE_MODE_USXGMII
) {
3599 if (mode
== PHY_INTERFACE_MODE_XGMII
)
3600 rtl931x_sds_mii_mode_set(sds
, mode
);
3602 rtl931x_sds_fiber_mode_set(sds
, mode
);
3606 int rtl931x_sds_cmu_band_set(int sds
, bool enable
, u32 band
, phy_interface_t mode
)
3609 int page
= rtl931x_sds_cmu_page_get(mode
);
3613 asds
= rtl931x_get_analog_sds(sds
);
3617 rtl9310_sds_field_w(asds
, page
, 0x7, 13, 13, 0);
3618 rtl9310_sds_field_w(asds
, page
, 0x7, 11, 11, 0);
3620 rtl9310_sds_field_w(asds
, page
, 0x7, 13, 13, 0);
3621 rtl9310_sds_field_w(asds
, page
, 0x7, 11, 11, 0);
3624 rtl9310_sds_field_w(asds
, page
, 0x7, 4, 0, band
);
3626 rtl931x_sds_rst(sds
);
3631 int rtl931x_sds_cmu_band_get(int sds
, phy_interface_t mode
)
3633 int page
= rtl931x_sds_cmu_page_get(mode
);
3637 asds
= rtl931x_get_analog_sds(sds
);
3639 rtl931x_write_sds_phy(asds
, 0x1f, 0x02, 73);
3641 rtl9310_sds_field_w(asds
, page
, 0x5, 15, 15, 1);
3642 band
= rtl9310_sds_field_r(asds
, 0x1f, 0x15, 8, 3);
3643 pr_info("%s band is: %d\n", __func__
, band
);
3649 int rtl931x_link_sts_get(u32 sds
)
3651 u32 sts
, sts1
, latch_sts
, latch_sts1
;
3653 u32 xsg_sdsid_0
, xsg_sdsid_1
;
3655 xsg_sdsid_0
= sds
< 2 ? sds
: (sds
- 1) * 2;
3656 xsg_sdsid_1
= xsg_sdsid_0
+ 1;
3658 sts
= rtl9310_sds_field_r(xsg_sdsid_0
, 0x1, 29, 8, 0);
3659 sts1
= rtl9310_sds_field_r(xsg_sdsid_1
, 0x1, 29, 8, 0);
3660 latch_sts
= rtl9310_sds_field_r(xsg_sdsid_0
, 0x1, 30, 8, 0);
3661 latch_sts1
= rtl9310_sds_field_r(xsg_sdsid_1
, 0x1, 30, 8, 0);
3665 asds
= rtl931x_get_analog_sds(sds
);
3666 sts
= rtl9310_sds_field_r(asds
, 0x5, 0, 12, 12);
3667 latch_sts
= rtl9310_sds_field_r(asds
, 0x4, 1, 2, 2);
3669 dsds
= sds
< 2 ? sds
: (sds
- 1) * 2;
3670 latch_sts1
= rtl9310_sds_field_r(dsds
, 0x2, 1, 2, 2);
3671 sts1
= rtl9310_sds_field_r(dsds
, 0x2, 1, 2, 2);
3674 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__
,
3675 sds
, sts
, sts1
, latch_sts
, latch_sts1
);
3679 static int rtl8214fc_sfp_insert(void *upstream
, const struct sfp_eeprom_id
*id
)
3681 struct phy_device
*phydev
= upstream
;
3683 rtl8214fc_media_set(phydev
, true);
3688 static void rtl8214fc_sfp_remove(void *upstream
)
3690 struct phy_device
*phydev
= upstream
;
3692 rtl8214fc_media_set(phydev
, false);
3695 static const struct sfp_upstream_ops rtl8214fc_sfp_ops
= {
3696 .attach
= phy_sfp_attach
,
3697 .detach
= phy_sfp_detach
,
3698 .module_insert
= rtl8214fc_sfp_insert
,
3699 .module_remove
= rtl8214fc_sfp_remove
,
3702 static int rtl8214fc_phy_probe(struct phy_device
*phydev
)
3704 struct device
*dev
= &phydev
->mdio
.dev
;
3705 int addr
= phydev
->mdio
.addr
;
3708 /* 839x has internal SerDes */
3709 if (soc_info
.id
== 0x8393)
3712 /* All base addresses of the PHYs start at multiples of 8 */
3713 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3714 sizeof(struct rtl83xx_shared_private
));
3717 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3718 shared
->name
= "RTL8214FC";
3719 /* Configuration must be done while patching still possible */
3720 ret
= rtl8380_configure_rtl8214fc(phydev
);
3725 return phy_sfp_probe(phydev
, &rtl8214fc_sfp_ops
);
3728 static int rtl8214c_phy_probe(struct phy_device
*phydev
)
3730 struct device
*dev
= &phydev
->mdio
.dev
;
3731 int addr
= phydev
->mdio
.addr
;
3733 /* All base addresses of the PHYs start at multiples of 8 */
3734 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3735 sizeof(struct rtl83xx_shared_private
));
3738 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3739 shared
->name
= "RTL8214C";
3740 /* Configuration must be done whil patching still possible */
3741 return rtl8380_configure_rtl8214c(phydev
);
3746 static int rtl8218b_ext_phy_probe(struct phy_device
*phydev
)
3748 struct device
*dev
= &phydev
->mdio
.dev
;
3749 int addr
= phydev
->mdio
.addr
;
3751 /* All base addresses of the PHYs start at multiples of 8 */
3752 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3753 sizeof(struct rtl83xx_shared_private
));
3756 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3757 shared
->name
= "RTL8218B (external)";
3758 if (soc_info
.family
== RTL8380_FAMILY_ID
) {
3759 /* Configuration must be done while patching still possible */
3760 return rtl8380_configure_ext_rtl8218b(phydev
);
3767 static int rtl8218b_int_phy_probe(struct phy_device
*phydev
)
3769 struct device
*dev
= &phydev
->mdio
.dev
;
3770 int addr
= phydev
->mdio
.addr
;
3772 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
3777 pr_debug("%s: id: %d\n", __func__
, addr
);
3778 /* All base addresses of the PHYs start at multiples of 8 */
3779 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3780 sizeof(struct rtl83xx_shared_private
));
3783 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3784 shared
->name
= "RTL8218B (internal)";
3785 /* Configuration must be done while patching still possible */
3786 return rtl8380_configure_int_rtl8218b(phydev
);
3792 static int rtl8218d_phy_probe(struct phy_device
*phydev
)
3794 struct device
*dev
= &phydev
->mdio
.dev
;
3795 int addr
= phydev
->mdio
.addr
;
3797 pr_debug("%s: id: %d\n", __func__
, addr
);
3798 /* All base addresses of the PHYs start at multiples of 8 */
3799 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3800 sizeof(struct rtl83xx_shared_private
));
3802 /* All base addresses of the PHYs start at multiples of 8 */
3804 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3805 shared
->name
= "RTL8218D";
3806 /* Configuration must be done while patching still possible */
3807 // TODO: return configure_rtl8218d(phydev);
3812 static int rtl838x_serdes_probe(struct phy_device
*phydev
)
3814 int addr
= phydev
->mdio
.addr
;
3816 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
3821 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3822 if (soc_info
.id
== 0x8380) {
3824 return rtl8380_configure_serdes(phydev
);
3830 static int rtl8393_serdes_probe(struct phy_device
*phydev
)
3832 int addr
= phydev
->mdio
.addr
;
3834 pr_info("%s: id: %d\n", __func__
, addr
);
3835 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
3841 return rtl8390_configure_serdes(phydev
);
3844 static int rtl8390_serdes_probe(struct phy_device
*phydev
)
3846 int addr
= phydev
->mdio
.addr
;
3848 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
3854 return rtl8390_configure_generic(phydev
);
3857 static int rtl9300_serdes_probe(struct phy_device
*phydev
)
3859 if (soc_info
.family
!= RTL9300_FAMILY_ID
)
3862 phydev_info(phydev
, "Detected internal RTL9300 Serdes\n");
3864 return rtl9300_configure_serdes(phydev
);
3867 static struct phy_driver rtl83xx_phy_driver
[] = {
3869 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C
),
3870 .name
= "Realtek RTL8214C",
3871 .features
= PHY_GBIT_FEATURES
,
3872 .flags
= PHY_HAS_REALTEK_PAGES
,
3873 .match_phy_device
= rtl8214c_match_phy_device
,
3874 .probe
= rtl8214c_phy_probe
,
3875 .suspend
= genphy_suspend
,
3876 .resume
= genphy_resume
,
3877 .set_loopback
= genphy_loopback
,
3880 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
),
3881 .name
= "Realtek RTL8214FC",
3882 .features
= PHY_GBIT_FIBRE_FEATURES
,
3883 .flags
= PHY_HAS_REALTEK_PAGES
,
3884 .match_phy_device
= rtl8214fc_match_phy_device
,
3885 .probe
= rtl8214fc_phy_probe
,
3886 .suspend
= rtl8214fc_suspend
,
3887 .resume
= rtl8214fc_resume
,
3888 .set_loopback
= genphy_loopback
,
3889 .set_port
= rtl8214fc_set_port
,
3890 .get_port
= rtl8214fc_get_port
,
3891 .set_eee
= rtl8214fc_set_eee
,
3892 .get_eee
= rtl8214fc_get_eee
,
3895 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E
),
3896 .name
= "Realtek RTL8218B (external)",
3897 .features
= PHY_GBIT_FEATURES
,
3898 .flags
= PHY_HAS_REALTEK_PAGES
,
3899 .match_phy_device
= rtl8218b_ext_match_phy_device
,
3900 .probe
= rtl8218b_ext_phy_probe
,
3901 .suspend
= genphy_suspend
,
3902 .resume
= genphy_resume
,
3903 .set_loopback
= genphy_loopback
,
3904 .set_eee
= rtl8218b_set_eee
,
3905 .get_eee
= rtl8218b_get_eee
,
3908 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D
),
3909 .name
= "REALTEK RTL8218D",
3910 .features
= PHY_GBIT_FEATURES
,
3911 .flags
= PHY_HAS_REALTEK_PAGES
,
3912 .probe
= rtl8218d_phy_probe
,
3913 .suspend
= genphy_suspend
,
3914 .resume
= genphy_resume
,
3915 .set_loopback
= genphy_loopback
,
3916 .set_eee
= rtl8218d_set_eee
,
3917 .get_eee
= rtl8218d_get_eee
,
3920 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B
),
3921 .name
= "REALTEK RTL8221B",
3922 .features
= PHY_GBIT_FEATURES
,
3923 .flags
= PHY_HAS_REALTEK_PAGES
,
3924 .suspend
= genphy_suspend
,
3925 .resume
= genphy_resume
,
3926 .set_loopback
= genphy_loopback
,
3927 .read_page
= rtl8226_read_page
,
3928 .write_page
= rtl8226_write_page
,
3929 .read_status
= rtl8226_read_status
,
3930 .config_aneg
= rtl8226_config_aneg
,
3931 .set_eee
= rtl8226_set_eee
,
3932 .get_eee
= rtl8226_get_eee
,
3935 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226
),
3936 .name
= "REALTEK RTL8226",
3937 .features
= PHY_GBIT_FEATURES
,
3938 .flags
= PHY_HAS_REALTEK_PAGES
,
3939 .suspend
= genphy_suspend
,
3940 .resume
= genphy_resume
,
3941 .set_loopback
= genphy_loopback
,
3942 .read_page
= rtl8226_read_page
,
3943 .write_page
= rtl8226_write_page
,
3944 .read_status
= rtl8226_read_status
,
3945 .config_aneg
= rtl8226_config_aneg
,
3946 .set_eee
= rtl8226_set_eee
,
3947 .get_eee
= rtl8226_get_eee
,
3950 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
3951 .name
= "Realtek RTL8218B (internal)",
3952 .features
= PHY_GBIT_FEATURES
,
3953 .flags
= PHY_HAS_REALTEK_PAGES
,
3954 .probe
= rtl8218b_int_phy_probe
,
3955 .suspend
= genphy_suspend
,
3956 .resume
= genphy_resume
,
3957 .set_loopback
= genphy_loopback
,
3958 .set_eee
= rtl8218b_set_eee
,
3959 .get_eee
= rtl8218b_get_eee
,
3962 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
3963 .name
= "Realtek RTL8380 SERDES",
3964 .features
= PHY_GBIT_FIBRE_FEATURES
,
3965 .flags
= PHY_HAS_REALTEK_PAGES
,
3966 .probe
= rtl838x_serdes_probe
,
3967 .suspend
= genphy_suspend
,
3968 .resume
= genphy_resume
,
3969 .set_loopback
= genphy_loopback
,
3970 .read_status
= rtl8380_read_status
,
3973 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I
),
3974 .name
= "Realtek RTL8393 SERDES",
3975 .features
= PHY_GBIT_FIBRE_FEATURES
,
3976 .flags
= PHY_HAS_REALTEK_PAGES
,
3977 .probe
= rtl8393_serdes_probe
,
3978 .suspend
= genphy_suspend
,
3979 .resume
= genphy_resume
,
3980 .set_loopback
= genphy_loopback
,
3981 .read_status
= rtl8393_read_status
,
3984 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC
),
3985 .name
= "Realtek RTL8390 Generic",
3986 .features
= PHY_GBIT_FIBRE_FEATURES
,
3987 .flags
= PHY_HAS_REALTEK_PAGES
,
3988 .probe
= rtl8390_serdes_probe
,
3989 .suspend
= genphy_suspend
,
3990 .resume
= genphy_resume
,
3991 .set_loopback
= genphy_loopback
,
3994 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I
),
3995 .name
= "REALTEK RTL9300 SERDES",
3996 .features
= PHY_GBIT_FIBRE_FEATURES
,
3997 .flags
= PHY_HAS_REALTEK_PAGES
,
3998 .probe
= rtl9300_serdes_probe
,
3999 .suspend
= genphy_suspend
,
4000 .resume
= genphy_resume
,
4001 .set_loopback
= genphy_loopback
,
4002 .read_status
= rtl9300_read_status
,
4006 module_phy_driver(rtl83xx_phy_driver
);
4008 static struct mdio_device_id __maybe_unused rtl83xx_tbl
[] = {
4009 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
) },
4013 MODULE_DEVICE_TABLE(mdio
, rtl83xx_tbl
);
4015 MODULE_AUTHOR("B. Koblitz");
4016 MODULE_DESCRIPTION("RTL83xx PHY driver");
4017 MODULE_LICENSE("GPL");