1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
4 * Copyright (C) 2020 B. Koblitz
7 #include <linux/module.h>
8 #include <linux/delay.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
18 extern struct rtl83xx_soc_info soc_info
;
19 extern struct mutex smi_lock
;
22 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
23 * bus to detect e.g. link and media changes. For operations on the PHYs such as
24 * patching or other configuration changes such as EEE, polling needs to be disabled
25 * since otherwise these operations may fails or lead to unpredictable results.
27 DEFINE_MUTEX(poll_lock
);
29 static const struct firmware rtl838x_8380_fw
;
30 static const struct firmware rtl838x_8214fc_fw
;
31 static const struct firmware rtl838x_8218b_fw
;
33 int rtl838x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
34 int rtl838x_write_mmd_phy(u32 port
, u32 devnum
, u32 reg
, u32 val
);
35 int rtl839x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
36 int rtl839x_write_mmd_phy(u32 port
, u32 devnum
, u32 reg
, u32 val
);
37 int rtl930x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
38 int rtl930x_write_mmd_phy(u32 port
, u32 devnum
, u32 reg
, u32 val
);
39 int rtl931x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
40 int rtl931x_write_mmd_phy(u32 port
, u32 devnum
, u32 reg
, u32 val
);
42 static int read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
43 { switch (soc_info
.family
) {
44 case RTL8380_FAMILY_ID
:
45 return rtl838x_read_phy(port
, page
, reg
, val
);
46 case RTL8390_FAMILY_ID
:
47 return rtl839x_read_phy(port
, page
, reg
, val
);
48 case RTL9300_FAMILY_ID
:
49 return rtl930x_read_phy(port
, page
, reg
, val
);
50 case RTL9310_FAMILY_ID
:
51 return rtl931x_read_phy(port
, page
, reg
, val
);
56 static int write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
58 switch (soc_info
.family
) {
59 case RTL8380_FAMILY_ID
:
60 return rtl838x_write_phy(port
, page
, reg
, val
);
61 case RTL8390_FAMILY_ID
:
62 return rtl839x_write_phy(port
, page
, reg
, val
);
63 case RTL9300_FAMILY_ID
:
64 return rtl930x_write_phy(port
, page
, reg
, val
);
65 case RTL9310_FAMILY_ID
:
66 return rtl931x_write_phy(port
, page
, reg
, val
);
71 static int read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
73 switch (soc_info
.family
) {
74 case RTL8380_FAMILY_ID
:
75 return rtl838x_read_mmd_phy(port
, devnum
, regnum
, val
);
76 case RTL8390_FAMILY_ID
:
77 return rtl839x_read_mmd_phy(port
, devnum
, regnum
, val
);
78 case RTL9300_FAMILY_ID
:
79 return rtl930x_read_mmd_phy(port
, devnum
, regnum
, val
);
80 case RTL9310_FAMILY_ID
:
81 return rtl931x_read_mmd_phy(port
, devnum
, regnum
, val
);
86 int write_mmd_phy(u32 port
, u32 devnum
, u32 reg
, u32 val
)
88 switch (soc_info
.family
) {
89 case RTL8380_FAMILY_ID
:
90 return rtl838x_write_mmd_phy(port
, devnum
, reg
, val
);
91 case RTL8390_FAMILY_ID
:
92 return rtl839x_write_mmd_phy(port
, devnum
, reg
, val
);
93 case RTL9300_FAMILY_ID
:
94 return rtl930x_write_mmd_phy(port
, devnum
, reg
, val
);
95 case RTL9310_FAMILY_ID
:
96 return rtl931x_write_mmd_phy(port
, devnum
, reg
, val
);
101 static u64
disable_polling(int port
)
105 mutex_lock(&poll_lock
);
107 switch (soc_info
.family
) {
108 case RTL8380_FAMILY_ID
:
109 saved_state
= sw_r32(RTL838X_SMI_POLL_CTRL
);
110 sw_w32_mask(BIT(port
), 0, RTL838X_SMI_POLL_CTRL
);
112 case RTL8390_FAMILY_ID
:
113 saved_state
= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
115 saved_state
|= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL
);
116 sw_w32_mask(BIT(port
% 32), 0,
117 RTL839X_SMI_PORT_POLLING_CTRL
+ ((port
>> 5) << 2));
119 case RTL9300_FAMILY_ID
:
120 saved_state
= sw_r32(RTL930X_SMI_POLL_CTRL
);
121 sw_w32_mask(BIT(port
), 0, RTL930X_SMI_POLL_CTRL
);
123 case RTL9310_FAMILY_ID
:
124 pr_warn("%s not implemented for RTL931X\n", __func__
);
128 mutex_unlock(&poll_lock
);
133 static int resume_polling(u64 saved_state
)
135 mutex_lock(&poll_lock
);
137 switch (soc_info
.family
) {
138 case RTL8380_FAMILY_ID
:
139 sw_w32(saved_state
, RTL838X_SMI_POLL_CTRL
);
141 case RTL8390_FAMILY_ID
:
142 sw_w32(saved_state
>> 32, RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
143 sw_w32(saved_state
, RTL839X_SMI_PORT_POLLING_CTRL
);
145 case RTL9300_FAMILY_ID
:
146 sw_w32(saved_state
, RTL930X_SMI_POLL_CTRL
);
148 case RTL9310_FAMILY_ID
:
149 pr_warn("%s not implemented for RTL931X\n", __func__
);
153 mutex_unlock(&poll_lock
);
158 static void rtl8380_int_phy_on_off(int mac
, bool on
)
162 read_phy(mac
, 0, 0, &val
);
164 write_phy(mac
, 0, 0, val
& ~BIT(11));
166 write_phy(mac
, 0, 0, val
| BIT(11));
169 static void rtl8380_rtl8214fc_on_off(int mac
, bool on
)
174 write_phy(mac
, 4095, 30, 3);
175 read_phy(mac
, 0, 16, &val
);
177 write_phy(mac
, 0, 16, val
& ~BIT(11));
179 write_phy(mac
, 0, 16, val
| BIT(11));
182 write_phy(mac
, 4095, 30, 1);
183 read_phy(mac
, 0, 16, &val
);
185 write_phy(mac
, 0xa40, 16, val
& ~BIT(11));
187 write_phy(mac
, 0xa40, 16, val
| BIT(11));
190 static void rtl8380_phy_reset(int mac
)
194 read_phy(mac
, 0, 0, &val
);
195 write_phy(mac
, 0, 0, val
| BIT(15));
199 * Reset the SerDes by powering it off and set a new operations mode
200 * of the SerDes. 0x1f is off. Other modes are
201 * 0x01: QSGMII 0x04: 1000BX_FIBER 0x05: FIBER100
202 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
203 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
204 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
205 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
207 void rtl9300_sds_rst(int sds_num
, u32 mode
)
209 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
210 u16 regs
[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
211 0x02A4, 0x02A4, 0x0198, 0x0198 };
212 u8 lsb
[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
214 pr_info("SerDes: %s %d\n", __func__
, mode
);
215 if (sds_num
< 0 || sds_num
> 11) {
216 pr_err("Wrong SerDes number: %d\n", sds_num
);
220 sw_w32_mask(0x1f << lsb
[sds_num
], 0x1f << lsb
[sds_num
], regs
[sds_num
]);
223 sw_w32_mask(0x1f << lsb
[sds_num
], mode
<< lsb
[sds_num
], regs
[sds_num
]);
226 pr_info("SDS: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n",
227 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
231 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
232 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
234 int rtl839x_read_sds_phy(int phy_addr
, int phy_reg
)
244 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
245 * which would otherwise read as 0.
247 if (soc_info
.id
== 0x8393) {
255 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
256 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
257 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
258 * one 32 bit register.
260 reg
= (phy_reg
<< 1) & 0xfc;
261 val
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
264 val
= (val
>> 16) & 0xffff;
271 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
272 * register which simulates commands to an internal MDIO bus.
274 int rtl930x_read_sds_phy(int phy_addr
, int page
, int phy_reg
)
277 u32 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 1;
279 pr_info("%s: phy_addr %d, phy_reg: %d\n", __func__
, phy_addr
, phy_reg
);
280 sw_w32(cmd
, RTL930X_SDS_INDACS_CMD
);
282 for (i
= 0; i
< 100; i
++) {
283 if (!(sw_r32(RTL930X_SDS_INDACS_CMD
) & 0x1))
291 pr_info("%s: returning %04x\n", __func__
, sw_r32(RTL930X_SDS_INDACS_DATA
) & 0xffff);
292 return sw_r32(RTL930X_SDS_INDACS_DATA
) & 0xffff;
295 int rtl930x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
)
300 sw_w32(v
, RTL930X_SDS_INDACS_DATA
);
301 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 0x3;
303 for (i
= 0; i
< 100; i
++) {
304 if (!(sw_r32(RTL930X_SDS_INDACS_CMD
) & 0x1))
316 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
317 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
318 * in a standard page 0 of a PHY
320 int rtl838x_read_sds_phy(int phy_addr
, int phy_reg
)
327 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
332 int rtl839x_write_sds_phy(int phy_addr
, int phy_reg
, u16 v
)
341 reg
= (phy_reg
<< 1) & 0xfc;
345 sw_w32_mask(0xffff0000, val
,
346 RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
348 sw_w32_mask(0xffff, val
,
349 RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
355 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
356 * ports of the RTL838x SoCs
358 static int rtl8380_read_status(struct phy_device
*phydev
)
362 err
= genphy_read_status(phydev
);
365 phydev
->speed
= SPEED_1000
;
366 phydev
->duplex
= DUPLEX_FULL
;
372 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
373 * ports of the RTL8393 SoC
375 static int rtl8393_read_status(struct phy_device
*phydev
)
379 int phy_addr
= phydev
->mdio
.addr
;
382 err
= genphy_read_status(phydev
);
387 phydev
->speed
= SPEED_100
;
388 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
391 v
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80);
392 if (!(v
& (1 << 13)) && (v
& (1 << 6)))
393 phydev
->speed
= SPEED_1000
;
394 phydev
->duplex
= DUPLEX_FULL
;
400 static int rtl8226_read_page(struct phy_device
*phydev
)
402 return __phy_read(phydev
, 0x1f);
405 static int rtl8226_write_page(struct phy_device
*phydev
, int page
)
407 return __phy_write(phydev
, 0x1f, page
);
410 static int rtl8226_read_status(struct phy_device
*phydev
)
414 int port
= phydev
->mdio
.addr
;
416 // TODO: ret = genphy_read_status(phydev);
418 // pr_info("%s: genphy_read_status failed\n", __func__);
422 // Link status must be read twice
423 for (i
= 0; i
< 2; i
++) {
424 read_mmd_phy(port
, MMD_VEND2
, 0xA402, &val
);
426 phydev
->link
= val
& BIT(2) ? 1 : 0;
430 // Read duplex status
431 ret
= read_mmd_phy(port
, MMD_VEND2
, 0xA434, &val
);
434 phydev
->duplex
= !!(val
& BIT(3));
437 ret
= read_mmd_phy(port
, MMD_VEND2
, 0xA434, &val
);
438 switch (val
& 0x0630) {
440 phydev
->speed
= SPEED_10
;
443 phydev
->speed
= SPEED_100
;
446 phydev
->speed
= SPEED_1000
;
449 phydev
->speed
= SPEED_10000
;
452 phydev
->speed
= SPEED_2500
;
455 phydev
->speed
= SPEED_5000
;
464 static int rtl8226_advertise_aneg(struct phy_device
*phydev
)
468 int port
= phydev
->mdio
.addr
;
470 pr_info("In %s\n", __func__
);
472 ret
= read_mmd_phy(port
, MMD_AN
, 16, &v
);
476 v
|= BIT(5); // HD 10M
477 v
|= BIT(6); // FD 10M
478 v
|= BIT(7); // HD 100M
479 v
|= BIT(8); // FD 100M
481 ret
= write_mmd_phy(port
, MMD_AN
, 16, v
);
484 ret
= read_mmd_phy(port
, MMD_VEND2
, 0xA412, &v
);
487 v
|= BIT(9); // FD 1000M
489 ret
= write_mmd_phy(port
, MMD_VEND2
, 0xA412, v
);
494 ret
= read_mmd_phy(port
, MMD_AN
, 32, &v
);
499 ret
= write_mmd_phy(port
, MMD_AN
, 32, v
);
505 static int rtl8226_config_aneg(struct phy_device
*phydev
)
509 int port
= phydev
->mdio
.addr
;
511 pr_info("In %s\n", __func__
);
512 if (phydev
->autoneg
== AUTONEG_ENABLE
) {
513 ret
= rtl8226_advertise_aneg(phydev
);
516 // AutoNegotiationEnable
517 ret
= read_mmd_phy(port
, MMD_AN
, 0, &v
);
521 v
|= BIT(12); // Enable AN
522 ret
= write_mmd_phy(port
, MMD_AN
, 0, v
);
526 // RestartAutoNegotiation
527 ret
= read_mmd_phy(port
, MMD_VEND2
, 0xA400, &v
);
532 ret
= write_mmd_phy(port
, MMD_VEND2
, 0xA400, v
);
535 pr_info("%s: Ret is already: %d\n", __func__
, ret
);
536 // TODO: ret = __genphy_config_aneg(phydev, ret);
539 pr_info("%s: And ret is now: %d\n", __func__
, ret
);
543 static int rtl8226_get_eee(struct phy_device
*phydev
,
544 struct ethtool_eee
*e
)
547 int addr
= phydev
->mdio
.addr
;
549 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
551 read_mmd_phy(addr
, MMD_AN
, 60, &val
);
552 if (e
->eee_enabled
) {
553 e
->eee_enabled
= !!(val
& BIT(1));
554 if (!e
->eee_enabled
) {
555 read_mmd_phy(addr
, MMD_AN
, 62, &val
);
556 e
->eee_enabled
= !!(val
& BIT(0));
559 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
564 static int rtl8226_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
566 int port
= phydev
->mdio
.addr
;
571 pr_info("In %s, port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
573 poll_state
= disable_polling(port
);
575 // Remember aneg state
576 read_mmd_phy(port
, MMD_AN
, 0, &val
);
577 an_enabled
= !!(val
& BIT(12));
579 // Setup 100/1000MBit
580 read_mmd_phy(port
, MMD_AN
, 60, &val
);
585 write_mmd_phy(port
, MMD_AN
, 60, val
);
588 read_mmd_phy(port
, MMD_AN
, 62, &val
);
593 write_mmd_phy(port
, MMD_AN
, 62, val
);
595 // RestartAutoNegotiation
596 read_mmd_phy(port
, MMD_VEND2
, 0xA400, &val
);
598 write_mmd_phy(port
, MMD_VEND2
, 0xA400, val
);
600 resume_polling(poll_state
);
605 static struct fw_header
*rtl838x_request_fw(struct phy_device
*phydev
,
606 const struct firmware
*fw
,
609 struct device
*dev
= &phydev
->mdio
.dev
;
612 uint32_t checksum
, my_checksum
;
614 err
= request_firmware(&fw
, name
, dev
);
618 if (fw
->size
< sizeof(struct fw_header
)) {
619 pr_err("Firmware size too small.\n");
624 h
= (struct fw_header
*) fw
->data
;
625 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw
->size
, h
->magic
);
627 if (h
->magic
!= 0x83808380) {
628 pr_err("Wrong firmware file: MAGIC mismatch.\n");
632 checksum
= h
->checksum
;
634 my_checksum
= ~crc32(0xFFFFFFFFU
, fw
->data
, fw
->size
);
635 if (checksum
!= my_checksum
) {
636 pr_err("Firmware checksum mismatch.\n");
640 h
->checksum
= checksum
;
644 dev_err(dev
, "Unable to load firmware %s (%d)\n", name
, err
);
648 static int rtl8390_configure_generic(struct phy_device
*phydev
)
651 int mac
= phydev
->mdio
.addr
;
653 read_phy(mac
, 0, 2, &val
);
655 read_phy(mac
, 0, 3, &val
);
657 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
659 /* Read internal PHY ID */
660 write_phy(mac
, 31, 27, 0x0002);
661 read_phy(mac
, 31, 28, &val
);
663 /* Internal RTL8218B, version 2 */
664 phydev_info(phydev
, "Detected unknown %x\n", val
);
668 static int rtl8380_configure_int_rtl8218b(struct phy_device
*phydev
)
672 int mac
= phydev
->mdio
.addr
;
674 u32
*rtl838x_6275B_intPhy_perport
;
675 u32
*rtl8218b_6276B_hwEsd_perport
;
678 read_phy(mac
, 0, 2, &val
);
680 read_phy(mac
, 0, 3, &val
);
682 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
684 /* Read internal PHY ID */
685 write_phy(mac
, 31, 27, 0x0002);
686 read_phy(mac
, 31, 28, &val
);
688 phydev_err(phydev
, "Expected internal RTL8218B, found PHY-ID %x\n", val
);
692 /* Internal RTL8218B, version 2 */
693 phydev_info(phydev
, "Detected internal RTL8218B\n");
695 h
= rtl838x_request_fw(phydev
, &rtl838x_8380_fw
, FIRMWARE_838X_8380_1
);
699 if (h
->phy
!= 0x83800000) {
700 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
704 rtl838x_6275B_intPhy_perport
= (void *)h
+ sizeof(struct fw_header
)
707 rtl8218b_6276B_hwEsd_perport
= (void *)h
+ sizeof(struct fw_header
)
710 if (sw_r32(RTL838X_DMY_REG31
) == 0x1)
713 read_phy(mac
, 0, 0, &val
);
715 rtl8380_int_phy_on_off(mac
, true);
717 rtl8380_phy_reset(mac
);
720 /* Ready PHY for patch */
721 for (p
= 0; p
< 8; p
++) {
722 write_phy(mac
+ p
, 0xfff, 0x1f, 0x0b82);
723 write_phy(mac
+ p
, 0xfff, 0x10, 0x0010);
726 for (p
= 0; p
< 8; p
++) {
727 for (i
= 0; i
< 100 ; i
++) {
728 read_phy(mac
+ p
, 0x0b80, 0x10, &val
);
734 "ERROR: Port %d not ready for patch.\n",
739 for (p
= 0; p
< 8; p
++) {
741 while (rtl838x_6275B_intPhy_perport
[i
* 2]) {
742 write_phy(mac
+ p
, 0xfff,
743 rtl838x_6275B_intPhy_perport
[i
* 2],
744 rtl838x_6275B_intPhy_perport
[i
* 2 + 1]);
748 while (rtl8218b_6276B_hwEsd_perport
[i
* 2]) {
749 write_phy(mac
+ p
, 0xfff,
750 rtl8218b_6276B_hwEsd_perport
[i
* 2],
751 rtl8218b_6276B_hwEsd_perport
[i
* 2 + 1]);
758 static int rtl8380_configure_ext_rtl8218b(struct phy_device
*phydev
)
760 u32 val
, ipd
, phy_id
;
762 int mac
= phydev
->mdio
.addr
;
764 u32
*rtl8380_rtl8218b_perchip
;
765 u32
*rtl8218B_6276B_rtl8380_perport
;
766 u32
*rtl8380_rtl8218b_perport
;
768 if (soc_info
.family
== RTL8380_FAMILY_ID
&& mac
!= 0 && mac
!= 16) {
769 phydev_err(phydev
, "External RTL8218B must have PHY-IDs 0 or 16!\n");
772 read_phy(mac
, 0, 2, &val
);
774 read_phy(mac
, 0, 3, &val
);
776 pr_info("Phy on MAC %d: %x\n", mac
, phy_id
);
778 /* Read internal PHY ID */
779 write_phy(mac
, 31, 27, 0x0002);
780 read_phy(mac
, 31, 28, &val
);
782 phydev_err(phydev
, "Expected external RTL8218B, found PHY-ID %x\n", val
);
785 phydev_info(phydev
, "Detected external RTL8218B\n");
787 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8218b_1
);
791 if (h
->phy
!= 0x8218b000) {
792 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
796 rtl8380_rtl8218b_perchip
= (void *)h
+ sizeof(struct fw_header
)
799 rtl8218B_6276B_rtl8380_perport
= (void *)h
+ sizeof(struct fw_header
)
802 rtl8380_rtl8218b_perport
= (void *)h
+ sizeof(struct fw_header
)
805 read_phy(mac
, 0, 0, &val
);
807 rtl8380_int_phy_on_off(mac
, true);
809 rtl8380_phy_reset(mac
);
812 /* Get Chip revision */
813 write_phy(mac
, 0xfff, 0x1f, 0x0);
814 write_phy(mac
, 0xfff, 0x1b, 0x4);
815 read_phy(mac
, 0xfff, 0x1c, &val
);
818 while (rtl8380_rtl8218b_perchip
[i
* 3]
819 && rtl8380_rtl8218b_perchip
[i
* 3 + 1]) {
820 write_phy(mac
+ rtl8380_rtl8218b_perchip
[i
* 3],
821 0xfff, rtl8380_rtl8218b_perchip
[i
* 3 + 1],
822 rtl8380_rtl8218b_perchip
[i
* 3 + 2]);
827 for (i
= 0; i
< 8; i
++) {
828 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
829 write_phy(mac
+ i
, 0xfff, 0x00, 0x1140);
834 for (i
= 0; i
< 8; i
++) {
835 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0b82);
836 write_phy(mac
+ i
, 0xfff, 0x10, 0x0010);
840 /* Verify patch readiness */
841 for (i
= 0; i
< 8; i
++) {
842 for (l
= 0; l
< 100; l
++) {
843 read_phy(mac
+ i
, 0xb80, 0x10, &val
);
848 phydev_err(phydev
, "Could not patch PHY\n");
853 /* Use Broadcast ID method for patching */
854 write_phy(mac
, 0xfff, 0x1f, 0x0000);
855 write_phy(mac
, 0xfff, 0x1d, 0x0008);
856 write_phy(mac
, 0xfff, 0x1f, 0x0266);
857 write_phy(mac
, 0xfff, 0x16, 0xff00 + mac
);
858 write_phy(mac
, 0xfff, 0x1f, 0x0000);
859 write_phy(mac
, 0xfff, 0x1d, 0x0000);
862 write_phy(mac
, 0xfff, 30, 8);
863 write_phy(mac
, 0x26e, 17, 0xb);
864 write_phy(mac
, 0x26e, 16, 0x2);
866 read_phy(mac
, 0x26e, 19, &ipd
);
867 write_phy(mac
, 0, 30, 0);
868 ipd
= (ipd
>> 4) & 0xf;
871 while (rtl8218B_6276B_rtl8380_perport
[i
* 2]) {
872 write_phy(mac
, 0xfff, rtl8218B_6276B_rtl8380_perport
[i
* 2],
873 rtl8218B_6276B_rtl8380_perport
[i
* 2 + 1]);
877 /*Disable broadcast ID*/
878 write_phy(mac
, 0xfff, 0x1f, 0x0000);
879 write_phy(mac
, 0xfff, 0x1d, 0x0008);
880 write_phy(mac
, 0xfff, 0x1f, 0x0266);
881 write_phy(mac
, 0xfff, 0x16, 0x00 + mac
);
882 write_phy(mac
, 0xfff, 0x1f, 0x0000);
883 write_phy(mac
, 0xfff, 0x1d, 0x0000);
889 static int rtl8218b_ext_match_phy_device(struct phy_device
*phydev
)
891 int addr
= phydev
->mdio
.addr
;
893 /* Both the RTL8214FC and the external RTL8218B have the same
894 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
895 * at PHY IDs 0-7, while the RTL8214FC must be attached via
896 * the pair of SGMII/1000Base-X with higher PHY-IDs
898 if (soc_info
.family
== RTL8380_FAMILY_ID
)
899 return phydev
->phy_id
== PHY_ID_RTL8218B_E
&& addr
< 8;
901 return phydev
->phy_id
== PHY_ID_RTL8218B_E
;
904 static int rtl8218b_read_mmd(struct phy_device
*phydev
,
905 int devnum
, u16 regnum
)
909 int addr
= phydev
->mdio
.addr
;
911 ret
= read_mmd_phy(addr
, devnum
, regnum
, &val
);
917 static int rtl8218b_write_mmd(struct phy_device
*phydev
,
918 int devnum
, u16 regnum
, u16 val
)
920 int addr
= phydev
->mdio
.addr
;
922 return rtl838x_write_mmd_phy(addr
, devnum
, regnum
, val
);
925 static int rtl8226_read_mmd(struct phy_device
*phydev
, int devnum
, u16 regnum
)
927 int port
= phydev
->mdio
.addr
; // the SoC translates port addresses to PHY addr
931 err
= read_mmd_phy(port
, devnum
, regnum
, &val
);
937 static int rtl8226_write_mmd(struct phy_device
*phydev
, int devnum
, u16 regnum
, u16 val
)
939 int port
= phydev
->mdio
.addr
; // the SoC translates port addresses to PHY addr
941 return write_mmd_phy(port
, devnum
, regnum
, val
);
944 static void rtl8380_rtl8214fc_media_set(int mac
, bool set_fibre
)
946 int base
= mac
- (mac
% 4);
947 static int reg
[] = {16, 19, 20, 21};
948 int val
, media
, power
;
950 pr_info("%s: port %d, set_fibre: %d\n", __func__
, mac
, set_fibre
);
951 write_phy(base
, 0xfff, 29, 8);
952 read_phy(base
, 0x266, reg
[mac
% 4], &val
);
954 media
= (val
>> 10) & 0x3;
955 pr_info("Current media %x\n", media
);
957 pr_info("Powering off COPPER\n");
958 write_phy(base
, 0xfff, 29, 1);
959 /* Ensure power is off */
960 read_phy(base
, 0xa40, 16, &power
);
961 if (!(power
& (1 << 11)))
962 write_phy(base
, 0xa40, 16, power
| (1 << 11));
964 pr_info("Powering off FIBRE");
965 write_phy(base
, 0xfff, 29, 3);
966 /* Ensure power is off */
967 read_phy(base
, 0xa40, 16, &power
);
968 if (!(power
& (1 << 11)))
969 write_phy(base
, 0xa40, 16, power
| (1 << 11));
979 write_phy(base
, 0xfff, 29, 8);
980 write_phy(base
, 0x266, reg
[mac
% 4], val
);
981 write_phy(base
, 0xfff, 29, 0);
984 pr_info("Powering on FIBRE");
985 write_phy(base
, 0xfff, 29, 3);
986 /* Ensure power is off */
987 read_phy(base
, 0xa40, 16, &power
);
988 if (power
& (1 << 11))
989 write_phy(base
, 0xa40, 16, power
& ~(1 << 11));
991 pr_info("Powering on COPPER\n");
992 write_phy(base
, 0xfff, 29, 1);
993 /* Ensure power is off */
994 read_phy(base
, 0xa40, 16, &power
);
995 if (power
& (1 << 11))
996 write_phy(base
, 0xa40, 16, power
& ~(1 << 11));
999 write_phy(base
, 0xfff, 29, 0);
1002 static bool rtl8380_rtl8214fc_media_is_fibre(int mac
)
1004 int base
= mac
- (mac
% 4);
1005 static int reg
[] = {16, 19, 20, 21};
1008 write_phy(base
, 0xfff, 29, 8);
1009 read_phy(base
, 0x266, reg
[mac
% 4], &val
);
1010 write_phy(base
, 0xfff, 29, 0);
1011 if (val
& (1 << 11))
1016 static int rtl8214fc_set_port(struct phy_device
*phydev
, int port
)
1018 bool is_fibre
= (port
== PORT_FIBRE
? true : false);
1019 int addr
= phydev
->mdio
.addr
;
1021 pr_debug("%s port %d to %d\n", __func__
, addr
, port
);
1023 rtl8380_rtl8214fc_media_set(addr
, is_fibre
);
1027 static int rtl8214fc_get_port(struct phy_device
*phydev
)
1029 int addr
= phydev
->mdio
.addr
;
1031 pr_debug("%s: port %d\n", __func__
, addr
);
1032 if (rtl8380_rtl8214fc_media_is_fibre(addr
))
1038 * Enable EEE on the RTL8218B PHYs
1039 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1040 * but the only way that works since the kernel first enables EEE in the MAC
1041 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1043 void rtl8218d_eee_set(int port
, bool enable
)
1048 pr_debug("In %s %d, enable %d\n", __func__
, port
, enable
);
1049 /* Set GPHY page to copper */
1050 write_phy(port
, 0xa42, 30, 0x0001);
1052 read_phy(port
, 0, 0, &val
);
1053 an_enabled
= val
& BIT(12);
1055 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1056 read_mmd_phy(port
, 7, 60, &val
);
1057 val
|= BIT(2) | BIT(1);
1058 write_mmd_phy(port
, 7, 60, enable
? 0x6 : 0);
1060 /* 500M EEE ability */
1061 read_phy(port
, 0xa42, 20, &val
);
1066 write_phy(port
, 0xa42, 20, val
);
1068 /* Restart AN if enabled */
1070 read_phy(port
, 0, 0, &val
);
1072 write_phy(port
, 0, 0, val
);
1075 /* GPHY page back to auto*/
1076 write_phy(port
, 0xa42, 30, 0);
1079 static int rtl8218b_get_eee(struct phy_device
*phydev
,
1080 struct ethtool_eee
*e
)
1083 int addr
= phydev
->mdio
.addr
;
1085 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
1087 /* Set GPHY page to copper */
1088 write_phy(addr
, 0xa42, 29, 0x0001);
1090 read_phy(addr
, 7, 60, &val
);
1091 if (e
->eee_enabled
) {
1092 // Verify vs MAC-based EEE
1093 e
->eee_enabled
= !!(val
& BIT(7));
1094 if (!e
->eee_enabled
) {
1095 read_phy(addr
, 0x0A43, 25, &val
);
1096 e
->eee_enabled
= !!(val
& BIT(4));
1099 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
1101 /* GPHY page to auto */
1102 write_phy(addr
, 0xa42, 29, 0x0000);
1107 static int rtl8218d_get_eee(struct phy_device
*phydev
,
1108 struct ethtool_eee
*e
)
1111 int addr
= phydev
->mdio
.addr
;
1113 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
1115 /* Set GPHY page to copper */
1116 write_phy(addr
, 0xa42, 30, 0x0001);
1118 read_phy(addr
, 7, 60, &val
);
1120 e
->eee_enabled
= !!(val
& BIT(7));
1121 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
1123 /* GPHY page to auto */
1124 write_phy(addr
, 0xa42, 30, 0x0000);
1129 static int rtl8214fc_set_eee(struct phy_device
*phydev
,
1130 struct ethtool_eee
*e
)
1133 int port
= phydev
->mdio
.addr
;
1137 pr_debug("In %s port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
1139 if (rtl8380_rtl8214fc_media_is_fibre(port
)) {
1140 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", port
);
1144 poll_state
= disable_polling(port
);
1146 /* Set GPHY page to copper */
1147 write_phy(port
, 0xa42, 29, 0x0001);
1149 // Get auto-negotiation status
1150 read_phy(port
, 0, 0, &val
);
1151 an_enabled
= val
& BIT(12);
1153 pr_info("%s: aneg: %d\n", __func__
, an_enabled
);
1154 read_phy(port
, 0x0A43, 25, &val
);
1155 val
&= ~BIT(5); // Use MAC-based EEE
1156 write_phy(port
, 0x0A43, 25, val
);
1158 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1159 write_phy(port
, 7, 60, e
->eee_enabled
? 0x6 : 0);
1161 /* 500M EEE ability */
1162 read_phy(port
, 0xa42, 20, &val
);
1167 write_phy(port
, 0xa42, 20, val
);
1169 /* Restart AN if enabled */
1171 pr_info("%s: doing aneg\n", __func__
);
1172 read_phy(port
, 0, 0, &val
);
1174 write_phy(port
, 0, 0, val
);
1177 /* GPHY page back to auto*/
1178 write_phy(port
, 0xa42, 29, 0);
1180 resume_polling(poll_state
);
1185 static int rtl8214fc_get_eee(struct phy_device
*phydev
,
1186 struct ethtool_eee
*e
)
1188 int addr
= phydev
->mdio
.addr
;
1190 pr_debug("In %s port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
1191 if (rtl8380_rtl8214fc_media_is_fibre(addr
)) {
1192 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", addr
);
1196 return rtl8218b_get_eee(phydev
, e
);
1199 static int rtl8218b_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
1201 int port
= phydev
->mdio
.addr
;
1206 pr_info("In %s, port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
1208 poll_state
= disable_polling(port
);
1210 /* Set GPHY page to copper */
1211 write_phy(port
, 0, 30, 0x0001);
1212 read_phy(port
, 0, 0, &val
);
1213 an_enabled
= val
& BIT(12);
1215 if (e
->eee_enabled
) {
1216 /* 100/1000M EEE Capability */
1217 write_phy(port
, 0, 13, 0x0007);
1218 write_phy(port
, 0, 14, 0x003C);
1219 write_phy(port
, 0, 13, 0x4007);
1220 write_phy(port
, 0, 14, 0x0006);
1222 read_phy(port
, 0x0A43, 25, &val
);
1224 write_phy(port
, 0x0A43, 25, val
);
1226 /* 100/1000M EEE Capability */
1227 write_phy(port
, 0, 13, 0x0007);
1228 write_phy(port
, 0, 14, 0x003C);
1229 write_phy(port
, 0, 13, 0x0007);
1230 write_phy(port
, 0, 14, 0x0000);
1232 read_phy(port
, 0x0A43, 25, &val
);
1234 write_phy(port
, 0x0A43, 25, val
);
1237 /* Restart AN if enabled */
1239 read_phy(port
, 0, 0, &val
);
1241 write_phy(port
, 0, 0, val
);
1244 /* GPHY page back to auto*/
1245 write_phy(port
, 0xa42, 30, 0);
1247 pr_info("%s done\n", __func__
);
1248 resume_polling(poll_state
);
1253 static int rtl8218d_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
1255 int addr
= phydev
->mdio
.addr
;
1258 pr_info("In %s, port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
1260 poll_state
= disable_polling(addr
);
1262 rtl8218d_eee_set(addr
, (bool) e
->eee_enabled
);
1264 resume_polling(poll_state
);
1269 static int rtl8214c_match_phy_device(struct phy_device
*phydev
)
1271 return phydev
->phy_id
== PHY_ID_RTL8214C
;
1274 static int rtl8380_configure_rtl8214c(struct phy_device
*phydev
)
1277 int mac
= phydev
->mdio
.addr
;
1279 read_phy(mac
, 0, 2, &val
);
1281 read_phy(mac
, 0, 3, &val
);
1283 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
1285 phydev_info(phydev
, "Detected external RTL8214C\n");
1287 /* GPHY auto conf */
1288 write_phy(mac
, 0xa42, 29, 0);
1292 static int rtl8380_configure_rtl8214fc(struct phy_device
*phydev
)
1294 u32 phy_id
, val
, page
= 0;
1296 int mac
= phydev
->mdio
.addr
;
1297 struct fw_header
*h
;
1298 u32
*rtl8380_rtl8214fc_perchip
;
1299 u32
*rtl8380_rtl8214fc_perport
;
1301 read_phy(mac
, 0, 2, &val
);
1303 read_phy(mac
, 0, 3, &val
);
1305 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
1307 /* Read internal PHY id */
1308 write_phy(mac
, 0, 30, 0x0001);
1309 write_phy(mac
, 0, 31, 0x0a42);
1310 write_phy(mac
, 31, 27, 0x0002);
1311 read_phy(mac
, 31, 28, &val
);
1312 if (val
!= 0x6276) {
1313 phydev_err(phydev
, "Expected external RTL8214FC, found PHY-ID %x\n", val
);
1316 phydev_info(phydev
, "Detected external RTL8214FC\n");
1318 h
= rtl838x_request_fw(phydev
, &rtl838x_8214fc_fw
, FIRMWARE_838X_8214FC_1
);
1322 if (h
->phy
!= 0x8214fc00) {
1323 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
1327 rtl8380_rtl8214fc_perchip
= (void *)h
+ sizeof(struct fw_header
)
1328 + h
->parts
[0].start
;
1330 rtl8380_rtl8214fc_perport
= (void *)h
+ sizeof(struct fw_header
)
1331 + h
->parts
[1].start
;
1333 /* detect phy version */
1334 write_phy(mac
, 0xfff, 27, 0x0004);
1335 read_phy(mac
, 0xfff, 28, &val
);
1337 read_phy(mac
, 0, 16, &val
);
1338 if (val
& (1 << 11))
1339 rtl8380_rtl8214fc_on_off(mac
, true);
1341 rtl8380_phy_reset(mac
);
1344 write_phy(mac
, 0, 30, 0x0001);
1347 while (rtl8380_rtl8214fc_perchip
[i
* 3]
1348 && rtl8380_rtl8214fc_perchip
[i
* 3 + 1]) {
1349 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x1f)
1350 page
= rtl8380_rtl8214fc_perchip
[i
* 3 + 2];
1351 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x13 && page
== 0x260) {
1352 read_phy(mac
+ rtl8380_rtl8214fc_perchip
[i
* 3], 0x260, 13, &val
);
1353 val
= (val
& 0x1f00) | (rtl8380_rtl8214fc_perchip
[i
* 3 + 2]
1355 write_phy(mac
+ rtl8380_rtl8214fc_perchip
[i
* 3],
1356 0xfff, rtl8380_rtl8214fc_perchip
[i
* 3 + 1], val
);
1358 write_phy(mac
+ rtl8380_rtl8214fc_perchip
[i
* 3],
1359 0xfff, rtl8380_rtl8214fc_perchip
[i
* 3 + 1],
1360 rtl8380_rtl8214fc_perchip
[i
* 3 + 2]);
1365 /* Force copper medium */
1366 for (i
= 0; i
< 4; i
++) {
1367 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
1368 write_phy(mac
+ i
, 0xfff, 0x1e, 0x0001);
1372 for (i
= 0; i
< 4; i
++) {
1373 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
1374 write_phy(mac
+ i
, 0xfff, 0x00, 0x1140);
1378 /* Disable Autosensing */
1379 for (i
= 0; i
< 4; i
++) {
1380 for (l
= 0; l
< 100; l
++) {
1381 read_phy(mac
+ i
, 0x0a42, 0x10, &val
);
1382 if ((val
& 0x7) >= 3)
1386 phydev_err(phydev
, "Could not disable autosensing\n");
1392 for (i
= 0; i
< 4; i
++) {
1393 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0b82);
1394 write_phy(mac
+ i
, 0xfff, 0x10, 0x0010);
1398 /* Verify patch readiness */
1399 for (i
= 0; i
< 4; i
++) {
1400 for (l
= 0; l
< 100; l
++) {
1401 read_phy(mac
+ i
, 0xb80, 0x10, &val
);
1406 phydev_err(phydev
, "Could not patch PHY\n");
1411 /* Use Broadcast ID method for patching */
1412 write_phy(mac
, 0xfff, 0x1f, 0x0000);
1413 write_phy(mac
, 0xfff, 0x1d, 0x0008);
1414 write_phy(mac
, 0xfff, 0x1f, 0x0266);
1415 write_phy(mac
, 0xfff, 0x16, 0xff00 + mac
);
1416 write_phy(mac
, 0xfff, 0x1f, 0x0000);
1417 write_phy(mac
, 0xfff, 0x1d, 0x0000);
1421 while (rtl8380_rtl8214fc_perport
[i
* 2]) {
1422 write_phy(mac
, 0xfff, rtl8380_rtl8214fc_perport
[i
* 2],
1423 rtl8380_rtl8214fc_perport
[i
* 2 + 1]);
1427 /*Disable broadcast ID*/
1428 write_phy(mac
, 0xfff, 0x1f, 0x0000);
1429 write_phy(mac
, 0xfff, 0x1d, 0x0008);
1430 write_phy(mac
, 0xfff, 0x1f, 0x0266);
1431 write_phy(mac
, 0xfff, 0x16, 0x00 + mac
);
1432 write_phy(mac
, 0xfff, 0x1f, 0x0000);
1433 write_phy(mac
, 0xfff, 0x1d, 0x0000);
1436 /* Auto medium selection */
1437 for (i
= 0; i
< 4; i
++) {
1438 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
1439 write_phy(mac
+ i
, 0xfff, 0x1e, 0x0000);
1445 static int rtl8214fc_match_phy_device(struct phy_device
*phydev
)
1447 int addr
= phydev
->mdio
.addr
;
1449 return phydev
->phy_id
== PHY_ID_RTL8214FC
&& addr
>= 24;
1452 static int rtl8380_configure_serdes(struct phy_device
*phydev
)
1457 struct fw_header
*h
;
1458 u32
*rtl8380_sds_take_reset
;
1459 u32
*rtl8380_sds_common
;
1460 u32
*rtl8380_sds01_qsgmii_6275b
;
1461 u32
*rtl8380_sds23_qsgmii_6275b
;
1462 u32
*rtl8380_sds4_fiber_6275b
;
1463 u32
*rtl8380_sds5_fiber_6275b
;
1464 u32
*rtl8380_sds_reset
;
1465 u32
*rtl8380_sds_release_reset
;
1467 phydev_info(phydev
, "Detected internal RTL8380 SERDES\n");
1469 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8380_1
);
1473 if (h
->magic
!= 0x83808380) {
1474 phydev_err(phydev
, "Wrong firmware file: magic number mismatch.\n");
1478 rtl8380_sds_take_reset
= (void *)h
+ sizeof(struct fw_header
)
1479 + h
->parts
[0].start
;
1481 rtl8380_sds_common
= (void *)h
+ sizeof(struct fw_header
)
1482 + h
->parts
[1].start
;
1484 rtl8380_sds01_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
)
1485 + h
->parts
[2].start
;
1487 rtl8380_sds23_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
)
1488 + h
->parts
[3].start
;
1490 rtl8380_sds4_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
)
1491 + h
->parts
[4].start
;
1493 rtl8380_sds5_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
)
1494 + h
->parts
[5].start
;
1496 rtl8380_sds_reset
= (void *)h
+ sizeof(struct fw_header
)
1497 + h
->parts
[6].start
;
1499 rtl8380_sds_release_reset
= (void *)h
+ sizeof(struct fw_header
)
1500 + h
->parts
[7].start
;
1502 /* Back up serdes power off value */
1503 sds_conf_value
= sw_r32(RTL838X_SDS_CFG_REG
);
1504 pr_info("SDS power down value: %x\n", sds_conf_value
);
1506 /* take serdes into reset */
1508 while (rtl8380_sds_take_reset
[2 * i
]) {
1509 sw_w32(rtl8380_sds_take_reset
[2 * i
+ 1], rtl8380_sds_take_reset
[2 * i
]);
1514 /* apply common serdes patch */
1516 while (rtl8380_sds_common
[2 * i
]) {
1517 sw_w32(rtl8380_sds_common
[2 * i
+ 1], rtl8380_sds_common
[2 * i
]);
1522 /* internal R/W enable */
1523 sw_w32(3, RTL838X_INT_RW_CTRL
);
1525 /* SerDes ports 4 and 5 are FIBRE ports */
1526 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL
);
1528 /* SerDes module settings, SerDes 0-3 are QSGMII */
1529 v
= 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1530 /* SerDes 4 and 5 are 1000BX FIBRE */
1531 v
|= 0x4 << 5 | 0x4;
1532 sw_w32(v
, RTL838X_SDS_MODE_SEL
);
1534 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL
));
1535 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL
);
1537 while (rtl8380_sds01_qsgmii_6275b
[2 * i
]) {
1538 sw_w32(rtl8380_sds01_qsgmii_6275b
[2 * i
+ 1],
1539 rtl8380_sds01_qsgmii_6275b
[2 * i
]);
1544 while (rtl8380_sds23_qsgmii_6275b
[2 * i
]) {
1545 sw_w32(rtl8380_sds23_qsgmii_6275b
[2 * i
+ 1], rtl8380_sds23_qsgmii_6275b
[2 * i
]);
1550 while (rtl8380_sds4_fiber_6275b
[2 * i
]) {
1551 sw_w32(rtl8380_sds4_fiber_6275b
[2 * i
+ 1], rtl8380_sds4_fiber_6275b
[2 * i
]);
1556 while (rtl8380_sds5_fiber_6275b
[2 * i
]) {
1557 sw_w32(rtl8380_sds5_fiber_6275b
[2 * i
+ 1], rtl8380_sds5_fiber_6275b
[2 * i
]);
1562 while (rtl8380_sds_reset
[2 * i
]) {
1563 sw_w32(rtl8380_sds_reset
[2 * i
+ 1], rtl8380_sds_reset
[2 * i
]);
1568 while (rtl8380_sds_release_reset
[2 * i
]) {
1569 sw_w32(rtl8380_sds_release_reset
[2 * i
+ 1], rtl8380_sds_release_reset
[2 * i
]);
1573 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG
));
1574 sw_w32(sds_conf_value
, RTL838X_SDS_CFG_REG
);
1576 pr_info("Configuration of SERDES done\n");
1580 static int rtl8390_configure_serdes(struct phy_device
*phydev
)
1582 phydev_info(phydev
, "Detected internal RTL8390 SERDES\n");
1584 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1585 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0
+ 0x0a);
1587 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1588 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1589 * and FRE16_EEE_QUIET_FIB1G
1591 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0
+ 0xe0);
1596 int rtl9300_configure_serdes(struct phy_device
*phydev
)
1598 struct device
*dev
= &phydev
->mdio
.dev
;
1599 int phy_addr
= phydev
->mdio
.addr
;
1603 phydev_info(phydev
, "Configuring internal RTL9300 SERDES\n");
1613 dev_err(dev
, "Not a SerDes PHY\n");
1617 /* Set default Medium to fibre */
1618 v
= rtl930x_read_sds_phy(sds_num
, 0x1f, 11);
1620 dev_err(dev
, "Cannot access SerDes PHY %d\n", phy_addr
);
1624 rtl930x_write_sds_phy(sds_num
, 0x1f, 11, v
);
1626 // TODO: this needs to be configurable via ethtool/.dts
1627 pr_info("Setting 10G/1000BX auto fibre medium\n");
1628 rtl9300_sds_rst(sds_num
, 0x1b);
1630 // TODO: Apply patch set for fibre type
1635 static int rtl8214fc_phy_probe(struct phy_device
*phydev
)
1637 struct device
*dev
= &phydev
->mdio
.dev
;
1638 struct rtl838x_phy_priv
*priv
;
1639 int addr
= phydev
->mdio
.addr
;
1641 /* 839x has internal SerDes */
1642 if (soc_info
.id
== 0x8393)
1645 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1649 priv
->name
= "RTL8214FC";
1651 /* All base addresses of the PHYs start at multiples of 8 */
1653 /* Configuration must be done whil patching still possible */
1654 return rtl8380_configure_rtl8214fc(phydev
);
1659 static int rtl8214c_phy_probe(struct phy_device
*phydev
)
1661 struct device
*dev
= &phydev
->mdio
.dev
;
1662 struct rtl838x_phy_priv
*priv
;
1663 int addr
= phydev
->mdio
.addr
;
1665 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1669 priv
->name
= "RTL8214C";
1671 /* All base addresses of the PHYs start at multiples of 8 */
1673 /* Configuration must be done whil patching still possible */
1674 return rtl8380_configure_rtl8214c(phydev
);
1679 static int rtl8218b_ext_phy_probe(struct phy_device
*phydev
)
1681 struct device
*dev
= &phydev
->mdio
.dev
;
1682 struct rtl838x_phy_priv
*priv
;
1683 int addr
= phydev
->mdio
.addr
;
1685 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1689 priv
->name
= "RTL8218B (external)";
1691 /* All base addresses of the PHYs start at multiples of 8 */
1692 if (!(addr
% 8) && soc_info
.family
== RTL8380_FAMILY_ID
) {
1693 /* Configuration must be done while patching still possible */
1694 return rtl8380_configure_ext_rtl8218b(phydev
);
1699 static int rtl8218b_int_phy_probe(struct phy_device
*phydev
)
1701 struct device
*dev
= &phydev
->mdio
.dev
;
1702 struct rtl838x_phy_priv
*priv
;
1703 int addr
= phydev
->mdio
.addr
;
1705 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
1710 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1714 priv
->name
= "RTL8218B (internal)";
1716 /* All base addresses of the PHYs start at multiples of 8 */
1718 /* Configuration must be done while patching still possible */
1719 return rtl8380_configure_int_rtl8218b(phydev
);
1724 static int rtl8218d_phy_probe(struct phy_device
*phydev
)
1726 struct device
*dev
= &phydev
->mdio
.dev
;
1727 struct rtl838x_phy_priv
*priv
;
1728 int addr
= phydev
->mdio
.addr
;
1730 pr_info("%s: id: %d\n", __func__
, addr
);
1731 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1735 priv
->name
= "RTL8218D";
1737 /* All base addresses of the PHYs start at multiples of 8 */
1739 /* Configuration must be done while patching still possible */
1740 // TODO: return configure_rtl8218d(phydev);
1745 static int rtl8226_phy_probe(struct phy_device
*phydev
)
1747 struct device
*dev
= &phydev
->mdio
.dev
;
1748 struct rtl838x_phy_priv
*priv
;
1749 int addr
= phydev
->mdio
.addr
;
1751 pr_info("%s: id: %d\n", __func__
, addr
);
1752 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1756 priv
->name
= "RTL8226";
1761 static int rtl838x_serdes_probe(struct phy_device
*phydev
)
1763 struct device
*dev
= &phydev
->mdio
.dev
;
1764 struct rtl838x_phy_priv
*priv
;
1765 int addr
= phydev
->mdio
.addr
;
1767 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
1772 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1776 priv
->name
= "RTL8380 Serdes";
1778 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
1779 if (soc_info
.id
== 0x8380) {
1781 return rtl8380_configure_serdes(phydev
);
1787 static int rtl8393_serdes_probe(struct phy_device
*phydev
)
1789 struct device
*dev
= &phydev
->mdio
.dev
;
1790 struct rtl838x_phy_priv
*priv
;
1791 int addr
= phydev
->mdio
.addr
;
1793 pr_info("%s: id: %d\n", __func__
, addr
);
1794 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
1800 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1804 priv
->name
= "RTL8393 Serdes";
1805 return rtl8390_configure_serdes(phydev
);
1808 static int rtl8390_serdes_probe(struct phy_device
*phydev
)
1810 struct device
*dev
= &phydev
->mdio
.dev
;
1811 struct rtl838x_phy_priv
*priv
;
1812 int addr
= phydev
->mdio
.addr
;
1814 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
1820 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1824 priv
->name
= "RTL8390 Serdes";
1825 return rtl8390_configure_generic(phydev
);
1828 static int rtl9300_serdes_probe(struct phy_device
*phydev
)
1830 struct device
*dev
= &phydev
->mdio
.dev
;
1831 struct rtl838x_phy_priv
*priv
;
1832 int addr
= phydev
->mdio
.addr
;
1834 if (soc_info
.family
!= RTL9300_FAMILY_ID
)
1840 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1844 priv
->name
= "RTL9300 Serdes";
1845 return rtl9300_configure_serdes(phydev
);
1848 static struct phy_driver rtl83xx_phy_driver
[] = {
1850 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C
),
1851 .name
= "Realtek RTL8214C",
1852 .features
= PHY_GBIT_FEATURES
,
1853 .match_phy_device
= rtl8214c_match_phy_device
,
1854 .probe
= rtl8214c_phy_probe
,
1855 .suspend
= genphy_suspend
,
1856 .resume
= genphy_resume
,
1857 .set_loopback
= genphy_loopback
,
1860 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
),
1861 .name
= "Realtek RTL8214FC",
1862 .features
= PHY_GBIT_FIBRE_FEATURES
,
1863 .match_phy_device
= rtl8214fc_match_phy_device
,
1864 .probe
= rtl8214fc_phy_probe
,
1865 .suspend
= genphy_suspend
,
1866 .resume
= genphy_resume
,
1867 .set_loopback
= genphy_loopback
,
1868 .read_mmd
= rtl8218b_read_mmd
,
1869 .write_mmd
= rtl8218b_write_mmd
,
1870 .set_port
= rtl8214fc_set_port
,
1871 .get_port
= rtl8214fc_get_port
,
1872 .set_eee
= rtl8214fc_set_eee
,
1873 .get_eee
= rtl8214fc_get_eee
,
1876 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E
),
1877 .name
= "Realtek RTL8218B (external)",
1878 .features
= PHY_GBIT_FEATURES
,
1879 .match_phy_device
= rtl8218b_ext_match_phy_device
,
1880 .probe
= rtl8218b_ext_phy_probe
,
1881 .suspend
= genphy_suspend
,
1882 .resume
= genphy_resume
,
1883 .set_loopback
= genphy_loopback
,
1884 .read_mmd
= rtl8218b_read_mmd
,
1885 .write_mmd
= rtl8218b_write_mmd
,
1886 .set_eee
= rtl8218b_set_eee
,
1887 .get_eee
= rtl8218b_get_eee
,
1890 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D
),
1891 .name
= "REALTEK RTL8218D",
1892 .features
= PHY_GBIT_FEATURES
,
1893 .probe
= rtl8218d_phy_probe
,
1894 .suspend
= genphy_suspend
,
1895 .resume
= genphy_resume
,
1896 .set_loopback
= genphy_loopback
,
1897 .set_eee
= rtl8218d_set_eee
,
1898 .get_eee
= rtl8218d_get_eee
,
1901 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226
),
1902 .name
= "REALTEK RTL8226",
1903 .features
= PHY_GBIT_FEATURES
,
1904 .probe
= rtl8226_phy_probe
,
1905 .suspend
= genphy_suspend
,
1906 .resume
= genphy_resume
,
1907 .set_loopback
= genphy_loopback
,
1908 .read_mmd
= rtl8226_read_mmd
,
1909 .write_mmd
= rtl8226_write_mmd
,
1910 .read_page
= rtl8226_read_page
,
1911 .write_page
= rtl8226_write_page
,
1912 .read_status
= rtl8226_read_status
,
1913 .config_aneg
= rtl8226_config_aneg
,
1914 .set_eee
= rtl8226_set_eee
,
1915 .get_eee
= rtl8226_get_eee
,
1918 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
1919 .name
= "Realtek RTL8218B (internal)",
1920 .features
= PHY_GBIT_FEATURES
,
1921 .probe
= rtl8218b_int_phy_probe
,
1922 .suspend
= genphy_suspend
,
1923 .resume
= genphy_resume
,
1924 .set_loopback
= genphy_loopback
,
1925 .read_mmd
= rtl8218b_read_mmd
,
1926 .write_mmd
= rtl8218b_write_mmd
,
1927 .set_eee
= rtl8218b_set_eee
,
1928 .get_eee
= rtl8218b_get_eee
,
1931 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
1932 .name
= "Realtek RTL8380 SERDES",
1933 .features
= PHY_GBIT_FIBRE_FEATURES
,
1934 .probe
= rtl838x_serdes_probe
,
1935 .suspend
= genphy_suspend
,
1936 .resume
= genphy_resume
,
1937 .set_loopback
= genphy_loopback
,
1938 .read_mmd
= rtl8218b_read_mmd
,
1939 .write_mmd
= rtl8218b_write_mmd
,
1940 .read_status
= rtl8380_read_status
,
1943 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I
),
1944 .name
= "Realtek RTL8393 SERDES",
1945 .features
= PHY_GBIT_FIBRE_FEATURES
,
1946 .probe
= rtl8393_serdes_probe
,
1947 .suspend
= genphy_suspend
,
1948 .resume
= genphy_resume
,
1949 .set_loopback
= genphy_loopback
,
1950 .read_status
= rtl8393_read_status
,
1953 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC
),
1954 .name
= "Realtek RTL8390 Generic",
1955 .features
= PHY_GBIT_FIBRE_FEATURES
,
1956 .probe
= rtl8390_serdes_probe
,
1957 .suspend
= genphy_suspend
,
1958 .resume
= genphy_resume
,
1959 .set_loopback
= genphy_loopback
,
1962 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I
),
1963 .name
= "REALTEK RTL9300 SERDES",
1964 .features
= PHY_GBIT_FIBRE_FEATURES
,
1965 .probe
= rtl9300_serdes_probe
,
1966 .suspend
= genphy_suspend
,
1967 .resume
= genphy_resume
,
1968 .set_loopback
= genphy_loopback
,
1972 module_phy_driver(rtl83xx_phy_driver
);
1974 static struct mdio_device_id __maybe_unused rtl83xx_tbl
[] = {
1975 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
) },
1979 MODULE_DEVICE_TABLE(mdio
, rtl83xx_tbl
);
1981 MODULE_AUTHOR("B. Koblitz");
1982 MODULE_DESCRIPTION("RTL83xx PHY driver");
1983 MODULE_LICENSE("GPL");