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realtek: Add support for the RTL8221B PHY
[openwrt/staging/wigyori.git] / target / linux / realtek / files-5.10 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/phy.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
16
17 extern struct rtl83xx_soc_info soc_info;
18 extern struct mutex smi_lock;
19
20 #define PHY_CTRL_REG 0
21 #define PHY_POWER_BIT 11
22
23 #define PHY_PAGE_2 2
24 #define PHY_PAGE_4 4
25 #define PARK_PAGE 0x1f
26
27 #define RTL9300_PHY_ID_MASK 0xf0ffffff
28
29 /*
30 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
31 * bus to detect e.g. link and media changes. For operations on the PHYs such as
32 * patching or other configuration changes such as EEE, polling needs to be disabled
33 * since otherwise these operations may fails or lead to unpredictable results.
34 */
35 DEFINE_MUTEX(poll_lock);
36
37 static const struct firmware rtl838x_8380_fw;
38 static const struct firmware rtl838x_8214fc_fw;
39 static const struct firmware rtl838x_8218b_fw;
40
41 int rtl838x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
42 int rtl838x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
43 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
44 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
45 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
46 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
47 int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
48 int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
49
50 static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
51 { switch (soc_info.family) {
52 case RTL8380_FAMILY_ID:
53 return rtl838x_read_phy(port, page, reg, val);
54 case RTL8390_FAMILY_ID:
55 return rtl839x_read_phy(port, page, reg, val);
56 case RTL9300_FAMILY_ID:
57 return rtl930x_read_phy(port, page, reg, val);
58 case RTL9310_FAMILY_ID:
59 return rtl931x_read_phy(port, page, reg, val);
60 }
61 return -1;
62 }
63
64 static int write_phy(u32 port, u32 page, u32 reg, u32 val)
65 {
66 switch (soc_info.family) {
67 case RTL8380_FAMILY_ID:
68 return rtl838x_write_phy(port, page, reg, val);
69 case RTL8390_FAMILY_ID:
70 return rtl839x_write_phy(port, page, reg, val);
71 case RTL9300_FAMILY_ID:
72 return rtl930x_write_phy(port, page, reg, val);
73 case RTL9310_FAMILY_ID:
74 return rtl931x_write_phy(port, page, reg, val);
75 }
76 return -1;
77 }
78
79 static int read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
80 {
81 switch (soc_info.family) {
82 case RTL8380_FAMILY_ID:
83 return rtl838x_read_mmd_phy(port, devnum, regnum, val);
84 case RTL8390_FAMILY_ID:
85 return rtl839x_read_mmd_phy(port, devnum, regnum, val);
86 case RTL9300_FAMILY_ID:
87 return rtl930x_read_mmd_phy(port, devnum, regnum, val);
88 case RTL9310_FAMILY_ID:
89 return rtl931x_read_mmd_phy(port, devnum, regnum, val);
90 }
91 return -1;
92 }
93
94 int write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val)
95 {
96 switch (soc_info.family) {
97 case RTL8380_FAMILY_ID:
98 return rtl838x_write_mmd_phy(port, devnum, reg, val);
99 case RTL8390_FAMILY_ID:
100 return rtl839x_write_mmd_phy(port, devnum, reg, val);
101 case RTL9300_FAMILY_ID:
102 return rtl930x_write_mmd_phy(port, devnum, reg, val);
103 case RTL9310_FAMILY_ID:
104 return rtl931x_write_mmd_phy(port, devnum, reg, val);
105 }
106 return -1;
107 }
108
109 static u64 disable_polling(int port)
110 {
111 u64 saved_state;
112
113 mutex_lock(&poll_lock);
114
115 switch (soc_info.family) {
116 case RTL8380_FAMILY_ID:
117 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
118 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
119 break;
120 case RTL8390_FAMILY_ID:
121 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
122 saved_state <<= 32;
123 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
124 sw_w32_mask(BIT(port % 32), 0,
125 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
126 break;
127 case RTL9300_FAMILY_ID:
128 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
129 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
130 break;
131 case RTL9310_FAMILY_ID:
132 pr_warn("%s not implemented for RTL931X\n", __func__);
133 break;
134 }
135
136 mutex_unlock(&poll_lock);
137
138 return saved_state;
139 }
140
141 static int resume_polling(u64 saved_state)
142 {
143 mutex_lock(&poll_lock);
144
145 switch (soc_info.family) {
146 case RTL8380_FAMILY_ID:
147 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
148 break;
149 case RTL8390_FAMILY_ID:
150 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
151 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
152 break;
153 case RTL9300_FAMILY_ID:
154 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
155 break;
156 case RTL9310_FAMILY_ID:
157 pr_warn("%s not implemented for RTL931X\n", __func__);
158 break;
159 }
160
161 mutex_unlock(&poll_lock);
162
163 return 0;
164 }
165
166 static void rtl8380_int_phy_on_off(int mac, bool on)
167 {
168 u32 val;
169
170 read_phy(mac, 0, 0, &val);
171 if (on)
172 write_phy(mac, 0, 0, val & ~BIT(11));
173 else
174 write_phy(mac, 0, 0, val | BIT(11));
175 }
176
177 static void rtl8380_rtl8214fc_on_off(int mac, bool on)
178 {
179 u32 val;
180
181 /* fiber ports */
182 write_phy(mac, 4095, 30, 3);
183 read_phy(mac, 0, 16, &val);
184 if (on)
185 write_phy(mac, 0, 16, val & ~BIT(11));
186 else
187 write_phy(mac, 0, 16, val | BIT(11));
188
189 /* copper ports */
190 write_phy(mac, 4095, 30, 1);
191 read_phy(mac, 0, 16, &val);
192 if (on)
193 write_phy(mac, 0xa40, 16, val & ~BIT(11));
194 else
195 write_phy(mac, 0xa40, 16, val | BIT(11));
196 }
197
198 static void rtl8380_phy_reset(int mac)
199 {
200 u32 val;
201
202 read_phy(mac, 0, 0, &val);
203 write_phy(mac, 0, 0, val | BIT(15));
204 }
205
206 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
207 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
208 0x02A4, 0x02A4, 0x0198, 0x0198 };
209 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
210
211 /*
212 * Reset the SerDes by powering it off and set a new operations mode
213 * of the SerDes. 0x1f is off. Other modes are
214 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
215 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
216 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
217 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
218 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
219 */
220 void rtl9300_sds_rst(int sds_num, u32 mode)
221 {
222 pr_info("%s %d\n", __func__, mode);
223 if (sds_num < 0 || sds_num > 11) {
224 pr_err("Wrong SerDes number: %d\n", sds_num);
225 return;
226 }
227
228 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
229 rtl9300_sds_regs[sds_num]);
230 mdelay(10);
231
232 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
233 rtl9300_sds_regs[sds_num]);
234 mdelay(10);
235
236 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
237 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
238 }
239
240 void rtl9300_sds_set(int sds_num, u32 mode)
241 {
242 pr_info("%s %d\n", __func__, mode);
243 if (sds_num < 0 || sds_num > 11) {
244 pr_err("Wrong SerDes number: %d\n", sds_num);
245 return;
246 }
247
248 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
249 rtl9300_sds_regs[sds_num]);
250 mdelay(10);
251
252 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
253 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
254 }
255
256 u32 rtl9300_sds_mode_get(int sds_num)
257 {
258 u32 v;
259
260 if (sds_num < 0 || sds_num > 11) {
261 pr_err("Wrong SerDes number: %d\n", sds_num);
262 return 0;
263 }
264
265 v = sw_r32(rtl9300_sds_regs[sds_num]);
266 v >>= rtl9300_sds_lsb[sds_num];
267
268 return v & 0x1f;
269 }
270
271 /*
272 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
273 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
274 */
275 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
276 {
277 int offset = 0;
278 int reg;
279 u32 val;
280
281 if (phy_addr == 49)
282 offset = 0x100;
283
284 /*
285 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
286 * which would otherwise read as 0.
287 */
288 if (soc_info.id == 0x8393) {
289 if (phy_reg == 2)
290 return 0x1c;
291 if (phy_reg == 3)
292 return 0x8393;
293 }
294
295 /*
296 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
297 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
298 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
299 * one 32 bit register.
300 */
301 reg = (phy_reg << 1) & 0xfc;
302 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
303
304 if (phy_reg & 1)
305 val = (val >> 16) & 0xffff;
306 else
307 val &= 0xffff;
308 return val;
309 }
310
311 /*
312 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
313 * register which simulates commands to an internal MDIO bus.
314 */
315 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
316 {
317 int i;
318 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
319
320 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
321
322 for (i = 0; i < 100; i++) {
323 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
324 break;
325 mdelay(1);
326 }
327
328 if (i >= 100)
329 return -EIO;
330
331 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
332 }
333
334 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
335 {
336 int i;
337 u32 cmd;
338
339 sw_w32(v, RTL930X_SDS_INDACS_DATA);
340 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
341
342 for (i = 0; i < 100; i++) {
343 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
344 break;
345 mdelay(1);
346 }
347
348
349 if (i >= 100) {
350 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
351 return -EIO;
352 }
353
354 return 0;
355 }
356
357 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
358 {
359 int i;
360 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
361
362 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
363 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
364
365 for (i = 0; i < 100; i++) {
366 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
367 break;
368 mdelay(1);
369 }
370
371 if (i >= 100)
372 return -EIO;
373
374 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
375 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
376 }
377
378 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
379 {
380 int i;
381 u32 cmd;
382
383 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
384 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
385
386 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
387
388 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
389 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
390
391 for (i = 0; i < 100; i++) {
392 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
393 break;
394 mdelay(1);
395 }
396
397 if (i >= 100)
398 return -EIO;
399
400 return 0;
401 }
402
403 /*
404 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
405 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
406 * in a standard page 0 of a PHY
407 */
408 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
409 {
410 int offset = 0;
411 u32 val;
412
413 if (phy_addr == 26)
414 offset = 0x100;
415 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
416
417 return val;
418 }
419
420 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
421 {
422 int offset = 0;
423 int reg;
424 u32 val;
425
426 if (phy_addr == 49)
427 offset = 0x100;
428
429 reg = (phy_reg << 1) & 0xfc;
430 val = v;
431 if (phy_reg & 1) {
432 val = val << 16;
433 sw_w32_mask(0xffff0000, val,
434 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
435 } else {
436 sw_w32_mask(0xffff, val,
437 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
438 }
439
440 return 0;
441 }
442
443 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
444 * ports of the RTL838x SoCs
445 */
446 static int rtl8380_read_status(struct phy_device *phydev)
447 {
448 int err;
449
450 err = genphy_read_status(phydev);
451
452 if (phydev->link) {
453 phydev->speed = SPEED_1000;
454 phydev->duplex = DUPLEX_FULL;
455 }
456
457 return err;
458 }
459
460 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
461 * ports of the RTL8393 SoC
462 */
463 static int rtl8393_read_status(struct phy_device *phydev)
464 {
465 int offset = 0;
466 int err;
467 int phy_addr = phydev->mdio.addr;
468 u32 v;
469
470 err = genphy_read_status(phydev);
471 if (phy_addr == 49)
472 offset = 0x100;
473
474 if (phydev->link) {
475 phydev->speed = SPEED_100;
476 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
477 * PHY registers
478 */
479 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
480 if (!(v & (1 << 13)) && (v & (1 << 6)))
481 phydev->speed = SPEED_1000;
482 phydev->duplex = DUPLEX_FULL;
483 }
484
485 return err;
486 }
487
488 static int rtl8226_read_page(struct phy_device *phydev)
489 {
490 return __phy_read(phydev, 0x1f);
491 }
492
493 static int rtl8226_write_page(struct phy_device *phydev, int page)
494 {
495 return __phy_write(phydev, 0x1f, page);
496 }
497
498 static int rtl8226_read_status(struct phy_device *phydev)
499 {
500 int ret = 0, i;
501 u32 val;
502 int port = phydev->mdio.addr;
503
504 // TODO: ret = genphy_read_status(phydev);
505 // if (ret < 0) {
506 // pr_info("%s: genphy_read_status failed\n", __func__);
507 // return ret;
508 // }
509
510 // Link status must be read twice
511 for (i = 0; i < 2; i++) {
512 read_mmd_phy(port, MMD_VEND2, 0xA402, &val);
513 }
514 phydev->link = val & BIT(2) ? 1 : 0;
515 if (!phydev->link)
516 goto out;
517
518 // Read duplex status
519 ret = read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
520 if (ret)
521 goto out;
522 phydev->duplex = !!(val & BIT(3));
523
524 // Read speed
525 ret = read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
526 switch (val & 0x0630) {
527 case 0x0000:
528 phydev->speed = SPEED_10;
529 break;
530 case 0x0010:
531 phydev->speed = SPEED_100;
532 break;
533 case 0x0020:
534 phydev->speed = SPEED_1000;
535 break;
536 case 0x0200:
537 phydev->speed = SPEED_10000;
538 break;
539 case 0x0210:
540 phydev->speed = SPEED_2500;
541 break;
542 case 0x0220:
543 phydev->speed = SPEED_5000;
544 break;
545 default:
546 break;
547 }
548 out:
549 return ret;
550 }
551
552 static int rtl8226_advertise_aneg(struct phy_device *phydev)
553 {
554 int ret = 0;
555 u32 v;
556 int port = phydev->mdio.addr;
557
558 pr_info("In %s\n", __func__);
559
560 ret = read_mmd_phy(port, MMD_AN, 16, &v);
561 if (ret)
562 goto out;
563
564 v |= BIT(5); // HD 10M
565 v |= BIT(6); // FD 10M
566 v |= BIT(7); // HD 100M
567 v |= BIT(8); // FD 100M
568
569 ret = write_mmd_phy(port, MMD_AN, 16, v);
570
571 // Allow 1GBit
572 ret = read_mmd_phy(port, MMD_VEND2, 0xA412, &v);
573 if (ret)
574 goto out;
575 v |= BIT(9); // FD 1000M
576
577 ret = write_mmd_phy(port, MMD_VEND2, 0xA412, v);
578 if (ret)
579 goto out;
580
581 // Allow 2.5G
582 ret = read_mmd_phy(port, MMD_AN, 32, &v);
583 if (ret)
584 goto out;
585
586 v |= BIT(7);
587 ret = write_mmd_phy(port, MMD_AN, 32, v);
588
589 out:
590 return ret;
591 }
592
593 static int rtl8226_config_aneg(struct phy_device *phydev)
594 {
595 int ret = 0;
596 u32 v;
597 int port = phydev->mdio.addr;
598
599 pr_debug("In %s\n", __func__);
600 if (phydev->autoneg == AUTONEG_ENABLE) {
601 ret = rtl8226_advertise_aneg(phydev);
602 if (ret)
603 goto out;
604 // AutoNegotiationEnable
605 ret = read_mmd_phy(port, MMD_AN, 0, &v);
606 if (ret)
607 goto out;
608
609 v |= BIT(12); // Enable AN
610 ret = write_mmd_phy(port, MMD_AN, 0, v);
611 if (ret)
612 goto out;
613
614 // RestartAutoNegotiation
615 ret = read_mmd_phy(port, MMD_VEND2, 0xA400, &v);
616 if (ret)
617 goto out;
618 v |= BIT(9);
619
620 ret = write_mmd_phy(port, MMD_VEND2, 0xA400, v);
621 }
622
623 // TODO: ret = __genphy_config_aneg(phydev, ret);
624
625 out:
626 return ret;
627 }
628
629 static int rtl8226_get_eee(struct phy_device *phydev,
630 struct ethtool_eee *e)
631 {
632 u32 val;
633 int addr = phydev->mdio.addr;
634
635 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
636
637 read_mmd_phy(addr, MMD_AN, 60, &val);
638 if (e->eee_enabled) {
639 e->eee_enabled = !!(val & BIT(1));
640 if (!e->eee_enabled) {
641 read_mmd_phy(addr, MMD_AN, 62, &val);
642 e->eee_enabled = !!(val & BIT(0));
643 }
644 }
645 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
646
647 return 0;
648 }
649
650 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
651 {
652 int port = phydev->mdio.addr;
653 u64 poll_state;
654 bool an_enabled;
655 u32 val;
656
657 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
658
659 poll_state = disable_polling(port);
660
661 // Remember aneg state
662 read_mmd_phy(port, MMD_AN, 0, &val);
663 an_enabled = !!(val & BIT(12));
664
665 // Setup 100/1000MBit
666 read_mmd_phy(port, MMD_AN, 60, &val);
667 if (e->eee_enabled)
668 val |= 0x6;
669 else
670 val &= 0x6;
671 write_mmd_phy(port, MMD_AN, 60, val);
672
673 // Setup 2.5GBit
674 read_mmd_phy(port, MMD_AN, 62, &val);
675 if (e->eee_enabled)
676 val |= 0x1;
677 else
678 val &= 0x1;
679 write_mmd_phy(port, MMD_AN, 62, val);
680
681 // RestartAutoNegotiation
682 read_mmd_phy(port, MMD_VEND2, 0xA400, &val);
683 val |= BIT(9);
684 write_mmd_phy(port, MMD_VEND2, 0xA400, val);
685
686 resume_polling(poll_state);
687
688 return 0;
689 }
690
691 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
692 const struct firmware *fw,
693 const char *name)
694 {
695 struct device *dev = &phydev->mdio.dev;
696 int err;
697 struct fw_header *h;
698 uint32_t checksum, my_checksum;
699
700 err = request_firmware(&fw, name, dev);
701 if (err < 0)
702 goto out;
703
704 if (fw->size < sizeof(struct fw_header)) {
705 pr_err("Firmware size too small.\n");
706 err = -EINVAL;
707 goto out;
708 }
709
710 h = (struct fw_header *) fw->data;
711 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
712
713 if (h->magic != 0x83808380) {
714 pr_err("Wrong firmware file: MAGIC mismatch.\n");
715 goto out;
716 }
717
718 checksum = h->checksum;
719 h->checksum = 0;
720 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
721 if (checksum != my_checksum) {
722 pr_err("Firmware checksum mismatch.\n");
723 err = -EINVAL;
724 goto out;
725 }
726 h->checksum = checksum;
727
728 return h;
729 out:
730 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
731 return NULL;
732 }
733
734 static int rtl8390_configure_generic(struct phy_device *phydev)
735 {
736 u32 val, phy_id;
737 int mac = phydev->mdio.addr;
738
739 read_phy(mac, 0, 2, &val);
740 phy_id = val << 16;
741 read_phy(mac, 0, 3, &val);
742 phy_id |= val;
743 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
744
745 /* Read internal PHY ID */
746 write_phy(mac, 31, 27, 0x0002);
747 read_phy(mac, 31, 28, &val);
748
749 /* Internal RTL8218B, version 2 */
750 phydev_info(phydev, "Detected unknown %x\n", val);
751 return 0;
752 }
753
754 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
755 {
756 u32 val, phy_id;
757 int i, p, ipd_flag;
758 int mac = phydev->mdio.addr;
759 struct fw_header *h;
760 u32 *rtl838x_6275B_intPhy_perport;
761 u32 *rtl8218b_6276B_hwEsd_perport;
762
763
764 read_phy(mac, 0, 2, &val);
765 phy_id = val << 16;
766 read_phy(mac, 0, 3, &val);
767 phy_id |= val;
768 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
769
770 /* Read internal PHY ID */
771 write_phy(mac, 31, 27, 0x0002);
772 read_phy(mac, 31, 28, &val);
773 if (val != 0x6275) {
774 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
775 return -1;
776 }
777
778 /* Internal RTL8218B, version 2 */
779 phydev_info(phydev, "Detected internal RTL8218B\n");
780
781 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
782 if (!h)
783 return -1;
784
785 if (h->phy != 0x83800000) {
786 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
787 return -1;
788 }
789
790 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
791 + h->parts[8].start;
792
793 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
794 + h->parts[9].start;
795
796 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
797 ipd_flag = 1;
798
799 read_phy(mac, 0, 0, &val);
800 if (val & (1 << 11))
801 rtl8380_int_phy_on_off(mac, true);
802 else
803 rtl8380_phy_reset(mac);
804 msleep(100);
805
806 /* Ready PHY for patch */
807 for (p = 0; p < 8; p++) {
808 write_phy(mac + p, 0xfff, 0x1f, 0x0b82);
809 write_phy(mac + p, 0xfff, 0x10, 0x0010);
810 }
811 msleep(500);
812 for (p = 0; p < 8; p++) {
813 for (i = 0; i < 100 ; i++) {
814 read_phy(mac + p, 0x0b80, 0x10, &val);
815 if (val & 0x40)
816 break;
817 }
818 if (i >= 100) {
819 phydev_err(phydev,
820 "ERROR: Port %d not ready for patch.\n",
821 mac + p);
822 return -1;
823 }
824 }
825 for (p = 0; p < 8; p++) {
826 i = 0;
827 while (rtl838x_6275B_intPhy_perport[i * 2]) {
828 write_phy(mac + p, 0xfff,
829 rtl838x_6275B_intPhy_perport[i * 2],
830 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
831 i++;
832 }
833 i = 0;
834 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
835 write_phy(mac + p, 0xfff,
836 rtl8218b_6276B_hwEsd_perport[i * 2],
837 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
838 i++;
839 }
840 }
841 return 0;
842 }
843
844 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
845 {
846 u32 val, ipd, phy_id;
847 int i, l;
848 int mac = phydev->mdio.addr;
849 struct fw_header *h;
850 u32 *rtl8380_rtl8218b_perchip;
851 u32 *rtl8218B_6276B_rtl8380_perport;
852 u32 *rtl8380_rtl8218b_perport;
853
854 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
855 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
856 return -1;
857 }
858 read_phy(mac, 0, 2, &val);
859 phy_id = val << 16;
860 read_phy(mac, 0, 3, &val);
861 phy_id |= val;
862 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
863
864 /* Read internal PHY ID */
865 write_phy(mac, 31, 27, 0x0002);
866 read_phy(mac, 31, 28, &val);
867 if (val != 0x6276) {
868 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
869 return -1;
870 }
871 phydev_info(phydev, "Detected external RTL8218B\n");
872
873 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
874 if (!h)
875 return -1;
876
877 if (h->phy != 0x8218b000) {
878 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
879 return -1;
880 }
881
882 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
883 + h->parts[0].start;
884
885 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
886 + h->parts[1].start;
887
888 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
889 + h->parts[2].start;
890
891 read_phy(mac, 0, 0, &val);
892 if (val & (1 << 11))
893 rtl8380_int_phy_on_off(mac, true);
894 else
895 rtl8380_phy_reset(mac);
896 msleep(100);
897
898 /* Get Chip revision */
899 write_phy(mac, 0xfff, 0x1f, 0x0);
900 write_phy(mac, 0xfff, 0x1b, 0x4);
901 read_phy(mac, 0xfff, 0x1c, &val);
902
903 i = 0;
904 while (rtl8380_rtl8218b_perchip[i * 3]
905 && rtl8380_rtl8218b_perchip[i * 3 + 1]) {
906 write_phy(mac + rtl8380_rtl8218b_perchip[i * 3],
907 0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1],
908 rtl8380_rtl8218b_perchip[i * 3 + 2]);
909 i++;
910 }
911
912 /* Enable PHY */
913 for (i = 0; i < 8; i++) {
914 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
915 write_phy(mac + i, 0xfff, 0x00, 0x1140);
916 }
917 mdelay(100);
918
919 /* Request patch */
920 for (i = 0; i < 8; i++) {
921 write_phy(mac + i, 0xfff, 0x1f, 0x0b82);
922 write_phy(mac + i, 0xfff, 0x10, 0x0010);
923 }
924 mdelay(300);
925
926 /* Verify patch readiness */
927 for (i = 0; i < 8; i++) {
928 for (l = 0; l < 100; l++) {
929 read_phy(mac + i, 0xb80, 0x10, &val);
930 if (val & 0x40)
931 break;
932 }
933 if (l >= 100) {
934 phydev_err(phydev, "Could not patch PHY\n");
935 return -1;
936 }
937 }
938
939 /* Use Broadcast ID method for patching */
940 write_phy(mac, 0xfff, 0x1f, 0x0000);
941 write_phy(mac, 0xfff, 0x1d, 0x0008);
942 write_phy(mac, 0xfff, 0x1f, 0x0266);
943 write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
944 write_phy(mac, 0xfff, 0x1f, 0x0000);
945 write_phy(mac, 0xfff, 0x1d, 0x0000);
946 mdelay(1);
947
948 write_phy(mac, 0xfff, 30, 8);
949 write_phy(mac, 0x26e, 17, 0xb);
950 write_phy(mac, 0x26e, 16, 0x2);
951 mdelay(1);
952 read_phy(mac, 0x26e, 19, &ipd);
953 write_phy(mac, 0, 30, 0);
954 ipd = (ipd >> 4) & 0xf;
955
956 i = 0;
957 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
958 write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2],
959 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
960 i++;
961 }
962
963 /*Disable broadcast ID*/
964 write_phy(mac, 0xfff, 0x1f, 0x0000);
965 write_phy(mac, 0xfff, 0x1d, 0x0008);
966 write_phy(mac, 0xfff, 0x1f, 0x0266);
967 write_phy(mac, 0xfff, 0x16, 0x00 + mac);
968 write_phy(mac, 0xfff, 0x1f, 0x0000);
969 write_phy(mac, 0xfff, 0x1d, 0x0000);
970 mdelay(1);
971
972 return 0;
973 }
974
975 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
976 {
977 int addr = phydev->mdio.addr;
978
979 /* Both the RTL8214FC and the external RTL8218B have the same
980 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
981 * at PHY IDs 0-7, while the RTL8214FC must be attached via
982 * the pair of SGMII/1000Base-X with higher PHY-IDs
983 */
984 if (soc_info.family == RTL8380_FAMILY_ID)
985 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
986 else
987 return phydev->phy_id == PHY_ID_RTL8218B_E;
988 }
989
990 static int rtl8218b_read_mmd(struct phy_device *phydev,
991 int devnum, u16 regnum)
992 {
993 int ret;
994 u32 val;
995 int addr = phydev->mdio.addr;
996
997 ret = read_mmd_phy(addr, devnum, regnum, &val);
998 if (ret)
999 return ret;
1000 return val;
1001 }
1002
1003 static int rtl8218b_write_mmd(struct phy_device *phydev,
1004 int devnum, u16 regnum, u16 val)
1005 {
1006 int addr = phydev->mdio.addr;
1007
1008 return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
1009 }
1010
1011 static int rtl8226_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
1012 {
1013 int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
1014 int err;
1015 u32 val;
1016
1017 err = read_mmd_phy(port, devnum, regnum, &val);
1018 if (err)
1019 return err;
1020 return val;
1021 }
1022
1023 static int rtl8226_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val)
1024 {
1025 int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
1026
1027 return write_mmd_phy(port, devnum, regnum, val);
1028 }
1029
1030 static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre)
1031 {
1032 int base = mac - (mac % 4);
1033 static int reg[] = {16, 19, 20, 21};
1034 int val, media, power;
1035
1036 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1037 write_phy(base, 0xfff, 29, 8);
1038 read_phy(base, 0x266, reg[mac % 4], &val);
1039
1040 media = (val >> 10) & 0x3;
1041 pr_info("Current media %x\n", media);
1042 if (media & 0x2) {
1043 pr_info("Powering off COPPER\n");
1044 write_phy(base, 0xfff, 29, 1);
1045 /* Ensure power is off */
1046 read_phy(base, 0xa40, 16, &power);
1047 if (!(power & (1 << 11)))
1048 write_phy(base, 0xa40, 16, power | (1 << 11));
1049 } else {
1050 pr_info("Powering off FIBRE");
1051 write_phy(base, 0xfff, 29, 3);
1052 /* Ensure power is off */
1053 read_phy(base, 0xa40, 16, &power);
1054 if (!(power & (1 << 11)))
1055 write_phy(base, 0xa40, 16, power | (1 << 11));
1056 }
1057
1058 if (set_fibre) {
1059 val |= 1 << 10;
1060 val &= ~(1 << 11);
1061 } else {
1062 val |= 1 << 10;
1063 val |= 1 << 11;
1064 }
1065 write_phy(base, 0xfff, 29, 8);
1066 write_phy(base, 0x266, reg[mac % 4], val);
1067 write_phy(base, 0xfff, 29, 0);
1068
1069 if (set_fibre) {
1070 pr_info("Powering on FIBRE");
1071 write_phy(base, 0xfff, 29, 3);
1072 /* Ensure power is off */
1073 read_phy(base, 0xa40, 16, &power);
1074 if (power & (1 << 11))
1075 write_phy(base, 0xa40, 16, power & ~(1 << 11));
1076 } else {
1077 pr_info("Powering on COPPER\n");
1078 write_phy(base, 0xfff, 29, 1);
1079 /* Ensure power is off */
1080 read_phy(base, 0xa40, 16, &power);
1081 if (power & (1 << 11))
1082 write_phy(base, 0xa40, 16, power & ~(1 << 11));
1083 }
1084
1085 write_phy(base, 0xfff, 29, 0);
1086 }
1087
1088 static bool rtl8380_rtl8214fc_media_is_fibre(int mac)
1089 {
1090 int base = mac - (mac % 4);
1091 static int reg[] = {16, 19, 20, 21};
1092 u32 val;
1093
1094 write_phy(base, 0xfff, 29, 8);
1095 read_phy(base, 0x266, reg[mac % 4], &val);
1096 write_phy(base, 0xfff, 29, 0);
1097 if (val & (1 << 11))
1098 return false;
1099 return true;
1100 }
1101
1102 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1103 {
1104 bool is_fibre = (port == PORT_FIBRE ? true : false);
1105 int addr = phydev->mdio.addr;
1106
1107 pr_debug("%s port %d to %d\n", __func__, addr, port);
1108
1109 rtl8380_rtl8214fc_media_set(addr, is_fibre);
1110 return 0;
1111 }
1112
1113 static int rtl8214fc_get_port(struct phy_device *phydev)
1114 {
1115 int addr = phydev->mdio.addr;
1116
1117 pr_debug("%s: port %d\n", __func__, addr);
1118 if (rtl8380_rtl8214fc_media_is_fibre(addr))
1119 return PORT_FIBRE;
1120 return PORT_MII;
1121 }
1122
1123 /*
1124 * Enable EEE on the RTL8218B PHYs
1125 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1126 * but the only way that works since the kernel first enables EEE in the MAC
1127 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1128 */
1129 void rtl8218d_eee_set(int port, bool enable)
1130 {
1131 u32 val;
1132 bool an_enabled;
1133
1134 pr_debug("In %s %d, enable %d\n", __func__, port, enable);
1135 /* Set GPHY page to copper */
1136 write_phy(port, 0xa42, 30, 0x0001);
1137
1138 read_phy(port, 0, 0, &val);
1139 an_enabled = val & BIT(12);
1140
1141 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1142 read_mmd_phy(port, 7, 60, &val);
1143 val |= BIT(2) | BIT(1);
1144 write_mmd_phy(port, 7, 60, enable ? 0x6 : 0);
1145
1146 /* 500M EEE ability */
1147 read_phy(port, 0xa42, 20, &val);
1148 if (enable)
1149 val |= BIT(7);
1150 else
1151 val &= ~BIT(7);
1152 write_phy(port, 0xa42, 20, val);
1153
1154 /* Restart AN if enabled */
1155 if (an_enabled) {
1156 read_phy(port, 0, 0, &val);
1157 val |= BIT(9);
1158 write_phy(port, 0, 0, val);
1159 }
1160
1161 /* GPHY page back to auto*/
1162 write_phy(port, 0xa42, 30, 0);
1163 }
1164
1165 static int rtl8218b_get_eee(struct phy_device *phydev,
1166 struct ethtool_eee *e)
1167 {
1168 u32 val;
1169 int addr = phydev->mdio.addr;
1170
1171 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1172
1173 /* Set GPHY page to copper */
1174 write_phy(addr, 0xa42, 29, 0x0001);
1175
1176 read_phy(addr, 7, 60, &val);
1177 if (e->eee_enabled) {
1178 // Verify vs MAC-based EEE
1179 e->eee_enabled = !!(val & BIT(7));
1180 if (!e->eee_enabled) {
1181 read_phy(addr, 0x0A43, 25, &val);
1182 e->eee_enabled = !!(val & BIT(4));
1183 }
1184 }
1185 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1186
1187 /* GPHY page to auto */
1188 write_phy(addr, 0xa42, 29, 0x0000);
1189
1190 return 0;
1191 }
1192
1193 static int rtl8218d_get_eee(struct phy_device *phydev,
1194 struct ethtool_eee *e)
1195 {
1196 u32 val;
1197 int addr = phydev->mdio.addr;
1198
1199 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1200
1201 /* Set GPHY page to copper */
1202 write_phy(addr, 0xa42, 30, 0x0001);
1203
1204 read_phy(addr, 7, 60, &val);
1205 if (e->eee_enabled)
1206 e->eee_enabled = !!(val & BIT(7));
1207 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1208
1209 /* GPHY page to auto */
1210 write_phy(addr, 0xa42, 30, 0x0000);
1211
1212 return 0;
1213 }
1214
1215 static int rtl8214fc_set_eee(struct phy_device *phydev,
1216 struct ethtool_eee *e)
1217 {
1218 u32 poll_state;
1219 int port = phydev->mdio.addr;
1220 bool an_enabled;
1221 u32 val;
1222
1223 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1224
1225 if (rtl8380_rtl8214fc_media_is_fibre(port)) {
1226 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1227 return -ENOTSUPP;
1228 }
1229
1230 poll_state = disable_polling(port);
1231
1232 /* Set GPHY page to copper */
1233 write_phy(port, 0xa42, 29, 0x0001);
1234
1235 // Get auto-negotiation status
1236 read_phy(port, 0, 0, &val);
1237 an_enabled = val & BIT(12);
1238
1239 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1240 read_phy(port, 0x0A43, 25, &val);
1241 val &= ~BIT(5); // Use MAC-based EEE
1242 write_phy(port, 0x0A43, 25, val);
1243
1244 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1245 write_phy(port, 7, 60, e->eee_enabled ? 0x6 : 0);
1246
1247 /* 500M EEE ability */
1248 read_phy(port, 0xa42, 20, &val);
1249 if (e->eee_enabled)
1250 val |= BIT(7);
1251 else
1252 val &= ~BIT(7);
1253 write_phy(port, 0xa42, 20, val);
1254
1255 /* Restart AN if enabled */
1256 if (an_enabled) {
1257 pr_info("%s: doing aneg\n", __func__);
1258 read_phy(port, 0, 0, &val);
1259 val |= BIT(9);
1260 write_phy(port, 0, 0, val);
1261 }
1262
1263 /* GPHY page back to auto*/
1264 write_phy(port, 0xa42, 29, 0);
1265
1266 resume_polling(poll_state);
1267
1268 return 0;
1269 }
1270
1271 static int rtl8214fc_get_eee(struct phy_device *phydev,
1272 struct ethtool_eee *e)
1273 {
1274 int addr = phydev->mdio.addr;
1275
1276 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1277 if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
1278 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1279 return -ENOTSUPP;
1280 }
1281
1282 return rtl8218b_get_eee(phydev, e);
1283 }
1284
1285 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1286 {
1287 int port = phydev->mdio.addr;
1288 u64 poll_state;
1289 u32 val;
1290 bool an_enabled;
1291
1292 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1293
1294 poll_state = disable_polling(port);
1295
1296 /* Set GPHY page to copper */
1297 write_phy(port, 0, 30, 0x0001);
1298 read_phy(port, 0, 0, &val);
1299 an_enabled = val & BIT(12);
1300
1301 if (e->eee_enabled) {
1302 /* 100/1000M EEE Capability */
1303 write_phy(port, 0, 13, 0x0007);
1304 write_phy(port, 0, 14, 0x003C);
1305 write_phy(port, 0, 13, 0x4007);
1306 write_phy(port, 0, 14, 0x0006);
1307
1308 read_phy(port, 0x0A43, 25, &val);
1309 val |= BIT(4);
1310 write_phy(port, 0x0A43, 25, val);
1311 } else {
1312 /* 100/1000M EEE Capability */
1313 write_phy(port, 0, 13, 0x0007);
1314 write_phy(port, 0, 14, 0x003C);
1315 write_phy(port, 0, 13, 0x0007);
1316 write_phy(port, 0, 14, 0x0000);
1317
1318 read_phy(port, 0x0A43, 25, &val);
1319 val &= ~BIT(4);
1320 write_phy(port, 0x0A43, 25, val);
1321 }
1322
1323 /* Restart AN if enabled */
1324 if (an_enabled) {
1325 read_phy(port, 0, 0, &val);
1326 val |= BIT(9);
1327 write_phy(port, 0, 0, val);
1328 }
1329
1330 /* GPHY page back to auto*/
1331 write_phy(port, 0xa42, 30, 0);
1332
1333 pr_info("%s done\n", __func__);
1334 resume_polling(poll_state);
1335
1336 return 0;
1337 }
1338
1339 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1340 {
1341 int addr = phydev->mdio.addr;
1342 u64 poll_state;
1343
1344 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1345
1346 poll_state = disable_polling(addr);
1347
1348 rtl8218d_eee_set(addr, (bool) e->eee_enabled);
1349
1350 resume_polling(poll_state);
1351
1352 return 0;
1353 }
1354
1355 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1356 {
1357 return phydev->phy_id == PHY_ID_RTL8214C;
1358 }
1359
1360 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1361 {
1362 u32 phy_id, val;
1363 int mac = phydev->mdio.addr;
1364
1365 read_phy(mac, 0, 2, &val);
1366 phy_id = val << 16;
1367 read_phy(mac, 0, 3, &val);
1368 phy_id |= val;
1369 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1370
1371 phydev_info(phydev, "Detected external RTL8214C\n");
1372
1373 /* GPHY auto conf */
1374 write_phy(mac, 0xa42, 29, 0);
1375 return 0;
1376 }
1377
1378 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1379 {
1380 u32 phy_id, val, page = 0;
1381 int i, l;
1382 int mac = phydev->mdio.addr;
1383 struct fw_header *h;
1384 u32 *rtl8380_rtl8214fc_perchip;
1385 u32 *rtl8380_rtl8214fc_perport;
1386
1387 read_phy(mac, 0, 2, &val);
1388 phy_id = val << 16;
1389 read_phy(mac, 0, 3, &val);
1390 phy_id |= val;
1391 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1392
1393 /* Read internal PHY id */
1394 write_phy(mac, 0, 30, 0x0001);
1395 write_phy(mac, 0, 31, 0x0a42);
1396 write_phy(mac, 31, 27, 0x0002);
1397 read_phy(mac, 31, 28, &val);
1398 if (val != 0x6276) {
1399 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1400 return -1;
1401 }
1402 phydev_info(phydev, "Detected external RTL8214FC\n");
1403
1404 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1405 if (!h)
1406 return -1;
1407
1408 if (h->phy != 0x8214fc00) {
1409 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1410 return -1;
1411 }
1412
1413 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
1414 + h->parts[0].start;
1415
1416 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
1417 + h->parts[1].start;
1418
1419 /* detect phy version */
1420 write_phy(mac, 0xfff, 27, 0x0004);
1421 read_phy(mac, 0xfff, 28, &val);
1422
1423 read_phy(mac, 0, 16, &val);
1424 if (val & (1 << 11))
1425 rtl8380_rtl8214fc_on_off(mac, true);
1426 else
1427 rtl8380_phy_reset(mac);
1428
1429 msleep(100);
1430 write_phy(mac, 0, 30, 0x0001);
1431
1432 i = 0;
1433 while (rtl8380_rtl8214fc_perchip[i * 3]
1434 && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1435 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1436 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1437 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1438 read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val);
1439 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
1440 & 0xe0ff);
1441 write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
1442 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1443 } else {
1444 write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
1445 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1],
1446 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1447 }
1448 i++;
1449 }
1450
1451 /* Force copper medium */
1452 for (i = 0; i < 4; i++) {
1453 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1454 write_phy(mac + i, 0xfff, 0x1e, 0x0001);
1455 }
1456
1457 /* Enable PHY */
1458 for (i = 0; i < 4; i++) {
1459 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1460 write_phy(mac + i, 0xfff, 0x00, 0x1140);
1461 }
1462 mdelay(100);
1463
1464 /* Disable Autosensing */
1465 for (i = 0; i < 4; i++) {
1466 for (l = 0; l < 100; l++) {
1467 read_phy(mac + i, 0x0a42, 0x10, &val);
1468 if ((val & 0x7) >= 3)
1469 break;
1470 }
1471 if (l >= 100) {
1472 phydev_err(phydev, "Could not disable autosensing\n");
1473 return -1;
1474 }
1475 }
1476
1477 /* Request patch */
1478 for (i = 0; i < 4; i++) {
1479 write_phy(mac + i, 0xfff, 0x1f, 0x0b82);
1480 write_phy(mac + i, 0xfff, 0x10, 0x0010);
1481 }
1482 mdelay(300);
1483
1484 /* Verify patch readiness */
1485 for (i = 0; i < 4; i++) {
1486 for (l = 0; l < 100; l++) {
1487 read_phy(mac + i, 0xb80, 0x10, &val);
1488 if (val & 0x40)
1489 break;
1490 }
1491 if (l >= 100) {
1492 phydev_err(phydev, "Could not patch PHY\n");
1493 return -1;
1494 }
1495 }
1496
1497 /* Use Broadcast ID method for patching */
1498 write_phy(mac, 0xfff, 0x1f, 0x0000);
1499 write_phy(mac, 0xfff, 0x1d, 0x0008);
1500 write_phy(mac, 0xfff, 0x1f, 0x0266);
1501 write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
1502 write_phy(mac, 0xfff, 0x1f, 0x0000);
1503 write_phy(mac, 0xfff, 0x1d, 0x0000);
1504 mdelay(1);
1505
1506 i = 0;
1507 while (rtl8380_rtl8214fc_perport[i * 2]) {
1508 write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2],
1509 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1510 i++;
1511 }
1512
1513 /*Disable broadcast ID*/
1514 write_phy(mac, 0xfff, 0x1f, 0x0000);
1515 write_phy(mac, 0xfff, 0x1d, 0x0008);
1516 write_phy(mac, 0xfff, 0x1f, 0x0266);
1517 write_phy(mac, 0xfff, 0x16, 0x00 + mac);
1518 write_phy(mac, 0xfff, 0x1f, 0x0000);
1519 write_phy(mac, 0xfff, 0x1d, 0x0000);
1520 mdelay(1);
1521
1522 /* Auto medium selection */
1523 for (i = 0; i < 4; i++) {
1524 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1525 write_phy(mac + i, 0xfff, 0x1e, 0x0000);
1526 }
1527
1528 return 0;
1529 }
1530
1531 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1532 {
1533 int addr = phydev->mdio.addr;
1534
1535 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1536 }
1537
1538 static int rtl8380_configure_serdes(struct phy_device *phydev)
1539 {
1540 u32 v;
1541 u32 sds_conf_value;
1542 int i;
1543 struct fw_header *h;
1544 u32 *rtl8380_sds_take_reset;
1545 u32 *rtl8380_sds_common;
1546 u32 *rtl8380_sds01_qsgmii_6275b;
1547 u32 *rtl8380_sds23_qsgmii_6275b;
1548 u32 *rtl8380_sds4_fiber_6275b;
1549 u32 *rtl8380_sds5_fiber_6275b;
1550 u32 *rtl8380_sds_reset;
1551 u32 *rtl8380_sds_release_reset;
1552
1553 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1554
1555 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1556 if (!h)
1557 return -1;
1558
1559 if (h->magic != 0x83808380) {
1560 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1561 return -1;
1562 }
1563
1564 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
1565 + h->parts[0].start;
1566
1567 rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
1568 + h->parts[1].start;
1569
1570 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1571 + h->parts[2].start;
1572
1573 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1574 + h->parts[3].start;
1575
1576 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
1577 + h->parts[4].start;
1578
1579 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
1580 + h->parts[5].start;
1581
1582 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
1583 + h->parts[6].start;
1584
1585 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
1586 + h->parts[7].start;
1587
1588 /* Back up serdes power off value */
1589 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1590 pr_info("SDS power down value: %x\n", sds_conf_value);
1591
1592 /* take serdes into reset */
1593 i = 0;
1594 while (rtl8380_sds_take_reset[2 * i]) {
1595 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1596 i++;
1597 udelay(1000);
1598 }
1599
1600 /* apply common serdes patch */
1601 i = 0;
1602 while (rtl8380_sds_common[2 * i]) {
1603 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1604 i++;
1605 udelay(1000);
1606 }
1607
1608 /* internal R/W enable */
1609 sw_w32(3, RTL838X_INT_RW_CTRL);
1610
1611 /* SerDes ports 4 and 5 are FIBRE ports */
1612 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1613
1614 /* SerDes module settings, SerDes 0-3 are QSGMII */
1615 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1616 /* SerDes 4 and 5 are 1000BX FIBRE */
1617 v |= 0x4 << 5 | 0x4;
1618 sw_w32(v, RTL838X_SDS_MODE_SEL);
1619
1620 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1621 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1622 i = 0;
1623 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1624 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1625 rtl8380_sds01_qsgmii_6275b[2 * i]);
1626 i++;
1627 }
1628
1629 i = 0;
1630 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1631 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1632 i++;
1633 }
1634
1635 i = 0;
1636 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1637 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1638 i++;
1639 }
1640
1641 i = 0;
1642 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1643 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1644 i++;
1645 }
1646
1647 i = 0;
1648 while (rtl8380_sds_reset[2 * i]) {
1649 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1650 i++;
1651 }
1652
1653 i = 0;
1654 while (rtl8380_sds_release_reset[2 * i]) {
1655 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1656 i++;
1657 }
1658
1659 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1660 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1661
1662 pr_info("Configuration of SERDES done\n");
1663 return 0;
1664 }
1665
1666 static int rtl8390_configure_serdes(struct phy_device *phydev)
1667 {
1668 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1669
1670 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1671 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1672
1673 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1674 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1675 * and FRE16_EEE_QUIET_FIB1G
1676 */
1677 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1678
1679 return 0;
1680 }
1681
1682 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1683 {
1684 int l = end_bit - start_bit + 1;
1685 u32 data = v;
1686
1687 if (l < 32) {
1688 u32 mask = BIT(l) - 1;
1689
1690 data = rtl930x_read_sds_phy(sds, page, reg);
1691 data &= ~(mask << start_bit);
1692 data |= (v & mask) << start_bit;
1693 }
1694
1695 rtl930x_write_sds_phy(sds, page, reg, data);
1696 }
1697
1698 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1699 {
1700 int l = end_bit - start_bit + 1;
1701 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1702
1703 if (l >= 32)
1704 return v;
1705
1706 return (v >> start_bit) & (BIT(l) - 1);
1707 }
1708
1709 /* Read the link and speed status of the internal SerDes of the RTL9300
1710 */
1711 static int rtl9300_read_status(struct phy_device *phydev)
1712 {
1713 struct device *dev = &phydev->mdio.dev;
1714 int phy_addr = phydev->mdio.addr;
1715 struct device_node *dn;
1716 u32 sds_num = 0, status, latch_status, mode;
1717
1718 if (dev->of_node) {
1719 dn = dev->of_node;
1720
1721 if (of_property_read_u32(dn, "sds", &sds_num))
1722 sds_num = -1;
1723 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1724 } else {
1725 dev_err(dev, "No DT node.\n");
1726 return -EINVAL;
1727 }
1728
1729 if (sds_num < 0)
1730 return 0;
1731
1732 mode = rtl9300_sds_mode_get(sds_num);
1733 pr_info("%s got SDS mode %02x\n", __func__, mode);
1734 if (mode == 0x1a) { // 10GR mode
1735 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1736 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1737 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1738 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1739 } else {
1740 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1741 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1742 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1743 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1744 }
1745
1746 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1747
1748 if (latch_status) {
1749 phydev->link = true;
1750 if (mode == 0x1a)
1751 phydev->speed = SPEED_10000;
1752 else
1753 phydev->speed = SPEED_1000;
1754
1755 phydev->duplex = DUPLEX_FULL;
1756 }
1757
1758 return 0;
1759 }
1760
1761 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1762 {
1763 int page = 0x2e; // 10GR and USXGMII
1764
1765 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1766 page = 0x24;
1767
1768 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1769 mdelay(5);
1770 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1771 }
1772
1773 /*
1774 * Force PHY modes on 10GBit Serdes
1775 */
1776 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1777 {
1778 int sds_mode;
1779 bool lc_on;
1780 int i, lc_value;
1781 int lane_0 = (sds % 2) ? sds - 1 : sds;
1782 u32 v, cr_0, cr_1, cr_2;
1783 u32 m_bit, l_bit;
1784
1785 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1786 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1787 switch (phy_if) {
1788 case PHY_INTERFACE_MODE_SGMII:
1789 sds_mode = 0x2;
1790 lc_on = false;
1791 lc_value = 0x1;
1792 break;
1793
1794 case PHY_INTERFACE_MODE_HSGMII:
1795 sds_mode = 0x12;
1796 lc_value = 0x3;
1797 // Configure LC
1798 break;
1799
1800 case PHY_INTERFACE_MODE_1000BASEX:
1801 sds_mode = 0x04;
1802 lc_on = false;
1803 break;
1804
1805 case PHY_INTERFACE_MODE_2500BASEX:
1806 sds_mode = 0x16;
1807 lc_value = 0x3;
1808 // Configure LC
1809 break;
1810
1811 case PHY_INTERFACE_MODE_10GBASER:
1812 sds_mode = 0x1a;
1813 lc_on = true;
1814 lc_value = 0x5;
1815 break;
1816
1817 case PHY_INTERFACE_MODE_NA:
1818 // This will disable SerDes
1819 sds_mode = 0x1f;
1820 break;
1821
1822 default:
1823 pr_err("%s: unknown serdes mode: %s\n",
1824 __func__, phy_modes(phy_if));
1825 return;
1826 }
1827
1828 pr_info("%s: SDS mode %x\n", __func__, sds_mode);
1829 // Power down SerDes
1830 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1831 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1832
1833 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1834 // Force mode enable
1835 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1836 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1837
1838 /* SerDes off */
1839 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1840
1841 if (phy_if == PHY_INTERFACE_MODE_NA)
1842 return;
1843
1844 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1845 // Enable LC and ring
1846 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1847
1848 if (sds == lane_0)
1849 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1850 else
1851 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1852
1853 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1854
1855 if (lc_on)
1856 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1857 else
1858 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1859
1860 // Force analog LC & ring on
1861 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1862
1863 v = lc_on ? 0x3 : 0x1;
1864
1865 if (sds == lane_0)
1866 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1867 else
1868 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1869
1870 // Force SerDes mode
1871 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1872 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1873
1874 // Toggle LC or Ring
1875 for (i = 0; i < 20; i++) {
1876 mdelay(200);
1877
1878 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1879
1880 m_bit = (lane_0 == sds) ? (4) : (5);
1881 l_bit = (lane_0 == sds) ? (4) : (5);
1882
1883 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1884 mdelay(10);
1885 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1886 mdelay(10);
1887 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1888
1889 if (cr_0 && cr_1 && cr_2) {
1890 u32 t;
1891 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1892 break;
1893
1894 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1895 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1896
1897 // Reset FSM
1898 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1899 mdelay(10);
1900 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1901 mdelay(10);
1902
1903 // Need to read this twice
1904 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1905 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1906
1907 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1908
1909 // Reset FSM again
1910 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1911 mdelay(10);
1912 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1913 mdelay(10);
1914
1915 if (v == 1)
1916 break;
1917 }
1918
1919 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1920 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1921
1922 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1923 mdelay(10);
1924 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1925 }
1926
1927 rtl930x_sds_rx_rst(sds, phy_if);
1928
1929 // Re-enable power
1930 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1931
1932 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1933 }
1934
1935 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1936 {
1937 // parameters: rtl9303_80G_txParam_s2
1938 int impedance = 0x8;
1939 int pre_amp = 0x2;
1940 int main_amp = 0x9;
1941 int post_amp = 0x2;
1942 int pre_en = 0x1;
1943 int post_en = 0x1;
1944 int page;
1945
1946 switch(phy_if) {
1947 case PHY_INTERFACE_MODE_1000BASEX:
1948 page = 0x25;
1949 break;
1950 case PHY_INTERFACE_MODE_HSGMII:
1951 case PHY_INTERFACE_MODE_2500BASEX:
1952 page = 0x29;
1953 break;
1954 case PHY_INTERFACE_MODE_10GBASER:
1955 page = 0x2f;
1956 break;
1957 default:
1958 pr_err("%s: unsupported PHY mode\n", __func__);
1959 return;
1960 }
1961
1962 rtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp);
1963 rtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en);
1964 rtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp);
1965 rtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp);
1966 rtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en);
1967 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1968 }
1969
1970 /*
1971 * Wait for clock ready, this assumes the SerDes is in XGMII mode
1972 * timeout is in ms
1973 */
1974 int rtl9300_sds_clock_wait(int timeout)
1975 {
1976 u32 v;
1977 unsigned long start = jiffies;
1978
1979 do {
1980 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1981 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1982 if (v == 3)
1983 return 0;
1984 } while (jiffies < start + (HZ / 1000) * timeout);
1985
1986 return 1;
1987 }
1988
1989 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1990 {
1991 u32 v10, v1;
1992
1993 v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2
1994 v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0
1995 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1996
1997 v10 &= ~(BIT(13) | BIT(14));
1998 v1 &= ~(BIT(8) | BIT(9));
1999
2000 v10 |= rx_normal ? 0 : BIT(13);
2001 v1 |= rx_normal ? 0 : BIT(9);
2002
2003 v10 |= tx_normal ? 0 : BIT(14);
2004 v1 |= tx_normal ? 0 : BIT(8);
2005
2006 rtl930x_write_sds_phy(sds, 6, 2, v10);
2007 rtl930x_write_sds_phy(sds, 0, 0, v1);
2008
2009 v10 = rtl930x_read_sds_phy(sds, 6, 2);
2010 v1 = rtl930x_read_sds_phy(sds, 0, 0);
2011 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
2012 }
2013
2014 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
2015 {
2016 if (manual) {
2017 switch(dcvs_id) {
2018 case 0:
2019 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
2020 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
2021 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
2022 break;
2023 case 1:
2024 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
2025 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
2026 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
2027 break;
2028 case 2:
2029 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
2030 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
2031 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
2032 break;
2033 case 3:
2034 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
2035 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
2036 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
2037 break;
2038 case 4:
2039 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
2040 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
2041 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
2042 break;
2043 case 5:
2044 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
2045 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
2046 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
2047 break;
2048 default:
2049 break;
2050 }
2051 } else {
2052 switch(dcvs_id) {
2053 case 0:
2054 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
2055 break;
2056 case 1:
2057 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
2058 break;
2059 case 2:
2060 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
2061 break;
2062 case 3:
2063 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
2064 break;
2065 case 4:
2066 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
2067 break;
2068 case 5:
2069 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
2070 break;
2071 default:
2072 break;
2073 }
2074 mdelay(1);
2075 }
2076 }
2077
2078 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
2079 {
2080 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
2081 bool dcvs_manual;
2082
2083 if (!(sds_num % 2))
2084 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2085 else
2086 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2087
2088 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2089 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2090
2091 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2092 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2093
2094 switch(dcvs_id) {
2095 case 0:
2096 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2097 mdelay(1);
2098
2099 // ##DCVS0 Read Out
2100 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2101 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2102 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2103 break;
2104
2105 case 1:
2106 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2107 mdelay(1);
2108
2109 // ##DCVS0 Read Out
2110 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2111 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2112 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2113 break;
2114
2115 case 2:
2116 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2117 mdelay(1);
2118
2119 // ##DCVS0 Read Out
2120 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2121 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2122 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2123 break;
2124 case 3:
2125 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2126 mdelay(1);
2127
2128 // ##DCVS0 Read Out
2129 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2130 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2131 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2132 break;
2133
2134 case 4:
2135 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2136 mdelay(1);
2137
2138 // ##DCVS0 Read Out
2139 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2140 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2141 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2142 break;
2143
2144 case 5:
2145 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2146 mdelay(1);
2147
2148 // ##DCVS0 Read Out
2149 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2150 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2151 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2152 break;
2153
2154 default:
2155 break;
2156 }
2157
2158 if (dcvs_sign_out)
2159 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2160 else
2161 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2162
2163 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2164 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2165
2166 dcvs_list[0] = dcvs_sign_out;
2167 dcvs_list[1] = dcvs_coef_bin;
2168 }
2169
2170 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2171 {
2172 if (manual) {
2173 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2174 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2175 } else {
2176 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2177 mdelay(100);
2178 }
2179 }
2180
2181 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2182 {
2183 if (manual) {
2184 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2185 } else {
2186 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2187 mdelay(1);
2188 }
2189 }
2190
2191 #define GRAY_BITS 5
2192 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2193 {
2194 int i, j, m;
2195 u32 g[GRAY_BITS];
2196 u32 c[GRAY_BITS];
2197 u32 leq_binary = 0;
2198
2199 for(i = 0; i < GRAY_BITS; i++)
2200 g[i] = (gray_code & BIT(i)) >> i;
2201
2202 m = GRAY_BITS - 1;
2203
2204 c[m] = g[m];
2205
2206 for(i = 0; i < m; i++) {
2207 c[i] = g[i];
2208 for(j = i + 1; j < GRAY_BITS; j++)
2209 c[i] = c[i] ^ g[j];
2210 }
2211
2212 for(i = 0; i < GRAY_BITS; i++)
2213 leq_binary += c[i] << i;
2214
2215 return leq_binary;
2216 }
2217
2218 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2219 {
2220 u32 leq_gray, leq_bin;
2221 bool leq_manual;
2222
2223 if (!(sds_num % 2))
2224 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2225 else
2226 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2227
2228 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2229 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2230
2231 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]
2232 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2233 mdelay(1);
2234
2235 // ##LEQ Read Out
2236 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2237 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2238 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2239
2240 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2241 pr_info("LEQ manual: %u", leq_manual);
2242
2243 return leq_bin;
2244 }
2245
2246 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2247 {
2248 if (manual) {
2249 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2250 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2251 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2252 } else {
2253 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2254 mdelay(10);
2255 }
2256 }
2257
2258 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2259 {
2260 u32 vth_manual;
2261
2262 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0
2263 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1
2264 if (!(sds_num % 2))
2265 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2266 else
2267 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2268
2269 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2270 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2271 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2272 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2273 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]
2274 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2275
2276 mdelay(1);
2277
2278 //##VthP & VthN Read Out
2279 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin
2280 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin
2281
2282 pr_info("vth_set_bin = %d", vth_list[0]);
2283 pr_info("vth_set_bin = %d", vth_list[1]);
2284
2285 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2286 pr_info("Vth Maunal = %d", vth_manual);
2287 }
2288
2289 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2290 {
2291 if (manual) {
2292 switch(tap_id) {
2293 case 0:
2294 //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value
2295 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2296 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2297 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2298 break;
2299 case 1:
2300 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2301 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2302 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2303 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2304 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2305 break;
2306 case 2:
2307 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2308 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2309 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2310 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2311 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2312 break;
2313 case 3:
2314 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2315 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2316 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2317 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2318 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2319 break;
2320 case 4:
2321 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2322 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2323 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2324 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2325 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2326 break;
2327 default:
2328 break;
2329 }
2330 } else {
2331 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2332 mdelay(10);
2333 }
2334 }
2335
2336 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2337 {
2338 u32 tap0_sign_out;
2339 u32 tap0_coef_bin;
2340 u32 tap_sign_out_even;
2341 u32 tap_coef_bin_even;
2342 u32 tap_sign_out_odd;
2343 u32 tap_coef_bin_odd;
2344 bool tap_manual;
2345
2346 if (!(sds_num % 2))
2347 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2348 else
2349 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2350
2351 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2352 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2353 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2354 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2355
2356 if (!tap_id) {
2357 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2358 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2359 //##Tap1 Even Read Out
2360 mdelay(1);
2361 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2362 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2363
2364 if (tap0_sign_out == 1)
2365 pr_info("Tap0 Sign : -");
2366 else
2367 pr_info("Tap0 Sign : +");
2368
2369 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2370
2371 tap_list[0] = tap0_sign_out;
2372 tap_list[1] = tap0_coef_bin;
2373
2374 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2375 pr_info("tap0 manual = %u",tap_manual);
2376 } else {
2377 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2378 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2379 mdelay(1);
2380 //##Tap1 Even Read Out
2381 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2382 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2383
2384 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]
2385 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2386 //##Tap1 Odd Read Out
2387 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2388 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2389
2390 if (tap_sign_out_even == 1)
2391 pr_info("Tap %u even sign: -", tap_id);
2392 else
2393 pr_info("Tap %u even sign: +", tap_id);
2394
2395 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2396
2397 if (tap_sign_out_odd == 1)
2398 pr_info("Tap %u odd sign: -", tap_id);
2399 else
2400 pr_info("Tap %u odd sign: +", tap_id);
2401
2402 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2403
2404 tap_list[0] = tap_sign_out_even;
2405 tap_list[1] = tap_coef_bin_even;
2406 tap_list[2] = tap_sign_out_odd;
2407 tap_list[3] = tap_coef_bin_odd;
2408
2409 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2410 pr_info("tap %u manual = %d",tap_id, tap_manual);
2411 }
2412 }
2413
2414 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2415 {
2416 // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam
2417 int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap
2418 int vth_min = 0x0;
2419
2420 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2421 rtl930x_write_sds_phy(sds, 6, 0, 0);
2422
2423 // FGCAL
2424 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0);
2425 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2426 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1);
2427
2428 // DCVS
2429 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0);
2430 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0);
2431 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0);
2432 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0);
2433 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0);
2434 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0);
2435 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0);
2436 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0);
2437 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0);
2438 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf);
2439 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1);
2440 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1);
2441
2442 // LEQ (Long Term Equivalent signal level)
2443 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0);
2444
2445 // DFE (Decision Fed Equalizer)
2446 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2447 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0);
2448 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0);
2449 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0);
2450 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2451 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0);
2452 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0);
2453 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0);
2454 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2455
2456 // Vth
2457 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7);
2458 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7);
2459 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2460
2461 pr_info("end_1.1.1 --\n");
2462
2463 pr_info("start_1.1.2 Load DFE init. value\n");
2464
2465 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2466
2467 pr_info("end_1.1.2\n");
2468
2469 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2470
2471 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0);
2472 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0);
2473 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0);
2474 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1);
2475 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0);
2476 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0);
2477
2478 pr_info("end_1.1.3 --\n");
2479
2480 pr_info("start_1.1.4 offset cali setting\n");
2481
2482 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3);
2483
2484 pr_info("end_1.1.4\n");
2485
2486 pr_info("start_1.1.5 LEQ and DFE setting\n");
2487
2488 // TODO: make this work for DAC cables of different lengths
2489 // For a 10GBit serdes wit Fibre, SDS 8 or 9
2490 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2491 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2492 else
2493 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2494
2495 // No serdes, check for Aquantia PHYs
2496 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2497
2498 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2499 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2500 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2501 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2502 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3);
2503
2504 pr_info("end_1.1.5\n");
2505 }
2506
2507 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2508 {
2509 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2510
2511 // Gray config endis to 1
2512 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1);
2513
2514 // ForegroundOffsetCal_Manual(auto mode)
2515 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0);
2516
2517 pr_info("end_1.2.1");
2518 }
2519
2520 void rtl9300_do_rx_calibration_2_2(int sds_num)
2521 {
2522 //Force Rx-Run = 0
2523 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2524
2525 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2526 }
2527
2528 void rtl9300_do_rx_calibration_2_3(int sds_num)
2529 {
2530 u32 fgcal_binary, fgcal_gray;
2531 u32 offset_range;
2532
2533 pr_info("start_1.2.3 Foreground Calibration\n");
2534
2535 while(1) {
2536 if (!(sds_num % 2))
2537 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2538 else
2539 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2540
2541 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2542 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2543 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2544 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2545 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]
2546 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2547 // ##FGCAL read gray
2548 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2549 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]
2550 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2551 // ##FGCAL read binary
2552 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2553
2554 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2555 __func__, fgcal_gray, fgcal_binary);
2556
2557 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2558
2559 if (fgcal_binary > 60 || fgcal_binary < 3) {
2560 if (offset_range == 3) {
2561 pr_info("%s: Foreground Calibration result marginal!", __func__);
2562 break;
2563 } else {
2564 offset_range++;
2565 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2566 rtl9300_do_rx_calibration_2_2(sds_num);
2567 }
2568 } else {
2569 break;
2570 }
2571 }
2572 pr_info("%s: end_1.2.3\n", __func__);
2573 }
2574
2575 void rtl9300_do_rx_calibration_2(int sds)
2576 {
2577 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2578 rtl9300_do_rx_calibration_2_1(sds);
2579 rtl9300_do_rx_calibration_2_2(sds);
2580 rtl9300_do_rx_calibration_2_3(sds);
2581 }
2582
2583 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2584 {
2585 pr_info("start_1.3.1");
2586
2587 // ##1.3.1
2588 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2589 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2590
2591 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2592 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2593
2594 pr_info("end_1.3.1");
2595 }
2596
2597 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2598 {
2599 u32 sum10 = 0, avg10, int10;
2600 int dac_long_cable_offset;
2601 bool eq_hold_enabled;
2602 int i;
2603
2604 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2605 // rtl9300_rxCaliConf_serdes_myParam
2606 dac_long_cable_offset = 3;
2607 eq_hold_enabled = true;
2608 } else {
2609 // rtl9300_rxCaliConf_phy_myParam
2610 dac_long_cable_offset = 0;
2611 eq_hold_enabled = false;
2612 }
2613
2614 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2615 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2616
2617 pr_info("start_1.3.2");
2618
2619 for(i = 0; i < 10; i++) {
2620 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2621 mdelay(10);
2622 }
2623
2624 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2625 int10 = sum10 / 10;
2626
2627 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2628
2629 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2630 if (dac_long_cable_offset) {
2631 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2632 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2633 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2634 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2635 } else {
2636 if (sum10 >= 5) {
2637 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2638 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2639 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2640 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2641 } else {
2642 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2643 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2644 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2645 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2646 }
2647 }
2648 }
2649
2650 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2651
2652 pr_info("end_1.3.2");
2653 }
2654
2655 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2656 {
2657 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2658
2659 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2660 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2661 }
2662
2663 void rtl9300_do_rx_calibration_4_1(int sds_num)
2664 {
2665 u32 vth_list[2] = {0, 0};
2666 u32 tap0_list[4] = {0, 0, 0, 0};
2667
2668 pr_info("start_1.4.1");
2669
2670 // ##1.4.1
2671 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2672 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2673 mdelay(200);
2674
2675 pr_info("end_1.4.1");
2676 }
2677
2678 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2679 {
2680 u32 vth_list[2];
2681 u32 tap_list[4];
2682
2683 pr_info("start_1.4.2");
2684
2685 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2686 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2687
2688 mdelay(100);
2689
2690 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2691 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2692
2693 pr_info("end_1.4.2");
2694 }
2695
2696 void rtl9300_do_rx_calibration_4(u32 sds_num)
2697 {
2698 rtl9300_do_rx_calibration_4_1(sds_num);
2699 rtl9300_do_rx_calibration_4_2(sds_num);
2700 }
2701
2702 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2703 {
2704 u32 tap1_list[4] = {0};
2705 u32 tap2_list[4] = {0};
2706 u32 tap3_list[4] = {0};
2707 u32 tap4_list[4] = {0};
2708
2709 pr_info("start_1.5.2");
2710
2711 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2712 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2713 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2714 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2715
2716 mdelay(30);
2717
2718 pr_info("end_1.5.2");
2719 }
2720
2721 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2722 {
2723 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true
2724 rtl9300_do_rx_calibration_5_2(sds_num);
2725 }
2726
2727
2728 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2729 {
2730 u32 tap1_list[4] = {0};
2731 u32 tap2_list[4] = {0};
2732 u32 tap3_list[4] = {0};
2733 u32 tap4_list[4] = {0};
2734
2735 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2736 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2737 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2738 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2739
2740 mdelay(10);
2741 }
2742
2743 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2744 {
2745 u32 latch_sts;
2746
2747 rtl9300_do_rx_calibration_1(sds, phy_mode);
2748 rtl9300_do_rx_calibration_2(sds);
2749 rtl9300_do_rx_calibration_4(sds);
2750 rtl9300_do_rx_calibration_5(sds, phy_mode);
2751 mdelay(20);
2752
2753 // Do this only for 10GR mode, SDS active in mode 0x1a
2754 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2755 pr_info("%s: SDS enabled\n", __func__);
2756 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2757 mdelay(1);
2758 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2759 if (latch_sts) {
2760 rtl9300_do_rx_calibration_dfe_disable(sds);
2761 rtl9300_do_rx_calibration_4(sds);
2762 rtl9300_do_rx_calibration_5(sds, phy_mode);
2763 }
2764 }
2765 }
2766
2767 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2768 {
2769 switch (phy_mode) {
2770 case PHY_INTERFACE_MODE_XGMII:
2771 break;
2772
2773 case PHY_INTERFACE_MODE_10GBASER:
2774 // Read twice to clear
2775 rtl930x_read_sds_phy(sds_num, 5, 1);
2776 rtl930x_read_sds_phy(sds_num, 5, 1);
2777 break;
2778
2779 case PHY_INTERFACE_MODE_1000BASEX:
2780 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2781 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2782 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2783 break;
2784
2785 default:
2786 pr_info("%s unsupported phy mode\n", __func__);
2787 return -1;
2788 }
2789
2790 return 0;
2791 }
2792
2793 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2794 {
2795 u32 v = 0;
2796
2797 switch (phy_mode) {
2798 case PHY_INTERFACE_MODE_XGMII:
2799 break;
2800
2801 case PHY_INTERFACE_MODE_10GBASER:
2802 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2803 return v & 0xff;
2804
2805 default:
2806 pr_info("%s unsupported PHY-mode\n", __func__);
2807 }
2808
2809 return v;
2810 }
2811
2812 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2813 {
2814 u32 errors1, errors2;
2815
2816 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2817 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2818
2819 // Count errors during 1ms
2820 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2821 mdelay(1);
2822 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2823
2824 switch (phy_mode) {
2825 case PHY_INTERFACE_MODE_XGMII:
2826
2827 if ((errors2 - errors1 > 100)
2828 || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2829 pr_info("%s XSGMII error rate too high\n", __func__);
2830 return 1;
2831 }
2832 break;
2833 case PHY_INTERFACE_MODE_10GBASER:
2834 if (errors2 > 0) {
2835 pr_info("%s 10GBASER error rate too high\n", __func__);
2836 return 1;
2837 }
2838 break;
2839 default:
2840 return 1;
2841 }
2842 return 0;
2843 }
2844
2845 void rtl9300_phy_enable_10g_1g(int sds_num)
2846 {
2847 u32 v;
2848
2849 // Enable 1GBit PHY
2850 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);
2851 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2852 v &= ~BIT(PHY_POWER_BIT);
2853 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);
2854 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2855
2856 // Enable 10GBit PHY
2857 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);
2858 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2859 v &= ~BIT(PHY_POWER_BIT);
2860 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);
2861 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2862
2863 // dal_longan_construct_mac_default_10gmedia_fiber
2864 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2865 pr_info("%s set medium: %08x\n", __func__, v);
2866 v |= BIT(1);
2867 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2868 pr_info("%s set medium after: %08x\n", __func__, v);
2869 }
2870
2871 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2872 // phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a
2873 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2874 {
2875 int sds_mode;
2876 int calib_tries = 0;
2877
2878 switch (phy_mode) {
2879 case PHY_INTERFACE_MODE_HSGMII:
2880 sds_mode = 0x12;
2881 break;
2882 case PHY_INTERFACE_MODE_1000BASEX:
2883 sds_mode = 0x04;
2884 break;
2885 case PHY_INTERFACE_MODE_XGMII:
2886 sds_mode = 0x10;
2887 break;
2888 case PHY_INTERFACE_MODE_10GBASER:
2889 sds_mode = 0x1a;
2890 break;
2891 case PHY_INTERFACE_MODE_USXGMII:
2892 sds_mode = 0x0d;
2893 break;
2894 default:
2895 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2896 return -EINVAL;
2897 }
2898
2899 // Maybe use dal_longan_sds_init
2900
2901 // dal_longan_construct_serdesConfig_init // Serdes Construct
2902 rtl9300_phy_enable_10g_1g(sds_num);
2903
2904 // Set Serdes Mode
2905 rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO
2906
2907 // Do RX calibration
2908 do {
2909 rtl9300_do_rx_calibration(sds_num, phy_mode);
2910 calib_tries++;
2911 mdelay(50);
2912 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2913
2914
2915 return 0;
2916 }
2917
2918 typedef struct {
2919 u8 page;
2920 u8 reg;
2921 u16 data;
2922 } sds_config;
2923
2924 sds_config rtl9300_a_sds_10gr_lane0[] =
2925 {
2926 /*1G*/
2927 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2928 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2929 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2930 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2931 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2932 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2933 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2934 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2935 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2936 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2937 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2938 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2939 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2940 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2941 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2942 {0x2F, 0x1D, 0x66E1},
2943 /*3.125G*/
2944 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2945 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2946 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2947 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2948 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2949 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2950 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2951 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2952 /*10G*/
2953 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2954 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2955 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2956 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2957 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2958 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2959 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2960 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2961 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2962 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2963 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2964 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2965 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2966 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2967 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2968 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2969 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2970 };
2971
2972 sds_config rtl9300_a_sds_10gr_lane1[] =
2973 {
2974 /*1G*/
2975 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2976 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2977 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2978 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2979 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2980 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2981 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2982 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2983 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2984 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2985 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2986 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2987 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2988 {0x2D, 0x14, 0x1808},
2989 /*3.125G*/
2990 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2991 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2992 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2993 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2994 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2995 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2996 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2997 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2998 /*10G*/
2999 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
3000 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
3001 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
3002 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
3003 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
3004 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
3005 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
3006 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
3007 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
3008 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
3009 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
3010 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
3011 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
3012 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
3013 };
3014
3015 int rtl9300_sds_cmu_band_get(int sds)
3016 {
3017 u32 page;
3018 u32 en;
3019 u32 cmu_band;
3020
3021 // page = rtl9300_sds_cmu_page_get(sds);
3022 page = 0x25; // 10GR and 1000BX
3023 sds = (sds % 2) ? (sds - 1) : (sds);
3024
3025 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
3026 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
3027
3028 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
3029 if(!en) { // Auto mode
3030 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
3031
3032 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
3033 } else {
3034 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
3035 }
3036
3037 return cmu_band;
3038 }
3039
3040 int rtl9300_configure_serdes(struct phy_device *phydev)
3041 {
3042 struct device *dev = &phydev->mdio.dev;
3043 int phy_addr = phydev->mdio.addr;
3044 struct device_node *dn;
3045 u32 sds_num = 0;
3046 int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i;
3047
3048 if (dev->of_node) {
3049 dn = dev->of_node;
3050
3051 if (of_property_read_u32(dn, "sds", &sds_num))
3052 sds_num = -1;
3053 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
3054 } else {
3055 dev_err(dev, "No DT node.\n");
3056 return -EINVAL;
3057 }
3058
3059 if (sds_num < 0)
3060 return 0;
3061
3062 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes
3063 return 0;
3064
3065 switch (phy_mode) {
3066 case PHY_INTERFACE_MODE_HSGMII:
3067 sds_mode = 0x12;
3068 break;
3069 case PHY_INTERFACE_MODE_1000BASEX:
3070 sds_mode = 0x04;
3071 break;
3072 case PHY_INTERFACE_MODE_XGMII:
3073 sds_mode = 0x10;
3074 break;
3075 case PHY_INTERFACE_MODE_10GBASER:
3076 sds_mode = 0x1a;
3077 break;
3078 case PHY_INTERFACE_MODE_USXGMII:
3079 sds_mode = 0x0d;
3080 break;
3081 default:
3082 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
3083 return -EINVAL;
3084 }
3085
3086 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
3087
3088 // Turn Off Serdes
3089 rtl9300_sds_rst(sds_num, 0x1f);
3090
3091 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
3092 if (sds_num % 2) {
3093 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
3094 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
3095 rtl9300_a_sds_10gr_lane1[i].reg,
3096 rtl9300_a_sds_10gr_lane1[i].data);
3097 }
3098 } else {
3099 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
3100 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3101 rtl9300_a_sds_10gr_lane0[i].reg,
3102 rtl9300_a_sds_10gr_lane0[i].data);
3103 }
3104 }
3105
3106 rtl9300_phy_enable_10g_1g(sds_num);
3107
3108 // Disable MAC
3109 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3110 mdelay(20);
3111
3112 // ----> dal_longan_sds_mode_set
3113 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3114
3115 // Configure link to MAC
3116 rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct
3117
3118 // Disable MAC
3119 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3120 mdelay(20);
3121
3122 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3123
3124 // Re-Enable MAC
3125 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3126
3127 rtl9300_force_sds_mode(sds_num, phy_mode);
3128
3129 // Do RX calibration
3130 do {
3131 rtl9300_do_rx_calibration(sds_num, phy_mode);
3132 calib_tries++;
3133 mdelay(50);
3134 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3135
3136 if (calib_tries >= 3)
3137 pr_err("%s CALIBTRATION FAILED\n", __func__);
3138
3139 rtl9300_sds_tx_config(sds_num, phy_mode);
3140
3141 // The clock needs only to be configured on the FPGA implementation
3142
3143 return 0;
3144 }
3145
3146 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3147 {
3148 int l = end_bit - start_bit + 1;
3149 u32 data = v;
3150
3151 if (l < 32) {
3152 u32 mask = BIT(l) - 1;
3153
3154 data = rtl930x_read_sds_phy(sds, page, reg);
3155 data &= ~(mask << start_bit);
3156 data |= (v & mask) << start_bit;
3157 }
3158
3159 rtl931x_write_sds_phy(sds, page, reg, data);
3160 }
3161
3162
3163 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3164 {
3165 int l = end_bit - start_bit + 1;
3166 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3167
3168 if (l >= 32)
3169 return v;
3170
3171 return (v >> start_bit) & (BIT(l) - 1);
3172 }
3173
3174 static void rtl931x_sds_rst(u32 sds)
3175 {
3176 u32 o, v, o_mode;
3177 int shift = ((sds & 0x3) << 3);
3178
3179 // TODO: We need to lock this!
3180
3181 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3182 v = o | BIT(sds);
3183 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3184
3185 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3186 v = BIT(7) | 0x1F;
3187 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3188 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3189
3190 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3191 }
3192
3193 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3194 {
3195 u32 i;
3196 u32 xsg_sdsid_0, xsg_sdsid_1;
3197
3198 switch (mode) {
3199 case PHY_INTERFACE_MODE_NA:
3200 break;
3201 case PHY_INTERFACE_MODE_XGMII:
3202 if (sds < 2)
3203 xsg_sdsid_0 = sds;
3204 else
3205 xsg_sdsid_0 = (sds - 1) * 2;
3206 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3207
3208 for (i = 0; i < 4; ++i) {
3209 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3210 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3211 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3212 }
3213
3214 for (i = 0; i < 4; ++i) {
3215 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3216 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3217 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3218 }
3219
3220 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3221 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3222 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3223 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3224 break;
3225 default:
3226 break;
3227 }
3228
3229 return;
3230 }
3231
3232 static u32 rtl931x_get_analog_sds(u32 sds)
3233 {
3234 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3235
3236 if (sds < 14)
3237 return sds_map[sds];
3238 return sds;
3239 }
3240
3241 void rtl931x_sds_fiber_disable(u32 sds)
3242 {
3243 u32 v = 0x3F;
3244 u32 asds = rtl931x_get_analog_sds(sds);
3245
3246 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3247 }
3248
3249 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3250 {
3251 u32 val, asds = rtl931x_get_analog_sds(sds);
3252
3253 /* clear symbol error count before changing mode */
3254 rtl931x_symerr_clear(sds, mode);
3255
3256 val = 0x9F;
3257 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3258
3259 switch (mode) {
3260 case PHY_INTERFACE_MODE_SGMII:
3261 val = 0x5;
3262 break;
3263
3264 case PHY_INTERFACE_MODE_1000BASEX:
3265 /* serdes mode FIBER1G */
3266 val = 0x9;
3267 break;
3268
3269 case PHY_INTERFACE_MODE_10GBASER:
3270 case PHY_INTERFACE_MODE_10GKR:
3271 val = 0x35;
3272 break;
3273 /* case MII_10GR1000BX_AUTO:
3274 val = 0x39;
3275 break; */
3276
3277
3278 case PHY_INTERFACE_MODE_USXGMII:
3279 val = 0x1B;
3280 break;
3281 default:
3282 val = 0x25;
3283 }
3284
3285 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3286 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3287
3288 return;
3289 }
3290
3291 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3292 {
3293 switch (mode) {
3294 case PHY_INTERFACE_MODE_SGMII:
3295 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO
3296 return 0x24;
3297 case PHY_INTERFACE_MODE_HSGMII:
3298 case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X:
3299 return 0x28;
3300 // case MII_HISGMII_5G:
3301 // return 0x2a;
3302 case PHY_INTERFACE_MODE_QSGMII:
3303 return 0x2a; // Code also has 0x34
3304 case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE:
3305 return 0x2c;
3306 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3307 case PHY_INTERFACE_MODE_10GKR:
3308 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR
3309 return 0x2e;
3310 default:
3311 return -1;
3312 }
3313 return -1;
3314 }
3315
3316 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3317 {
3318 int cmu_type = 0; // Clock Management Unit
3319 u32 cmu_page = 0;
3320 u32 frc_cmu_spd;
3321 u32 evenSds;
3322 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3323
3324 switch (mode) {
3325 case PHY_INTERFACE_MODE_NA:
3326 case PHY_INTERFACE_MODE_10GKR:
3327 case PHY_INTERFACE_MODE_XGMII:
3328 case PHY_INTERFACE_MODE_10GBASER:
3329 case PHY_INTERFACE_MODE_USXGMII:
3330 return;
3331
3332 /* case MII_10GR1000BX_AUTO:
3333 if (chiptype)
3334 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3335 return; */
3336
3337 case PHY_INTERFACE_MODE_QSGMII:
3338 cmu_type = 1;
3339 frc_cmu_spd = 0;
3340 break;
3341
3342 case PHY_INTERFACE_MODE_HSGMII:
3343 cmu_type = 1;
3344 frc_cmu_spd = 1;
3345 break;
3346
3347 case PHY_INTERFACE_MODE_1000BASEX:
3348 cmu_type = 1;
3349 frc_cmu_spd = 0;
3350 break;
3351
3352 /* case MII_1000BX100BX_AUTO:
3353 cmu_type = 1;
3354 frc_cmu_spd = 0;
3355 break; */
3356
3357 case PHY_INTERFACE_MODE_SGMII:
3358 cmu_type = 1;
3359 frc_cmu_spd = 0;
3360 break;
3361
3362 case PHY_INTERFACE_MODE_2500BASEX:
3363 cmu_type = 1;
3364 frc_cmu_spd = 1;
3365 break;
3366
3367 default:
3368 pr_info("SerDes %d mode is invalid\n", asds);
3369 return;
3370 }
3371
3372 if (cmu_type == 1)
3373 cmu_page = rtl931x_sds_cmu_page_get(mode);
3374
3375 lane = asds % 2;
3376
3377 if (!lane) {
3378 frc_lc_mode_bitnum = 4;
3379 frc_lc_mode_val_bitnum = 5;
3380 } else {
3381 frc_lc_mode_bitnum = 6;
3382 frc_lc_mode_val_bitnum = 7;
3383 }
3384
3385 evenSds = asds - lane;
3386
3387 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3388 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3389
3390 if (cmu_type == 1) {
3391 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3392 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3393 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3394 if (chiptype) {
3395 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3396 }
3397
3398 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3399 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3400 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3401 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3402 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3403 }
3404
3405 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3406 return;
3407 }
3408
3409 static void rtl931x_sds_rx_rst(u32 sds)
3410 {
3411 u32 asds = rtl931x_get_analog_sds(sds);
3412
3413 if (sds < 2)
3414 return;
3415
3416 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3417 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3418 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3419 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3420
3421 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3422 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3423 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3424 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3425
3426 mdelay(50);
3427 }
3428
3429 static void rtl931x_sds_disable(u32 sds)
3430 {
3431 u32 v = 0x1f;
3432
3433 v |= BIT(7);
3434 sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3435 }
3436
3437 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3438 {
3439 u32 val;
3440
3441 switch (mode) {
3442 case PHY_INTERFACE_MODE_QSGMII:
3443 val = 0x6;
3444 break;
3445 case PHY_INTERFACE_MODE_XGMII:
3446 val = 0x10; // serdes mode XSGMII
3447 break;
3448 case PHY_INTERFACE_MODE_USXGMII:
3449 case PHY_INTERFACE_MODE_2500BASEX:
3450 val = 0xD;
3451 break;
3452 case PHY_INTERFACE_MODE_HSGMII:
3453 val = 0x12;
3454 break;
3455 case PHY_INTERFACE_MODE_SGMII:
3456 val = 0x2;
3457 break;
3458 default:
3459 return;
3460 }
3461
3462 val |= (1 << 7);
3463
3464 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3465 }
3466
3467 static sds_config sds_config_10p3125g_type1[] = {
3468 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3469 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3470 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3471 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3472 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3473 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3474 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3475 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3476 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3477 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3478 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3479 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3480 { 0x2F, 0x13, 0x0000 }
3481 };
3482
3483 static sds_config sds_config_10p3125g_cmu_type1[] = {
3484 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3485 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3486 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3487 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3488 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3489 };
3490
3491 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3492 {
3493
3494 u32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3,
3495 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163
3496 };
3497
3498 u32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200,
3499 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3
3500 };
3501
3502 u32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160,
3503 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3
3504 };
3505
3506 u32 asds, dSds, ori, model_info, val;
3507 int chiptype = 0;
3508
3509 asds = rtl931x_get_analog_sds(sds);
3510
3511 if (sds > 13)
3512 return;
3513
3514 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3515 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3516
3517 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3518 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3519 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3520 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3521 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3522 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3523 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3524 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3525 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3526 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3527 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3528 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3529
3530 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3531 if ((model_info >> 4) & 0x1) {
3532 pr_info("detected chiptype 1\n");
3533 chiptype = 1;
3534 } else {
3535 pr_info("detected chiptype 0\n");
3536 }
3537
3538 if (sds < 2)
3539 dSds = sds;
3540 else
3541 dSds = (sds - 1) * 2;
3542
3543 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3544 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3545
3546 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3547 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3548 val = ori | (1 << sds);
3549 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3550
3551 switch (mode) {
3552 case PHY_INTERFACE_MODE_NA:
3553 break;
3554
3555 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3556
3557 if (chiptype) {
3558 u32 xsg_sdsid_1;
3559 xsg_sdsid_1 = dSds + 1;
3560 //fifo inv clk
3561 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3562 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3563
3564 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3565 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3566
3567 }
3568
3569 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3570 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3571 break;
3572
3573 case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:
3574 u32 i, evenSds;
3575 u32 op_code = 0x6003;
3576
3577 if (chiptype) {
3578 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3579
3580 for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3581 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3582 }
3583
3584 evenSds = asds - (asds % 2);
3585
3586 for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3587 rtl931x_write_sds_phy(evenSds,
3588 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3589 }
3590
3591 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3592 } else {
3593
3594 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3595 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3596
3597 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3598 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3599 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3600 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3601 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3602
3603 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3604 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3605
3606 rtl931x_sds_rx_rst(sds);
3607
3608 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3609 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3610 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3611 }
3612 break;
3613
3614 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO:
3615 // configure 10GR fiber mode=1
3616 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3617
3618 // init fiber_1g
3619 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3620
3621 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3622 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3623 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3624
3625 // init auto
3626 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3627 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3628 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3629 break;
3630
3631 case PHY_INTERFACE_MODE_HSGMII:
3632 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3633 break;
3634
3635 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER
3636 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3637
3638 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3639 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3640 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3641 break;
3642
3643 case PHY_INTERFACE_MODE_SGMII:
3644 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3645 break;
3646
3647 case PHY_INTERFACE_MODE_2500BASEX:
3648 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3649 break;
3650
3651 case PHY_INTERFACE_MODE_QSGMII:
3652 default:
3653 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3654 __func__, phy_modes(mode), sds);
3655 return;
3656 }
3657
3658 rtl931x_cmu_type_set(asds, mode, chiptype);
3659
3660 if (sds >= 2 && sds <= 13) {
3661 if (chiptype)
3662 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3663 else {
3664 val = 0xa0000;
3665 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3666 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3667 if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))
3668 {
3669 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3670 } else {
3671 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3672 }
3673 val = 0;
3674 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3675 }
3676 }
3677
3678 val = ori & ~BIT(sds);
3679 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3680 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3681
3682 if (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII
3683 || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII
3684 || mode == PHY_INTERFACE_MODE_USXGMII) {
3685 if (mode == PHY_INTERFACE_MODE_XGMII)
3686 rtl931x_sds_mii_mode_set(sds, mode);
3687 else
3688 rtl931x_sds_fiber_mode_set(sds, mode);
3689 }
3690 }
3691
3692 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3693 {
3694 u32 asds;
3695 int page = rtl931x_sds_cmu_page_get(mode);
3696
3697 sds -= (sds % 2);
3698 sds = sds & ~1;
3699 asds = rtl931x_get_analog_sds(sds);
3700 page += 1;
3701
3702 if (enable) {
3703 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3704 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3705 } else {
3706 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3707 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3708 }
3709
3710 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3711
3712 rtl931x_sds_rst(sds);
3713
3714 return 0;
3715 }
3716
3717 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3718 {
3719 int page = rtl931x_sds_cmu_page_get(mode);
3720 u32 asds, band;
3721
3722 sds -= (sds % 2);
3723 asds = rtl931x_get_analog_sds(sds);
3724 page += 1;
3725 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3726
3727 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3728 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3729 pr_info("%s band is: %d\n", __func__, band);
3730
3731 return band;
3732 }
3733
3734
3735 int rtl931x_link_sts_get(u32 sds)
3736 {
3737 u32 sts, sts1, latch_sts, latch_sts1;
3738 if (0){
3739 u32 xsg_sdsid_0, xsg_sdsid_1;
3740
3741 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3742 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3743
3744 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3745 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3746 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3747 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3748 } else {
3749 u32 asds, dsds;
3750
3751 asds = rtl931x_get_analog_sds(sds);
3752 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3753 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3754
3755 dsds = sds < 2 ? sds : (sds - 1) * 2;
3756 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3757 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3758 }
3759
3760 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3761 sds, sts, sts1, latch_sts, latch_sts1);
3762 return sts1;
3763 }
3764
3765 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3766 {
3767 struct device *dev = &phydev->mdio.dev;
3768 struct rtl838x_phy_priv *priv;
3769 int addr = phydev->mdio.addr;
3770
3771 /* 839x has internal SerDes */
3772 if (soc_info.id == 0x8393)
3773 return -ENODEV;
3774
3775 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3776 if (!priv)
3777 return -ENOMEM;
3778
3779 priv->name = "RTL8214FC";
3780
3781 /* All base addresses of the PHYs start at multiples of 8 */
3782 if (!(addr % 8)) {
3783 /* Configuration must be done whil patching still possible */
3784 return rtl8380_configure_rtl8214fc(phydev);
3785 }
3786 return 0;
3787 }
3788
3789 static int rtl8214c_phy_probe(struct phy_device *phydev)
3790 {
3791 struct device *dev = &phydev->mdio.dev;
3792 struct rtl838x_phy_priv *priv;
3793 int addr = phydev->mdio.addr;
3794
3795 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3796 if (!priv)
3797 return -ENOMEM;
3798
3799 priv->name = "RTL8214C";
3800
3801 /* All base addresses of the PHYs start at multiples of 8 */
3802 if (!(addr % 8)) {
3803 /* Configuration must be done whil patching still possible */
3804 return rtl8380_configure_rtl8214c(phydev);
3805 }
3806 return 0;
3807 }
3808
3809 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3810 {
3811 struct device *dev = &phydev->mdio.dev;
3812 struct rtl838x_phy_priv *priv;
3813 int addr = phydev->mdio.addr;
3814
3815 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3816 if (!priv)
3817 return -ENOMEM;
3818
3819 priv->name = "RTL8218B (external)";
3820
3821 /* All base addresses of the PHYs start at multiples of 8 */
3822 if (!(addr % 8) && soc_info.family == RTL8380_FAMILY_ID) {
3823 /* Configuration must be done while patching still possible */
3824 return rtl8380_configure_ext_rtl8218b(phydev);
3825 }
3826 return 0;
3827 }
3828
3829 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3830 {
3831 struct device *dev = &phydev->mdio.dev;
3832 struct rtl838x_phy_priv *priv;
3833 int addr = phydev->mdio.addr;
3834
3835 if (soc_info.family != RTL8380_FAMILY_ID)
3836 return -ENODEV;
3837 if (addr >= 24)
3838 return -ENODEV;
3839
3840 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3841 if (!priv)
3842 return -ENOMEM;
3843
3844 priv->name = "RTL8218B (internal)";
3845
3846 /* All base addresses of the PHYs start at multiples of 8 */
3847 if (!(addr % 8)) {
3848 /* Configuration must be done while patching still possible */
3849 return rtl8380_configure_int_rtl8218b(phydev);
3850 }
3851 return 0;
3852 }
3853
3854 static int rtl8218d_phy_probe(struct phy_device *phydev)
3855 {
3856 struct device *dev = &phydev->mdio.dev;
3857 struct rtl838x_phy_priv *priv;
3858 int addr = phydev->mdio.addr;
3859
3860 pr_debug("%s: id: %d\n", __func__, addr);
3861 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3862 if (!priv)
3863 return -ENOMEM;
3864
3865 priv->name = "RTL8218D";
3866
3867 /* All base addresses of the PHYs start at multiples of 8 */
3868 if (!(addr % 8)) {
3869 /* Configuration must be done while patching still possible */
3870 // TODO: return configure_rtl8218d(phydev);
3871 }
3872 return 0;
3873 }
3874
3875 static int rtl8226_phy_probe(struct phy_device *phydev)
3876 {
3877 struct device *dev = &phydev->mdio.dev;
3878 struct rtl838x_phy_priv *priv;
3879 int addr = phydev->mdio.addr;
3880
3881 pr_info("%s: id: %d\n", __func__, addr);
3882 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3883 if (!priv)
3884 return -ENOMEM;
3885
3886 priv->name = "RTL8226";
3887
3888 return 0;
3889 }
3890
3891 static int rtl838x_serdes_probe(struct phy_device *phydev)
3892 {
3893 struct device *dev = &phydev->mdio.dev;
3894 struct rtl838x_phy_priv *priv;
3895 int addr = phydev->mdio.addr;
3896
3897 if (soc_info.family != RTL8380_FAMILY_ID)
3898 return -ENODEV;
3899 if (addr < 24)
3900 return -ENODEV;
3901
3902 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3903 if (!priv)
3904 return -ENOMEM;
3905
3906 priv->name = "RTL8380 Serdes";
3907
3908 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3909 if (soc_info.id == 0x8380) {
3910 if (addr == 24)
3911 return rtl8380_configure_serdes(phydev);
3912 return 0;
3913 }
3914 return -ENODEV;
3915 }
3916
3917 static int rtl8393_serdes_probe(struct phy_device *phydev)
3918 {
3919 struct device *dev = &phydev->mdio.dev;
3920 struct rtl838x_phy_priv *priv;
3921 int addr = phydev->mdio.addr;
3922
3923 pr_info("%s: id: %d\n", __func__, addr);
3924 if (soc_info.family != RTL8390_FAMILY_ID)
3925 return -ENODEV;
3926
3927 if (addr < 24)
3928 return -ENODEV;
3929
3930 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3931 if (!priv)
3932 return -ENOMEM;
3933
3934 priv->name = "RTL8393 Serdes";
3935 return rtl8390_configure_serdes(phydev);
3936 }
3937
3938 static int rtl8390_serdes_probe(struct phy_device *phydev)
3939 {
3940 struct device *dev = &phydev->mdio.dev;
3941 struct rtl838x_phy_priv *priv;
3942 int addr = phydev->mdio.addr;
3943
3944 if (soc_info.family != RTL8390_FAMILY_ID)
3945 return -ENODEV;
3946
3947 if (addr < 24)
3948 return -ENODEV;
3949
3950 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3951 if (!priv)
3952 return -ENOMEM;
3953
3954 priv->name = "RTL8390 Serdes";
3955 return rtl8390_configure_generic(phydev);
3956 }
3957
3958 static int rtl9300_serdes_probe(struct phy_device *phydev)
3959 {
3960 struct device *dev = &phydev->mdio.dev;
3961 struct rtl838x_phy_priv *priv;
3962
3963 if (soc_info.family != RTL9300_FAMILY_ID)
3964 return -ENODEV;
3965
3966 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3967 if (!priv)
3968 return -ENOMEM;
3969
3970 priv->name = "RTL9300 Serdes";
3971 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3972
3973 return rtl9300_configure_serdes(phydev);
3974 }
3975
3976 static struct phy_driver rtl83xx_phy_driver[] = {
3977 {
3978 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3979 .name = "Realtek RTL8214C",
3980 .features = PHY_GBIT_FEATURES,
3981 .match_phy_device = rtl8214c_match_phy_device,
3982 .probe = rtl8214c_phy_probe,
3983 .suspend = genphy_suspend,
3984 .resume = genphy_resume,
3985 .set_loopback = genphy_loopback,
3986 },
3987 {
3988 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3989 .name = "Realtek RTL8214FC",
3990 .features = PHY_GBIT_FIBRE_FEATURES,
3991 .match_phy_device = rtl8214fc_match_phy_device,
3992 .probe = rtl8214fc_phy_probe,
3993 .suspend = genphy_suspend,
3994 .resume = genphy_resume,
3995 .set_loopback = genphy_loopback,
3996 .read_mmd = rtl8218b_read_mmd,
3997 .write_mmd = rtl8218b_write_mmd,
3998 .set_port = rtl8214fc_set_port,
3999 .get_port = rtl8214fc_get_port,
4000 .set_eee = rtl8214fc_set_eee,
4001 .get_eee = rtl8214fc_get_eee,
4002 },
4003 {
4004 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
4005 .name = "Realtek RTL8218B (external)",
4006 .features = PHY_GBIT_FEATURES,
4007 .match_phy_device = rtl8218b_ext_match_phy_device,
4008 .probe = rtl8218b_ext_phy_probe,
4009 .suspend = genphy_suspend,
4010 .resume = genphy_resume,
4011 .set_loopback = genphy_loopback,
4012 .read_mmd = rtl8218b_read_mmd,
4013 .write_mmd = rtl8218b_write_mmd,
4014 .set_eee = rtl8218b_set_eee,
4015 .get_eee = rtl8218b_get_eee,
4016 },
4017 {
4018 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
4019 .name = "REALTEK RTL8218D",
4020 .features = PHY_GBIT_FEATURES,
4021 .probe = rtl8218d_phy_probe,
4022 .suspend = genphy_suspend,
4023 .resume = genphy_resume,
4024 .set_loopback = genphy_loopback,
4025 .set_eee = rtl8218d_set_eee,
4026 .get_eee = rtl8218d_get_eee,
4027 },
4028 {
4029 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
4030 .name = "REALTEK RTL8221B",
4031 .features = PHY_GBIT_FEATURES,
4032 .probe = rtl8226_phy_probe,
4033 .suspend = genphy_suspend,
4034 .resume = genphy_resume,
4035 .set_loopback = genphy_loopback,
4036 .read_mmd = rtl8226_read_mmd,
4037 .write_mmd = rtl8226_write_mmd,
4038 .read_page = rtl8226_read_page,
4039 .write_page = rtl8226_write_page,
4040 .read_status = rtl8226_read_status,
4041 .config_aneg = rtl8226_config_aneg,
4042 .set_eee = rtl8226_set_eee,
4043 .get_eee = rtl8226_get_eee,
4044 },
4045 {
4046 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
4047 .name = "REALTEK RTL8226",
4048 .features = PHY_GBIT_FEATURES,
4049 .probe = rtl8226_phy_probe,
4050 .suspend = genphy_suspend,
4051 .resume = genphy_resume,
4052 .set_loopback = genphy_loopback,
4053 .read_mmd = rtl8226_read_mmd,
4054 .write_mmd = rtl8226_write_mmd,
4055 .read_page = rtl8226_read_page,
4056 .write_page = rtl8226_write_page,
4057 .read_status = rtl8226_read_status,
4058 .config_aneg = rtl8226_config_aneg,
4059 .set_eee = rtl8226_set_eee,
4060 .get_eee = rtl8226_get_eee,
4061 },
4062 {
4063 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
4064 .name = "Realtek RTL8218B (internal)",
4065 .features = PHY_GBIT_FEATURES,
4066 .probe = rtl8218b_int_phy_probe,
4067 .suspend = genphy_suspend,
4068 .resume = genphy_resume,
4069 .set_loopback = genphy_loopback,
4070 .read_mmd = rtl8218b_read_mmd,
4071 .write_mmd = rtl8218b_write_mmd,
4072 .set_eee = rtl8218b_set_eee,
4073 .get_eee = rtl8218b_get_eee,
4074 },
4075 {
4076 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
4077 .name = "Realtek RTL8380 SERDES",
4078 .features = PHY_GBIT_FIBRE_FEATURES,
4079 .probe = rtl838x_serdes_probe,
4080 .suspend = genphy_suspend,
4081 .resume = genphy_resume,
4082 .set_loopback = genphy_loopback,
4083 .read_mmd = rtl8218b_read_mmd,
4084 .write_mmd = rtl8218b_write_mmd,
4085 .read_status = rtl8380_read_status,
4086 },
4087 {
4088 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
4089 .name = "Realtek RTL8393 SERDES",
4090 .features = PHY_GBIT_FIBRE_FEATURES,
4091 .probe = rtl8393_serdes_probe,
4092 .suspend = genphy_suspend,
4093 .resume = genphy_resume,
4094 .set_loopback = genphy_loopback,
4095 .read_status = rtl8393_read_status,
4096 },
4097 {
4098 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
4099 .name = "Realtek RTL8390 Generic",
4100 .features = PHY_GBIT_FIBRE_FEATURES,
4101 .probe = rtl8390_serdes_probe,
4102 .suspend = genphy_suspend,
4103 .resume = genphy_resume,
4104 .set_loopback = genphy_loopback,
4105 },
4106 {
4107 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
4108 .name = "REALTEK RTL9300 SERDES",
4109 .features = PHY_GBIT_FIBRE_FEATURES,
4110 .probe = rtl9300_serdes_probe,
4111 .suspend = genphy_suspend,
4112 .resume = genphy_resume,
4113 .set_loopback = genphy_loopback,
4114 .read_status = rtl9300_read_status,
4115 },
4116 };
4117
4118 module_phy_driver(rtl83xx_phy_driver);
4119
4120 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
4121 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
4122 { }
4123 };
4124
4125 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
4126
4127 MODULE_AUTHOR("B. Koblitz");
4128 MODULE_DESCRIPTION("RTL83xx PHY driver");
4129 MODULE_LICENSE("GPL");
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