target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   4  * Copyright (C) 2020 B. Koblitz
   5  */
   6 #ifndef _MACH_RTL838X_H_
   7 #define _MACH_RTL838X_H_
   8
   9 #include <asm/types.h>
  10 /*
  11  * Register access macros
  12  */
  13
  14 #define RTL838X_SW_BASE         ((volatile void *) 0xBB000000)
  15
  16 #define rtl83xx_r32(reg)        readl(reg)
  17 #define rtl83xx_w32(val, reg)   writel(val, reg)
  18 #define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
  19
  20 #define rtl83xx_r8(reg)         readb(reg)
  21 #define rtl83xx_w8(val, reg)    writeb(val, reg)
  22
  23 #define sw_r32(reg)             readl(RTL838X_SW_BASE + reg)
  24 #define sw_w32(val, reg)        writel(val, RTL838X_SW_BASE + reg)
  25 #define sw_w32_mask(clear, set, reg)    \
  26                                 sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
  27 #define sw_r64(reg)             ((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
  28                                 readl(RTL838X_SW_BASE + reg + 4))
  29
  30 #define sw_w64(val, reg)        do { \
  31                                         writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
  32                                         writel((u32)((val) & 0xffffffff), \
  33                                                         RTL838X_SW_BASE + reg + 4); \
  34                                 } while (0)
  35
  36 /*
  37  * SPRAM
  38  */
  39 #define RTL838X_ISPRAM_BASE     0x0
  40 #define RTL838X_DSPRAM_BASE     0x0
  41
  42 /*
  43  * IRQ Controller
  44  */
  45 #define RTL838X_IRQ_CPU_BASE    0
  46 #define RTL838X_IRQ_CPU_NUM     8
  47 #define RTL838X_IRQ_ICTL_BASE   (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
  48 #define RTL838X_IRQ_ICTL_NUM    32
  49
  50 #define RTL83XX_IRQ_UART0               31
  51 #define RTL83XX_IRQ_UART1               30
  52 #define RTL83XX_IRQ_TC0                 29
  53 #define RTL83XX_IRQ_TC1                 28
  54 #define RTL83XX_IRQ_OCPTO               27
  55 #define RTL83XX_IRQ_HLXTO               26
  56 #define RTL83XX_IRQ_SLXTO               25
  57 #define RTL83XX_IRQ_NIC                 24
  58 #define RTL83XX_IRQ_GPIO_ABCD           23
  59 #define RTL83XX_IRQ_GPIO_EFGH           22
  60 #define RTL83XX_IRQ_RTC                 21
  61 #define RTL83XX_IRQ_SWCORE              20
  62 #define RTL83XX_IRQ_WDT_IP1             19
  63 #define RTL83XX_IRQ_WDT_IP2             18
  64
  65 #define RTL9300_UART1_IRQ               31
  66 #define RTL9300_UART0_IRQ               30
  67 #define RTL9300_USB_H2_IRQ              28
  68 #define RTL9300_NIC_IRQ                 24
  69 #define RTL9300_SWCORE_IRQ              23
  70 #define RTL9300_GPIO_ABC_IRQ            13
  71 #define RTL9300_TC4_IRQ                 11
  72 #define RTL9300_TC3_IRQ                 10
  73 #define RTL9300_TC2_IRQ                  9
  74 #define RTL9300_TC1_IRQ                  8
  75 #define RTL9300_TC0_IRQ                  7
  76
  77
  78 /*
  79  * MIPS32R2 counter
  80  */
  81 #define RTL838X_COMPARE_IRQ     (RTL838X_IRQ_CPU_BASE + 7)
  82
  83 /*
  84  *  ICTL
  85  *  Base address 0xb8003000UL
  86  */
  87 #define RTL838X_ICTL1_IRQ       (RTL838X_IRQ_CPU_BASE + 2)
  88 #define RTL838X_ICTL2_IRQ       (RTL838X_IRQ_CPU_BASE + 3)
  89 #define RTL838X_ICTL3_IRQ       (RTL838X_IRQ_CPU_BASE + 4)
  90 #define RTL838X_ICTL4_IRQ       (RTL838X_IRQ_CPU_BASE + 5)
  91 #define RTL838X_ICTL5_IRQ       (RTL838X_IRQ_CPU_BASE + 6)
  92
  93 #define GIMR                    (0x00)
  94 #define UART0_IE                (1 << 31)
  95 #define UART1_IE                (1 << 30)
  96 #define TC0_IE                  (1 << 29)
  97 #define TC1_IE                  (1 << 28)
  98 #define OCPTO_IE                (1 << 27)
  99 #define HLXTO_IE                (1 << 26)
 100 #define SLXTO_IE                (1 << 25)
 101 #define NIC_IE                  (1 << 24)
 102 #define GPIO_ABCD_IE            (1 << 23)
 103 #define GPIO_EFGH_IE            (1 << 22)
 104 #define RTC_IE                  (1 << 21)
 105 #define WDT_IP1_IE              (1 << 19)
 106 #define WDT_IP2_IE              (1 << 18)
 107
 108 #define GISR                    (0x04)
 109 #define UART0_IP                (1 << 31)
 110 #define UART1_IP                (1 << 30)
 111 #define TC0_IP                  (1 << 29)
 112 #define TC1_IP                  (1 << 28)
 113 #define OCPTO_IP                (1 << 27)
 114 #define HLXTO_IP                (1 << 26)
 115 #define SLXTO_IP                (1 << 25)
 116 #define NIC_IP                  (1 << 24)
 117 #define GPIO_ABCD_IP            (1 << 23)
 118 #define GPIO_EFGH_IP            (1 << 22)
 119 #define RTC_IP                  (1 << 21)
 120 #define WDT_IP1_IP              (1 << 19)
 121 #define WDT_IP2_IP              (1 << 18)
 122
 123
 124 /* Interrupt Routing Selection */
 125 #define UART0_RS                2
 126 #define UART1_RS                1
 127 #define TC0_RS                  5
 128 #define TC1_RS                  1
 129 #define OCPTO_RS                1
 130 #define HLXTO_RS                1
 131 #define SLXTO_RS                1
 132 #define NIC_RS                  4
 133 #define GPIO_ABCD_RS            4
 134 #define GPIO_EFGH_RS            4
 135 #define RTC_RS                  4
 136 #define SWCORE_RS               3
 137 #define WDT_IP1_RS              4
 138 #define WDT_IP2_RS              5
 139
 140 /* Interrupt IRQ Assignments */
 141 #define UART0_IRQ               31
 142 #define UART1_IRQ               30
 143 #define TC0_IRQ                 29
 144 #define TC1_IRQ                 28
 145 #define OCPTO_IRQ               27
 146 #define HLXTO_IRQ               26
 147 #define SLXTO_IRQ               25
 148 #define NIC_IRQ                 24
 149 #define GPIO_ABCD_IRQ           23
 150 #define GPIO_EFGH_IRQ           22
 151 #define RTC_IRQ                 21
 152 #define SWCORE_IRQ              20
 153 #define WDT_IP1_IRQ             19
 154 #define WDT_IP2_IRQ             18
 155
 156 #define SYSTEM_FREQ             200000000
 157 #define RTL838X_UART0_BASE      ((volatile void *)(0xb8002000UL))
 158 #define RTL838X_UART0_BAUD      38400  /* ex. 19200 or 38400 or 57600 or 115200 */
 159 #define RTL838X_UART0_FREQ      (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
 160 #define RTL838X_UART0_MAPBASE   0x18002000UL
 161 #define RTL838X_UART0_MAPSIZE   0x100
 162 #define RTL838X_UART0_IRQ       UART0_IRQ
 163
 164 #define RTL838X_UART1_BASE      ((volatile void *)(0xb8002100UL))
 165 #define RTL838X_UART1_BAUD      38400  /* ex. 19200 or 38400 or 57600 or 115200 */
 166 #define RTL838X_UART1_FREQ      (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
 167 #define RTL838X_UART1_MAPBASE   0x18002100UL
 168 #define RTL838X_UART1_MAPSIZE   0x100
 169 #define RTL838X_UART1_IRQ       UART1_IRQ
 170
 171 #define UART0_RBR               (RTL838X_UART0_BASE + 0x000)
 172 #define UART0_THR               (RTL838X_UART0_BASE + 0x000)
 173 #define UART0_DLL               (RTL838X_UART0_BASE + 0x000)
 174 #define UART0_IER               (RTL838X_UART0_BASE + 0x004)
 175 #define UART0_DLM               (RTL838X_UART0_BASE + 0x004)
 176 #define UART0_IIR               (RTL838X_UART0_BASE + 0x008)
 177 #define UART0_FCR               (RTL838X_UART0_BASE + 0x008)
 178 #define UART0_LCR               (RTL838X_UART0_BASE + 0x00C)
 179 #define UART0_MCR               (RTL838X_UART0_BASE + 0x010)
 180 #define UART0_LSR               (RTL838X_UART0_BASE + 0x014)
 181
 182 #define UART1_RBR               (RTL838X_UART1_BASE + 0x000)
 183 #define UART1_THR               (RTL838X_UART1_BASE + 0x000)
 184 #define UART1_DLL               (RTL838X_UART1_BASE + 0x000)
 185 #define UART1_IER               (RTL838X_UART1_BASE + 0x004)
 186 #define UART1_DLM               (RTL838X_UART1_BASE + 0x004)
 187 #define UART1_IIR               (RTL838X_UART1_BASE + 0x008)
 188 #define UART1_FCR               (RTL838X_UART1_BASE + 0x008)
 189 #define UART1_LCR               (RTL838X_UART1_BASE + 0x00C)
 190 #define UART1_MCR               (RTL838X_UART1_BASE + 0x010)
 191 #define UART1_LSR               (RTL838X_UART1_BASE + 0x014)
 192
 193 /*
 194  * Memory Controller
 195  */
 196 #define MC_MCR                  0xB8001000
 197 #define MC_MCR_VAL              0x00000000
 198
 199 #define MC_DCR                  0xB8001004
 200 #define MC_DCR0_VAL             0x54480000
 201
 202 #define MC_DTCR                 0xB8001008
 203 #define MC_DTCR_VAL             0xFFFF05C0
 204
 205 /*
 206  * GPIO
 207  */
 208 #define GPIO_CTRL_REG_BASE              ((volatile void *) 0xb8003500)
 209 #define RTL838X_GPIO_PABC_CNR           (GPIO_CTRL_REG_BASE + 0x0)
 210 #define RTL838X_GPIO_PABC_TYPE          (GPIO_CTRL_REG_BASE + 0x04)
 211 #define RTL838X_GPIO_PABC_DIR           (GPIO_CTRL_REG_BASE + 0x8)
 212 #define RTL838X_GPIO_PABC_DATA          (GPIO_CTRL_REG_BASE + 0xc)
 213 #define RTL838X_GPIO_PABC_ISR           (GPIO_CTRL_REG_BASE + 0x10)
 214 #define RTL838X_GPIO_PAB_IMR            (GPIO_CTRL_REG_BASE + 0x14)
 215 #define RTL838X_GPIO_PC_IMR             (GPIO_CTRL_REG_BASE + 0x18)
 216
 217 #define RTL930X_GPIO_CTRL_REG_BASE      ((volatile void *) 0xb8003300)
 218 #define RTL930X_GPIO_PABCD_DIR          (RTL930X_GPIO_CTRL_REG_BASE + 0x8)
 219 #define RTL930X_GPIO_PABCD_DAT          (RTL930X_GPIO_CTRL_REG_BASE + 0xc)
 220 #define RTL930X_GPIO_PABCD_ISR          (RTL930X_GPIO_CTRL_REG_BASE + 0x10)
 221 #define RTL930X_GPIO_PAB_IMR            (RTL930X_GPIO_CTRL_REG_BASE + 0x14)
 222 #define RTL930X_GPIO_PCD_IMR            (RTL930X_GPIO_CTRL_REG_BASE + 0x18)
 223
 224 #define RTL838X_MODEL_NAME_INFO         (0x00D4)
 225 #define RTL839X_MODEL_NAME_INFO         (0x0FF0)
 226 #define RTL93XX_MODEL_NAME_INFO         (0x0004)
 227 #define RTL931X_CHIP_INFO_ADDR          (0x0008)
 228
 229 #define RTL838X_LED_GLB_CTRL            (0xA000)
 230 #define RTL839X_LED_GLB_CTRL            (0x00E4)
 231 #define RTL9302_LED_GLB_CTRL            (0xcc00)
 232 #define RTL930X_LED_GLB_CTRL            (0xCC00)
 233 #define RTL931X_LED_GLB_CTRL            (0x0600)
 234
 235 #define RTL838X_EXT_GPIO_DIR            (0xA08C)
 236 #define RTL839X_EXT_GPIO_DIR            (0x0214)
 237 #define RTL838X_EXT_GPIO_DATA           (0xA094)
 238 #define RTL839X_EXT_GPIO_DATA           (0x021c)
 239 #define RTL838X_EXT_GPIO_INDRT_ACCESS   (0xA09C)
 240 #define RTL839X_EXT_GPIO_INDRT_ACCESS   (0x0224)
 241 #define RTL838X_EXTRA_GPIO_CTRL         (0xA0E0)
 242 #define RTL838X_DMY_REG5                (0x0144)
 243 #define RTL838X_EXTRA_GPIO_CTRL         (0xA0E0)
 244
 245 #define RTL838X_GMII_INTF_SEL           (0x1000)
 246 #define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010)
 247
 248 #define RTL838X_GPIO_A7         31
 249 #define RTL838X_GPIO_A6         30
 250 #define RTL838X_GPIO_A5         29
 251 #define RTL838X_GPIO_A4         28
 252 #define RTL838X_GPIO_A3         27
 253 #define RTL838X_GPIO_A2         26
 254 #define RTL838X_GPIO_A1         25
 255 #define RTL838X_GPIO_A0         24
 256 #define RTL838X_GPIO_B7         23
 257 #define RTL838X_GPIO_B6         22
 258 #define RTL838X_GPIO_B5         21
 259 #define RTL838X_GPIO_B4         20
 260 #define RTL838X_GPIO_B3         19
 261 #define RTL838X_GPIO_B2         18
 262 #define RTL838X_GPIO_B1         17
 263 #define RTL838X_GPIO_B0         16
 264 #define RTL838X_GPIO_C7         15
 265 #define RTL838X_GPIO_C6         14
 266 #define RTL838X_GPIO_C5         13
 267 #define RTL838X_GPIO_C4         12
 268 #define RTL838X_GPIO_C3         11
 269 #define RTL838X_GPIO_C2         10
 270 #define RTL838X_GPIO_C1         9
 271 #define RTL838X_GPIO_C0         8
 272
 273 #define RTL838X_INT_RW_CTRL             (0x0058)
 274 #define RTL838X_EXT_VERSION             (0x00D0)
 275 #define RTL838X_PLL_CML_CTRL            (0x0FF8)
 276 #define RTL838X_STRAP_DBG               (0x100C)
 277
 278 /*
 279  * Reset
 280  */
 281 #define RGCR                            (0x1E70)
 282 #define RTL838X_RST_GLB_CTRL_0          (0x003c)
 283 #define RTL838X_RST_GLB_CTRL_1          (0x0040)
 284 #define RTL839X_RST_GLB_CTRL            (0x0014)
 285 #define RTL930X_RST_GLB_CTRL_0          (0x000c)
 286 #define RTL931X_RST_GLB_CTRL            (0x0400)
 287
 288 /* LED control by switch */
 289 #define RTL838X_LED_MODE_SEL            (0x1004)
 290 #define RTL838X_LED_MODE_CTRL           (0xA004)
 291 #define RTL838X_LED_P_EN_CTRL           (0xA008)
 292
 293 /* LED control by software */
 294 #define RTL838X_LED_SW_CTRL             (0x0128)
 295 #define RTL839X_LED_SW_CTRL             (0xA00C)
 296 #define RTL838X_LED_SW_P_EN_CTRL        (0xA010)
 297 #define RTL839X_LED_SW_P_EN_CTRL        (0x012C)
 298 #define RTL838X_LED0_SW_P_EN_CTRL       (0xA010)
 299 #define RTL839X_LED0_SW_P_EN_CTRL       (0x012C)
 300 #define RTL838X_LED1_SW_P_EN_CTRL       (0xA014)
 301 #define RTL839X_LED1_SW_P_EN_CTRL       (0x0130)
 302 #define RTL838X_LED2_SW_P_EN_CTRL       (0xA018)
 303 #define RTL839X_LED2_SW_P_EN_CTRL       (0x0134)
 304 #define RTL838X_LED_SW_P_CTRL           (0xA01C)
 305 #define RTL839X_LED_SW_P_CTRL           (0x0144)
 306
 307 #define RTL839X_MAC_EFUSE_CTRL          (0x02ac)
 308
 309 /*
 310  * MDIO via Realtek's SMI interface
 311  */
 312 #define RTL838X_SMI_GLB_CTRL            (0xa100)
 313 #define RTL838X_SMI_ACCESS_PHY_CTRL_0   (0xa1b8)
 314 #define RTL838X_SMI_ACCESS_PHY_CTRL_1   (0xa1bc)
 315 #define RTL838X_SMI_ACCESS_PHY_CTRL_2   (0xa1c0)
 316 #define RTL838X_SMI_ACCESS_PHY_CTRL_3   (0xa1c4)
 317 #define RTL838X_SMI_PORT0_5_ADDR_CTRL   (0xa1c8)
 318 #define RTL838X_SMI_POLL_CTRL           (0xa17c)
 319
 320 #define RTL839X_SMI_GLB_CTRL            (0x03f8)
 321 #define RTL839X_SMI_PORT_POLLING_CTRL   (0x03fc)
 322 #define RTL839X_PHYREG_ACCESS_CTRL      (0x03DC)
 323 #define RTL839X_PHYREG_CTRL             (0x03E0)
 324 #define RTL839X_PHYREG_PORT_CTRL        (0x03E4)
 325 #define RTL839X_PHYREG_DATA_CTRL        (0x03F0)
 326 #define RTL839X_PHYREG_MMD_CTRL         (0x3F4)
 327
 328 #define RTL930X_SMI_GLB_CTRL            (0xCA00)
 329 #define RTL930X_SMI_POLL_CTRL           (0xca90)
 330 #define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
 331 #define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
 332 #define RTL930X_SMI_PORT0_5_ADDR        (0xCB80)
 333 #define RTL930X_SMI_ACCESS_PHY_CTRL_0   (0xCB70)
 334 #define RTL930X_SMI_ACCESS_PHY_CTRL_1   (0xCB74)
 335 #define RTL930X_SMI_ACCESS_PHY_CTRL_2   (0xCB78)
 336 #define RTL930X_SMI_ACCESS_PHY_CTRL_3   (0xCB7C)
 337
 338 #define RTL931X_SMI_GLB_CTRL1           (0x0CBC)
 339 #define RTL931X_SMI_GLB_CTRL0           (0x0CC0)
 340 #define RTL931X_SMI_PORT_POLLING_CTRL   (0x0CCC)
 341 #define RTL931X_SMI_PORT_ADDR           (0x0C74)
 342 #define RTL931X_SMI_PORT_POLLING_SEL    (0x0C9C)
 343 #define RTL9310_SMI_PORT_POLLING_CTRL   (0x0CCC)
 344 #define RTL931X_SMI_INDRT_ACCESS_CTRL_0 (0x0C00)
 345 #define RTL931X_SMI_INDRT_ACCESS_CTRL_1 (0x0C04)
 346 #define RTL931X_SMI_INDRT_ACCESS_CTRL_2 (0x0C08)
 347 #define RTL931X_SMI_INDRT_ACCESS_CTRL_3 (0x0C10)
 348 #define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)
 349 #define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)
 350 #define RTL931X_MAC_L2_GLOBAL_CTRL2     (0x1358)
 351 #define RTL931X_MAC_L2_GLOBAL_CTRL1     (0x5548)
 352
 353 /*
 354  * Switch interrupts
 355  */
 356 #define RTL838X_IMR_GLB                 (0x1100)
 357 #define RTL838X_IMR_PORT_LINK_STS_CHG   (0x1104)
 358 #define RTL838X_ISR_GLB_SRC             (0x1148)
 359 #define RTL838X_ISR_PORT_LINK_STS_CHG   (0x114C)
 360
 361 #define RTL839X_IMR_GLB                 (0x0064)
 362 #define RTL839X_IMR_PORT_LINK_STS_CHG   (0x0068)
 363 #define RTL839X_ISR_GLB_SRC             (0x009c)
 364 #define RTL839X_ISR_PORT_LINK_STS_CHG   (0x00a0)
 365
 366 #define RTL930X_IMR_GLB                 (0xC628)
 367 #define RTL930X_IMR_PORT_LINK_STS_CHG   (0xC62C)
 368 #define RTL930X_ISR_GLB                 (0xC658)
 369 #define RTL930X_ISR_PORT_LINK_STS_CHG   (0xC660)
 370
 371 // IMR_GLB does not exit on RTL931X
 372 #define RTL931X_IMR_PORT_LINK_STS_CHG   (0x126C)
 373 #define RTL931X_ISR_GLB_SRC             (0x12B4)
 374 #define RTL931X_ISR_PORT_LINK_STS_CHG   (0x12B8)
 375
 376 /* Definition of family IDs */
 377 #define RTL8389_FAMILY_ID   (0x8389)
 378 #define RTL8328_FAMILY_ID   (0x8328)
 379 #define RTL8390_FAMILY_ID   (0x8390)
 380 #define RTL8350_FAMILY_ID   (0x8350)
 381 #define RTL8380_FAMILY_ID   (0x8380)
 382 #define RTL8330_FAMILY_ID   (0x8330)
 383 #define RTL9300_FAMILY_ID   (0x9300)
 384 #define RTL9310_FAMILY_ID   (0x9310)
 385
 386 /* SPI Support */
 387 #define RTL931X_SPI_CTRL0               (0x103C)
 388
 389 /* Basic SoC Features */
 390 #define RTL838X_CPU_PORT                        28
 391 #define RTL839X_CPU_PORT                        52
 392 #define RTL930X_CPU_PORT                        28
 393 #define RTL931X_CPU_PORT                        56
 394
 395 struct rtl83xx_soc_info {
 396         unsigned char *name;
 397         unsigned int id;
 398         unsigned int family;
 399         unsigned char *compatible;
 400         volatile void *sw_base;
 401         volatile void *icu_base;
 402         int cpu_port;
 403 };
 404
 405 /* rtl83xx-related functions used across subsystems */
 406 int rtl838x_smi_wait_op(int timeout);
 407 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 408 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 409 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 410 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 411 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 412 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 413 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 414 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 415
 416 #endif   /* _MACH_RTL838X_H_ */