1 // SPDX-License-Identifier: GPL-2.0-only
4 * Early intialization code for the Realtek RTL838X SoC
6 * based on the original BSP by
7 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
8 * Copyright (C) 2020 B. Koblitz
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/of_fdt.h>
16 #include <linux/libfdt.h>
17 #include <asm/bootinfo.h>
18 #include <asm/addrspace.h>
21 #include <asm/fw/fw.h>
22 #include <asm/smp-ops.h>
23 #include <asm/mips-cps.h>
25 #include <mach-rtl83xx.h>
27 extern char arcs_cmdline
[];
28 extern const char __appended_dtb
;
30 struct rtl83xx_soc_info soc_info
;
33 #ifdef CONFIG_MIPS_MT_SMP
34 extern const struct plat_smp_ops vsmp_smp_ops
;
35 static struct plat_smp_ops rtl_smp_ops
;
37 static void rtl_init_secondary(void)
39 #ifndef CONFIG_CEVT_R4K
41 * These devices are low on resources. There might be the chance that CEVT_R4K
42 * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might
43 * be active by default after startup of secondary VPE. With no registered
44 * handler that leads to continuous unhandeled interrupts. In this case disable
45 * counting (DC) in the core and confirm a pending interrupt.
47 write_c0_cause(read_c0_cause() | CAUSEF_DC
);
49 #endif /* CONFIG_CEVT_R4K */
51 * Enable all CPU interrupts, as everything is managed by the external
52 * controller. TODO: Standard vsmp_init_secondary() has special treatment for
53 * Malta if external GIC is available. Maybe we need this too.
55 if (mips_gic_present())
56 pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__
);
58 set_c0_status(ST0_IM
);
60 #endif /* CONFIG_MIPS_MT_SMP */
62 const char *get_system_type(void)
67 void __init
prom_free_prom_memory(void)
72 void __init
device_tree_init(void)
74 if (!fdt_check_header(&__appended_dtb
)) {
75 fdt
= &__appended_dtb
;
76 pr_info("Using appended Device Tree.\n");
78 initial_boot_params
= (void *)fdt
;
79 unflatten_and_copy_device_tree();
82 void __init
identify_rtl9302(void)
84 switch (sw_r32(RTL93XX_MODEL_NAME_INFO
) & 0xfffffff0) {
86 soc_info
.name
= "RTL9302A 12x2.5G";
89 soc_info
.name
= "RTL9302B 8x2.5G";
92 soc_info
.name
= "RTL9302C 16x2.5G";
95 soc_info
.name
= "RTL9302D 24x2.5G";
98 soc_info
.name
= "RTL9302A";
101 soc_info
.name
= "RTL9302B";
104 soc_info
.name
= "RTL9302C";
107 soc_info
.name
= "RTL9302D";
110 soc_info
.name
= "RTL9302F";
113 soc_info
.name
= "RTL9302";
117 void __init
prom_init(void)
122 setup_8250_early_printk_port(0xb8002000, 2, 0);
124 model
= sw_r32(RTL838X_MODEL_NAME_INFO
);
125 pr_info("RTL838X model is %x\n", model
);
126 model
= model
>> 16 & 0xFFFF;
128 if ((model
!= 0x8328) && (model
!= 0x8330) && (model
!= 0x8332)
129 && (model
!= 0x8380) && (model
!= 0x8382)) {
130 model
= sw_r32(RTL839X_MODEL_NAME_INFO
);
131 pr_info("RTL839X model is %x\n", model
);
132 model
= model
>> 16 & 0xFFFF;
135 if ((model
& 0x8390) != 0x8380 && (model
& 0x8390) != 0x8390) {
136 model
= sw_r32(RTL93XX_MODEL_NAME_INFO
);
137 pr_info("RTL93XX model is %x\n", model
);
138 model
= model
>> 16 & 0xFFFF;
145 soc_info
.name
= "RTL8328";
146 soc_info
.family
= RTL8328_FAMILY_ID
;
149 soc_info
.name
= "RTL8332";
150 soc_info
.family
= RTL8380_FAMILY_ID
;
153 soc_info
.name
= "RTL8380";
154 soc_info
.family
= RTL8380_FAMILY_ID
;
157 soc_info
.name
= "RTL8382";
158 soc_info
.family
= RTL8380_FAMILY_ID
;
161 soc_info
.name
= "RTL8390";
162 soc_info
.family
= RTL8390_FAMILY_ID
;
165 soc_info
.name
= "RTL8391";
166 soc_info
.family
= RTL8390_FAMILY_ID
;
169 soc_info
.name
= "RTL8392";
170 soc_info
.family
= RTL8390_FAMILY_ID
;
173 soc_info
.name
= "RTL8393";
174 soc_info
.family
= RTL8390_FAMILY_ID
;
177 soc_info
.name
= "RTL9301";
178 soc_info
.family
= RTL9300_FAMILY_ID
;
182 soc_info
.family
= RTL9300_FAMILY_ID
;
185 soc_info
.name
= "RTL9303";
186 soc_info
.family
= RTL9300_FAMILY_ID
;
189 soc_info
.name
= "RTL9313";
190 soc_info
.family
= RTL9310_FAMILY_ID
;
193 soc_info
.name
= "DEFAULT";
197 pr_info("SoC Type: %s\n", get_system_type());
203 if (!register_cps_smp_ops())
206 #ifdef CONFIG_MIPS_MT_SMP
207 if (cpu_has_mipsmt
) {
208 rtl_smp_ops
= vsmp_smp_ops
;
209 rtl_smp_ops
.init_secondary
= rtl_init_secondary
;
210 register_smp_ops(&rtl_smp_ops
);
215 register_up_smp_ops();