target/linux/realtek/files-5.15/drivers/clk/realtek/clk-rtl83xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Realtek RTL83XX clock headers
   4  * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
   5  */
   6
   7 /*
   8  * Switch registers (e.g. PLL)
   9  */
  10
  11 #define RTL_SW_CORE_BASE                        (0xbb000000)
  12
  13 #define RTL838X_PLL_GLB_CTRL                    (0x0fc0)
  14 #define RTL838X_PLL_CPU_CTRL0                   (0x0fc4)
  15 #define RTL838X_PLL_CPU_CTRL1                   (0x0fc8)
  16 #define RTL838X_PLL_LXB_CTRL0                   (0x0fd0)
  17 #define RTL838X_PLL_LXB_CTRL1                   (0x0fd4)
  18 #define RTL838X_PLL_MEM_CTRL0                   (0x0fdc)
  19 #define RTL838X_PLL_MEM_CTRL1                   (0x0fe0)
  20
  21 #define RTL839X_PLL_GLB_CTRL                    (0x0024)
  22 #define RTL839X_PLL_CPU_CTRL0                   (0x0028)
  23 #define RTL839X_PLL_CPU_CTRL1                   (0x002c)
  24 #define RTL839X_PLL_LXB_CTRL0                   (0x0038)
  25 #define RTL839X_PLL_LXB_CTRL1                   (0x003c)
  26 #define RTL839X_PLL_MEM_CTRL0                   (0x0048)
  27 #define RTL839X_PLL_MEM_CTRL1                   (0x004c)
  28
  29 #define RTL_PLL_CTRL0_CMU_SEL_PREDIV(v)         (((v) >> 0) & 0x3)
  30 #define RTL_PLL_CTRL0_CMU_SEL_DIV4(v)           (((v) >> 2) & 0x1)
  31 #define RTL_PLL_CTRL0_CMU_NCODE_IN(v)           (((v) >> 4) & 0xff)
  32 #define RTL_PLL_CTRL0_CMU_DIVN2(v)              (((v) >> 12) & 0xff)
  33
  34 #define RTL838X_GLB_CTRL_EN_CPU_PLL_MASK        (1 << 0)
  35 #define RTL838X_GLB_CTRL_EN_LXB_PLL_MASK        (1 << 1)
  36 #define RTL838X_GLB_CTRL_EN_MEM_PLL_MASK        (1 << 2)
  37 #define RTL838X_GLB_CTRL_CPU_PLL_READY_MASK     (1 << 8)
  38 #define RTL838X_GLB_CTRL_LXB_PLL_READY_MASK     (1 << 9)
  39 #define RTL838X_GLB_CTRL_MEM_PLL_READY_MASK     (1 << 10)
  40 #define RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK    (1 << 12)
  41
  42 #define RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(v)     (((v) >> 26) & 0x1)
  43 #define RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(v)      (((v) >> 27) & 0x3)
  44
  45 #define RTL839X_GLB_CTRL_CPU_CLKSEL_MASK        (1 << 11)
  46 #define RTL839X_GLB_CTRL_MEM_CLKSEL_MASK        (1 << 12)
  47 #define RTL839X_GLB_CTRL_LXB_CLKSEL_MASK        (1 << 13)
  48
  49 #define RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(v)     (((v) >> 2) & 0x1)
  50 #define RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(v)      (((v) >> 0) & 0x3)
  51
  52 /*
  53  * Core registers (e.g. memory controller)
  54  */
  55
  56 #define RTL_SOC_BASE                            (0xB8000000)
  57
  58 #define RTL_MC_MCR                              (0x1000)
  59 #define RTL_MC_DCR                              (0x1004)
  60 #define RTL_MC_DTR0                             (0x1008)
  61 #define RTL_MC_DTR1                             (0x100c)
  62 #define RTL_MC_DTR2                             (0x1010)
  63 #define RTL_MC_DMCR                             (0x101c)
  64 #define RTL_MC_DACCR                            (0x1500)
  65 #define RTL_MC_DCDR                             (0x1060)
  66
  67 #define RTL_MC_MCR_DRAMTYPE(v)                  ((((v) >> 28) & 0xf) + 1)
  68 #define RTL_MC_DCR_BUSWIDTH(v)                  (8 << (((v) >> 24) & 0xf))
  69
  70 /*
  71  * Other stuff
  72  */
  73
  74 #define RTL_SRAM_MARKER                         (0x5eaf00d5)
  75 #define RTL_SRAM_BASE                           (0x9f000000)