54d916d17a923c0b19ca2aa5adb16ae7139b6474
[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / i2c / busses / i2c-rtl9300.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/module.h>
4 #include <linux/of_platform.h>
5 #include "i2c-rtl9300.h"
6
7 #define REG(i, x) (i->base + x + (i->scl_num ? i->mst2_offset : 0))
8 #define REG_MASK(i, clear, set, reg) \
9 writel((readl(REG(i, reg)) & ~(clear)) | (set), REG(i, reg))
10
11 struct i2c_drv_data {
12 int scl0_pin;
13 int scl1_pin;
14 int sda0_pin;
15 struct i2c_algorithm *algo;
16 int (*read)(struct rtl9300_i2c *i2c, u8 *buf, int len);
17 int (*write)(struct rtl9300_i2c *i2c, u8 *buf, int len);
18 void (*reg_addr_set)(struct rtl9300_i2c *i2c, u32 reg, u16 len);
19 int (*config_xfer)(struct rtl9300_i2c *i2c, u16 addr, u16 len);
20 int (*execute_xfer)(struct rtl9300_i2c *i2c, char read_write, int size,
21 union i2c_smbus_data * data, int len);
22 void (*writel)(struct rtl9300_i2c *i2c, u32 data);
23 void (*config_io)(struct rtl9300_i2c *i2c, int scl_num, int sda_num);
24 u32 mst2_offset;
25 };
26
27 DEFINE_MUTEX(i2c_lock);
28
29 static void rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
30 {
31 /* Set register address width */
32 REG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_MADDR_WIDTH, len << RTL9300_I2C_CTRL2_MADDR_WIDTH,
33 RTL9300_I2C_CTRL2);
34
35 /* Set register address */
36 REG_MASK(i2c, 0xffffff << RTL9300_I2C_CTRL1_MEM_ADDR, reg << RTL9300_I2C_CTRL1_MEM_ADDR,
37 RTL9300_I2C_CTRL1);
38 }
39
40 static void rtl9310_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
41 {
42 /* Set register address width */
43 REG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_MADDR_WIDTH, len << RTL9310_I2C_CTRL_MADDR_WIDTH,
44 RTL9310_I2C_CTRL);
45
46 /* Set register address */
47 writel(reg, REG(i2c, RTL9310_I2C_MEMADDR));
48 }
49
50 static void rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_num)
51 {
52 u32 v;
53
54 /* Set SCL pin */
55 REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1);
56
57 /* Set SDA pin */
58 REG_MASK(i2c, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL,
59 i2c->sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1);
60
61 /* Set SDA pin to I2C functionality */
62 v = readl(i2c->base + RTL9300_I2C_MST_GLB_CTRL);
63 v |= BIT(i2c->sda_num);
64 writel(v, i2c->base + RTL9300_I2C_MST_GLB_CTRL);
65 }
66
67 static void rtl9310_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_num)
68 {
69 u32 v;
70
71 /* Set SCL pin */
72 REG_MASK(i2c, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + scl_num), RTL9310_I2C_MST_IF_SEL);
73
74 /* Set SDA pin */
75 REG_MASK(i2c, 0x7 << RTL9310_I2C_CTRL_SDA_OUT_SEL,
76 i2c->sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL);
77
78 /* Set SDA pin to I2C functionality */
79 v = readl(i2c->base + RTL9310_I2C_MST_IF_SEL);
80 v |= BIT(i2c->sda_num);
81 writel(v, i2c->base + RTL9310_I2C_MST_IF_SEL);
82 }
83
84 static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len)
85 {
86 /* Set bus frequency */
87 REG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_SCL_FREQ,
88 i2c->bus_freq << RTL9300_I2C_CTRL2_SCL_FREQ, RTL9300_I2C_CTRL2);
89
90 /* Set slave device address */
91 REG_MASK(i2c, 0x7f << RTL9300_I2C_CTRL2_DEV_ADDR,
92 addr << RTL9300_I2C_CTRL2_DEV_ADDR, RTL9300_I2C_CTRL2);
93
94 /* Set data length */
95 REG_MASK(i2c, 0xf << RTL9300_I2C_CTRL2_DATA_WIDTH,
96 ((len - 1) & 0xf) << RTL9300_I2C_CTRL2_DATA_WIDTH, RTL9300_I2C_CTRL2);
97
98 /* Set read mode to random */
99 REG_MASK(i2c, 0x1 << RTL9300_I2C_CTRL2_READ_MODE, 0, RTL9300_I2C_CTRL2);
100
101 return 0;
102 }
103
104 static int rtl9310_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len)
105 {
106 /* Set bus frequency */
107 REG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_SCL_FREQ,
108 i2c->bus_freq << RTL9310_I2C_CTRL_SCL_FREQ, RTL9310_I2C_CTRL);
109
110 /* Set slave device address */
111 REG_MASK(i2c, 0x7f << RTL9310_I2C_CTRL_DEV_ADDR,
112 addr << RTL9310_I2C_CTRL_DEV_ADDR, RTL9310_I2C_CTRL);
113
114 /* Set data length */
115 REG_MASK(i2c, 0xf << RTL9310_I2C_CTRL_DATA_WIDTH,
116 ((len - 1) & 0xf) << RTL9310_I2C_CTRL_DATA_WIDTH, RTL9310_I2C_CTRL);
117
118 /* Set read mode to random */
119 REG_MASK(i2c, 0x1 << RTL9310_I2C_CTRL_READ_MODE, 0, RTL9310_I2C_CTRL);
120
121 return 0;
122 }
123
124 static int i2c_read(void __iomem *r0, u8 *buf, int len)
125 {
126 if (len > 16)
127 return -EIO;
128
129 for (int i = 0; i < len; i++) {
130 u32 v;
131
132 if (i % 4 == 0)
133 v = readl(r0 + i);
134 buf[i] = v;
135 v >>= 8;
136 }
137
138 return len;
139 }
140
141 static int i2c_write(void __iomem *r0, u8 *buf, int len)
142 {
143 if (len > 16)
144 return -EIO;
145
146 for (int i = 0; i < len; i++) {
147 u32 v;
148
149 if (! (i % 4))
150 v = 0;
151 v <<= 8;
152 v |= buf[i];
153 if (i % 4 == 3 || i == len - 1)
154 writel(v, r0 + (i / 4) * 4);
155 }
156
157 return len;
158 }
159
160 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
161 {
162 return i2c_read(REG(i2c, RTL9300_I2C_DATA_WORD0), buf, len);
163 }
164
165 static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)
166 {
167 return i2c_write(REG(i2c, RTL9300_I2C_DATA_WORD0), buf, len);
168 }
169
170 static int rtl9310_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
171 {
172 return i2c_read(REG(i2c, RTL9310_I2C_DATA), buf, len);
173 }
174
175 static int rtl9310_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)
176 {
177 return i2c_write(REG(i2c, RTL9310_I2C_DATA), buf, len);
178 }
179
180 static void rtl9300_writel(struct rtl9300_i2c *i2c, u32 data)
181 {
182 writel(data, REG(i2c, RTL9300_I2C_DATA_WORD0));
183 }
184
185 static void rtl9310_writel(struct rtl9300_i2c *i2c, u32 data)
186 {
187 writel(data, REG(i2c, RTL9310_I2C_DATA));
188 }
189
190
191 static int rtl9300_execute_xfer(struct rtl9300_i2c *i2c, char read_write,
192 int size, union i2c_smbus_data * data, int len)
193 {
194 u32 v;
195
196 if (read_write == I2C_SMBUS_READ)
197 REG_MASK(i2c, BIT(RTL9300_I2C_CTRL1_RWOP), 0, RTL9300_I2C_CTRL1);
198 else
199 REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_RWOP), RTL9300_I2C_CTRL1);
200
201 REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_I2C_TRIG), RTL9300_I2C_CTRL1);
202 do {
203 v = readl(REG(i2c, RTL9300_I2C_CTRL1));
204 } while (v & BIT(RTL9300_I2C_CTRL1_I2C_TRIG));
205
206 if (v & BIT(RTL9300_I2C_CTRL1_I2C_FAIL))
207 return -EIO;
208
209 if (read_write == I2C_SMBUS_READ) {
210 if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA){
211 data->byte = readl(REG(i2c, RTL9300_I2C_DATA_WORD0));
212 } else if (size == I2C_SMBUS_WORD_DATA) {
213 data->word = readl(REG(i2c, RTL9300_I2C_DATA_WORD0));
214 } else if (len > 0) {
215 rtl9300_i2c_read(i2c, &data->block[0], len);
216 }
217 }
218
219 return 0;
220 }
221
222 static int rtl9310_execute_xfer(struct rtl9300_i2c *i2c, char read_write,
223 int size, union i2c_smbus_data * data, int len)
224 {
225 u32 v;
226
227 if (read_write == I2C_SMBUS_READ)
228 REG_MASK(i2c, BIT(RTL9310_I2C_CTRL_RWOP), 0, RTL9310_I2C_CTRL);
229 else
230 REG_MASK(i2c, 0, BIT(RTL9310_I2C_CTRL_RWOP), RTL9310_I2C_CTRL);
231
232 REG_MASK(i2c, 0, BIT(RTL9310_I2C_CTRL_I2C_TRIG), RTL9310_I2C_CTRL);
233 do {
234 v = readl(REG(i2c, RTL9310_I2C_CTRL));
235 } while (v & BIT(RTL9310_I2C_CTRL_I2C_TRIG));
236
237 if (v & BIT(RTL9310_I2C_CTRL_I2C_FAIL))
238 return -EIO;
239
240 if (read_write == I2C_SMBUS_READ) {
241 if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA){
242 data->byte = readl(REG(i2c, RTL9310_I2C_DATA));
243 } else if (size == I2C_SMBUS_WORD_DATA) {
244 data->word = readl(REG(i2c, RTL9310_I2C_DATA));
245 } else if (len > 0) {
246 rtl9310_i2c_read(i2c, &data->block[0], len);
247 }
248 }
249
250 return 0;
251 }
252
253 static int rtl9300_i2c_smbus_xfer(struct i2c_adapter * adap, u16 addr,
254 unsigned short flags, char read_write,
255 u8 command, int size, union i2c_smbus_data * data)
256 {
257 struct rtl9300_i2c *i2c = i2c_get_adapdata(adap);
258 struct i2c_drv_data *drv_data = (struct i2c_drv_data *)device_get_match_data(i2c->dev);
259 int len = 0, ret;
260
261 mutex_lock(&i2c_lock);
262 switch (size) {
263 case I2C_SMBUS_QUICK:
264 drv_data->config_xfer(i2c, addr, 0);
265 drv_data->reg_addr_set(i2c, 0, 0);
266 break;
267
268 case I2C_SMBUS_BYTE:
269 if (read_write == I2C_SMBUS_WRITE) {
270 drv_data->config_xfer(i2c, addr, 0);
271 drv_data->reg_addr_set(i2c, command, 1);
272 } else {
273 drv_data->config_xfer(i2c, addr, 1);
274 drv_data->reg_addr_set(i2c, 0, 0);
275 }
276 break;
277
278 case I2C_SMBUS_BYTE_DATA:
279 pr_debug("I2C_SMBUS_BYTE_DATA %02x, read %d cmd %02x\n", addr, read_write, command);
280 drv_data->reg_addr_set(i2c, command, 1);
281 drv_data->config_xfer(i2c, addr, 1);
282
283 if (read_write == I2C_SMBUS_WRITE) {
284 pr_debug("--> data %02x\n", data->byte);
285 drv_data->writel(i2c, data->byte);
286 }
287 break;
288
289 case I2C_SMBUS_WORD_DATA:
290 pr_debug("I2C_SMBUS_WORD %02x, read %d\n", addr, read_write);
291 drv_data->reg_addr_set(i2c, command, 1);
292 drv_data->config_xfer(i2c, addr, 2);
293 if (read_write == I2C_SMBUS_WRITE)
294 drv_data->writel(i2c, data->word);
295 break;
296
297 case I2C_SMBUS_BLOCK_DATA:
298 pr_debug("I2C_SMBUS_BLOCK_DATA %02x, read %d, len %d\n",
299 addr, read_write, data->block[0]);
300 drv_data->reg_addr_set(i2c, command, 1);
301 drv_data->config_xfer(i2c, addr, data->block[0]);
302 if (read_write == I2C_SMBUS_WRITE)
303 drv_data->write(i2c, &data->block[1], data->block[0]);
304 len = data->block[0];
305 break;
306
307 default:
308 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
309 return -EOPNOTSUPP;
310 }
311
312 ret = drv_data->execute_xfer(i2c, read_write, size, data, len);
313
314 mutex_unlock(&i2c_lock);
315
316 return ret;
317 }
318
319 static u32 rtl9300_i2c_func(struct i2c_adapter *a)
320 {
321 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
322 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
323 I2C_FUNC_SMBUS_BLOCK_DATA;
324 }
325
326 static const struct i2c_algorithm rtl9300_i2c_algo = {
327 .smbus_xfer = rtl9300_i2c_smbus_xfer,
328 .functionality = rtl9300_i2c_func,
329 };
330
331 struct i2c_adapter_quirks rtl9300_i2c_quirks = {
332 .flags = I2C_AQ_NO_CLK_STRETCH,
333 .max_read_len = 16,
334 .max_write_len = 16,
335 };
336
337 static int rtl9300_i2c_probe(struct platform_device *pdev)
338 {
339 struct resource *res;
340 struct rtl9300_i2c *i2c;
341 struct i2c_adapter *adap;
342 struct i2c_drv_data *drv_data;
343 struct device_node *node = pdev->dev.of_node;
344 u32 clock_freq, pin;
345 int ret = 0;
346
347 pr_info("%s probing I2C adapter\n", __func__);
348
349 if (!node) {
350 dev_err(i2c->dev, "No DT found\n");
351 return -EINVAL;
352 }
353
354 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
355
356 drv_data = (struct i2c_drv_data *) device_get_match_data(&pdev->dev);
357
358 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rtl9300_i2c), GFP_KERNEL);
359 if (!i2c)
360 return -ENOMEM;
361
362 i2c->base = devm_ioremap_resource(&pdev->dev, res);
363 i2c->mst2_offset = drv_data->mst2_offset;
364 if (IS_ERR(i2c->base))
365 return PTR_ERR(i2c->base);
366
367 pr_debug("%s base memory %08x\n", __func__, (u32)i2c->base);
368 i2c->dev = &pdev->dev;
369
370 if (of_property_read_u32(node, "clock-frequency", &clock_freq)) {
371 clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
372 }
373 switch(clock_freq) {
374 case I2C_MAX_STANDARD_MODE_FREQ:
375 i2c->bus_freq = RTL9300_I2C_STD_FREQ;
376 break;
377
378 case I2C_MAX_FAST_MODE_FREQ:
379 i2c->bus_freq = RTL9300_I2C_FAST_FREQ;
380 break;
381 default:
382 dev_warn(i2c->dev, "clock-frequency %d not supported\n", clock_freq);
383 return -EINVAL;
384 }
385
386 dev_info(&pdev->dev, "SCL speed %d, mode is %d\n", clock_freq, i2c->bus_freq);
387
388 if (of_property_read_u32(node, "scl-pin", &pin)) {
389 dev_warn(i2c->dev, "SCL pin not found in DT, using default\n");
390 pin = drv_data->scl0_pin;
391 }
392 if (!(pin == drv_data->scl0_pin || pin == drv_data->scl1_pin)) {
393 dev_warn(i2c->dev, "SCL pin %d not supported\n", pin);
394 return -EINVAL;
395 }
396 i2c->scl_num = pin == drv_data->scl0_pin ? 0 : 1;
397 pr_info("%s scl_num %d\n", __func__, i2c->scl_num);
398
399 if (of_property_read_u32(node, "sda-pin", &pin)) {
400 dev_warn(i2c->dev, "SDA pin not found in DT, using default \n");
401 pin = drv_data->sda0_pin;
402 }
403 i2c->sda_num = pin - drv_data->sda0_pin;
404 if (i2c->sda_num < 0 || i2c->sda_num > 7) {
405 dev_warn(i2c->dev, "SDA pin %d not supported\n", pin);
406 return -EINVAL;
407 }
408 pr_info("%s sda_num %d\n", __func__, i2c->sda_num);
409
410 adap = &i2c->adap;
411 adap->owner = THIS_MODULE;
412 adap->algo = &rtl9300_i2c_algo;
413 adap->retries = 3;
414 adap->dev.parent = &pdev->dev;
415 i2c_set_adapdata(adap, i2c);
416 adap->dev.of_node = node;
417 strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
418
419 platform_set_drvdata(pdev, i2c);
420
421 drv_data->config_io(i2c, i2c->scl_num, i2c->sda_num);
422
423 ret = i2c_add_adapter(adap);
424
425 return ret;
426 }
427
428 static int rtl9300_i2c_remove(struct platform_device *pdev)
429 {
430 struct rtl9300_i2c *i2c = platform_get_drvdata(pdev);
431
432 i2c_del_adapter(&i2c->adap);
433
434 return 0;
435 }
436
437 struct i2c_drv_data rtl9300_i2c_drv_data = {
438 .scl0_pin = 8,
439 .scl1_pin = 17,
440 .sda0_pin = 9,
441 .read = rtl9300_i2c_read,
442 .read = rtl9300_i2c_write,
443 .reg_addr_set = rtl9300_i2c_reg_addr_set,
444 .config_xfer = rtl9300_i2c_config_xfer,
445 .execute_xfer = rtl9300_execute_xfer,
446 .writel = rtl9300_writel,
447 .config_io = rtl9300_i2c_config_io,
448 .mst2_offset = 0x1c,
449 };
450
451 struct i2c_drv_data rtl9310_i2c_drv_data = {
452 .scl0_pin = 13,
453 .scl1_pin = 14,
454 .sda0_pin = 0,
455 .read = rtl9310_i2c_read,
456 .read = rtl9310_i2c_write,
457 .reg_addr_set = rtl9310_i2c_reg_addr_set,
458 .config_xfer = rtl9310_i2c_config_xfer,
459 .execute_xfer = rtl9310_execute_xfer,
460 .writel = rtl9310_writel,
461 .config_io = rtl9310_i2c_config_io,
462 .mst2_offset = 0x18,
463 };
464
465 static const struct of_device_id i2c_rtl9300_dt_ids[] = {
466 { .compatible = "realtek,rtl9300-i2c", .data = (void *) &rtl9300_i2c_drv_data },
467 { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data },
468 { /* sentinel */ }
469 };
470 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
471
472 static struct platform_driver rtl9300_i2c_driver = {
473 .probe = rtl9300_i2c_probe,
474 .remove = rtl9300_i2c_remove,
475 .driver = {
476 .name = "i2c-rtl9300",
477 .pm = NULL,
478 .of_match_table = i2c_rtl9300_dt_ids,
479 },
480 };
481
482 module_platform_driver(rtl9300_i2c_driver);
483
484 MODULE_AUTHOR("Birger Koblitz");
485 MODULE_DESCRIPTION("RTL9300 I2C host driver");
486 MODULE_LICENSE("GPL v2");