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realtek: don't treat first multicast portmask entry as reserved
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
12 {
13 mutex_lock(&priv->reg_mutex);
14
15 /* Enable statistics module: all counters plus debug.
16 * On RTL839x all counters are enabled by default
17 */
18 if (priv->family_id == RTL8380_FAMILY_ID)
19 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
20
21 /* Reset statistics counters */
22 sw_w32_mask(0, 1, priv->r->stat_rst);
23
24 mutex_unlock(&priv->reg_mutex);
25 }
26
27 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
28 {
29 u64 v = 0;
30
31 msleep(1000);
32 /* Enable all ports with a PHY, including the SFP-ports */
33 for (int i = 0; i < priv->cpu_port; i++) {
34 if (priv->ports[i].phy)
35 v |= BIT_ULL(i);
36 }
37
38 pr_info("%s: %16llx\n", __func__, v);
39 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
40
41 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
42 if (priv->family_id == RTL8390_FAMILY_ID)
43 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
44 else if(priv->family_id == RTL9300_FAMILY_ID)
45 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
46 }
47
48 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
49 MIB_DESC(2, 0xf8, "ifInOctets"),
50 MIB_DESC(2, 0xf0, "ifOutOctets"),
51 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
52 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
53 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
54 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
55 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
56 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
57 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
58 MIB_DESC(1, 0xd0, "ifOutDiscards"),
59 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
60 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
61 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
62 MIB_DESC(1, 0xc0, ".3LateCollisions"),
63 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
64 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
65 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
66 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
67 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
68 MIB_DESC(1, 0xa8, "DropEvents"),
69 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
70 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
71 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
72 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
73 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
74 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
75 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
76 MIB_DESC(1, 0x88, "rx_OversizePkts"),
77 MIB_DESC(1, 0x84, "Fragments"),
78 MIB_DESC(1, 0x80, "Jabbers"),
79 MIB_DESC(1, 0x7c, "Collisions"),
80 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
81 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
82 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
83 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
85 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
87 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
89 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
91 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
92 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
93 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x40, "rxMacDiscards")
95 };
96
97
98 /* DSA callbacks */
99
100
101 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
102 int port,
103 enum dsa_tag_protocol mprot)
104 {
105 /* The switch does not tag the frames, instead internally the header
106 * structure for each packet is tagged accordingly.
107 */
108 return DSA_TAG_PROTO_TRAILER;
109 }
110
111 /* Initialize all VLANS */
112 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
113 {
114 struct rtl838x_vlan_info info;
115
116 pr_info("In %s\n", __func__);
117
118 priv->r->vlan_profile_setup(0);
119 priv->r->vlan_profile_setup(1);
120 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
121 priv->r->vlan_profile_dump(0);
122
123 info.fid = 0; /* Default Forwarding ID / MSTI */
124 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
125 info.hash_mc_fid = false; /* Do the same for Multicast packets */
126 info.profile_id = 0; /* Use default Vlan Profile 0 */
127 info.tagged_ports = 0; /* Initially no port members */
128 if (priv->family_id == RTL9310_FAMILY_ID) {
129 info.if_id = 0;
130 info.multicast_grp_mask = 0;
131 info.l2_tunnel_list_id = -1;
132 }
133
134 /* Initialize all vlans 0-4095 */
135 for (int i = 0; i < MAX_VLANS; i ++)
136 priv->r->vlan_set_tagged(i, &info);
137
138 /* reset PVIDs; defaults to 1 on reset */
139 for (int i = 0; i <= priv->ds->num_ports; i++) {
140 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
142 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 }
145
146 /* Set forwarding action based on inner VLAN tag */
147 for (int i = 0; i < priv->cpu_port; i++)
148 priv->r->vlan_fwd_on_inner(i, true);
149 }
150
151 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
152 {
153 for (int i = 0; i < priv->cpu_port; i++)
154 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
155 }
156
157 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
158 int port, bool enable)
159 {
160 int shift = SALRN_PORT_SHIFT(port);
161 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
162
163 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
164 priv->r->l2_port_new_salrn(port));
165 }
166
167 static int rtl83xx_setup(struct dsa_switch *ds)
168 {
169 struct rtl838x_switch_priv *priv = ds->priv;
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (int i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Configure ports so they are disabled by default, but once enabled
181 * they will work in isolated mode (only traffic between port and CPU).
182 */
183 for (int i = 0; i < priv->cpu_port; i++) {
184 if (priv->ports[i].phy) {
185 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
186 priv->r->traffic_set(i, BIT_ULL(i));
187 }
188 }
189 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
190
191 /* For standalone ports, forward packets even if a static fdb
192 * entry for the source address exists on another port.
193 */
194 if (priv->r->set_static_move_action) {
195 for (int i = 0; i <= priv->cpu_port; i++)
196 priv->r->set_static_move_action(i, true);
197 }
198
199 if (priv->family_id == RTL8380_FAMILY_ID)
200 rtl838x_print_matrix();
201 else
202 rtl839x_print_matrix();
203
204 rtl83xx_init_stats(priv);
205
206 rtl83xx_vlan_setup(priv);
207
208 rtl83xx_setup_bpdu_traps(priv);
209
210 ds->configure_vlan_while_not_filtering = true;
211
212 priv->r->l2_learning_setup();
213
214 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
215 ds->assisted_learning_on_cpu_port = true;
216
217 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
218 * 0: FWD, 1: DROP, 2: TRAP2CPU
219 */
220 if (priv->family_id == RTL8380_FAMILY_ID)
221 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
222 else
223 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
224
225 /* Enable MAC Polling PHY again */
226 rtl83xx_enable_phy_polling(priv);
227 pr_debug("Please wait until PHY is settled\n");
228 msleep(1000);
229 priv->r->pie_init(priv);
230
231 return 0;
232 }
233
234 static int rtl93xx_setup(struct dsa_switch *ds)
235 {
236 struct rtl838x_switch_priv *priv = ds->priv;
237
238 pr_info("%s called\n", __func__);
239
240 /* Disable MAC polling the PHY so that we can start configuration */
241 if (priv->family_id == RTL9300_FAMILY_ID)
242 sw_w32(0, RTL930X_SMI_POLL_CTRL);
243
244 if (priv->family_id == RTL9310_FAMILY_ID) {
245 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
247 }
248
249 /* Disable all ports except CPU port */
250 for (int i = 0; i < ds->num_ports; i++)
251 priv->ports[i].enable = false;
252 priv->ports[priv->cpu_port].enable = true;
253
254 /* Configure ports so they are disabled by default, but once enabled
255 * they will work in isolated mode (only traffic between port and CPU).
256 */
257 for (int i = 0; i < priv->cpu_port; i++) {
258 if (priv->ports[i].phy) {
259 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
260 priv->r->traffic_set(i, BIT_ULL(i));
261 }
262 }
263 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
264
265 rtl930x_print_matrix();
266
267 /* TODO: Initialize statistics */
268
269 rtl83xx_vlan_setup(priv);
270
271 ds->configure_vlan_while_not_filtering = true;
272
273 priv->r->l2_learning_setup();
274
275 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
276 ds->assisted_learning_on_cpu_port = true;
277
278 rtl83xx_enable_phy_polling(priv);
279
280 priv->r->pie_init(priv);
281
282 priv->r->led_init(priv);
283
284 return 0;
285 }
286
287 static int rtl93xx_get_sds(struct phy_device *phydev)
288 {
289 struct device *dev = &phydev->mdio.dev;
290 struct device_node *dn;
291 u32 sds_num;
292
293 if (!dev)
294 return -1;
295 if (dev->of_node) {
296 dn = dev->of_node;
297 if (of_property_read_u32(dn, "sds", &sds_num))
298 sds_num = -1;
299 } else {
300 dev_err(dev, "No DT node.\n");
301 return -1;
302 }
303
304 return sds_num;
305 }
306
307 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
308 unsigned long *supported,
309 struct phylink_link_state *state)
310 {
311 struct rtl838x_switch_priv *priv = ds->priv;
312 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
313
314 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
315
316 if (!phy_interface_mode_is_rgmii(state->interface) &&
317 state->interface != PHY_INTERFACE_MODE_NA &&
318 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
319 state->interface != PHY_INTERFACE_MODE_MII &&
320 state->interface != PHY_INTERFACE_MODE_REVMII &&
321 state->interface != PHY_INTERFACE_MODE_GMII &&
322 state->interface != PHY_INTERFACE_MODE_QSGMII &&
323 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
324 state->interface != PHY_INTERFACE_MODE_SGMII) {
325 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
326 dev_err(ds->dev,
327 "Unsupported interface: %d for port %d\n",
328 state->interface, port);
329 return;
330 }
331
332 /* Allow all the expected bits */
333 phylink_set(mask, Autoneg);
334 phylink_set_port_modes(mask);
335 phylink_set(mask, Pause);
336 phylink_set(mask, Asym_Pause);
337
338 /* With the exclusion of MII and Reverse MII, we support Gigabit,
339 * including Half duplex
340 */
341 if (state->interface != PHY_INTERFACE_MODE_MII &&
342 state->interface != PHY_INTERFACE_MODE_REVMII) {
343 phylink_set(mask, 1000baseT_Full);
344 phylink_set(mask, 1000baseT_Half);
345 }
346
347 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
348 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
349 phylink_set(mask, 1000baseX_Full);
350
351 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
352 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
353 phylink_set(mask, 1000baseX_Full);
354
355 phylink_set(mask, 10baseT_Half);
356 phylink_set(mask, 10baseT_Full);
357 phylink_set(mask, 100baseT_Half);
358 phylink_set(mask, 100baseT_Full);
359
360 bitmap_and(supported, supported, mask,
361 __ETHTOOL_LINK_MODE_MASK_NBITS);
362 bitmap_and(state->advertising, state->advertising, mask,
363 __ETHTOOL_LINK_MODE_MASK_NBITS);
364 }
365
366 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
367 unsigned long *supported,
368 struct phylink_link_state *state)
369 {
370 struct rtl838x_switch_priv *priv = ds->priv;
371 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
372
373 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
374 phy_modes(state->interface));
375
376 if (!phy_interface_mode_is_rgmii(state->interface) &&
377 state->interface != PHY_INTERFACE_MODE_NA &&
378 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
379 state->interface != PHY_INTERFACE_MODE_MII &&
380 state->interface != PHY_INTERFACE_MODE_REVMII &&
381 state->interface != PHY_INTERFACE_MODE_GMII &&
382 state->interface != PHY_INTERFACE_MODE_QSGMII &&
383 state->interface != PHY_INTERFACE_MODE_XGMII &&
384 state->interface != PHY_INTERFACE_MODE_HSGMII &&
385 state->interface != PHY_INTERFACE_MODE_10GBASER &&
386 state->interface != PHY_INTERFACE_MODE_10GKR &&
387 state->interface != PHY_INTERFACE_MODE_USXGMII &&
388 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
389 state->interface != PHY_INTERFACE_MODE_SGMII) {
390 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
391 dev_err(ds->dev,
392 "Unsupported interface: %d for port %d\n",
393 state->interface, port);
394 return;
395 }
396
397 /* Allow all the expected bits */
398 phylink_set(mask, Autoneg);
399 phylink_set_port_modes(mask);
400 phylink_set(mask, Pause);
401 phylink_set(mask, Asym_Pause);
402
403 /* With the exclusion of MII and Reverse MII, we support Gigabit,
404 * including Half duplex
405 */
406 if (state->interface != PHY_INTERFACE_MODE_MII &&
407 state->interface != PHY_INTERFACE_MODE_REVMII) {
408 phylink_set(mask, 1000baseT_Full);
409 phylink_set(mask, 1000baseT_Half);
410 }
411
412 /* Internal phys of the RTL93xx family provide 10G */
413 if (priv->ports[port].phy_is_integrated &&
414 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
415 phylink_set(mask, 1000baseX_Full);
416 } else if (priv->ports[port].phy_is_integrated) {
417 phylink_set(mask, 1000baseX_Full);
418 phylink_set(mask, 10000baseKR_Full);
419 phylink_set(mask, 10000baseSR_Full);
420 phylink_set(mask, 10000baseCR_Full);
421 }
422 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
423 phylink_set(mask, 1000baseX_Full);
424 phylink_set(mask, 1000baseT_Full);
425 phylink_set(mask, 10000baseKR_Full);
426 phylink_set(mask, 10000baseT_Full);
427 phylink_set(mask, 10000baseSR_Full);
428 phylink_set(mask, 10000baseCR_Full);
429 }
430
431 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
432 phylink_set(mask, 10000baseT_Full);
433
434 phylink_set(mask, 10baseT_Half);
435 phylink_set(mask, 10baseT_Full);
436 phylink_set(mask, 100baseT_Half);
437 phylink_set(mask, 100baseT_Full);
438
439 bitmap_and(supported, supported, mask,
440 __ETHTOOL_LINK_MODE_MASK_NBITS);
441 bitmap_and(state->advertising, state->advertising, mask,
442 __ETHTOOL_LINK_MODE_MASK_NBITS);
443 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
444 }
445
446 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
447 struct phylink_link_state *state)
448 {
449 struct rtl838x_switch_priv *priv = ds->priv;
450 u64 speed;
451 u64 link;
452
453 if (port < 0 || port > priv->cpu_port)
454 return -EINVAL;
455
456 state->link = 0;
457 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
458 if (link & BIT_ULL(port))
459 state->link = 1;
460 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
461
462 state->duplex = 0;
463 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
464 state->duplex = 1;
465
466 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
467 speed >>= (port % 16) << 1;
468 switch (speed & 0x3) {
469 case 0:
470 state->speed = SPEED_10;
471 break;
472 case 1:
473 state->speed = SPEED_100;
474 break;
475 case 2:
476 state->speed = SPEED_1000;
477 break;
478 case 3:
479 if (priv->family_id == RTL9300_FAMILY_ID
480 && (port == 24 || port == 26)) /* Internal serdes */
481 state->speed = SPEED_2500;
482 else
483 state->speed = SPEED_100; /* Is in fact 500Mbit */
484 }
485
486 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
487 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
488 state->pause |= MLO_PAUSE_RX;
489 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
490 state->pause |= MLO_PAUSE_TX;
491
492 return 1;
493 }
494
495 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
496 struct phylink_link_state *state)
497 {
498 struct rtl838x_switch_priv *priv = ds->priv;
499 u64 speed;
500 u64 link;
501 u64 media;
502
503 if (port < 0 || port > priv->cpu_port)
504 return -EINVAL;
505
506 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
507 * state needs to be read twice in order to read a correct result.
508 * This would not be necessary for ports connected e.g. to RTL8218D
509 * PHYs.
510 */
511 state->link = 0;
512 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
513 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
514 if (link & BIT_ULL(port))
515 state->link = 1;
516
517 if (priv->family_id == RTL9310_FAMILY_ID)
518 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
519
520 if (priv->family_id == RTL9300_FAMILY_ID)
521 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
522
523 if (media & BIT_ULL(port))
524 state->link = 1;
525
526 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
527 link & BIT_ULL(port), media);
528
529 state->duplex = 0;
530 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
531 state->duplex = 1;
532
533 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
534 speed >>= (port % 8) << 2;
535 switch (speed & 0xf) {
536 case 0:
537 state->speed = SPEED_10;
538 break;
539 case 1:
540 state->speed = SPEED_100;
541 break;
542 case 2:
543 case 7:
544 state->speed = SPEED_1000;
545 break;
546 case 4:
547 state->speed = SPEED_10000;
548 break;
549 case 5:
550 case 8:
551 state->speed = SPEED_2500;
552 break;
553 case 6:
554 state->speed = SPEED_5000;
555 break;
556 default:
557 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
558 }
559
560 if (priv->family_id == RTL9310_FAMILY_ID
561 && (port >= 52 || port <= 55)) { /* Internal serdes */
562 state->speed = SPEED_10000;
563 state->link = 1;
564 state->duplex = 1;
565 }
566
567 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
568 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
569 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
570 state->pause |= MLO_PAUSE_RX;
571 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
572 state->pause |= MLO_PAUSE_TX;
573
574 return 1;
575 }
576
577 static void rtl83xx_config_interface(int port, phy_interface_t interface)
578 {
579 u32 old, int_shift, sds_shift;
580
581 switch (port) {
582 case 24:
583 int_shift = 0;
584 sds_shift = 5;
585 break;
586 case 26:
587 int_shift = 3;
588 sds_shift = 0;
589 break;
590 default:
591 return;
592 }
593
594 old = sw_r32(RTL838X_SDS_MODE_SEL);
595 switch (interface) {
596 case PHY_INTERFACE_MODE_1000BASEX:
597 if ((old >> sds_shift & 0x1f) == 4)
598 return;
599 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
600 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
601 break;
602 case PHY_INTERFACE_MODE_SGMII:
603 if ((old >> sds_shift & 0x1f) == 2)
604 return;
605 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
606 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
607 break;
608 default:
609 return;
610 }
611 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
612 }
613
614 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
615 unsigned int mode,
616 const struct phylink_link_state *state)
617 {
618 struct rtl838x_switch_priv *priv = ds->priv;
619 u32 reg;
620 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
621
622 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
623
624 if (port == priv->cpu_port) {
625 /* Set Speed, duplex, flow control
626 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
627 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
628 * | MEDIA_SEL
629 */
630 if (priv->family_id == RTL8380_FAMILY_ID) {
631 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
632 /* allow CRC errors on CPU-port */
633 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
634 } else {
635 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
636 }
637 return;
638 }
639
640 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
641 /* Auto-Negotiation does not work for MAC in RTL8390 */
642 if (priv->family_id == RTL8380_FAMILY_ID) {
643 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
644 pr_debug("PHY autonegotiates\n");
645 reg |= RTL838X_NWAY_EN;
646 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
647 rtl83xx_config_interface(port, state->interface);
648 return;
649 }
650 }
651
652 if (mode != MLO_AN_FIXED)
653 pr_debug("Fixed state.\n");
654
655 /* Clear id_mode_dis bit, and the existing port mode, let
656 * RGMII_MODE_EN bet set by mac_link_{up,down} */
657 if (priv->family_id == RTL8380_FAMILY_ID) {
658 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
659 if (state->pause & MLO_PAUSE_TXRX_MASK) {
660 if (state->pause & MLO_PAUSE_TX)
661 reg |= RTL838X_TX_PAUSE_EN;
662 reg |= RTL838X_RX_PAUSE_EN;
663 }
664 } else if (priv->family_id == RTL8390_FAMILY_ID) {
665 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
666 if (state->pause & MLO_PAUSE_TXRX_MASK) {
667 if (state->pause & MLO_PAUSE_TX)
668 reg |= RTL839X_TX_PAUSE_EN;
669 reg |= RTL839X_RX_PAUSE_EN;
670 }
671 }
672
673
674 reg &= ~(3 << speed_bit);
675 switch (state->speed) {
676 case SPEED_1000:
677 reg |= 2 << speed_bit;
678 break;
679 case SPEED_100:
680 reg |= 1 << speed_bit;
681 break;
682 default:
683 break; /* Ignore, including 10MBit which has a speed value of 0 */
684 }
685
686 if (priv->family_id == RTL8380_FAMILY_ID) {
687 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
688 if (state->link)
689 reg |= RTL838X_FORCE_LINK_EN;
690 if (state->duplex == RTL838X_DUPLEX_MODE)
691 reg |= RTL838X_DUPLEX_MODE;
692 } else if (priv->family_id == RTL8390_FAMILY_ID) {
693 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
694 if (state->link)
695 reg |= RTL839X_FORCE_LINK_EN;
696 if (state->duplex == RTL839X_DUPLEX_MODE)
697 reg |= RTL839X_DUPLEX_MODE;
698 }
699
700 /* LAG members must use DUPLEX and we need to enable the link */
701 if (priv->lagmembers & BIT_ULL(port)) {
702 switch(priv->family_id) {
703 case RTL8380_FAMILY_ID:
704 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
705 break;
706 case RTL8390_FAMILY_ID:
707 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
708 break;
709 }
710 }
711
712 /* Disable AN */
713 if (priv->family_id == RTL8380_FAMILY_ID)
714 reg &= ~RTL838X_NWAY_EN;
715 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
716 }
717
718 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
719 unsigned int mode,
720 const struct phylink_link_state *state)
721 {
722 struct rtl838x_switch_priv *priv = ds->priv;
723 int sds_num;
724 u32 reg, band;
725
726 sds_num = priv->ports[port].sds_num;
727 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
728
729 switch (state->interface) {
730 case PHY_INTERFACE_MODE_HSGMII:
731 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
732 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
733 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
734 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
735 break;
736 case PHY_INTERFACE_MODE_1000BASEX:
737 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
738 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
739 break;
740 case PHY_INTERFACE_MODE_XGMII:
741 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
742 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
743 break;
744 case PHY_INTERFACE_MODE_10GBASER:
745 case PHY_INTERFACE_MODE_10GKR:
746 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
747 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
748 break;
749 case PHY_INTERFACE_MODE_USXGMII:
750 /* Translates to MII_USXGMII_10GSXGMII */
751 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
752 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
753 break;
754 case PHY_INTERFACE_MODE_SGMII:
755 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
756 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
757 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
758 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
759 break;
760 case PHY_INTERFACE_MODE_QSGMII:
761 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
762 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
763 break;
764 default:
765 pr_err("%s: unknown serdes mode: %s\n",
766 __func__, phy_modes(state->interface));
767 return;
768 }
769
770 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
771 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
772
773 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
774
775 reg &= ~(0xf << 12);
776 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
777
778 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
779
780 if (priv->lagmembers & BIT_ULL(port))
781 reg |= RTL931X_DUPLEX_MODE;
782
783 if (state->duplex == DUPLEX_FULL)
784 reg |= RTL931X_DUPLEX_MODE;
785
786 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
787
788 }
789
790 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
791 unsigned int mode,
792 const struct phylink_link_state *state)
793 {
794 struct rtl838x_switch_priv *priv = ds->priv;
795 int sds_num, sds_mode;
796 u32 reg;
797
798 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
799 port, mode, phy_modes(state->interface), state->speed, state->link);
800
801 /* Nothing to be done for the CPU-port */
802 if (port == priv->cpu_port)
803 return;
804
805 if (priv->family_id == RTL9310_FAMILY_ID)
806 return rtl931x_phylink_mac_config(ds, port, mode, state);
807
808 sds_num = priv->ports[port].sds_num;
809 pr_info("%s SDS is %d\n", __func__, sds_num);
810 if (sds_num >= 0) {
811 switch (state->interface) {
812 case PHY_INTERFACE_MODE_HSGMII:
813 sds_mode = 0x12;
814 break;
815 case PHY_INTERFACE_MODE_1000BASEX:
816 sds_mode = 0x04;
817 break;
818 case PHY_INTERFACE_MODE_XGMII:
819 sds_mode = 0x10;
820 break;
821 case PHY_INTERFACE_MODE_10GBASER:
822 case PHY_INTERFACE_MODE_10GKR:
823 sds_mode = 0x1b; /* 10G 1000X Auto */
824 break;
825 case PHY_INTERFACE_MODE_USXGMII:
826 sds_mode = 0x0d;
827 break;
828 default:
829 pr_err("%s: unknown serdes mode: %s\n",
830 __func__, phy_modes(state->interface));
831 return;
832 }
833 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
834 rtl9300_serdes_setup(sds_num, state->interface);
835 }
836
837 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
838 reg &= ~(0xf << 3);
839
840 switch (state->speed) {
841 case SPEED_10000:
842 reg |= 4 << 3;
843 break;
844 case SPEED_5000:
845 reg |= 6 << 3;
846 break;
847 case SPEED_2500:
848 reg |= 5 << 3;
849 break;
850 case SPEED_1000:
851 reg |= 2 << 3;
852 break;
853 default:
854 reg |= 2 << 3;
855 break;
856 }
857
858 if (state->link)
859 reg |= RTL930X_FORCE_LINK_EN;
860
861 if (priv->lagmembers & BIT_ULL(port))
862 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
863
864 if (state->duplex == DUPLEX_FULL)
865 reg |= RTL930X_DUPLEX_MODE;
866
867 if (priv->ports[port].phy_is_integrated)
868 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
869 else
870 reg |= RTL930X_FORCE_EN;
871
872 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
873 }
874
875 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
876 unsigned int mode,
877 phy_interface_t interface)
878 {
879 struct rtl838x_switch_priv *priv = ds->priv;
880
881 /* Stop TX/RX to port */
882 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
883
884 /* No longer force link */
885 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
886 }
887
888 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
889 unsigned int mode,
890 phy_interface_t interface)
891 {
892 struct rtl838x_switch_priv *priv = ds->priv;
893 u32 v = 0;
894
895 /* Stop TX/RX to port */
896 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
897
898 /* No longer force link */
899 if (priv->family_id == RTL9300_FAMILY_ID)
900 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
901 else if (priv->family_id == RTL9310_FAMILY_ID)
902 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
903 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
904 }
905
906 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
907 unsigned int mode,
908 phy_interface_t interface,
909 struct phy_device *phydev,
910 int speed, int duplex,
911 bool tx_pause, bool rx_pause)
912 {
913 struct rtl838x_switch_priv *priv = ds->priv;
914 /* Restart TX/RX to port */
915 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
916 /* TODO: Set speed/duplex/pauses */
917 }
918
919 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
920 unsigned int mode,
921 phy_interface_t interface,
922 struct phy_device *phydev,
923 int speed, int duplex,
924 bool tx_pause, bool rx_pause)
925 {
926 struct rtl838x_switch_priv *priv = ds->priv;
927
928 /* Restart TX/RX to port */
929 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
930 /* TODO: Set speed/duplex/pauses */
931 }
932
933 static void rtl83xx_get_strings(struct dsa_switch *ds,
934 int port, u32 stringset, u8 *data)
935 {
936 if (stringset != ETH_SS_STATS)
937 return;
938
939 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
940 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
941 ETH_GSTRING_LEN);
942 }
943
944 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
945 uint64_t *data)
946 {
947 struct rtl838x_switch_priv *priv = ds->priv;
948 const struct rtl83xx_mib_desc *mib;
949 u64 h;
950
951 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
952 mib = &rtl83xx_mib[i];
953
954 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
955 if (mib->size == 2) {
956 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
957 data[i] |= h << 32;
958 }
959 }
960 }
961
962 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
963 {
964 if (sset != ETH_SS_STATS)
965 return 0;
966
967 return ARRAY_SIZE(rtl83xx_mib);
968 }
969
970 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
971 {
972 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
973 u64 portmask;
974
975 if (mc_group >= MAX_MC_GROUPS - 1)
976 return -1;
977
978 if (priv->is_lagmember[port]) {
979 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
980 return 0;
981 }
982
983 set_bit(mc_group, priv->mc_group_bm);
984 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
985 priv->r->write_mcast_pmask(mc_group, portmask);
986
987 return mc_group;
988 }
989
990 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
991 {
992 u64 portmask = priv->r->read_mcast_pmask(mc_group);
993
994 pr_debug("%s: %d\n", __func__, port);
995 if (priv->is_lagmember[port]) {
996 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
997 return portmask;
998 }
999 portmask |= BIT_ULL(port);
1000 priv->r->write_mcast_pmask(mc_group, portmask);
1001
1002 return portmask;
1003 }
1004
1005 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1006 {
1007 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1008
1009 pr_debug("%s: %d\n", __func__, port);
1010 if (priv->is_lagmember[port]) {
1011 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1012 return portmask;
1013 }
1014 priv->r->write_mcast_pmask(mc_group, portmask);
1015 if (portmask == BIT_ULL(priv->cpu_port)) {
1016 portmask &= ~BIT_ULL(priv->cpu_port);
1017 priv->r->write_mcast_pmask(mc_group, portmask);
1018 clear_bit(mc_group, priv->mc_group_bm);
1019 }
1020
1021 return portmask;
1022 }
1023
1024 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1025 {
1026 for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1027 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1028 if (portmask & BIT_ULL(port)) {
1029 priv->mc_group_saves[mc_group] = port;
1030 rtl83xx_mc_group_del_port(priv, mc_group, port);
1031 }
1032 }
1033 }
1034
1035 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1036 {
1037 for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1038 if (priv->mc_group_saves[mc_group] == port) {
1039 rtl83xx_mc_group_add_port(priv, mc_group, port);
1040 priv->mc_group_saves[mc_group] = -1;
1041 }
1042 }
1043 }
1044
1045 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1046 struct phy_device *phydev)
1047 {
1048 struct rtl838x_switch_priv *priv = ds->priv;
1049 u64 v;
1050
1051 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1052 priv->ports[port].enable = true;
1053
1054 /* enable inner tagging on egress, do not keep any tags */
1055 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1056
1057 if (dsa_is_cpu_port(ds, port))
1058 return 0;
1059
1060 /* add port to switch mask of CPU_PORT */
1061 priv->r->traffic_enable(priv->cpu_port, port);
1062
1063 load_mcgroups(priv, port);
1064
1065 if (priv->is_lagmember[port]) {
1066 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1067 return 0;
1068 }
1069
1070 /* add all other ports in the same bridge to switch mask of port */
1071 v = priv->r->traffic_get(port);
1072 v |= priv->ports[port].pm;
1073 priv->r->traffic_set(port, v);
1074
1075 /* TODO: Figure out if this is necessary */
1076 if (priv->family_id == RTL9300_FAMILY_ID) {
1077 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1078 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1079 }
1080
1081 if (priv->ports[port].sds_num < 0)
1082 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1083
1084 return 0;
1085 }
1086
1087 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1088 {
1089 struct rtl838x_switch_priv *priv = ds->priv;
1090 u64 v;
1091
1092 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1093 /* you can only disable user ports */
1094 if (!dsa_is_user_port(ds, port))
1095 return;
1096
1097 /* BUG: This does not work on RTL931X */
1098 /* remove port from switch mask of CPU_PORT */
1099 priv->r->traffic_disable(priv->cpu_port, port);
1100 store_mcgroups(priv, port);
1101
1102 /* remove all other ports in the same bridge from switch mask of port */
1103 v = priv->r->traffic_get(port);
1104 v &= ~priv->ports[port].pm;
1105 priv->r->traffic_set(port, v);
1106
1107 priv->ports[port].enable = false;
1108 }
1109
1110 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1111 struct ethtool_eee *e)
1112 {
1113 struct rtl838x_switch_priv *priv = ds->priv;
1114
1115 if (e->eee_enabled && !priv->eee_enabled) {
1116 pr_info("Globally enabling EEE\n");
1117 priv->r->init_eee(priv, true);
1118 }
1119
1120 priv->r->port_eee_set(priv, port, e->eee_enabled);
1121
1122 if (e->eee_enabled)
1123 pr_info("Enabled EEE for port %d\n", port);
1124 else
1125 pr_info("Disabled EEE for port %d\n", port);
1126
1127 return 0;
1128 }
1129
1130 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1131 struct ethtool_eee *e)
1132 {
1133 struct rtl838x_switch_priv *priv = ds->priv;
1134
1135 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1136
1137 priv->r->eee_port_ability(priv, e, port);
1138
1139 e->eee_enabled = priv->ports[port].eee_enabled;
1140
1141 e->eee_active = !!(e->advertised & e->lp_advertised);
1142
1143 return 0;
1144 }
1145
1146 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1147 struct ethtool_eee *e)
1148 {
1149 struct rtl838x_switch_priv *priv = ds->priv;
1150
1151 e->supported = SUPPORTED_100baseT_Full |
1152 SUPPORTED_1000baseT_Full |
1153 SUPPORTED_2500baseX_Full;
1154
1155 priv->r->eee_port_ability(priv, e, port);
1156
1157 e->eee_enabled = priv->ports[port].eee_enabled;
1158
1159 e->eee_active = !!(e->advertised & e->lp_advertised);
1160
1161 return 0;
1162 }
1163
1164 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1165 {
1166 struct rtl838x_switch_priv *priv = ds->priv;
1167
1168 priv->r->set_ageing_time(msec);
1169
1170 return 0;
1171 }
1172
1173 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1174 struct net_device *bridge)
1175 {
1176 struct rtl838x_switch_priv *priv = ds->priv;
1177 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1178
1179 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1180
1181 if (priv->is_lagmember[port]) {
1182 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1183 return 0;
1184 }
1185
1186 mutex_lock(&priv->reg_mutex);
1187 for (int i = 0; i < ds->num_ports; i++) {
1188 /* Add this port to the port matrix of the other ports in the
1189 * same bridge. If the port is disabled, port matrix is kept
1190 * and not being setup until the port becomes enabled.
1191 */
1192 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1193 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1194 continue;
1195 if (priv->ports[i].enable)
1196 priv->r->traffic_enable(i, port);
1197
1198 priv->ports[i].pm |= BIT_ULL(port);
1199 port_bitmap |= BIT_ULL(i);
1200 }
1201 }
1202 load_mcgroups(priv, port);
1203
1204 /* Add all other ports to this port matrix. */
1205 if (priv->ports[port].enable) {
1206 priv->r->traffic_enable(priv->cpu_port, port);
1207 v = priv->r->traffic_get(port);
1208 v |= port_bitmap;
1209 priv->r->traffic_set(port, v);
1210 }
1211 priv->ports[port].pm |= port_bitmap;
1212
1213 if (priv->r->set_static_move_action)
1214 priv->r->set_static_move_action(port, false);
1215
1216 mutex_unlock(&priv->reg_mutex);
1217
1218 return 0;
1219 }
1220
1221 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1222 struct net_device *bridge)
1223 {
1224 struct rtl838x_switch_priv *priv = ds->priv;
1225 u64 port_bitmap = 0, v;
1226
1227 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1228 mutex_lock(&priv->reg_mutex);
1229 for (int i = 0; i < ds->num_ports; i++) {
1230 /* Remove this port from the port matrix of the other ports
1231 * in the same bridge. If the port is disabled, port matrix
1232 * is kept and not being setup until the port becomes enabled.
1233 * And the other port's port matrix cannot be broken when the
1234 * other port is still a VLAN-aware port.
1235 */
1236 if (dsa_is_user_port(ds, i) && i != port) {
1237 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1238 continue;
1239 if (priv->ports[i].enable)
1240 priv->r->traffic_disable(i, port);
1241
1242 priv->ports[i].pm &= ~BIT_ULL(port);
1243 port_bitmap |= BIT_ULL(i);
1244 }
1245 }
1246 store_mcgroups(priv, port);
1247
1248 /* Remove all other ports from this port matrix. */
1249 if (priv->ports[port].enable) {
1250 v = priv->r->traffic_get(port);
1251 v &= ~port_bitmap;
1252 priv->r->traffic_set(port, v);
1253 }
1254 priv->ports[port].pm &= ~port_bitmap;
1255
1256 if (priv->r->set_static_move_action)
1257 priv->r->set_static_move_action(port, true);
1258
1259 mutex_unlock(&priv->reg_mutex);
1260 }
1261
1262 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1263 {
1264 u32 msti = 0;
1265 u32 port_state[4];
1266 int index, bit;
1267 int pos = port;
1268 struct rtl838x_switch_priv *priv = ds->priv;
1269 int n = priv->port_width << 1;
1270
1271 /* Ports above or equal CPU port can never be configured */
1272 if (port >= priv->cpu_port)
1273 return;
1274
1275 mutex_lock(&priv->reg_mutex);
1276
1277 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1278 * have 64 bit fields, 839x and 931x have 128 bit fields
1279 */
1280 if (priv->family_id == RTL8390_FAMILY_ID)
1281 pos += 12;
1282 if (priv->family_id == RTL9300_FAMILY_ID)
1283 pos += 3;
1284 if (priv->family_id == RTL9310_FAMILY_ID)
1285 pos += 8;
1286
1287 index = n - (pos >> 4) - 1;
1288 bit = (pos << 1) % 32;
1289
1290 priv->r->stp_get(priv, msti, port_state);
1291
1292 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1293 port_state[index] &= ~(3 << bit);
1294
1295 switch (state) {
1296 case BR_STATE_DISABLED: /* 0 */
1297 port_state[index] |= (0 << bit);
1298 break;
1299 case BR_STATE_BLOCKING: /* 4 */
1300 case BR_STATE_LISTENING: /* 1 */
1301 port_state[index] |= (1 << bit);
1302 break;
1303 case BR_STATE_LEARNING: /* 2 */
1304 port_state[index] |= (2 << bit);
1305 break;
1306 case BR_STATE_FORWARDING: /* 3 */
1307 port_state[index] |= (3 << bit);
1308 default:
1309 break;
1310 }
1311
1312 priv->r->stp_set(priv, msti, port_state);
1313
1314 mutex_unlock(&priv->reg_mutex);
1315 }
1316
1317 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1318 {
1319 struct rtl838x_switch_priv *priv = ds->priv;
1320 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1321
1322 pr_debug("FAST AGE port %d\n", port);
1323 mutex_lock(&priv->reg_mutex);
1324 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1325 * port fields:
1326 * 0-4: Replacing port
1327 * 5-9: Flushed/replaced port
1328 * 10-21: FVID
1329 * 22: Entry types: 1: dynamic, 0: also static
1330 * 23: Match flush port
1331 * 24: Match FVID
1332 * 25: Flush (0) or replace (1) L2 entries
1333 * 26: Status of action (1: Start, 0: Done)
1334 */
1335 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1336
1337 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1338
1339 mutex_unlock(&priv->reg_mutex);
1340 }
1341
1342 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1343 {
1344 struct rtl838x_switch_priv *priv = ds->priv;
1345
1346 pr_info("%s port %d\n", __func__, port);
1347 mutex_lock(&priv->reg_mutex);
1348 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1349
1350 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1351
1352 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1353
1354 mutex_unlock(&priv->reg_mutex);
1355 }
1356
1357 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1358 {
1359 struct rtl838x_switch_priv *priv = ds->priv;
1360
1361 if (priv->family_id == RTL9310_FAMILY_ID)
1362 return rtl931x_fast_age(ds, port);
1363
1364 pr_debug("FAST AGE port %d\n", port);
1365 mutex_lock(&priv->reg_mutex);
1366 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1367
1368 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1369
1370 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1371
1372 mutex_unlock(&priv->reg_mutex);
1373 }
1374
1375 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1376 bool vlan_filtering,
1377 struct netlink_ext_ack *extack)
1378 {
1379 struct rtl838x_switch_priv *priv = ds->priv;
1380
1381 pr_debug("%s: port %d\n", __func__, port);
1382 mutex_lock(&priv->reg_mutex);
1383
1384 if (vlan_filtering) {
1385 /* Enable ingress and egress filtering
1386 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1387 * the filter action:
1388 * 0: Always Forward
1389 * 1: Drop packet
1390 * 2: Trap packet to CPU port
1391 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1392 */
1393 if (port != priv->cpu_port)
1394 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1395
1396 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1397 } else {
1398 /* Disable ingress and egress filtering */
1399 if (port != priv->cpu_port)
1400 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1401
1402 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1403 }
1404
1405 /* Do we need to do something to the CPU-Port, too? */
1406 mutex_unlock(&priv->reg_mutex);
1407
1408 return 0;
1409 }
1410
1411 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1412 const struct switchdev_obj_port_vlan *vlan)
1413 {
1414 struct rtl838x_vlan_info info;
1415 struct rtl838x_switch_priv *priv = ds->priv;
1416
1417 priv->r->vlan_tables_read(0, &info);
1418
1419 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1420 info.tagged_ports, info.untagged_ports, info.profile_id,
1421 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1422
1423 priv->r->vlan_tables_read(1, &info);
1424 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1425 info.tagged_ports, info.untagged_ports, info.profile_id,
1426 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1427 priv->r->vlan_set_untagged(1, info.untagged_ports);
1428 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1429
1430 priv->r->vlan_set_tagged(1, &info);
1431 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1432
1433 return 0;
1434 }
1435
1436 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1437 int port, int pvid)
1438 {
1439 /* Set both inner and outer PVID of the port */
1440 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1441 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1442 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1443 PBVLAN_MODE_UNTAG_AND_PRITAG);
1444 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1445 PBVLAN_MODE_UNTAG_AND_PRITAG);
1446
1447 priv->ports[port].pvid = pvid;
1448 }
1449
1450 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1451 const struct switchdev_obj_port_vlan *vlan,
1452 struct netlink_ext_ack *extack)
1453 {
1454 struct rtl838x_vlan_info info;
1455 struct rtl838x_switch_priv *priv = ds->priv;
1456 int err;
1457
1458 pr_debug("%s port %d, vid %d, flags %x\n",
1459 __func__, port, vlan->vid, vlan->flags);
1460
1461 if (vlan->vid > 4095) {
1462 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1463 return -ENOTSUPP;
1464 }
1465
1466 err = rtl83xx_vlan_prepare(ds, port, vlan);
1467 if (err)
1468 return err;
1469
1470 mutex_lock(&priv->reg_mutex);
1471
1472 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1473 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1474 else if (priv->ports[port].pvid == vlan->vid)
1475 rtl83xx_vlan_set_pvid(priv, port, 0);
1476
1477 /* Get port memberships of this vlan */
1478 priv->r->vlan_tables_read(vlan->vid, &info);
1479
1480 /* new VLAN? */
1481 if (!info.tagged_ports) {
1482 info.fid = 0;
1483 info.hash_mc_fid = false;
1484 info.hash_uc_fid = false;
1485 info.profile_id = 0;
1486 }
1487
1488 /* sanitize untagged_ports - must be a subset */
1489 if (info.untagged_ports & ~info.tagged_ports)
1490 info.untagged_ports = 0;
1491
1492 info.tagged_ports |= BIT_ULL(port);
1493 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1494 info.untagged_ports |= BIT_ULL(port);
1495 else
1496 info.untagged_ports &= ~BIT_ULL(port);
1497
1498 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1499 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1500
1501 priv->r->vlan_set_tagged(vlan->vid, &info);
1502 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1503
1504 mutex_unlock(&priv->reg_mutex);
1505
1506 return 0;
1507 }
1508
1509 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1510 const struct switchdev_obj_port_vlan *vlan)
1511 {
1512 struct rtl838x_vlan_info info;
1513 struct rtl838x_switch_priv *priv = ds->priv;
1514 u16 pvid;
1515
1516 pr_debug("%s: port %d, vid %d, flags %x\n",
1517 __func__, port, vlan->vid, vlan->flags);
1518
1519 if (vlan->vid > 4095) {
1520 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1521 return -ENOTSUPP;
1522 }
1523
1524 mutex_lock(&priv->reg_mutex);
1525 pvid = priv->ports[port].pvid;
1526
1527 /* Reset to default if removing the current PVID */
1528 if (vlan->vid == pvid) {
1529 rtl83xx_vlan_set_pvid(priv, port, 0);
1530 }
1531 /* Get port memberships of this vlan */
1532 priv->r->vlan_tables_read(vlan->vid, &info);
1533
1534 /* remove port from both tables */
1535 info.untagged_ports &= (~BIT_ULL(port));
1536 info.tagged_ports &= (~BIT_ULL(port));
1537
1538 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1539 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1540
1541 priv->r->vlan_set_tagged(vlan->vid, &info);
1542 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1543
1544 mutex_unlock(&priv->reg_mutex);
1545
1546 return 0;
1547 }
1548
1549 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1550 {
1551 memset(e, 0, sizeof(*e));
1552
1553 e->type = L2_UNICAST;
1554 e->valid = true;
1555
1556 e->age = 3;
1557 e->is_static = true;
1558
1559 e->port = port;
1560
1561 e->rvid = e->vid = vid;
1562 e->is_ip_mc = e->is_ipv6_mc = false;
1563 u64_to_ether_addr(mac, e->mac);
1564 }
1565
1566 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1567 {
1568 memset(e, 0, sizeof(*e));
1569
1570 e->type = L2_MULTICAST;
1571 e->valid = true;
1572
1573 e->mc_portmask_index = mc_group;
1574
1575 e->rvid = e->vid = vid;
1576 e->is_ip_mc = e->is_ipv6_mc = false;
1577 u64_to_ether_addr(mac, e->mac);
1578 }
1579
1580 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1581 * over the entries in the bucket until either a matching entry is found or an empty slot
1582 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1583 * when an empty slot was found and must exist is false, the index of the slot is returned
1584 * when no slots are available returns -1
1585 */
1586 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1587 bool must_exist, struct rtl838x_l2_entry *e)
1588 {
1589 int idx = -1;
1590 u32 key = priv->r->l2_hash_key(priv, seed);
1591 u64 entry;
1592
1593 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1594 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1595 for (int i = 0; i < priv->l2_bucket_size; i++) {
1596 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1597 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1598 if (must_exist && !e->valid)
1599 continue;
1600 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1601 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1602 break;
1603 }
1604 }
1605
1606 return idx;
1607 }
1608
1609 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1610 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1611 * when an empty slot was found the index of the slot is returned
1612 * when no slots are available returns -1
1613 */
1614 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1615 bool must_exist, struct rtl838x_l2_entry *e)
1616 {
1617 int idx = -1;
1618 u64 entry;
1619
1620 for (int i = 0; i < 64; i++) {
1621 entry = priv->r->read_cam(i, e);
1622 if (!must_exist && !e->valid) {
1623 if (idx < 0) /* First empty entry? */
1624 idx = i;
1625 break;
1626 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1627 pr_debug("Found entry in CAM\n");
1628 idx = i;
1629 break;
1630 }
1631 }
1632
1633 return idx;
1634 }
1635
1636 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1637 const unsigned char *addr, u16 vid)
1638 {
1639 struct rtl838x_switch_priv *priv = ds->priv;
1640 u64 mac = ether_addr_to_u64(addr);
1641 struct rtl838x_l2_entry e;
1642 int err = 0, idx;
1643 u64 seed = priv->r->l2_hash_seed(mac, vid);
1644
1645 if (priv->is_lagmember[port]) {
1646 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1647 return 0;
1648 }
1649
1650 mutex_lock(&priv->reg_mutex);
1651
1652 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1653
1654 /* Found an existing or empty entry */
1655 if (idx >= 0) {
1656 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1657 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1658 goto out;
1659 }
1660
1661 /* Hash buckets full, try CAM */
1662 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1663
1664 if (idx >= 0) {
1665 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1666 priv->r->write_cam(idx, &e);
1667 goto out;
1668 }
1669
1670 err = -ENOTSUPP;
1671
1672 out:
1673 mutex_unlock(&priv->reg_mutex);
1674
1675 return err;
1676 }
1677
1678 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1679 const unsigned char *addr, u16 vid)
1680 {
1681 struct rtl838x_switch_priv *priv = ds->priv;
1682 u64 mac = ether_addr_to_u64(addr);
1683 struct rtl838x_l2_entry e;
1684 int err = 0, idx;
1685 u64 seed = priv->r->l2_hash_seed(mac, vid);
1686
1687 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1688 mutex_lock(&priv->reg_mutex);
1689
1690 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1691
1692 if (idx >= 0) {
1693 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1694 e.valid = false;
1695 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1696 goto out;
1697 }
1698
1699 /* Check CAM for spillover from hash buckets */
1700 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1701
1702 if (idx >= 0) {
1703 e.valid = false;
1704 priv->r->write_cam(idx, &e);
1705 goto out;
1706 }
1707 err = -ENOENT;
1708
1709 out:
1710 mutex_unlock(&priv->reg_mutex);
1711
1712 return err;
1713 }
1714
1715 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1716 dsa_fdb_dump_cb_t *cb, void *data)
1717 {
1718 struct rtl838x_l2_entry e;
1719 struct rtl838x_switch_priv *priv = ds->priv;
1720
1721 mutex_lock(&priv->reg_mutex);
1722
1723 for (int i = 0; i < priv->fib_entries; i++) {
1724 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1725
1726 if (!e.valid)
1727 continue;
1728
1729 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1730 cb(e.mac, e.vid, e.is_static, data);
1731
1732 if (!((i + 1) % 64))
1733 cond_resched();
1734 }
1735
1736 for (int i = 0; i < 64; i++) {
1737 priv->r->read_cam(i, &e);
1738
1739 if (!e.valid)
1740 continue;
1741
1742 if (e.port == port)
1743 cb(e.mac, e.vid, e.is_static, data);
1744 }
1745
1746 mutex_unlock(&priv->reg_mutex);
1747
1748 return 0;
1749 }
1750
1751 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1752 const struct switchdev_obj_port_mdb *mdb)
1753 {
1754 struct rtl838x_switch_priv *priv = ds->priv;
1755 u64 mac = ether_addr_to_u64(mdb->addr);
1756 struct rtl838x_l2_entry e;
1757 int err = 0, idx;
1758 int vid = mdb->vid;
1759 u64 seed = priv->r->l2_hash_seed(mac, vid);
1760 int mc_group;
1761
1762 if (priv->id >= 0x9300)
1763 return -EOPNOTSUPP;
1764
1765 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1766
1767 if (priv->is_lagmember[port]) {
1768 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1769 return -EINVAL;
1770 }
1771
1772 mutex_lock(&priv->reg_mutex);
1773
1774 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1775
1776 /* Found an existing or empty entry */
1777 if (idx >= 0) {
1778 if (e.valid) {
1779 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1780 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1781 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1782 } else {
1783 pr_debug("New entry for seed %016llx\n", seed);
1784 mc_group = rtl83xx_mc_group_alloc(priv, port);
1785 if (mc_group < 0) {
1786 err = -ENOTSUPP;
1787 goto out;
1788 }
1789 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1790 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1791 }
1792 goto out;
1793 }
1794
1795 /* Hash buckets full, try CAM */
1796 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1797
1798 if (idx >= 0) {
1799 if (e.valid) {
1800 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1801 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1802 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1803 } else {
1804 pr_debug("New entry\n");
1805 mc_group = rtl83xx_mc_group_alloc(priv, port);
1806 if (mc_group < 0) {
1807 err = -ENOTSUPP;
1808 goto out;
1809 }
1810 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1811 priv->r->write_cam(idx, &e);
1812 }
1813 goto out;
1814 }
1815
1816 err = -ENOTSUPP;
1817
1818 out:
1819 mutex_unlock(&priv->reg_mutex);
1820 if (err)
1821 dev_err(ds->dev, "failed to add MDB entry\n");
1822
1823 return err;
1824 }
1825
1826 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1827 const struct switchdev_obj_port_mdb *mdb)
1828 {
1829 struct rtl838x_switch_priv *priv = ds->priv;
1830 u64 mac = ether_addr_to_u64(mdb->addr);
1831 struct rtl838x_l2_entry e;
1832 int err = 0, idx;
1833 int vid = mdb->vid;
1834 u64 seed = priv->r->l2_hash_seed(mac, vid);
1835 u64 portmask;
1836
1837 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1838
1839 if (priv->is_lagmember[port]) {
1840 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1841 return 0;
1842 }
1843
1844 mutex_lock(&priv->reg_mutex);
1845
1846 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1847
1848 if (idx >= 0) {
1849 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1850 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1851 if (!portmask) {
1852 e.valid = false;
1853 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1854 }
1855 goto out;
1856 }
1857
1858 /* Check CAM for spillover from hash buckets */
1859 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1860
1861 if (idx >= 0) {
1862 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1863 if (!portmask) {
1864 e.valid = false;
1865 priv->r->write_cam(idx, &e);
1866 }
1867 goto out;
1868 }
1869 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1870
1871 out:
1872 mutex_unlock(&priv->reg_mutex);
1873
1874 return err;
1875 }
1876
1877 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1878 struct dsa_mall_mirror_tc_entry *mirror,
1879 bool ingress)
1880 {
1881 /* We support 4 mirror groups, one destination port per group */
1882 int group;
1883 struct rtl838x_switch_priv *priv = ds->priv;
1884 int ctrl_reg, dpm_reg, spm_reg;
1885
1886 pr_debug("In %s\n", __func__);
1887
1888 for (group = 0; group < 4; group++) {
1889 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1890 break;
1891 }
1892 if (group >= 4) {
1893 for (group = 0; group < 4; group++) {
1894 if (priv->mirror_group_ports[group] < 0)
1895 break;
1896 }
1897 }
1898
1899 if (group >= 4)
1900 return -ENOSPC;
1901
1902 ctrl_reg = priv->r->mir_ctrl + group * 4;
1903 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1904 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1905
1906 pr_debug("Using group %d\n", group);
1907 mutex_lock(&priv->reg_mutex);
1908
1909 if (priv->family_id == RTL8380_FAMILY_ID) {
1910 /* Enable mirroring to port across VLANs (bit 11) */
1911 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1912 } else {
1913 /* Enable mirroring to destination port */
1914 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1915 }
1916
1917 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1918 mutex_unlock(&priv->reg_mutex);
1919 return -EEXIST;
1920 }
1921 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1922 mutex_unlock(&priv->reg_mutex);
1923 return -EEXIST;
1924 }
1925
1926 if (ingress)
1927 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1928 else
1929 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1930
1931 priv->mirror_group_ports[group] = mirror->to_local_port;
1932 mutex_unlock(&priv->reg_mutex);
1933
1934 return 0;
1935 }
1936
1937 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1938 struct dsa_mall_mirror_tc_entry *mirror)
1939 {
1940 int group = 0;
1941 struct rtl838x_switch_priv *priv = ds->priv;
1942 int ctrl_reg, dpm_reg, spm_reg;
1943
1944 pr_debug("In %s\n", __func__);
1945 for (group = 0; group < 4; group++) {
1946 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1947 break;
1948 }
1949 if (group >= 4)
1950 return;
1951
1952 ctrl_reg = priv->r->mir_ctrl + group * 4;
1953 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1954 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1955
1956 mutex_lock(&priv->reg_mutex);
1957 if (mirror->ingress) {
1958 /* Ingress, clear source port matrix */
1959 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1960 } else {
1961 /* Egress, clear destination port matrix */
1962 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1963 }
1964
1965 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1966 priv->mirror_group_ports[group] = -1;
1967 sw_w32(0, ctrl_reg);
1968 }
1969
1970 mutex_unlock(&priv->reg_mutex);
1971 }
1972
1973 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1974 {
1975 struct rtl838x_switch_priv *priv = ds->priv;
1976 unsigned long features = 0;
1977 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1978 if (priv->r->enable_learning)
1979 features |= BR_LEARNING;
1980 if (priv->r->enable_flood)
1981 features |= BR_FLOOD;
1982 if (priv->r->enable_mcast_flood)
1983 features |= BR_MCAST_FLOOD;
1984 if (priv->r->enable_bcast_flood)
1985 features |= BR_BCAST_FLOOD;
1986 if (flags.mask & ~(features))
1987 return -EINVAL;
1988
1989 return 0;
1990 }
1991
1992 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1993 {
1994 struct rtl838x_switch_priv *priv = ds->priv;
1995
1996 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1997 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1998 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1999
2000 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
2001 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
2002
2003 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
2004 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
2005
2006 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
2007 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
2008
2009 return 0;
2010 }
2011
2012 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2013 struct net_device *lag,
2014 struct netdev_lag_upper_info *info)
2015 {
2016 int id;
2017
2018 id = dsa_lag_id(ds->dst, lag);
2019 if (id < 0 || id >= ds->num_lag_ids)
2020 return false;
2021
2022 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2023 return false;
2024 }
2025 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2026 return false;
2027
2028 return true;
2029 }
2030
2031 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2032 {
2033 struct rtl838x_switch_priv *priv = ds->priv;
2034
2035 pr_debug("%s: %d\n", __func__, port);
2036 /* Nothing to be done... */
2037
2038 return 0;
2039 }
2040
2041 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2042 struct net_device *lag,
2043 struct netdev_lag_upper_info *info)
2044 {
2045 struct rtl838x_switch_priv *priv = ds->priv;
2046 int i, err = 0;
2047
2048 if (!rtl83xx_lag_can_offload(ds, lag, info))
2049 return -EOPNOTSUPP;
2050
2051 mutex_lock(&priv->reg_mutex);
2052
2053 for (i = 0; i < priv->n_lags; i++) {
2054 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2055 break;
2056 }
2057 if (port >= priv->cpu_port) {
2058 err = -EINVAL;
2059 goto out;
2060 }
2061 pr_info("port_lag_join: group %d, port %d\n",i, port);
2062 if (!priv->lag_devs[i])
2063 priv->lag_devs[i] = lag;
2064
2065 if (priv->lag_primary[i] == -1) {
2066 priv->lag_primary[i] = port;
2067 } else
2068 priv->is_lagmember[port] = 1;
2069
2070 priv->lagmembers |= (1ULL << port);
2071
2072 pr_debug("lag_members = %llX\n", priv->lagmembers);
2073 err = rtl83xx_lag_add(priv->ds, i, port, info);
2074 if (err) {
2075 err = -EINVAL;
2076 goto out;
2077 }
2078
2079 out:
2080 mutex_unlock(&priv->reg_mutex);
2081
2082 return err;
2083 }
2084
2085 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2086 struct net_device *lag)
2087 {
2088 int i, group = -1, err;
2089 struct rtl838x_switch_priv *priv = ds->priv;
2090
2091 mutex_lock(&priv->reg_mutex);
2092 for (i = 0; i < priv->n_lags; i++) {
2093 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2094 group = i;
2095 break;
2096 }
2097 }
2098
2099 if (group == -1) {
2100 pr_info("port_lag_leave: port %d is not a member\n", port);
2101 err = -EINVAL;
2102 goto out;
2103 }
2104
2105 if (port >= priv->cpu_port) {
2106 err = -EINVAL;
2107 goto out;
2108 }
2109 pr_info("port_lag_del: group %d, port %d\n",group, port);
2110 priv->lagmembers &=~ (1ULL << port);
2111 priv->lag_primary[i] = -1;
2112 priv->is_lagmember[port] = 0;
2113 pr_debug("lag_members = %llX\n", priv->lagmembers);
2114 err = rtl83xx_lag_del(priv->ds, group, port);
2115 if (err) {
2116 err = -EINVAL;
2117 goto out;
2118 }
2119 if (!priv->lags_port_members[i])
2120 priv->lag_devs[i] = NULL;
2121
2122 out:
2123 mutex_unlock(&priv->reg_mutex);
2124 return 0;
2125 }
2126
2127 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2128 {
2129 u32 val;
2130 u32 offset = 0;
2131 struct rtl838x_switch_priv *priv = ds->priv;
2132
2133 if ((phy_addr >= 24) &&
2134 (phy_addr <= 27) &&
2135 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2136 if (phy_addr == 26)
2137 offset = 0x100;
2138 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2139 return val;
2140 }
2141
2142 read_phy(phy_addr, 0, phy_reg, &val);
2143 return val;
2144 }
2145
2146 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2147 {
2148 u32 offset = 0;
2149 struct rtl838x_switch_priv *priv = ds->priv;
2150
2151 if ((phy_addr >= 24) &&
2152 (phy_addr <= 27) &&
2153 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2154 if (phy_addr == 26)
2155 offset = 0x100;
2156 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2157 return 0;
2158 }
2159 return write_phy(phy_addr, 0, phy_reg, val);
2160 }
2161
2162 const struct dsa_switch_ops rtl83xx_switch_ops = {
2163 .get_tag_protocol = rtl83xx_get_tag_protocol,
2164 .setup = rtl83xx_setup,
2165
2166 .phy_read = dsa_phy_read,
2167 .phy_write = dsa_phy_write,
2168
2169 .phylink_validate = rtl83xx_phylink_validate,
2170 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2171 .phylink_mac_config = rtl83xx_phylink_mac_config,
2172 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2173 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2174
2175 .get_strings = rtl83xx_get_strings,
2176 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2177 .get_sset_count = rtl83xx_get_sset_count,
2178
2179 .port_enable = rtl83xx_port_enable,
2180 .port_disable = rtl83xx_port_disable,
2181
2182 .get_mac_eee = rtl83xx_get_mac_eee,
2183 .set_mac_eee = rtl83xx_set_mac_eee,
2184
2185 .set_ageing_time = rtl83xx_set_ageing_time,
2186 .port_bridge_join = rtl83xx_port_bridge_join,
2187 .port_bridge_leave = rtl83xx_port_bridge_leave,
2188 .port_stp_state_set = rtl83xx_port_stp_state_set,
2189 .port_fast_age = rtl83xx_fast_age,
2190
2191 .port_vlan_filtering = rtl83xx_vlan_filtering,
2192 .port_vlan_add = rtl83xx_vlan_add,
2193 .port_vlan_del = rtl83xx_vlan_del,
2194
2195 .port_fdb_add = rtl83xx_port_fdb_add,
2196 .port_fdb_del = rtl83xx_port_fdb_del,
2197 .port_fdb_dump = rtl83xx_port_fdb_dump,
2198
2199 .port_mdb_add = rtl83xx_port_mdb_add,
2200 .port_mdb_del = rtl83xx_port_mdb_del,
2201
2202 .port_mirror_add = rtl83xx_port_mirror_add,
2203 .port_mirror_del = rtl83xx_port_mirror_del,
2204
2205 .port_lag_change = rtl83xx_port_lag_change,
2206 .port_lag_join = rtl83xx_port_lag_join,
2207 .port_lag_leave = rtl83xx_port_lag_leave,
2208
2209 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2210 .port_bridge_flags = rtl83xx_port_bridge_flags,
2211 };
2212
2213 const struct dsa_switch_ops rtl930x_switch_ops = {
2214 .get_tag_protocol = rtl83xx_get_tag_protocol,
2215 .setup = rtl93xx_setup,
2216
2217 .phy_read = dsa_phy_read,
2218 .phy_write = dsa_phy_write,
2219
2220 .phylink_validate = rtl93xx_phylink_validate,
2221 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2222 .phylink_mac_config = rtl93xx_phylink_mac_config,
2223 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2224 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2225
2226 .get_strings = rtl83xx_get_strings,
2227 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2228 .get_sset_count = rtl83xx_get_sset_count,
2229
2230 .port_enable = rtl83xx_port_enable,
2231 .port_disable = rtl83xx_port_disable,
2232
2233 .get_mac_eee = rtl93xx_get_mac_eee,
2234 .set_mac_eee = rtl83xx_set_mac_eee,
2235
2236 .set_ageing_time = rtl83xx_set_ageing_time,
2237 .port_bridge_join = rtl83xx_port_bridge_join,
2238 .port_bridge_leave = rtl83xx_port_bridge_leave,
2239 .port_stp_state_set = rtl83xx_port_stp_state_set,
2240 .port_fast_age = rtl930x_fast_age,
2241
2242 .port_vlan_filtering = rtl83xx_vlan_filtering,
2243 .port_vlan_add = rtl83xx_vlan_add,
2244 .port_vlan_del = rtl83xx_vlan_del,
2245
2246 .port_fdb_add = rtl83xx_port_fdb_add,
2247 .port_fdb_del = rtl83xx_port_fdb_del,
2248 .port_fdb_dump = rtl83xx_port_fdb_dump,
2249
2250 .port_mdb_add = rtl83xx_port_mdb_add,
2251 .port_mdb_del = rtl83xx_port_mdb_del,
2252
2253 .port_lag_change = rtl83xx_port_lag_change,
2254 .port_lag_join = rtl83xx_port_lag_join,
2255 .port_lag_leave = rtl83xx_port_lag_leave,
2256
2257 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2258 .port_bridge_flags = rtl83xx_port_bridge_flags,
2259 };
Staging tree of Jo-Philipp Wich