1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
10 extern struct rtl83xx_soc_info soc_info
;
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv
*priv
)
14 mutex_lock(&priv
->reg_mutex
);
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
19 if (priv
->family_id
== RTL8380_FAMILY_ID
)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
25 mutex_unlock(&priv
->reg_mutex
);
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
35 if (priv
->ports
[i
].phy
)
39 pr_info("%s: %16llx\n", __func__
, v
);
40 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv
->family_id
== RTL8390_FAMILY_ID
)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL
);
45 else if(priv
->family_id
== RTL9300_FAMILY_ID
)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
49 const struct rtl83xx_mib_desc rtl83xx_mib
[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
102 static enum dsa_tag_protocol
rtl83xx_get_tag_protocol(struct dsa_switch
*ds
,
104 enum dsa_tag_protocol mprot
)
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
109 return DSA_TAG_PROTO_TRAILER
;
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv
*priv
)
115 struct rtl838x_vlan_info info
;
117 pr_info("In %s\n", __func__
);
119 priv
->r
->vlan_profile_setup(0);
120 priv
->r
->vlan_profile_setup(1);
121 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv
->r
->read_mcast_pmask(UNKNOWN_MC_PMASK
));
122 priv
->r
->vlan_profile_dump(0);
124 info
.fid
= 0; /* Default Forwarding ID / MSTI */
125 info
.hash_uc_fid
= false; /* Do not build the L2 lookup hash with FID, but VID */
126 info
.hash_mc_fid
= false; /* Do the same for Multicast packets */
127 info
.profile_id
= 0; /* Use default Vlan Profile 0 */
128 info
.tagged_ports
= 0; /* Initially no port members */
129 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
131 info
.multicast_grp_mask
= 0;
132 info
.l2_tunnel_list_id
= -1;
135 /* Initialize all vlans 0-4095 */
136 for (int i
= 0; i
< MAX_VLANS
; i
++)
137 priv
->r
->vlan_set_tagged(i
, &info
);
139 /* reset PVIDs; defaults to 1 on reset */
140 for (int i
= 0; i
<= priv
->ds
->num_ports
; i
++) {
141 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_INNER
, 0);
142 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_OUTER
, 0);
143 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_INNER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
144 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_OUTER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
147 /* Set forwarding action based on inner VLAN tag */
148 for (int i
= 0; i
< priv
->cpu_port
; i
++)
149 priv
->r
->vlan_fwd_on_inner(i
, true);
152 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv
*priv
)
154 for (int i
= 0; i
< priv
->cpu_port
; i
++)
155 priv
->r
->set_receive_management_action(i
, BPDU
, COPY2CPU
);
158 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv
*priv
,
159 int port
, bool enable
)
161 int shift
= SALRN_PORT_SHIFT(port
);
162 int val
= enable
? SALRN_MODE_HARDWARE
: SALRN_MODE_DISABLED
;
164 sw_w32_mask(SALRN_MODE_MASK
<< shift
, val
<< shift
,
165 priv
->r
->l2_port_new_salrn(port
));
168 static int rtl83xx_setup(struct dsa_switch
*ds
)
170 struct rtl838x_switch_priv
*priv
= ds
->priv
;
172 pr_debug("%s called\n", __func__
);
174 /* Disable MAC polling the PHY so that we can start configuration */
175 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
177 for (int i
= 0; i
< ds
->num_ports
; i
++)
178 priv
->ports
[i
].enable
= false;
179 priv
->ports
[priv
->cpu_port
].enable
= true;
181 /* Configure ports so they are disabled by default, but once enabled
182 * they will work in isolated mode (only traffic between port and CPU).
184 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
185 if (priv
->ports
[i
].phy
) {
186 priv
->ports
[i
].pm
= BIT_ULL(priv
->cpu_port
);
187 priv
->r
->traffic_set(i
, BIT_ULL(i
));
190 priv
->r
->traffic_set(priv
->cpu_port
, BIT_ULL(priv
->cpu_port
));
192 /* For standalone ports, forward packets even if a static fdb
193 * entry for the source address exists on another port.
195 if (priv
->r
->set_static_move_action
) {
196 for (int i
= 0; i
<= priv
->cpu_port
; i
++)
197 priv
->r
->set_static_move_action(i
, true);
200 if (priv
->family_id
== RTL8380_FAMILY_ID
)
201 rtl838x_print_matrix();
203 rtl839x_print_matrix();
205 rtl83xx_init_stats(priv
);
207 rtl83xx_vlan_setup(priv
);
209 rtl83xx_setup_bpdu_traps(priv
);
211 ds
->configure_vlan_while_not_filtering
= true;
213 priv
->r
->l2_learning_setup();
215 rtl83xx_port_set_salrn(priv
, priv
->cpu_port
, false);
216 ds
->assisted_learning_on_cpu_port
= true;
218 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
219 * 0: FWD, 1: DROP, 2: TRAP2CPU
221 if (priv
->family_id
== RTL8380_FAMILY_ID
)
222 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL
);
224 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL
);
226 /* Enable MAC Polling PHY again */
227 rtl83xx_enable_phy_polling(priv
);
228 pr_debug("Please wait until PHY is settled\n");
230 priv
->r
->pie_init(priv
);
235 static int rtl93xx_setup(struct dsa_switch
*ds
)
237 struct rtl838x_switch_priv
*priv
= ds
->priv
;
239 pr_info("%s called\n", __func__
);
241 /* Disable MAC polling the PHY so that we can start configuration */
242 if (priv
->family_id
== RTL9300_FAMILY_ID
)
243 sw_w32(0, RTL930X_SMI_POLL_CTRL
);
245 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
);
247 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
250 /* Disable all ports except CPU port */
251 for (int i
= 0; i
< ds
->num_ports
; i
++)
252 priv
->ports
[i
].enable
= false;
253 priv
->ports
[priv
->cpu_port
].enable
= true;
255 /* Configure ports so they are disabled by default, but once enabled
256 * they will work in isolated mode (only traffic between port and CPU).
258 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
259 if (priv
->ports
[i
].phy
) {
260 priv
->ports
[i
].pm
= BIT_ULL(priv
->cpu_port
);
261 priv
->r
->traffic_set(i
, BIT_ULL(i
));
264 priv
->r
->traffic_set(priv
->cpu_port
, BIT_ULL(priv
->cpu_port
));
266 rtl930x_print_matrix();
268 /* TODO: Initialize statistics */
270 rtl83xx_vlan_setup(priv
);
272 ds
->configure_vlan_while_not_filtering
= true;
274 priv
->r
->l2_learning_setup();
276 rtl83xx_port_set_salrn(priv
, priv
->cpu_port
, false);
277 ds
->assisted_learning_on_cpu_port
= true;
279 rtl83xx_enable_phy_polling(priv
);
281 priv
->r
->pie_init(priv
);
283 priv
->r
->led_init(priv
);
288 static int rtl93xx_get_sds(struct phy_device
*phydev
)
290 struct device
*dev
= &phydev
->mdio
.dev
;
291 struct device_node
*dn
;
298 if (of_property_read_u32(dn
, "sds", &sds_num
))
301 dev_err(dev
, "No DT node.\n");
308 static void rtl83xx_phylink_validate(struct dsa_switch
*ds
, int port
,
309 unsigned long *supported
,
310 struct phylink_link_state
*state
)
312 struct rtl838x_switch_priv
*priv
= ds
->priv
;
313 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
315 pr_debug("In %s port %d, state is %d", __func__
, port
, state
->interface
);
317 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
318 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
319 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
320 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
321 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
322 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
323 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
324 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
325 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
326 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
328 "Unsupported interface: %d for port %d\n",
329 state
->interface
, port
);
333 /* Allow all the expected bits */
334 phylink_set(mask
, Autoneg
);
335 phylink_set_port_modes(mask
);
336 phylink_set(mask
, Pause
);
337 phylink_set(mask
, Asym_Pause
);
339 /* With the exclusion of MII and Reverse MII, we support Gigabit,
340 * including Half duplex
342 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
343 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
344 phylink_set(mask
, 1000baseT_Full
);
345 phylink_set(mask
, 1000baseT_Half
);
348 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
349 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
350 phylink_set(mask
, 1000baseX_Full
);
352 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
353 if (port
>= 48 && port
<= 51 && priv
->family_id
== RTL8390_FAMILY_ID
)
354 phylink_set(mask
, 1000baseX_Full
);
356 phylink_set(mask
, 10baseT_Half
);
357 phylink_set(mask
, 10baseT_Full
);
358 phylink_set(mask
, 100baseT_Half
);
359 phylink_set(mask
, 100baseT_Full
);
361 bitmap_and(supported
, supported
, mask
,
362 __ETHTOOL_LINK_MODE_MASK_NBITS
);
363 bitmap_and(state
->advertising
, state
->advertising
, mask
,
364 __ETHTOOL_LINK_MODE_MASK_NBITS
);
367 static void rtl93xx_phylink_validate(struct dsa_switch
*ds
, int port
,
368 unsigned long *supported
,
369 struct phylink_link_state
*state
)
371 struct rtl838x_switch_priv
*priv
= ds
->priv
;
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
374 pr_debug("In %s port %d, state is %d (%s)", __func__
, port
, state
->interface
,
375 phy_modes(state
->interface
));
377 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
378 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
379 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
380 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
381 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
382 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
383 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
384 state
->interface
!= PHY_INTERFACE_MODE_XGMII
&&
385 state
->interface
!= PHY_INTERFACE_MODE_HSGMII
&&
386 state
->interface
!= PHY_INTERFACE_MODE_10GBASER
&&
387 state
->interface
!= PHY_INTERFACE_MODE_10GKR
&&
388 state
->interface
!= PHY_INTERFACE_MODE_USXGMII
&&
389 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
390 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
391 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
393 "Unsupported interface: %d for port %d\n",
394 state
->interface
, port
);
398 /* Allow all the expected bits */
399 phylink_set(mask
, Autoneg
);
400 phylink_set_port_modes(mask
);
401 phylink_set(mask
, Pause
);
402 phylink_set(mask
, Asym_Pause
);
404 /* With the exclusion of MII and Reverse MII, we support Gigabit,
405 * including Half duplex
407 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
408 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
409 phylink_set(mask
, 1000baseT_Full
);
410 phylink_set(mask
, 1000baseT_Half
);
413 /* Internal phys of the RTL93xx family provide 10G */
414 if (priv
->ports
[port
].phy_is_integrated
&&
415 state
->interface
== PHY_INTERFACE_MODE_1000BASEX
) {
416 phylink_set(mask
, 1000baseX_Full
);
417 } else if (priv
->ports
[port
].phy_is_integrated
) {
418 phylink_set(mask
, 1000baseX_Full
);
419 phylink_set(mask
, 10000baseKR_Full
);
420 phylink_set(mask
, 10000baseSR_Full
);
421 phylink_set(mask
, 10000baseCR_Full
);
423 if (state
->interface
== PHY_INTERFACE_MODE_INTERNAL
) {
424 phylink_set(mask
, 1000baseX_Full
);
425 phylink_set(mask
, 1000baseT_Full
);
426 phylink_set(mask
, 10000baseKR_Full
);
427 phylink_set(mask
, 10000baseT_Full
);
428 phylink_set(mask
, 10000baseSR_Full
);
429 phylink_set(mask
, 10000baseCR_Full
);
432 if (state
->interface
== PHY_INTERFACE_MODE_USXGMII
)
433 phylink_set(mask
, 10000baseT_Full
);
435 phylink_set(mask
, 10baseT_Half
);
436 phylink_set(mask
, 10baseT_Full
);
437 phylink_set(mask
, 100baseT_Half
);
438 phylink_set(mask
, 100baseT_Full
);
440 bitmap_and(supported
, supported
, mask
,
441 __ETHTOOL_LINK_MODE_MASK_NBITS
);
442 bitmap_and(state
->advertising
, state
->advertising
, mask
,
443 __ETHTOOL_LINK_MODE_MASK_NBITS
);
444 pr_debug("%s leaving supported: %*pb", __func__
, __ETHTOOL_LINK_MODE_MASK_NBITS
, supported
);
447 static int rtl83xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
448 struct phylink_link_state
*state
)
450 struct rtl838x_switch_priv
*priv
= ds
->priv
;
454 if (port
< 0 || port
> priv
->cpu_port
)
458 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
459 if (link
& BIT_ULL(port
))
461 pr_debug("%s: link state port %d: %llx\n", __func__
, port
, link
& BIT_ULL(port
));
464 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
467 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
468 speed
>>= (port
% 16) << 1;
469 switch (speed
& 0x3) {
471 state
->speed
= SPEED_10
;
474 state
->speed
= SPEED_100
;
477 state
->speed
= SPEED_1000
;
480 if (priv
->family_id
== RTL9300_FAMILY_ID
481 && (port
== 24 || port
== 26)) /* Internal serdes */
482 state
->speed
= SPEED_2500
;
484 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
487 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
488 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
489 state
->pause
|= MLO_PAUSE_RX
;
490 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
491 state
->pause
|= MLO_PAUSE_TX
;
496 static int rtl93xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
497 struct phylink_link_state
*state
)
499 struct rtl838x_switch_priv
*priv
= ds
->priv
;
504 if (port
< 0 || port
> priv
->cpu_port
)
507 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
508 * state needs to be read twice in order to read a correct result.
509 * This would not be necessary for ports connected e.g. to RTL8218D
513 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
514 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
515 if (link
& BIT_ULL(port
))
518 if (priv
->family_id
== RTL9310_FAMILY_ID
)
519 media
= priv
->r
->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS
);
521 if (priv
->family_id
== RTL9300_FAMILY_ID
)
522 media
= sw_r32(RTL930X_MAC_LINK_MEDIA_STS
);
524 if (media
& BIT_ULL(port
))
527 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__
, port
,
528 link
& BIT_ULL(port
), media
);
531 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
534 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
535 speed
>>= (port
% 8) << 2;
536 switch (speed
& 0xf) {
538 state
->speed
= SPEED_10
;
541 state
->speed
= SPEED_100
;
545 state
->speed
= SPEED_1000
;
548 state
->speed
= SPEED_10000
;
552 state
->speed
= SPEED_2500
;
555 state
->speed
= SPEED_5000
;
558 pr_err("%s: unknown speed: %d\n", __func__
, (u32
)speed
& 0xf);
561 if (priv
->family_id
== RTL9310_FAMILY_ID
562 && (port
>= 52 || port
<= 55)) { /* Internal serdes */
563 state
->speed
= SPEED_10000
;
568 pr_debug("%s: speed is: %d %d\n", __func__
, (u32
)speed
& 0xf, state
->speed
);
569 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
570 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
571 state
->pause
|= MLO_PAUSE_RX
;
572 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
573 state
->pause
|= MLO_PAUSE_TX
;
578 static void rtl83xx_config_interface(int port
, phy_interface_t interface
)
580 u32 old
, int_shift
, sds_shift
;
595 old
= sw_r32(RTL838X_SDS_MODE_SEL
);
597 case PHY_INTERFACE_MODE_1000BASEX
:
598 if ((old
>> sds_shift
& 0x1f) == 4)
600 sw_w32_mask(0x7 << int_shift
, 1 << int_shift
, RTL838X_INT_MODE_CTRL
);
601 sw_w32_mask(0x1f << sds_shift
, 4 << sds_shift
, RTL838X_SDS_MODE_SEL
);
603 case PHY_INTERFACE_MODE_SGMII
:
604 if ((old
>> sds_shift
& 0x1f) == 2)
606 sw_w32_mask(0x7 << int_shift
, 2 << int_shift
, RTL838X_INT_MODE_CTRL
);
607 sw_w32_mask(0x1f << sds_shift
, 2 << sds_shift
, RTL838X_SDS_MODE_SEL
);
612 pr_debug("configured port %d for interface %s\n", port
, phy_modes(interface
));
615 static void rtl83xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
617 const struct phylink_link_state
*state
)
619 struct rtl838x_switch_priv
*priv
= ds
->priv
;
621 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
623 pr_debug("%s port %d, mode %x\n", __func__
, port
, mode
);
625 if (port
== priv
->cpu_port
) {
626 /* Set Speed, duplex, flow control
627 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
628 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
631 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
632 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
633 /* allow CRC errors on CPU-port */
634 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
636 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
641 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
642 /* Auto-Negotiation does not work for MAC in RTL8390 */
643 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
644 if (mode
== MLO_AN_PHY
|| phylink_autoneg_inband(mode
)) {
645 pr_debug("PHY autonegotiates\n");
646 reg
|= RTL838X_NWAY_EN
;
647 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
648 rtl83xx_config_interface(port
, state
->interface
);
653 if (mode
!= MLO_AN_FIXED
)
654 pr_debug("Fixed state.\n");
656 /* Clear id_mode_dis bit, and the existing port mode, let
657 * RGMII_MODE_EN bet set by mac_link_{up,down} */
658 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
659 reg
&= ~(RTL838X_RX_PAUSE_EN
| RTL838X_TX_PAUSE_EN
);
660 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
661 if (state
->pause
& MLO_PAUSE_TX
)
662 reg
|= RTL838X_TX_PAUSE_EN
;
663 reg
|= RTL838X_RX_PAUSE_EN
;
665 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
666 reg
&= ~(RTL839X_RX_PAUSE_EN
| RTL839X_TX_PAUSE_EN
);
667 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
668 if (state
->pause
& MLO_PAUSE_TX
)
669 reg
|= RTL839X_TX_PAUSE_EN
;
670 reg
|= RTL839X_RX_PAUSE_EN
;
675 reg
&= ~(3 << speed_bit
);
676 switch (state
->speed
) {
678 reg
|= 2 << speed_bit
;
681 reg
|= 1 << speed_bit
;
684 break; /* Ignore, including 10MBit which has a speed value of 0 */
687 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
688 reg
&= ~(RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
690 reg
|= RTL838X_FORCE_LINK_EN
;
691 if (state
->duplex
== RTL838X_DUPLEX_MODE
)
692 reg
|= RTL838X_DUPLEX_MODE
;
693 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
694 reg
&= ~(RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
696 reg
|= RTL839X_FORCE_LINK_EN
;
697 if (state
->duplex
== RTL839X_DUPLEX_MODE
)
698 reg
|= RTL839X_DUPLEX_MODE
;
701 /* LAG members must use DUPLEX and we need to enable the link */
702 if (priv
->lagmembers
& BIT_ULL(port
)) {
703 switch(priv
->family_id
) {
704 case RTL8380_FAMILY_ID
:
705 reg
|= (RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
707 case RTL8390_FAMILY_ID
:
708 reg
|= (RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
714 if (priv
->family_id
== RTL8380_FAMILY_ID
)
715 reg
&= ~RTL838X_NWAY_EN
;
716 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
719 static void rtl931x_phylink_mac_config(struct dsa_switch
*ds
, int port
,
721 const struct phylink_link_state
*state
)
723 struct rtl838x_switch_priv
*priv
= ds
->priv
;
727 sds_num
= priv
->ports
[port
].sds_num
;
728 pr_info("%s: speed %d sds_num %d\n", __func__
, state
->speed
, sds_num
);
730 switch (state
->interface
) {
731 case PHY_INTERFACE_MODE_HSGMII
:
732 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__
);
733 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
734 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
735 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_HSGMII
);
737 case PHY_INTERFACE_MODE_1000BASEX
:
738 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
739 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
741 case PHY_INTERFACE_MODE_XGMII
:
742 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_XGMII
);
743 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_XGMII
);
745 case PHY_INTERFACE_MODE_10GBASER
:
746 case PHY_INTERFACE_MODE_10GKR
:
747 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
748 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
750 case PHY_INTERFACE_MODE_USXGMII
:
751 /* Translates to MII_USXGMII_10GSXGMII */
752 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
753 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
755 case PHY_INTERFACE_MODE_SGMII
:
756 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__
);
757 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_SGMII
);
758 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_SGMII
);
759 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_SGMII
);
761 case PHY_INTERFACE_MODE_QSGMII
:
762 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
763 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
766 pr_err("%s: unknown serdes mode: %s\n",
767 __func__
, phy_modes(state
->interface
));
771 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
772 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__
, reg
);
774 reg
&= ~(RTL931X_DUPLEX_MODE
| RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
);
777 reg
|= 0x2 << 12; /* Set SMI speed to 0x2 */
779 reg
|= RTL931X_TX_PAUSE_EN
| RTL931X_RX_PAUSE_EN
;
781 if (priv
->lagmembers
& BIT_ULL(port
))
782 reg
|= RTL931X_DUPLEX_MODE
;
784 if (state
->duplex
== DUPLEX_FULL
)
785 reg
|= RTL931X_DUPLEX_MODE
;
787 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
791 static void rtl93xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
793 const struct phylink_link_state
*state
)
795 struct rtl838x_switch_priv
*priv
= ds
->priv
;
796 int sds_num
, sds_mode
;
799 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__
,
800 port
, mode
, phy_modes(state
->interface
), state
->speed
, state
->link
);
802 /* Nothing to be done for the CPU-port */
803 if (port
== priv
->cpu_port
)
806 if (priv
->family_id
== RTL9310_FAMILY_ID
)
807 return rtl931x_phylink_mac_config(ds
, port
, mode
, state
);
809 sds_num
= priv
->ports
[port
].sds_num
;
810 pr_info("%s SDS is %d\n", __func__
, sds_num
);
812 switch (state
->interface
) {
813 case PHY_INTERFACE_MODE_HSGMII
:
816 case PHY_INTERFACE_MODE_1000BASEX
:
819 case PHY_INTERFACE_MODE_XGMII
:
822 case PHY_INTERFACE_MODE_10GBASER
:
823 case PHY_INTERFACE_MODE_10GKR
:
824 sds_mode
= 0x1b; /* 10G 1000X Auto */
826 case PHY_INTERFACE_MODE_USXGMII
:
830 pr_err("%s: unknown serdes mode: %s\n",
831 __func__
, phy_modes(state
->interface
));
834 if (state
->interface
== PHY_INTERFACE_MODE_10GBASER
)
835 rtl9300_serdes_setup(sds_num
, state
->interface
);
838 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
841 switch (state
->speed
) {
860 reg
|= RTL930X_FORCE_LINK_EN
;
862 if (priv
->lagmembers
& BIT_ULL(port
))
863 reg
|= RTL930X_DUPLEX_MODE
| RTL930X_FORCE_LINK_EN
;
865 if (state
->duplex
== DUPLEX_FULL
)
866 reg
|= RTL930X_DUPLEX_MODE
;
868 if (priv
->ports
[port
].phy_is_integrated
)
869 reg
&= ~RTL930X_FORCE_EN
; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
871 reg
|= RTL930X_FORCE_EN
;
873 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
876 static void rtl83xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
878 phy_interface_t interface
)
880 struct rtl838x_switch_priv
*priv
= ds
->priv
;
882 /* Stop TX/RX to port */
883 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
885 /* No longer force link */
886 sw_w32_mask(0x3, 0, priv
->r
->mac_force_mode_ctrl(port
));
889 static void rtl93xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
891 phy_interface_t interface
)
893 struct rtl838x_switch_priv
*priv
= ds
->priv
;
896 /* Stop TX/RX to port */
897 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
899 /* No longer force link */
900 if (priv
->family_id
== RTL9300_FAMILY_ID
)
901 v
= RTL930X_FORCE_EN
| RTL930X_FORCE_LINK_EN
;
902 else if (priv
->family_id
== RTL9310_FAMILY_ID
)
903 v
= RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
;
904 sw_w32_mask(v
, 0, priv
->r
->mac_force_mode_ctrl(port
));
907 static void rtl83xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
909 phy_interface_t interface
,
910 struct phy_device
*phydev
,
911 int speed
, int duplex
,
912 bool tx_pause
, bool rx_pause
)
914 struct rtl838x_switch_priv
*priv
= ds
->priv
;
915 /* Restart TX/RX to port */
916 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
917 /* TODO: Set speed/duplex/pauses */
920 static void rtl93xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
922 phy_interface_t interface
,
923 struct phy_device
*phydev
,
924 int speed
, int duplex
,
925 bool tx_pause
, bool rx_pause
)
927 struct rtl838x_switch_priv
*priv
= ds
->priv
;
929 /* Restart TX/RX to port */
930 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
931 /* TODO: Set speed/duplex/pauses */
934 static void rtl83xx_get_strings(struct dsa_switch
*ds
,
935 int port
, u32 stringset
, u8
*data
)
937 if (stringset
!= ETH_SS_STATS
)
940 for (int i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++)
941 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl83xx_mib
[i
].name
,
945 static void rtl83xx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
948 struct rtl838x_switch_priv
*priv
= ds
->priv
;
949 const struct rtl83xx_mib_desc
*mib
;
952 for (int i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++) {
953 mib
= &rtl83xx_mib
[i
];
955 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 252 - mib
->offset
);
956 if (mib
->size
== 2) {
957 h
= sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 248 - mib
->offset
);
963 static int rtl83xx_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
965 if (sset
!= ETH_SS_STATS
)
968 return ARRAY_SIZE(rtl83xx_mib
);
971 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv
*priv
, int port
)
973 int mc_group
= find_first_zero_bit(priv
->mc_group_bm
, MAX_MC_GROUPS
- 1);
976 if (mc_group
>= MAX_MC_GROUPS
- 1)
979 set_bit(mc_group
, priv
->mc_group_bm
);
980 portmask
= BIT_ULL(port
);
981 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
986 static u64
rtl83xx_mc_group_add_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
988 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
990 pr_debug("%s: %d\n", __func__
, port
);
992 portmask
|= BIT_ULL(port
);
993 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
998 static u64
rtl83xx_mc_group_del_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
1000 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
1002 pr_debug("%s: %d\n", __func__
, port
);
1004 portmask
&= ~BIT_ULL(port
);
1005 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1007 clear_bit(mc_group
, priv
->mc_group_bm
);
1012 static int rtl83xx_port_enable(struct dsa_switch
*ds
, int port
,
1013 struct phy_device
*phydev
)
1015 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1018 pr_debug("%s: %x %d", __func__
, (u32
) priv
, port
);
1019 priv
->ports
[port
].enable
= true;
1021 /* enable inner tagging on egress, do not keep any tags */
1022 priv
->r
->vlan_port_keep_tag_set(port
, 0, 1);
1024 if (dsa_is_cpu_port(ds
, port
))
1027 /* add port to switch mask of CPU_PORT */
1028 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1030 if (priv
->is_lagmember
[port
]) {
1031 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1035 /* add all other ports in the same bridge to switch mask of port */
1036 v
= priv
->r
->traffic_get(port
);
1037 v
|= priv
->ports
[port
].pm
;
1038 priv
->r
->traffic_set(port
, v
);
1040 /* TODO: Figure out if this is necessary */
1041 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
1042 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_SABLK_CTRL
);
1043 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_DABLK_CTRL
);
1046 if (priv
->ports
[port
].sds_num
< 0)
1047 priv
->ports
[port
].sds_num
= rtl93xx_get_sds(phydev
);
1052 static void rtl83xx_port_disable(struct dsa_switch
*ds
, int port
)
1054 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1057 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1058 /* you can only disable user ports */
1059 if (!dsa_is_user_port(ds
, port
))
1062 /* BUG: This does not work on RTL931X */
1063 /* remove port from switch mask of CPU_PORT */
1064 priv
->r
->traffic_disable(priv
->cpu_port
, port
);
1066 /* remove all other ports in the same bridge from switch mask of port */
1067 v
= priv
->r
->traffic_get(port
);
1068 v
&= ~priv
->ports
[port
].pm
;
1069 priv
->r
->traffic_set(port
, v
);
1071 priv
->ports
[port
].enable
= false;
1074 static int rtl83xx_set_mac_eee(struct dsa_switch
*ds
, int port
,
1075 struct ethtool_eee
*e
)
1077 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1079 if (e
->eee_enabled
&& !priv
->eee_enabled
) {
1080 pr_info("Globally enabling EEE\n");
1081 priv
->r
->init_eee(priv
, true);
1084 priv
->r
->port_eee_set(priv
, port
, e
->eee_enabled
);
1087 pr_info("Enabled EEE for port %d\n", port
);
1089 pr_info("Disabled EEE for port %d\n", port
);
1094 static int rtl83xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1095 struct ethtool_eee
*e
)
1097 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1099 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
1101 priv
->r
->eee_port_ability(priv
, e
, port
);
1103 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1105 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1110 static int rtl93xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1111 struct ethtool_eee
*e
)
1113 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1115 e
->supported
= SUPPORTED_100baseT_Full
|
1116 SUPPORTED_1000baseT_Full
|
1117 SUPPORTED_2500baseX_Full
;
1119 priv
->r
->eee_port_ability(priv
, e
, port
);
1121 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1123 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1128 static int rtl83xx_set_ageing_time(struct dsa_switch
*ds
, unsigned int msec
)
1130 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1132 priv
->r
->set_ageing_time(msec
);
1137 static int rtl83xx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1138 struct net_device
*bridge
)
1140 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1141 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
), v
;
1143 pr_debug("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
1145 if (priv
->is_lagmember
[port
]) {
1146 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1150 mutex_lock(&priv
->reg_mutex
);
1151 for (int i
= 0; i
< ds
->num_ports
; i
++) {
1152 /* Add this port to the port matrix of the other ports in the
1153 * same bridge. If the port is disabled, port matrix is kept
1154 * and not being setup until the port becomes enabled.
1156 if (dsa_is_user_port(ds
, i
) && !priv
->is_lagmember
[i
] && i
!= port
) {
1157 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1159 if (priv
->ports
[i
].enable
)
1160 priv
->r
->traffic_enable(i
, port
);
1162 priv
->ports
[i
].pm
|= BIT_ULL(port
);
1163 port_bitmap
|= BIT_ULL(i
);
1167 /* Add all other ports to this port matrix. */
1168 if (priv
->ports
[port
].enable
) {
1169 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1170 v
= priv
->r
->traffic_get(port
);
1172 priv
->r
->traffic_set(port
, v
);
1174 priv
->ports
[port
].pm
|= port_bitmap
;
1176 if (priv
->r
->set_static_move_action
)
1177 priv
->r
->set_static_move_action(port
, false);
1179 mutex_unlock(&priv
->reg_mutex
);
1184 static void rtl83xx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1185 struct net_device
*bridge
)
1187 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1188 u64 port_bitmap
= 0, v
;
1190 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1191 mutex_lock(&priv
->reg_mutex
);
1192 for (int i
= 0; i
< ds
->num_ports
; i
++) {
1193 /* Remove this port from the port matrix of the other ports
1194 * in the same bridge. If the port is disabled, port matrix
1195 * is kept and not being setup until the port becomes enabled.
1196 * And the other port's port matrix cannot be broken when the
1197 * other port is still a VLAN-aware port.
1199 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
1200 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1202 if (priv
->ports
[i
].enable
)
1203 priv
->r
->traffic_disable(i
, port
);
1205 priv
->ports
[i
].pm
&= ~BIT_ULL(port
);
1206 port_bitmap
|= BIT_ULL(i
);
1210 /* Remove all other ports from this port matrix. */
1211 if (priv
->ports
[port
].enable
) {
1212 v
= priv
->r
->traffic_get(port
);
1214 priv
->r
->traffic_set(port
, v
);
1216 priv
->ports
[port
].pm
&= ~port_bitmap
;
1218 if (priv
->r
->set_static_move_action
)
1219 priv
->r
->set_static_move_action(port
, true);
1221 mutex_unlock(&priv
->reg_mutex
);
1224 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1230 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1231 int n
= priv
->port_width
<< 1;
1233 /* Ports above or equal CPU port can never be configured */
1234 if (port
>= priv
->cpu_port
)
1237 mutex_lock(&priv
->reg_mutex
);
1239 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1240 * have 64 bit fields, 839x and 931x have 128 bit fields
1242 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1244 if (priv
->family_id
== RTL9300_FAMILY_ID
)
1246 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1249 index
= n
- (pos
>> 4) - 1;
1250 bit
= (pos
<< 1) % 32;
1252 priv
->r
->stp_get(priv
, msti
, port_state
);
1254 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
1255 port_state
[index
] &= ~(3 << bit
);
1258 case BR_STATE_DISABLED
: /* 0 */
1259 port_state
[index
] |= (0 << bit
);
1261 case BR_STATE_BLOCKING
: /* 4 */
1262 case BR_STATE_LISTENING
: /* 1 */
1263 port_state
[index
] |= (1 << bit
);
1265 case BR_STATE_LEARNING
: /* 2 */
1266 port_state
[index
] |= (2 << bit
);
1268 case BR_STATE_FORWARDING
: /* 3 */
1269 port_state
[index
] |= (3 << bit
);
1274 priv
->r
->stp_set(priv
, msti
, port_state
);
1276 mutex_unlock(&priv
->reg_mutex
);
1279 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
)
1281 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1282 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
1284 pr_debug("FAST AGE port %d\n", port
);
1285 mutex_lock(&priv
->reg_mutex
);
1286 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1288 * 0-4: Replacing port
1289 * 5-9: Flushed/replaced port
1291 * 22: Entry types: 1: dynamic, 0: also static
1292 * 23: Match flush port
1294 * 25: Flush (0) or replace (1) L2 entries
1295 * 26: Status of action (1: Start, 0: Done)
1297 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
1299 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(26 + s
));
1301 mutex_unlock(&priv
->reg_mutex
);
1304 void rtl931x_fast_age(struct dsa_switch
*ds
, int port
)
1306 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1308 pr_info("%s port %d\n", __func__
, port
);
1309 mutex_lock(&priv
->reg_mutex
);
1310 sw_w32(port
<< 11, RTL931X_L2_TBL_FLUSH_CTRL
+ 4);
1312 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL
);
1314 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL
) & BIT (28));
1316 mutex_unlock(&priv
->reg_mutex
);
1319 void rtl930x_fast_age(struct dsa_switch
*ds
, int port
)
1321 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1323 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1324 return rtl931x_fast_age(ds
, port
);
1326 pr_debug("FAST AGE port %d\n", port
);
1327 mutex_lock(&priv
->reg_mutex
);
1328 sw_w32(port
<< 11, RTL930X_L2_TBL_FLUSH_CTRL
+ 4);
1330 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL
);
1332 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(30));
1334 mutex_unlock(&priv
->reg_mutex
);
1337 static int rtl83xx_vlan_filtering(struct dsa_switch
*ds
, int port
,
1338 bool vlan_filtering
,
1339 struct netlink_ext_ack
*extack
)
1341 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1343 pr_debug("%s: port %d\n", __func__
, port
);
1344 mutex_lock(&priv
->reg_mutex
);
1346 if (vlan_filtering
) {
1347 /* Enable ingress and egress filtering
1348 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1349 * the filter action:
1352 * 2: Trap packet to CPU port
1353 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1355 if (port
!= priv
->cpu_port
)
1356 priv
->r
->set_vlan_igr_filter(port
, IGR_DROP
);
1358 priv
->r
->set_vlan_egr_filter(port
, EGR_ENABLE
);
1360 /* Disable ingress and egress filtering */
1361 if (port
!= priv
->cpu_port
)
1362 priv
->r
->set_vlan_igr_filter(port
, IGR_FORWARD
);
1364 priv
->r
->set_vlan_egr_filter(port
, EGR_DISABLE
);
1367 /* Do we need to do something to the CPU-Port, too? */
1368 mutex_unlock(&priv
->reg_mutex
);
1373 static int rtl83xx_vlan_prepare(struct dsa_switch
*ds
, int port
,
1374 const struct switchdev_obj_port_vlan
*vlan
)
1376 struct rtl838x_vlan_info info
;
1377 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1379 priv
->r
->vlan_tables_read(0, &info
);
1381 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1382 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1383 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1385 priv
->r
->vlan_tables_read(1, &info
);
1386 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1387 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1388 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1389 priv
->r
->vlan_set_untagged(1, info
.untagged_ports
);
1390 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info
.untagged_ports
);
1392 priv
->r
->vlan_set_tagged(1, &info
);
1393 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info
.tagged_ports
);
1398 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv
*priv
,
1401 /* Set both inner and outer PVID of the port */
1402 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_INNER
, pvid
);
1403 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_OUTER
, pvid
);
1404 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_INNER
,
1405 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1406 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_OUTER
,
1407 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1409 priv
->ports
[port
].pvid
= pvid
;
1412 static int rtl83xx_vlan_add(struct dsa_switch
*ds
, int port
,
1413 const struct switchdev_obj_port_vlan
*vlan
,
1414 struct netlink_ext_ack
*extack
)
1416 struct rtl838x_vlan_info info
;
1417 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1420 pr_debug("%s port %d, vid %d, flags %x\n",
1421 __func__
, port
, vlan
->vid
, vlan
->flags
);
1423 if (vlan
->vid
> 4095) {
1424 dev_err(priv
->dev
, "VLAN out of range: %d", vlan
->vid
);
1428 err
= rtl83xx_vlan_prepare(ds
, port
, vlan
);
1432 mutex_lock(&priv
->reg_mutex
);
1434 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
)
1435 rtl83xx_vlan_set_pvid(priv
, port
, vlan
->vid
);
1436 else if (priv
->ports
[port
].pvid
== vlan
->vid
)
1437 rtl83xx_vlan_set_pvid(priv
, port
, 0);
1439 /* Get port memberships of this vlan */
1440 priv
->r
->vlan_tables_read(vlan
->vid
, &info
);
1443 if (!info
.tagged_ports
) {
1445 info
.hash_mc_fid
= false;
1446 info
.hash_uc_fid
= false;
1447 info
.profile_id
= 0;
1450 /* sanitize untagged_ports - must be a subset */
1451 if (info
.untagged_ports
& ~info
.tagged_ports
)
1452 info
.untagged_ports
= 0;
1454 info
.tagged_ports
|= BIT_ULL(port
);
1455 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
1456 info
.untagged_ports
|= BIT_ULL(port
);
1458 info
.untagged_ports
&= ~BIT_ULL(port
);
1460 priv
->r
->vlan_set_untagged(vlan
->vid
, info
.untagged_ports
);
1461 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.untagged_ports
);
1463 priv
->r
->vlan_set_tagged(vlan
->vid
, &info
);
1464 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.tagged_ports
);
1466 mutex_unlock(&priv
->reg_mutex
);
1471 static int rtl83xx_vlan_del(struct dsa_switch
*ds
, int port
,
1472 const struct switchdev_obj_port_vlan
*vlan
)
1474 struct rtl838x_vlan_info info
;
1475 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1478 pr_debug("%s: port %d, vid %d, flags %x\n",
1479 __func__
, port
, vlan
->vid
, vlan
->flags
);
1481 if (vlan
->vid
> 4095) {
1482 dev_err(priv
->dev
, "VLAN out of range: %d", vlan
->vid
);
1486 mutex_lock(&priv
->reg_mutex
);
1487 pvid
= priv
->ports
[port
].pvid
;
1489 /* Reset to default if removing the current PVID */
1490 if (vlan
->vid
== pvid
) {
1491 rtl83xx_vlan_set_pvid(priv
, port
, 0);
1493 /* Get port memberships of this vlan */
1494 priv
->r
->vlan_tables_read(vlan
->vid
, &info
);
1496 /* remove port from both tables */
1497 info
.untagged_ports
&= (~BIT_ULL(port
));
1498 info
.tagged_ports
&= (~BIT_ULL(port
));
1500 priv
->r
->vlan_set_untagged(vlan
->vid
, info
.untagged_ports
);
1501 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.untagged_ports
);
1503 priv
->r
->vlan_set_tagged(vlan
->vid
, &info
);
1504 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.tagged_ports
);
1506 mutex_unlock(&priv
->reg_mutex
);
1511 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry
*e
, int port
, int vid
, u64 mac
)
1513 memset(e
, 0, sizeof(*e
));
1515 e
->type
= L2_UNICAST
;
1519 e
->is_static
= true;
1523 e
->rvid
= e
->vid
= vid
;
1524 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1525 u64_to_ether_addr(mac
, e
->mac
);
1528 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry
*e
, int vid
, u64 mac
, int mc_group
)
1530 memset(e
, 0, sizeof(*e
));
1532 e
->type
= L2_MULTICAST
;
1535 e
->mc_portmask_index
= mc_group
;
1537 e
->rvid
= e
->vid
= vid
;
1538 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1539 u64_to_ether_addr(mac
, e
->mac
);
1542 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1543 * over the entries in the bucket until either a matching entry is found or an empty slot
1544 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1545 * when an empty slot was found and must exist is false, the index of the slot is returned
1546 * when no slots are available returns -1
1548 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1549 bool must_exist
, struct rtl838x_l2_entry
*e
)
1552 u32 key
= priv
->r
->l2_hash_key(priv
, seed
);
1555 pr_debug("%s: using key %x, for seed %016llx\n", __func__
, key
, seed
);
1556 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1557 for (int i
= 0; i
< priv
->l2_bucket_size
; i
++) {
1558 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, e
);
1559 pr_debug("valid %d, mac %016llx\n", e
->valid
, ether_addr_to_u64(&e
->mac
[0]));
1560 if (must_exist
&& !e
->valid
)
1562 if (!e
->valid
|| ((entry
& 0x0fffffffffffffffULL
) == seed
)) {
1563 idx
= i
> 3 ? ((key
>> 14) & 0xffff) | i
>> 1 : ((key
<< 2) | i
) & 0xffff;
1571 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1572 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1573 * when an empty slot was found the index of the slot is returned
1574 * when no slots are available returns -1
1576 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1577 bool must_exist
, struct rtl838x_l2_entry
*e
)
1582 for (int i
= 0; i
< 64; i
++) {
1583 entry
= priv
->r
->read_cam(i
, e
);
1584 if (!must_exist
&& !e
->valid
) {
1585 if (idx
< 0) /* First empty entry? */
1588 } else if ((entry
& 0x0fffffffffffffffULL
) == seed
) {
1589 pr_debug("Found entry in CAM\n");
1598 static int rtl83xx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1599 const unsigned char *addr
, u16 vid
)
1601 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1602 u64 mac
= ether_addr_to_u64(addr
);
1603 struct rtl838x_l2_entry e
;
1605 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1607 if (priv
->is_lagmember
[port
]) {
1608 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1612 mutex_lock(&priv
->reg_mutex
);
1614 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1616 /* Found an existing or empty entry */
1618 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1619 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1623 /* Hash buckets full, try CAM */
1624 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1627 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1628 priv
->r
->write_cam(idx
, &e
);
1635 mutex_unlock(&priv
->reg_mutex
);
1640 static int rtl83xx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1641 const unsigned char *addr
, u16 vid
)
1643 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1644 u64 mac
= ether_addr_to_u64(addr
);
1645 struct rtl838x_l2_entry e
;
1647 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1649 pr_debug("In %s, mac %llx, vid: %d\n", __func__
, mac
, vid
);
1650 mutex_lock(&priv
->reg_mutex
);
1652 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1655 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1657 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1661 /* Check CAM for spillover from hash buckets */
1662 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1666 priv
->r
->write_cam(idx
, &e
);
1672 mutex_unlock(&priv
->reg_mutex
);
1677 static int rtl83xx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1678 dsa_fdb_dump_cb_t
*cb
, void *data
)
1680 struct rtl838x_l2_entry e
;
1681 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1683 mutex_lock(&priv
->reg_mutex
);
1685 for (int i
= 0; i
< priv
->fib_entries
; i
++) {
1686 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1691 if (e
.port
== port
|| e
.port
== RTL930X_PORT_IGNORE
)
1692 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1694 if (!((i
+ 1) % 64))
1698 for (int i
= 0; i
< 64; i
++) {
1699 priv
->r
->read_cam(i
, &e
);
1705 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1708 mutex_unlock(&priv
->reg_mutex
);
1713 static int rtl83xx_port_mdb_add(struct dsa_switch
*ds
, int port
,
1714 const struct switchdev_obj_port_mdb
*mdb
)
1716 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1717 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1718 struct rtl838x_l2_entry e
;
1721 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1724 if (priv
->id
>= 0x9300)
1727 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1729 if (priv
->is_lagmember
[port
]) {
1730 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1734 mutex_lock(&priv
->reg_mutex
);
1736 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1738 /* Found an existing or empty entry */
1741 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1742 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1743 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1745 pr_debug("New entry for seed %016llx\n", seed
);
1746 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1751 rtl83xx_setup_l2_mc_entry(&e
, vid
, mac
, mc_group
);
1752 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1757 /* Hash buckets full, try CAM */
1758 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1762 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1763 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1764 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1766 pr_debug("New entry\n");
1767 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1772 rtl83xx_setup_l2_mc_entry(&e
, vid
, mac
, mc_group
);
1773 priv
->r
->write_cam(idx
, &e
);
1781 mutex_unlock(&priv
->reg_mutex
);
1783 dev_err(ds
->dev
, "failed to add MDB entry\n");
1788 int rtl83xx_port_mdb_del(struct dsa_switch
*ds
, int port
,
1789 const struct switchdev_obj_port_mdb
*mdb
)
1791 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1792 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1793 struct rtl838x_l2_entry e
;
1796 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1799 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1801 if (priv
->is_lagmember
[port
]) {
1802 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1806 mutex_lock(&priv
->reg_mutex
);
1808 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1811 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1812 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1815 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1820 /* Check CAM for spillover from hash buckets */
1821 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1824 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1827 priv
->r
->write_cam(idx
, &e
);
1831 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1834 mutex_unlock(&priv
->reg_mutex
);
1839 static int rtl83xx_port_mirror_add(struct dsa_switch
*ds
, int port
,
1840 struct dsa_mall_mirror_tc_entry
*mirror
,
1843 /* We support 4 mirror groups, one destination port per group */
1845 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1846 int ctrl_reg
, dpm_reg
, spm_reg
;
1848 pr_debug("In %s\n", __func__
);
1850 for (group
= 0; group
< 4; group
++) {
1851 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1855 for (group
= 0; group
< 4; group
++) {
1856 if (priv
->mirror_group_ports
[group
] < 0)
1864 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1865 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1866 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1868 pr_debug("Using group %d\n", group
);
1869 mutex_lock(&priv
->reg_mutex
);
1871 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1872 /* Enable mirroring to port across VLANs (bit 11) */
1873 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1875 /* Enable mirroring to destination port */
1876 sw_w32((mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1879 if (ingress
&& (priv
->r
->get_port_reg_be(spm_reg
) & (1ULL << port
))) {
1880 mutex_unlock(&priv
->reg_mutex
);
1883 if ((!ingress
) && (priv
->r
->get_port_reg_be(dpm_reg
) & (1ULL << port
))) {
1884 mutex_unlock(&priv
->reg_mutex
);
1889 priv
->r
->mask_port_reg_be(0, 1ULL << port
, spm_reg
);
1891 priv
->r
->mask_port_reg_be(0, 1ULL << port
, dpm_reg
);
1893 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1894 mutex_unlock(&priv
->reg_mutex
);
1899 static void rtl83xx_port_mirror_del(struct dsa_switch
*ds
, int port
,
1900 struct dsa_mall_mirror_tc_entry
*mirror
)
1903 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1904 int ctrl_reg
, dpm_reg
, spm_reg
;
1906 pr_debug("In %s\n", __func__
);
1907 for (group
= 0; group
< 4; group
++) {
1908 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1914 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1915 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1916 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1918 mutex_lock(&priv
->reg_mutex
);
1919 if (mirror
->ingress
) {
1920 /* Ingress, clear source port matrix */
1921 priv
->r
->mask_port_reg_be(1ULL << port
, 0, spm_reg
);
1923 /* Egress, clear destination port matrix */
1924 priv
->r
->mask_port_reg_be(1ULL << port
, 0, dpm_reg
);
1927 if (!(sw_r32(spm_reg
) || sw_r32(dpm_reg
))) {
1928 priv
->mirror_group_ports
[group
] = -1;
1929 sw_w32(0, ctrl_reg
);
1932 mutex_unlock(&priv
->reg_mutex
);
1935 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch
*ds
, int port
, struct switchdev_brport_flags flags
, struct netlink_ext_ack
*extack
)
1937 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1938 unsigned long features
= 0;
1939 pr_debug("%s: %d %lX\n", __func__
, port
, flags
.val
);
1940 if (priv
->r
->enable_learning
)
1941 features
|= BR_LEARNING
;
1942 if (priv
->r
->enable_flood
)
1943 features
|= BR_FLOOD
;
1944 if (priv
->r
->enable_mcast_flood
)
1945 features
|= BR_MCAST_FLOOD
;
1946 if (priv
->r
->enable_bcast_flood
)
1947 features
|= BR_BCAST_FLOOD
;
1948 if (flags
.mask
& ~(features
))
1954 static int rtl83xx_port_bridge_flags(struct dsa_switch
*ds
, int port
, struct switchdev_brport_flags flags
, struct netlink_ext_ack
*extack
)
1956 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1958 pr_debug("%s: %d %lX\n", __func__
, port
, flags
.val
);
1959 if (priv
->r
->enable_learning
&& (flags
.mask
& BR_LEARNING
))
1960 priv
->r
->enable_learning(port
, !!(flags
.val
& BR_LEARNING
));
1962 if (priv
->r
->enable_flood
&& (flags
.mask
& BR_FLOOD
))
1963 priv
->r
->enable_flood(port
, !!(flags
.val
& BR_FLOOD
));
1965 if (priv
->r
->enable_mcast_flood
&& (flags
.mask
& BR_MCAST_FLOOD
))
1966 priv
->r
->enable_mcast_flood(port
, !!(flags
.val
& BR_MCAST_FLOOD
));
1968 if (priv
->r
->enable_bcast_flood
&& (flags
.mask
& BR_BCAST_FLOOD
))
1969 priv
->r
->enable_bcast_flood(port
, !!(flags
.val
& BR_BCAST_FLOOD
));
1974 static bool rtl83xx_lag_can_offload(struct dsa_switch
*ds
,
1975 struct net_device
*lag
,
1976 struct netdev_lag_upper_info
*info
)
1980 id
= dsa_lag_id(ds
->dst
, lag
);
1981 if (id
< 0 || id
>= ds
->num_lag_ids
)
1984 if (info
->tx_type
!= NETDEV_LAG_TX_TYPE_HASH
) {
1987 if (info
->hash_type
!= NETDEV_LAG_HASH_L2
&& info
->hash_type
!= NETDEV_LAG_HASH_L23
)
1993 static int rtl83xx_port_lag_change(struct dsa_switch
*ds
, int port
)
1995 pr_debug("%s: %d\n", __func__
, port
);
1996 /* Nothing to be done... */
2001 static int rtl83xx_port_lag_join(struct dsa_switch
*ds
, int port
,
2002 struct net_device
*lag
,
2003 struct netdev_lag_upper_info
*info
)
2005 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2008 if (!rtl83xx_lag_can_offload(ds
, lag
, info
))
2011 mutex_lock(&priv
->reg_mutex
);
2013 for (i
= 0; i
< priv
->n_lags
; i
++) {
2014 if ((!priv
->lag_devs
[i
]) || (priv
->lag_devs
[i
] == lag
))
2017 if (port
>= priv
->cpu_port
) {
2021 pr_info("port_lag_join: group %d, port %d\n",i
, port
);
2022 if (!priv
->lag_devs
[i
])
2023 priv
->lag_devs
[i
] = lag
;
2025 if (priv
->lag_primary
[i
] == -1) {
2026 priv
->lag_primary
[i
] = port
;
2028 priv
->is_lagmember
[port
] = 1;
2030 priv
->lagmembers
|= (1ULL << port
);
2032 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2033 err
= rtl83xx_lag_add(priv
->ds
, i
, port
, info
);
2040 mutex_unlock(&priv
->reg_mutex
);
2045 static int rtl83xx_port_lag_leave(struct dsa_switch
*ds
, int port
,
2046 struct net_device
*lag
)
2048 int i
, group
= -1, err
;
2049 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2051 mutex_lock(&priv
->reg_mutex
);
2052 for (i
= 0; i
< priv
->n_lags
; i
++) {
2053 if (priv
->lags_port_members
[i
] & BIT_ULL(port
)) {
2060 pr_info("port_lag_leave: port %d is not a member\n", port
);
2065 if (port
>= priv
->cpu_port
) {
2069 pr_info("port_lag_del: group %d, port %d\n",group
, port
);
2070 priv
->lagmembers
&=~ (1ULL << port
);
2071 priv
->lag_primary
[i
] = -1;
2072 priv
->is_lagmember
[port
] = 0;
2073 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2074 err
= rtl83xx_lag_del(priv
->ds
, group
, port
);
2079 if (!priv
->lags_port_members
[i
])
2080 priv
->lag_devs
[i
] = NULL
;
2083 mutex_unlock(&priv
->reg_mutex
);
2087 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
2091 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2093 if ((phy_addr
>= 24) &&
2095 (priv
->ports
[24].phy
== PHY_RTL838X_SDS
)) {
2098 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
2102 read_phy(phy_addr
, 0, phy_reg
, &val
);
2106 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
2109 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2111 if ((phy_addr
>= 24) &&
2113 (priv
->ports
[24].phy
== PHY_RTL838X_SDS
)) {
2116 sw_w32(val
, RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2));
2119 return write_phy(phy_addr
, 0, phy_reg
, val
);
2122 const struct dsa_switch_ops rtl83xx_switch_ops
= {
2123 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2124 .setup
= rtl83xx_setup
,
2126 .phy_read
= dsa_phy_read
,
2127 .phy_write
= dsa_phy_write
,
2129 .phylink_validate
= rtl83xx_phylink_validate
,
2130 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
2131 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
2132 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
2133 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
2135 .get_strings
= rtl83xx_get_strings
,
2136 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2137 .get_sset_count
= rtl83xx_get_sset_count
,
2139 .port_enable
= rtl83xx_port_enable
,
2140 .port_disable
= rtl83xx_port_disable
,
2142 .get_mac_eee
= rtl83xx_get_mac_eee
,
2143 .set_mac_eee
= rtl83xx_set_mac_eee
,
2145 .set_ageing_time
= rtl83xx_set_ageing_time
,
2146 .port_bridge_join
= rtl83xx_port_bridge_join
,
2147 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2148 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2149 .port_fast_age
= rtl83xx_fast_age
,
2151 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2152 .port_vlan_add
= rtl83xx_vlan_add
,
2153 .port_vlan_del
= rtl83xx_vlan_del
,
2155 .port_fdb_add
= rtl83xx_port_fdb_add
,
2156 .port_fdb_del
= rtl83xx_port_fdb_del
,
2157 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2159 .port_mdb_add
= rtl83xx_port_mdb_add
,
2160 .port_mdb_del
= rtl83xx_port_mdb_del
,
2162 .port_mirror_add
= rtl83xx_port_mirror_add
,
2163 .port_mirror_del
= rtl83xx_port_mirror_del
,
2165 .port_lag_change
= rtl83xx_port_lag_change
,
2166 .port_lag_join
= rtl83xx_port_lag_join
,
2167 .port_lag_leave
= rtl83xx_port_lag_leave
,
2169 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2170 .port_bridge_flags
= rtl83xx_port_bridge_flags
,
2173 const struct dsa_switch_ops rtl930x_switch_ops
= {
2174 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2175 .setup
= rtl93xx_setup
,
2177 .phy_read
= dsa_phy_read
,
2178 .phy_write
= dsa_phy_write
,
2180 .phylink_validate
= rtl93xx_phylink_validate
,
2181 .phylink_mac_link_state
= rtl93xx_phylink_mac_link_state
,
2182 .phylink_mac_config
= rtl93xx_phylink_mac_config
,
2183 .phylink_mac_link_down
= rtl93xx_phylink_mac_link_down
,
2184 .phylink_mac_link_up
= rtl93xx_phylink_mac_link_up
,
2186 .get_strings
= rtl83xx_get_strings
,
2187 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2188 .get_sset_count
= rtl83xx_get_sset_count
,
2190 .port_enable
= rtl83xx_port_enable
,
2191 .port_disable
= rtl83xx_port_disable
,
2193 .get_mac_eee
= rtl93xx_get_mac_eee
,
2194 .set_mac_eee
= rtl83xx_set_mac_eee
,
2196 .set_ageing_time
= rtl83xx_set_ageing_time
,
2197 .port_bridge_join
= rtl83xx_port_bridge_join
,
2198 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2199 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2200 .port_fast_age
= rtl930x_fast_age
,
2202 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2203 .port_vlan_add
= rtl83xx_vlan_add
,
2204 .port_vlan_del
= rtl83xx_vlan_del
,
2206 .port_fdb_add
= rtl83xx_port_fdb_add
,
2207 .port_fdb_del
= rtl83xx_port_fdb_del
,
2208 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2210 .port_mdb_add
= rtl83xx_port_mdb_add
,
2211 .port_mdb_del
= rtl83xx_port_mdb_del
,
2213 .port_lag_change
= rtl83xx_port_lag_change
,
2214 .port_lag_join
= rtl83xx_port_lag_join
,
2215 .port_lag_leave
= rtl83xx_port_lag_leave
,
2217 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2218 .port_bridge_flags
= rtl83xx_port_bridge_flags
,