1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/if_bridge.h>
5 #include <asm/mach-rtl838x/mach-rtl83xx.h>
9 extern struct rtl83xx_soc_info soc_info
;
11 static void rtl83xx_init_stats(struct rtl838x_switch_priv
*priv
)
13 mutex_lock(&priv
->reg_mutex
);
15 /* Enable statistics module: all counters plus debug.
16 * On RTL839x all counters are enabled by default
18 if (priv
->family_id
== RTL8380_FAMILY_ID
)
19 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
21 /* Reset statistics counters */
22 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
24 mutex_unlock(&priv
->reg_mutex
);
27 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
32 /* Enable all ports with a PHY, including the SFP-ports */
33 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
34 if (priv
->ports
[i
].phy
)
38 pr_info("%s: %16llx\n", __func__
, v
);
39 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
41 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
42 if (priv
->family_id
== RTL8390_FAMILY_ID
)
43 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL
);
44 else if(priv
->family_id
== RTL9300_FAMILY_ID
)
45 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
48 const struct rtl83xx_mib_desc rtl83xx_mib
[] = {
49 MIB_DESC(2, 0xf8, "ifInOctets"),
50 MIB_DESC(2, 0xf0, "ifOutOctets"),
51 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
52 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
53 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
54 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
55 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
56 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
57 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
58 MIB_DESC(1, 0xd0, "ifOutDiscards"),
59 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
60 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
61 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
62 MIB_DESC(1, 0xc0, ".3LateCollisions"),
63 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
64 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
65 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
66 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
67 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
68 MIB_DESC(1, 0xa8, "DropEvents"),
69 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
70 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
71 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
72 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
73 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
74 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
75 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
76 MIB_DESC(1, 0x88, "rx_OversizePkts"),
77 MIB_DESC(1, 0x84, "Fragments"),
78 MIB_DESC(1, 0x80, "Jabbers"),
79 MIB_DESC(1, 0x7c, "Collisions"),
80 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
81 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
82 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
83 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
85 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
87 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
89 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
91 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
92 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
93 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x40, "rxMacDiscards")
101 static enum dsa_tag_protocol
rtl83xx_get_tag_protocol(struct dsa_switch
*ds
,
103 enum dsa_tag_protocol mprot
)
105 /* The switch does not tag the frames, instead internally the header
106 * structure for each packet is tagged accordingly.
108 return DSA_TAG_PROTO_TRAILER
;
111 /* Initialize all VLANS */
112 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv
*priv
)
114 struct rtl838x_vlan_info info
;
116 pr_info("In %s\n", __func__
);
118 priv
->r
->vlan_profile_setup(0);
119 priv
->r
->vlan_profile_setup(1);
120 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv
->r
->read_mcast_pmask(UNKNOWN_MC_PMASK
));
121 priv
->r
->vlan_profile_dump(0);
123 info
.fid
= 0; /* Default Forwarding ID / MSTI */
124 info
.hash_uc_fid
= false; /* Do not build the L2 lookup hash with FID, but VID */
125 info
.hash_mc_fid
= false; /* Do the same for Multicast packets */
126 info
.profile_id
= 0; /* Use default Vlan Profile 0 */
127 info
.tagged_ports
= 0; /* Initially no port members */
128 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
130 info
.multicast_grp_mask
= 0;
131 info
.l2_tunnel_list_id
= -1;
134 /* Initialize all vlans 0-4095 */
135 for (int i
= 0; i
< MAX_VLANS
; i
++)
136 priv
->r
->vlan_set_tagged(i
, &info
);
138 /* reset PVIDs; defaults to 1 on reset */
139 for (int i
= 0; i
<= priv
->ds
->num_ports
; i
++) {
140 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_INNER
, 0);
141 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_OUTER
, 0);
142 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_INNER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
143 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_OUTER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
146 /* Set forwarding action based on inner VLAN tag */
147 for (int i
= 0; i
< priv
->cpu_port
; i
++)
148 priv
->r
->vlan_fwd_on_inner(i
, true);
151 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv
*priv
)
153 for (int i
= 0; i
< priv
->cpu_port
; i
++)
154 priv
->r
->set_receive_management_action(i
, BPDU
, COPY2CPU
);
157 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv
*priv
,
158 int port
, bool enable
)
160 int shift
= SALRN_PORT_SHIFT(port
);
161 int val
= enable
? SALRN_MODE_HARDWARE
: SALRN_MODE_DISABLED
;
163 sw_w32_mask(SALRN_MODE_MASK
<< shift
, val
<< shift
,
164 priv
->r
->l2_port_new_salrn(port
));
167 static int rtl83xx_setup(struct dsa_switch
*ds
)
169 struct rtl838x_switch_priv
*priv
= ds
->priv
;
171 pr_debug("%s called\n", __func__
);
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
176 for (int i
= 0; i
< ds
->num_ports
; i
++)
177 priv
->ports
[i
].enable
= false;
178 priv
->ports
[priv
->cpu_port
].enable
= true;
180 /* Configure ports so they are disabled by default, but once enabled
181 * they will work in isolated mode (only traffic between port and CPU).
183 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
184 if (priv
->ports
[i
].phy
) {
185 priv
->ports
[i
].pm
= BIT_ULL(priv
->cpu_port
);
186 priv
->r
->traffic_set(i
, BIT_ULL(i
));
189 priv
->r
->traffic_set(priv
->cpu_port
, BIT_ULL(priv
->cpu_port
));
191 /* For standalone ports, forward packets even if a static fdb
192 * entry for the source address exists on another port.
194 if (priv
->r
->set_static_move_action
) {
195 for (int i
= 0; i
<= priv
->cpu_port
; i
++)
196 priv
->r
->set_static_move_action(i
, true);
199 if (priv
->family_id
== RTL8380_FAMILY_ID
)
200 rtl838x_print_matrix();
202 rtl839x_print_matrix();
204 rtl83xx_init_stats(priv
);
206 rtl83xx_vlan_setup(priv
);
208 rtl83xx_setup_bpdu_traps(priv
);
210 ds
->configure_vlan_while_not_filtering
= true;
212 priv
->r
->l2_learning_setup();
214 rtl83xx_port_set_salrn(priv
, priv
->cpu_port
, false);
215 ds
->assisted_learning_on_cpu_port
= true;
217 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
218 * 0: FWD, 1: DROP, 2: TRAP2CPU
220 if (priv
->family_id
== RTL8380_FAMILY_ID
)
221 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL
);
223 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL
);
225 /* Enable MAC Polling PHY again */
226 rtl83xx_enable_phy_polling(priv
);
227 pr_debug("Please wait until PHY is settled\n");
229 priv
->r
->pie_init(priv
);
234 static int rtl93xx_setup(struct dsa_switch
*ds
)
236 struct rtl838x_switch_priv
*priv
= ds
->priv
;
238 pr_info("%s called\n", __func__
);
240 /* Disable MAC polling the PHY so that we can start configuration */
241 if (priv
->family_id
== RTL9300_FAMILY_ID
)
242 sw_w32(0, RTL930X_SMI_POLL_CTRL
);
244 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
245 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
);
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
249 /* Disable all ports except CPU port */
250 for (int i
= 0; i
< ds
->num_ports
; i
++)
251 priv
->ports
[i
].enable
= false;
252 priv
->ports
[priv
->cpu_port
].enable
= true;
254 /* Configure ports so they are disabled by default, but once enabled
255 * they will work in isolated mode (only traffic between port and CPU).
257 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
258 if (priv
->ports
[i
].phy
) {
259 priv
->ports
[i
].pm
= BIT_ULL(priv
->cpu_port
);
260 priv
->r
->traffic_set(i
, BIT_ULL(i
));
263 priv
->r
->traffic_set(priv
->cpu_port
, BIT_ULL(priv
->cpu_port
));
265 rtl930x_print_matrix();
267 /* TODO: Initialize statistics */
269 rtl83xx_vlan_setup(priv
);
271 ds
->configure_vlan_while_not_filtering
= true;
273 priv
->r
->l2_learning_setup();
275 rtl83xx_port_set_salrn(priv
, priv
->cpu_port
, false);
276 ds
->assisted_learning_on_cpu_port
= true;
278 rtl83xx_enable_phy_polling(priv
);
280 priv
->r
->pie_init(priv
);
282 priv
->r
->led_init(priv
);
287 static int rtl93xx_get_sds(struct phy_device
*phydev
)
289 struct device
*dev
= &phydev
->mdio
.dev
;
290 struct device_node
*dn
;
297 if (of_property_read_u32(dn
, "sds", &sds_num
))
300 dev_err(dev
, "No DT node.\n");
307 static void rtl83xx_phylink_validate(struct dsa_switch
*ds
, int port
,
308 unsigned long *supported
,
309 struct phylink_link_state
*state
)
311 struct rtl838x_switch_priv
*priv
= ds
->priv
;
312 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
314 pr_debug("In %s port %d, state is %d", __func__
, port
, state
->interface
);
316 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
317 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
318 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
319 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
320 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
321 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
322 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
323 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
324 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
325 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
327 "Unsupported interface: %d for port %d\n",
328 state
->interface
, port
);
332 /* Allow all the expected bits */
333 phylink_set(mask
, Autoneg
);
334 phylink_set_port_modes(mask
);
335 phylink_set(mask
, Pause
);
336 phylink_set(mask
, Asym_Pause
);
338 /* With the exclusion of MII and Reverse MII, we support Gigabit,
339 * including Half duplex
341 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
342 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
343 phylink_set(mask
, 1000baseT_Full
);
344 phylink_set(mask
, 1000baseT_Half
);
347 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
348 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
349 phylink_set(mask
, 1000baseX_Full
);
351 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
352 if (port
>= 48 && port
<= 51 && priv
->family_id
== RTL8390_FAMILY_ID
)
353 phylink_set(mask
, 1000baseX_Full
);
355 phylink_set(mask
, 10baseT_Half
);
356 phylink_set(mask
, 10baseT_Full
);
357 phylink_set(mask
, 100baseT_Half
);
358 phylink_set(mask
, 100baseT_Full
);
360 bitmap_and(supported
, supported
, mask
,
361 __ETHTOOL_LINK_MODE_MASK_NBITS
);
362 bitmap_and(state
->advertising
, state
->advertising
, mask
,
363 __ETHTOOL_LINK_MODE_MASK_NBITS
);
366 static void rtl93xx_phylink_validate(struct dsa_switch
*ds
, int port
,
367 unsigned long *supported
,
368 struct phylink_link_state
*state
)
370 struct rtl838x_switch_priv
*priv
= ds
->priv
;
371 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
373 pr_debug("In %s port %d, state is %d (%s)", __func__
, port
, state
->interface
,
374 phy_modes(state
->interface
));
376 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
377 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
378 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
379 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
380 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
381 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
382 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
383 state
->interface
!= PHY_INTERFACE_MODE_XGMII
&&
384 state
->interface
!= PHY_INTERFACE_MODE_HSGMII
&&
385 state
->interface
!= PHY_INTERFACE_MODE_10GBASER
&&
386 state
->interface
!= PHY_INTERFACE_MODE_10GKR
&&
387 state
->interface
!= PHY_INTERFACE_MODE_USXGMII
&&
388 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
389 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
390 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
392 "Unsupported interface: %d for port %d\n",
393 state
->interface
, port
);
397 /* Allow all the expected bits */
398 phylink_set(mask
, Autoneg
);
399 phylink_set_port_modes(mask
);
400 phylink_set(mask
, Pause
);
401 phylink_set(mask
, Asym_Pause
);
403 /* With the exclusion of MII and Reverse MII, we support Gigabit,
404 * including Half duplex
406 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
407 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
408 phylink_set(mask
, 1000baseT_Full
);
409 phylink_set(mask
, 1000baseT_Half
);
412 /* Internal phys of the RTL93xx family provide 10G */
413 if (priv
->ports
[port
].phy_is_integrated
&&
414 state
->interface
== PHY_INTERFACE_MODE_1000BASEX
) {
415 phylink_set(mask
, 1000baseX_Full
);
416 } else if (priv
->ports
[port
].phy_is_integrated
) {
417 phylink_set(mask
, 1000baseX_Full
);
418 phylink_set(mask
, 10000baseKR_Full
);
419 phylink_set(mask
, 10000baseSR_Full
);
420 phylink_set(mask
, 10000baseCR_Full
);
422 if (state
->interface
== PHY_INTERFACE_MODE_INTERNAL
) {
423 phylink_set(mask
, 1000baseX_Full
);
424 phylink_set(mask
, 1000baseT_Full
);
425 phylink_set(mask
, 10000baseKR_Full
);
426 phylink_set(mask
, 10000baseT_Full
);
427 phylink_set(mask
, 10000baseSR_Full
);
428 phylink_set(mask
, 10000baseCR_Full
);
431 if (state
->interface
== PHY_INTERFACE_MODE_USXGMII
)
432 phylink_set(mask
, 10000baseT_Full
);
434 phylink_set(mask
, 10baseT_Half
);
435 phylink_set(mask
, 10baseT_Full
);
436 phylink_set(mask
, 100baseT_Half
);
437 phylink_set(mask
, 100baseT_Full
);
439 bitmap_and(supported
, supported
, mask
,
440 __ETHTOOL_LINK_MODE_MASK_NBITS
);
441 bitmap_and(state
->advertising
, state
->advertising
, mask
,
442 __ETHTOOL_LINK_MODE_MASK_NBITS
);
443 pr_debug("%s leaving supported: %*pb", __func__
, __ETHTOOL_LINK_MODE_MASK_NBITS
, supported
);
446 static int rtl83xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
447 struct phylink_link_state
*state
)
449 struct rtl838x_switch_priv
*priv
= ds
->priv
;
453 if (port
< 0 || port
> priv
->cpu_port
)
457 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
458 if (link
& BIT_ULL(port
))
460 pr_debug("%s: link state port %d: %llx\n", __func__
, port
, link
& BIT_ULL(port
));
463 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
466 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
467 speed
>>= (port
% 16) << 1;
468 switch (speed
& 0x3) {
470 state
->speed
= SPEED_10
;
473 state
->speed
= SPEED_100
;
476 state
->speed
= SPEED_1000
;
479 if (priv
->family_id
== RTL9300_FAMILY_ID
480 && (port
== 24 || port
== 26)) /* Internal serdes */
481 state
->speed
= SPEED_2500
;
483 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
486 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
487 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
488 state
->pause
|= MLO_PAUSE_RX
;
489 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
490 state
->pause
|= MLO_PAUSE_TX
;
495 static int rtl93xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
496 struct phylink_link_state
*state
)
498 struct rtl838x_switch_priv
*priv
= ds
->priv
;
503 if (port
< 0 || port
> priv
->cpu_port
)
506 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
507 * state needs to be read twice in order to read a correct result.
508 * This would not be necessary for ports connected e.g. to RTL8218D
512 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
513 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
514 if (link
& BIT_ULL(port
))
517 if (priv
->family_id
== RTL9310_FAMILY_ID
)
518 media
= priv
->r
->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS
);
520 if (priv
->family_id
== RTL9300_FAMILY_ID
)
521 media
= sw_r32(RTL930X_MAC_LINK_MEDIA_STS
);
523 if (media
& BIT_ULL(port
))
526 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__
, port
,
527 link
& BIT_ULL(port
), media
);
530 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
533 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
534 speed
>>= (port
% 8) << 2;
535 switch (speed
& 0xf) {
537 state
->speed
= SPEED_10
;
540 state
->speed
= SPEED_100
;
544 state
->speed
= SPEED_1000
;
547 state
->speed
= SPEED_10000
;
551 state
->speed
= SPEED_2500
;
554 state
->speed
= SPEED_5000
;
557 pr_err("%s: unknown speed: %d\n", __func__
, (u32
)speed
& 0xf);
560 if (priv
->family_id
== RTL9310_FAMILY_ID
561 && (port
>= 52 || port
<= 55)) { /* Internal serdes */
562 state
->speed
= SPEED_10000
;
567 pr_debug("%s: speed is: %d %d\n", __func__
, (u32
)speed
& 0xf, state
->speed
);
568 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
569 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
570 state
->pause
|= MLO_PAUSE_RX
;
571 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
572 state
->pause
|= MLO_PAUSE_TX
;
577 static void rtl83xx_config_interface(int port
, phy_interface_t interface
)
579 u32 old
, int_shift
, sds_shift
;
594 old
= sw_r32(RTL838X_SDS_MODE_SEL
);
596 case PHY_INTERFACE_MODE_1000BASEX
:
597 if ((old
>> sds_shift
& 0x1f) == 4)
599 sw_w32_mask(0x7 << int_shift
, 1 << int_shift
, RTL838X_INT_MODE_CTRL
);
600 sw_w32_mask(0x1f << sds_shift
, 4 << sds_shift
, RTL838X_SDS_MODE_SEL
);
602 case PHY_INTERFACE_MODE_SGMII
:
603 if ((old
>> sds_shift
& 0x1f) == 2)
605 sw_w32_mask(0x7 << int_shift
, 2 << int_shift
, RTL838X_INT_MODE_CTRL
);
606 sw_w32_mask(0x1f << sds_shift
, 2 << sds_shift
, RTL838X_SDS_MODE_SEL
);
611 pr_debug("configured port %d for interface %s\n", port
, phy_modes(interface
));
614 static void rtl83xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
616 const struct phylink_link_state
*state
)
618 struct rtl838x_switch_priv
*priv
= ds
->priv
;
620 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
622 pr_debug("%s port %d, mode %x\n", __func__
, port
, mode
);
624 if (port
== priv
->cpu_port
) {
625 /* Set Speed, duplex, flow control
626 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
627 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
630 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
631 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
632 /* allow CRC errors on CPU-port */
633 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
635 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
640 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
641 /* Auto-Negotiation does not work for MAC in RTL8390 */
642 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
643 if (mode
== MLO_AN_PHY
|| phylink_autoneg_inband(mode
)) {
644 pr_debug("PHY autonegotiates\n");
645 reg
|= RTL838X_NWAY_EN
;
646 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
647 rtl83xx_config_interface(port
, state
->interface
);
652 if (mode
!= MLO_AN_FIXED
)
653 pr_debug("Fixed state.\n");
655 /* Clear id_mode_dis bit, and the existing port mode, let
656 * RGMII_MODE_EN bet set by mac_link_{up,down} */
657 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
658 reg
&= ~(RTL838X_RX_PAUSE_EN
| RTL838X_TX_PAUSE_EN
);
659 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
660 if (state
->pause
& MLO_PAUSE_TX
)
661 reg
|= RTL838X_TX_PAUSE_EN
;
662 reg
|= RTL838X_RX_PAUSE_EN
;
664 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
665 reg
&= ~(RTL839X_RX_PAUSE_EN
| RTL839X_TX_PAUSE_EN
);
666 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
667 if (state
->pause
& MLO_PAUSE_TX
)
668 reg
|= RTL839X_TX_PAUSE_EN
;
669 reg
|= RTL839X_RX_PAUSE_EN
;
674 reg
&= ~(3 << speed_bit
);
675 switch (state
->speed
) {
677 reg
|= 2 << speed_bit
;
680 reg
|= 1 << speed_bit
;
683 break; /* Ignore, including 10MBit which has a speed value of 0 */
686 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
687 reg
&= ~(RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
689 reg
|= RTL838X_FORCE_LINK_EN
;
690 if (state
->duplex
== RTL838X_DUPLEX_MODE
)
691 reg
|= RTL838X_DUPLEX_MODE
;
692 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
693 reg
&= ~(RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
695 reg
|= RTL839X_FORCE_LINK_EN
;
696 if (state
->duplex
== RTL839X_DUPLEX_MODE
)
697 reg
|= RTL839X_DUPLEX_MODE
;
700 /* LAG members must use DUPLEX and we need to enable the link */
701 if (priv
->lagmembers
& BIT_ULL(port
)) {
702 switch(priv
->family_id
) {
703 case RTL8380_FAMILY_ID
:
704 reg
|= (RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
706 case RTL8390_FAMILY_ID
:
707 reg
|= (RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
713 if (priv
->family_id
== RTL8380_FAMILY_ID
)
714 reg
&= ~RTL838X_NWAY_EN
;
715 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
718 static void rtl931x_phylink_mac_config(struct dsa_switch
*ds
, int port
,
720 const struct phylink_link_state
*state
)
722 struct rtl838x_switch_priv
*priv
= ds
->priv
;
726 sds_num
= priv
->ports
[port
].sds_num
;
727 pr_info("%s: speed %d sds_num %d\n", __func__
, state
->speed
, sds_num
);
729 switch (state
->interface
) {
730 case PHY_INTERFACE_MODE_HSGMII
:
731 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__
);
732 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
733 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
734 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_HSGMII
);
736 case PHY_INTERFACE_MODE_1000BASEX
:
737 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
738 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
740 case PHY_INTERFACE_MODE_XGMII
:
741 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_XGMII
);
742 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_XGMII
);
744 case PHY_INTERFACE_MODE_10GBASER
:
745 case PHY_INTERFACE_MODE_10GKR
:
746 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
747 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
749 case PHY_INTERFACE_MODE_USXGMII
:
750 /* Translates to MII_USXGMII_10GSXGMII */
751 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
752 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
754 case PHY_INTERFACE_MODE_SGMII
:
755 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__
);
756 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_SGMII
);
757 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_SGMII
);
758 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_SGMII
);
760 case PHY_INTERFACE_MODE_QSGMII
:
761 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
762 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
765 pr_err("%s: unknown serdes mode: %s\n",
766 __func__
, phy_modes(state
->interface
));
770 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
771 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__
, reg
);
773 reg
&= ~(RTL931X_DUPLEX_MODE
| RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
);
776 reg
|= 0x2 << 12; /* Set SMI speed to 0x2 */
778 reg
|= RTL931X_TX_PAUSE_EN
| RTL931X_RX_PAUSE_EN
;
780 if (priv
->lagmembers
& BIT_ULL(port
))
781 reg
|= RTL931X_DUPLEX_MODE
;
783 if (state
->duplex
== DUPLEX_FULL
)
784 reg
|= RTL931X_DUPLEX_MODE
;
786 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
790 static void rtl93xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
792 const struct phylink_link_state
*state
)
794 struct rtl838x_switch_priv
*priv
= ds
->priv
;
795 int sds_num
, sds_mode
;
798 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__
,
799 port
, mode
, phy_modes(state
->interface
), state
->speed
, state
->link
);
801 /* Nothing to be done for the CPU-port */
802 if (port
== priv
->cpu_port
)
805 if (priv
->family_id
== RTL9310_FAMILY_ID
)
806 return rtl931x_phylink_mac_config(ds
, port
, mode
, state
);
808 sds_num
= priv
->ports
[port
].sds_num
;
809 pr_info("%s SDS is %d\n", __func__
, sds_num
);
811 switch (state
->interface
) {
812 case PHY_INTERFACE_MODE_HSGMII
:
815 case PHY_INTERFACE_MODE_1000BASEX
:
818 case PHY_INTERFACE_MODE_XGMII
:
821 case PHY_INTERFACE_MODE_10GBASER
:
822 case PHY_INTERFACE_MODE_10GKR
:
823 sds_mode
= 0x1b; /* 10G 1000X Auto */
825 case PHY_INTERFACE_MODE_USXGMII
:
829 pr_err("%s: unknown serdes mode: %s\n",
830 __func__
, phy_modes(state
->interface
));
833 if (state
->interface
== PHY_INTERFACE_MODE_10GBASER
)
834 rtl9300_serdes_setup(sds_num
, state
->interface
);
837 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
840 switch (state
->speed
) {
859 reg
|= RTL930X_FORCE_LINK_EN
;
861 if (priv
->lagmembers
& BIT_ULL(port
))
862 reg
|= RTL930X_DUPLEX_MODE
| RTL930X_FORCE_LINK_EN
;
864 if (state
->duplex
== DUPLEX_FULL
)
865 reg
|= RTL930X_DUPLEX_MODE
;
867 if (priv
->ports
[port
].phy_is_integrated
)
868 reg
&= ~RTL930X_FORCE_EN
; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
870 reg
|= RTL930X_FORCE_EN
;
872 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
875 static void rtl83xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
877 phy_interface_t interface
)
879 struct rtl838x_switch_priv
*priv
= ds
->priv
;
881 /* Stop TX/RX to port */
882 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
884 /* No longer force link */
885 sw_w32_mask(0x3, 0, priv
->r
->mac_force_mode_ctrl(port
));
888 static void rtl93xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
890 phy_interface_t interface
)
892 struct rtl838x_switch_priv
*priv
= ds
->priv
;
895 /* Stop TX/RX to port */
896 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
898 /* No longer force link */
899 if (priv
->family_id
== RTL9300_FAMILY_ID
)
900 v
= RTL930X_FORCE_EN
| RTL930X_FORCE_LINK_EN
;
901 else if (priv
->family_id
== RTL9310_FAMILY_ID
)
902 v
= RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
;
903 sw_w32_mask(v
, 0, priv
->r
->mac_force_mode_ctrl(port
));
906 static void rtl83xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
908 phy_interface_t interface
,
909 struct phy_device
*phydev
,
910 int speed
, int duplex
,
911 bool tx_pause
, bool rx_pause
)
913 struct rtl838x_switch_priv
*priv
= ds
->priv
;
914 /* Restart TX/RX to port */
915 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
916 /* TODO: Set speed/duplex/pauses */
919 static void rtl93xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
921 phy_interface_t interface
,
922 struct phy_device
*phydev
,
923 int speed
, int duplex
,
924 bool tx_pause
, bool rx_pause
)
926 struct rtl838x_switch_priv
*priv
= ds
->priv
;
928 /* Restart TX/RX to port */
929 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
930 /* TODO: Set speed/duplex/pauses */
933 static void rtl83xx_get_strings(struct dsa_switch
*ds
,
934 int port
, u32 stringset
, u8
*data
)
936 if (stringset
!= ETH_SS_STATS
)
939 for (int i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++)
940 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl83xx_mib
[i
].name
,
944 static void rtl83xx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
947 struct rtl838x_switch_priv
*priv
= ds
->priv
;
948 const struct rtl83xx_mib_desc
*mib
;
951 for (int i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++) {
952 mib
= &rtl83xx_mib
[i
];
954 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 252 - mib
->offset
);
955 if (mib
->size
== 2) {
956 h
= sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 248 - mib
->offset
);
962 static int rtl83xx_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
964 if (sset
!= ETH_SS_STATS
)
967 return ARRAY_SIZE(rtl83xx_mib
);
970 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv
*priv
, int port
)
972 int mc_group
= find_first_zero_bit(priv
->mc_group_bm
, MAX_MC_GROUPS
- 1);
975 if (mc_group
>= MAX_MC_GROUPS
- 1)
978 set_bit(mc_group
, priv
->mc_group_bm
);
979 portmask
= BIT_ULL(port
);
980 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
985 static u64
rtl83xx_mc_group_add_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
987 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
989 pr_debug("%s: %d\n", __func__
, port
);
991 portmask
|= BIT_ULL(port
);
992 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
997 static u64
rtl83xx_mc_group_del_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
999 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
1001 pr_debug("%s: %d\n", __func__
, port
);
1003 portmask
&= ~BIT_ULL(port
);
1004 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1006 clear_bit(mc_group
, priv
->mc_group_bm
);
1011 static int rtl83xx_port_enable(struct dsa_switch
*ds
, int port
,
1012 struct phy_device
*phydev
)
1014 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1017 pr_debug("%s: %x %d", __func__
, (u32
) priv
, port
);
1018 priv
->ports
[port
].enable
= true;
1020 /* enable inner tagging on egress, do not keep any tags */
1021 priv
->r
->vlan_port_keep_tag_set(port
, 0, 1);
1023 if (dsa_is_cpu_port(ds
, port
))
1026 /* add port to switch mask of CPU_PORT */
1027 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1029 if (priv
->is_lagmember
[port
]) {
1030 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1034 /* add all other ports in the same bridge to switch mask of port */
1035 v
= priv
->r
->traffic_get(port
);
1036 v
|= priv
->ports
[port
].pm
;
1037 priv
->r
->traffic_set(port
, v
);
1039 /* TODO: Figure out if this is necessary */
1040 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
1041 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_SABLK_CTRL
);
1042 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_DABLK_CTRL
);
1045 if (priv
->ports
[port
].sds_num
< 0)
1046 priv
->ports
[port
].sds_num
= rtl93xx_get_sds(phydev
);
1051 static void rtl83xx_port_disable(struct dsa_switch
*ds
, int port
)
1053 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1056 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1057 /* you can only disable user ports */
1058 if (!dsa_is_user_port(ds
, port
))
1061 /* BUG: This does not work on RTL931X */
1062 /* remove port from switch mask of CPU_PORT */
1063 priv
->r
->traffic_disable(priv
->cpu_port
, port
);
1065 /* remove all other ports in the same bridge from switch mask of port */
1066 v
= priv
->r
->traffic_get(port
);
1067 v
&= ~priv
->ports
[port
].pm
;
1068 priv
->r
->traffic_set(port
, v
);
1070 priv
->ports
[port
].enable
= false;
1073 static int rtl83xx_set_mac_eee(struct dsa_switch
*ds
, int port
,
1074 struct ethtool_eee
*e
)
1076 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1078 if (e
->eee_enabled
&& !priv
->eee_enabled
) {
1079 pr_info("Globally enabling EEE\n");
1080 priv
->r
->init_eee(priv
, true);
1083 priv
->r
->port_eee_set(priv
, port
, e
->eee_enabled
);
1086 pr_info("Enabled EEE for port %d\n", port
);
1088 pr_info("Disabled EEE for port %d\n", port
);
1093 static int rtl83xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1094 struct ethtool_eee
*e
)
1096 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1098 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
1100 priv
->r
->eee_port_ability(priv
, e
, port
);
1102 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1104 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1109 static int rtl93xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1110 struct ethtool_eee
*e
)
1112 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1114 e
->supported
= SUPPORTED_100baseT_Full
|
1115 SUPPORTED_1000baseT_Full
|
1116 SUPPORTED_2500baseX_Full
;
1118 priv
->r
->eee_port_ability(priv
, e
, port
);
1120 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1122 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1127 static int rtl83xx_set_ageing_time(struct dsa_switch
*ds
, unsigned int msec
)
1129 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1131 priv
->r
->set_ageing_time(msec
);
1136 static int rtl83xx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1137 struct net_device
*bridge
)
1139 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1140 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
), v
;
1142 pr_debug("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
1144 if (priv
->is_lagmember
[port
]) {
1145 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1149 mutex_lock(&priv
->reg_mutex
);
1150 for (int i
= 0; i
< ds
->num_ports
; i
++) {
1151 /* Add this port to the port matrix of the other ports in the
1152 * same bridge. If the port is disabled, port matrix is kept
1153 * and not being setup until the port becomes enabled.
1155 if (dsa_is_user_port(ds
, i
) && !priv
->is_lagmember
[i
] && i
!= port
) {
1156 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1158 if (priv
->ports
[i
].enable
)
1159 priv
->r
->traffic_enable(i
, port
);
1161 priv
->ports
[i
].pm
|= BIT_ULL(port
);
1162 port_bitmap
|= BIT_ULL(i
);
1166 /* Add all other ports to this port matrix. */
1167 if (priv
->ports
[port
].enable
) {
1168 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1169 v
= priv
->r
->traffic_get(port
);
1171 priv
->r
->traffic_set(port
, v
);
1173 priv
->ports
[port
].pm
|= port_bitmap
;
1175 if (priv
->r
->set_static_move_action
)
1176 priv
->r
->set_static_move_action(port
, false);
1178 mutex_unlock(&priv
->reg_mutex
);
1183 static void rtl83xx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1184 struct net_device
*bridge
)
1186 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1187 u64 port_bitmap
= 0, v
;
1189 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1190 mutex_lock(&priv
->reg_mutex
);
1191 for (int i
= 0; i
< ds
->num_ports
; i
++) {
1192 /* Remove this port from the port matrix of the other ports
1193 * in the same bridge. If the port is disabled, port matrix
1194 * is kept and not being setup until the port becomes enabled.
1195 * And the other port's port matrix cannot be broken when the
1196 * other port is still a VLAN-aware port.
1198 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
1199 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1201 if (priv
->ports
[i
].enable
)
1202 priv
->r
->traffic_disable(i
, port
);
1204 priv
->ports
[i
].pm
&= ~BIT_ULL(port
);
1205 port_bitmap
|= BIT_ULL(i
);
1209 /* Remove all other ports from this port matrix. */
1210 if (priv
->ports
[port
].enable
) {
1211 v
= priv
->r
->traffic_get(port
);
1213 priv
->r
->traffic_set(port
, v
);
1215 priv
->ports
[port
].pm
&= ~port_bitmap
;
1217 if (priv
->r
->set_static_move_action
)
1218 priv
->r
->set_static_move_action(port
, true);
1220 mutex_unlock(&priv
->reg_mutex
);
1223 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1229 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1230 int n
= priv
->port_width
<< 1;
1232 /* Ports above or equal CPU port can never be configured */
1233 if (port
>= priv
->cpu_port
)
1236 mutex_lock(&priv
->reg_mutex
);
1238 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1239 * have 64 bit fields, 839x and 931x have 128 bit fields
1241 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1243 if (priv
->family_id
== RTL9300_FAMILY_ID
)
1245 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1248 index
= n
- (pos
>> 4) - 1;
1249 bit
= (pos
<< 1) % 32;
1251 priv
->r
->stp_get(priv
, msti
, port_state
);
1253 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
1254 port_state
[index
] &= ~(3 << bit
);
1257 case BR_STATE_DISABLED
: /* 0 */
1258 port_state
[index
] |= (0 << bit
);
1260 case BR_STATE_BLOCKING
: /* 4 */
1261 case BR_STATE_LISTENING
: /* 1 */
1262 port_state
[index
] |= (1 << bit
);
1264 case BR_STATE_LEARNING
: /* 2 */
1265 port_state
[index
] |= (2 << bit
);
1267 case BR_STATE_FORWARDING
: /* 3 */
1268 port_state
[index
] |= (3 << bit
);
1273 priv
->r
->stp_set(priv
, msti
, port_state
);
1275 mutex_unlock(&priv
->reg_mutex
);
1278 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
)
1280 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1281 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
1283 pr_debug("FAST AGE port %d\n", port
);
1284 mutex_lock(&priv
->reg_mutex
);
1285 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1287 * 0-4: Replacing port
1288 * 5-9: Flushed/replaced port
1290 * 22: Entry types: 1: dynamic, 0: also static
1291 * 23: Match flush port
1293 * 25: Flush (0) or replace (1) L2 entries
1294 * 26: Status of action (1: Start, 0: Done)
1296 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
1298 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(26 + s
));
1300 mutex_unlock(&priv
->reg_mutex
);
1303 void rtl931x_fast_age(struct dsa_switch
*ds
, int port
)
1305 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1307 pr_info("%s port %d\n", __func__
, port
);
1308 mutex_lock(&priv
->reg_mutex
);
1309 sw_w32(port
<< 11, RTL931X_L2_TBL_FLUSH_CTRL
+ 4);
1311 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL
);
1313 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL
) & BIT (28));
1315 mutex_unlock(&priv
->reg_mutex
);
1318 void rtl930x_fast_age(struct dsa_switch
*ds
, int port
)
1320 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1322 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1323 return rtl931x_fast_age(ds
, port
);
1325 pr_debug("FAST AGE port %d\n", port
);
1326 mutex_lock(&priv
->reg_mutex
);
1327 sw_w32(port
<< 11, RTL930X_L2_TBL_FLUSH_CTRL
+ 4);
1329 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL
);
1331 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(30));
1333 mutex_unlock(&priv
->reg_mutex
);
1336 static int rtl83xx_vlan_filtering(struct dsa_switch
*ds
, int port
,
1337 bool vlan_filtering
,
1338 struct netlink_ext_ack
*extack
)
1340 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1342 pr_debug("%s: port %d\n", __func__
, port
);
1343 mutex_lock(&priv
->reg_mutex
);
1345 if (vlan_filtering
) {
1346 /* Enable ingress and egress filtering
1347 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1348 * the filter action:
1351 * 2: Trap packet to CPU port
1352 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1354 if (port
!= priv
->cpu_port
)
1355 priv
->r
->set_vlan_igr_filter(port
, IGR_DROP
);
1357 priv
->r
->set_vlan_egr_filter(port
, EGR_ENABLE
);
1359 /* Disable ingress and egress filtering */
1360 if (port
!= priv
->cpu_port
)
1361 priv
->r
->set_vlan_igr_filter(port
, IGR_FORWARD
);
1363 priv
->r
->set_vlan_egr_filter(port
, EGR_DISABLE
);
1366 /* Do we need to do something to the CPU-Port, too? */
1367 mutex_unlock(&priv
->reg_mutex
);
1372 static int rtl83xx_vlan_prepare(struct dsa_switch
*ds
, int port
,
1373 const struct switchdev_obj_port_vlan
*vlan
)
1375 struct rtl838x_vlan_info info
;
1376 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1378 priv
->r
->vlan_tables_read(0, &info
);
1380 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1381 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1382 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1384 priv
->r
->vlan_tables_read(1, &info
);
1385 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1386 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1387 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1388 priv
->r
->vlan_set_untagged(1, info
.untagged_ports
);
1389 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info
.untagged_ports
);
1391 priv
->r
->vlan_set_tagged(1, &info
);
1392 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info
.tagged_ports
);
1397 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv
*priv
,
1400 /* Set both inner and outer PVID of the port */
1401 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_INNER
, pvid
);
1402 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_OUTER
, pvid
);
1403 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_INNER
,
1404 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1405 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_OUTER
,
1406 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1408 priv
->ports
[port
].pvid
= pvid
;
1411 static int rtl83xx_vlan_add(struct dsa_switch
*ds
, int port
,
1412 const struct switchdev_obj_port_vlan
*vlan
,
1413 struct netlink_ext_ack
*extack
)
1415 struct rtl838x_vlan_info info
;
1416 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1419 pr_debug("%s port %d, vid %d, flags %x\n",
1420 __func__
, port
, vlan
->vid
, vlan
->flags
);
1422 if (vlan
->vid
> 4095) {
1423 dev_err(priv
->dev
, "VLAN out of range: %d", vlan
->vid
);
1427 err
= rtl83xx_vlan_prepare(ds
, port
, vlan
);
1431 mutex_lock(&priv
->reg_mutex
);
1433 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
)
1434 rtl83xx_vlan_set_pvid(priv
, port
, vlan
->vid
);
1435 else if (priv
->ports
[port
].pvid
== vlan
->vid
)
1436 rtl83xx_vlan_set_pvid(priv
, port
, 0);
1438 /* Get port memberships of this vlan */
1439 priv
->r
->vlan_tables_read(vlan
->vid
, &info
);
1442 if (!info
.tagged_ports
) {
1444 info
.hash_mc_fid
= false;
1445 info
.hash_uc_fid
= false;
1446 info
.profile_id
= 0;
1449 /* sanitize untagged_ports - must be a subset */
1450 if (info
.untagged_ports
& ~info
.tagged_ports
)
1451 info
.untagged_ports
= 0;
1453 info
.tagged_ports
|= BIT_ULL(port
);
1454 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
1455 info
.untagged_ports
|= BIT_ULL(port
);
1457 info
.untagged_ports
&= ~BIT_ULL(port
);
1459 priv
->r
->vlan_set_untagged(vlan
->vid
, info
.untagged_ports
);
1460 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.untagged_ports
);
1462 priv
->r
->vlan_set_tagged(vlan
->vid
, &info
);
1463 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.tagged_ports
);
1465 mutex_unlock(&priv
->reg_mutex
);
1470 static int rtl83xx_vlan_del(struct dsa_switch
*ds
, int port
,
1471 const struct switchdev_obj_port_vlan
*vlan
)
1473 struct rtl838x_vlan_info info
;
1474 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1477 pr_debug("%s: port %d, vid %d, flags %x\n",
1478 __func__
, port
, vlan
->vid
, vlan
->flags
);
1480 if (vlan
->vid
> 4095) {
1481 dev_err(priv
->dev
, "VLAN out of range: %d", vlan
->vid
);
1485 mutex_lock(&priv
->reg_mutex
);
1486 pvid
= priv
->ports
[port
].pvid
;
1488 /* Reset to default if removing the current PVID */
1489 if (vlan
->vid
== pvid
) {
1490 rtl83xx_vlan_set_pvid(priv
, port
, 0);
1492 /* Get port memberships of this vlan */
1493 priv
->r
->vlan_tables_read(vlan
->vid
, &info
);
1495 /* remove port from both tables */
1496 info
.untagged_ports
&= (~BIT_ULL(port
));
1497 info
.tagged_ports
&= (~BIT_ULL(port
));
1499 priv
->r
->vlan_set_untagged(vlan
->vid
, info
.untagged_ports
);
1500 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.untagged_ports
);
1502 priv
->r
->vlan_set_tagged(vlan
->vid
, &info
);
1503 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.tagged_ports
);
1505 mutex_unlock(&priv
->reg_mutex
);
1510 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry
*e
, int port
, int vid
, u64 mac
)
1512 memset(e
, 0, sizeof(*e
));
1514 e
->type
= L2_UNICAST
;
1518 e
->is_static
= true;
1522 e
->rvid
= e
->vid
= vid
;
1523 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1524 u64_to_ether_addr(mac
, e
->mac
);
1527 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry
*e
, int vid
, u64 mac
, int mc_group
)
1529 memset(e
, 0, sizeof(*e
));
1531 e
->type
= L2_MULTICAST
;
1534 e
->mc_portmask_index
= mc_group
;
1536 e
->rvid
= e
->vid
= vid
;
1537 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1538 u64_to_ether_addr(mac
, e
->mac
);
1541 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1542 * over the entries in the bucket until either a matching entry is found or an empty slot
1543 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1544 * when an empty slot was found and must exist is false, the index of the slot is returned
1545 * when no slots are available returns -1
1547 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1548 bool must_exist
, struct rtl838x_l2_entry
*e
)
1551 u32 key
= priv
->r
->l2_hash_key(priv
, seed
);
1554 pr_debug("%s: using key %x, for seed %016llx\n", __func__
, key
, seed
);
1555 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1556 for (int i
= 0; i
< priv
->l2_bucket_size
; i
++) {
1557 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, e
);
1558 pr_debug("valid %d, mac %016llx\n", e
->valid
, ether_addr_to_u64(&e
->mac
[0]));
1559 if (must_exist
&& !e
->valid
)
1561 if (!e
->valid
|| ((entry
& 0x0fffffffffffffffULL
) == seed
)) {
1562 idx
= i
> 3 ? ((key
>> 14) & 0xffff) | i
>> 1 : ((key
<< 2) | i
) & 0xffff;
1570 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1571 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1572 * when an empty slot was found the index of the slot is returned
1573 * when no slots are available returns -1
1575 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1576 bool must_exist
, struct rtl838x_l2_entry
*e
)
1581 for (int i
= 0; i
< 64; i
++) {
1582 entry
= priv
->r
->read_cam(i
, e
);
1583 if (!must_exist
&& !e
->valid
) {
1584 if (idx
< 0) /* First empty entry? */
1587 } else if ((entry
& 0x0fffffffffffffffULL
) == seed
) {
1588 pr_debug("Found entry in CAM\n");
1597 static int rtl83xx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1598 const unsigned char *addr
, u16 vid
)
1600 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1601 u64 mac
= ether_addr_to_u64(addr
);
1602 struct rtl838x_l2_entry e
;
1604 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1606 if (priv
->is_lagmember
[port
]) {
1607 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1611 mutex_lock(&priv
->reg_mutex
);
1613 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1615 /* Found an existing or empty entry */
1617 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1618 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1622 /* Hash buckets full, try CAM */
1623 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1626 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1627 priv
->r
->write_cam(idx
, &e
);
1634 mutex_unlock(&priv
->reg_mutex
);
1639 static int rtl83xx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1640 const unsigned char *addr
, u16 vid
)
1642 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1643 u64 mac
= ether_addr_to_u64(addr
);
1644 struct rtl838x_l2_entry e
;
1646 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1648 pr_debug("In %s, mac %llx, vid: %d\n", __func__
, mac
, vid
);
1649 mutex_lock(&priv
->reg_mutex
);
1651 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1654 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1656 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1660 /* Check CAM for spillover from hash buckets */
1661 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1665 priv
->r
->write_cam(idx
, &e
);
1671 mutex_unlock(&priv
->reg_mutex
);
1676 static int rtl83xx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1677 dsa_fdb_dump_cb_t
*cb
, void *data
)
1679 struct rtl838x_l2_entry e
;
1680 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1682 mutex_lock(&priv
->reg_mutex
);
1684 for (int i
= 0; i
< priv
->fib_entries
; i
++) {
1685 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1690 if (e
.port
== port
|| e
.port
== RTL930X_PORT_IGNORE
)
1691 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1693 if (!((i
+ 1) % 64))
1697 for (int i
= 0; i
< 64; i
++) {
1698 priv
->r
->read_cam(i
, &e
);
1704 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1707 mutex_unlock(&priv
->reg_mutex
);
1712 static int rtl83xx_port_mdb_add(struct dsa_switch
*ds
, int port
,
1713 const struct switchdev_obj_port_mdb
*mdb
)
1715 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1716 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1717 struct rtl838x_l2_entry e
;
1720 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1723 if (priv
->id
>= 0x9300)
1726 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1728 if (priv
->is_lagmember
[port
]) {
1729 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1733 mutex_lock(&priv
->reg_mutex
);
1735 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1737 /* Found an existing or empty entry */
1740 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1741 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1742 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1744 pr_debug("New entry for seed %016llx\n", seed
);
1745 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1750 rtl83xx_setup_l2_mc_entry(&e
, vid
, mac
, mc_group
);
1751 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1756 /* Hash buckets full, try CAM */
1757 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1761 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1762 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1763 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1765 pr_debug("New entry\n");
1766 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1771 rtl83xx_setup_l2_mc_entry(&e
, vid
, mac
, mc_group
);
1772 priv
->r
->write_cam(idx
, &e
);
1780 mutex_unlock(&priv
->reg_mutex
);
1782 dev_err(ds
->dev
, "failed to add MDB entry\n");
1787 int rtl83xx_port_mdb_del(struct dsa_switch
*ds
, int port
,
1788 const struct switchdev_obj_port_mdb
*mdb
)
1790 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1791 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1792 struct rtl838x_l2_entry e
;
1795 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1798 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1800 if (priv
->is_lagmember
[port
]) {
1801 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1805 mutex_lock(&priv
->reg_mutex
);
1807 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1810 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1811 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1814 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1819 /* Check CAM for spillover from hash buckets */
1820 idx
= rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1823 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1826 priv
->r
->write_cam(idx
, &e
);
1830 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1833 mutex_unlock(&priv
->reg_mutex
);
1838 static int rtl83xx_port_mirror_add(struct dsa_switch
*ds
, int port
,
1839 struct dsa_mall_mirror_tc_entry
*mirror
,
1842 /* We support 4 mirror groups, one destination port per group */
1844 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1845 int ctrl_reg
, dpm_reg
, spm_reg
;
1847 pr_debug("In %s\n", __func__
);
1849 for (group
= 0; group
< 4; group
++) {
1850 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1854 for (group
= 0; group
< 4; group
++) {
1855 if (priv
->mirror_group_ports
[group
] < 0)
1863 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1864 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1865 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1867 pr_debug("Using group %d\n", group
);
1868 mutex_lock(&priv
->reg_mutex
);
1870 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1871 /* Enable mirroring to port across VLANs (bit 11) */
1872 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1874 /* Enable mirroring to destination port */
1875 sw_w32((mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1878 if (ingress
&& (priv
->r
->get_port_reg_be(spm_reg
) & (1ULL << port
))) {
1879 mutex_unlock(&priv
->reg_mutex
);
1882 if ((!ingress
) && (priv
->r
->get_port_reg_be(dpm_reg
) & (1ULL << port
))) {
1883 mutex_unlock(&priv
->reg_mutex
);
1888 priv
->r
->mask_port_reg_be(0, 1ULL << port
, spm_reg
);
1890 priv
->r
->mask_port_reg_be(0, 1ULL << port
, dpm_reg
);
1892 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1893 mutex_unlock(&priv
->reg_mutex
);
1898 static void rtl83xx_port_mirror_del(struct dsa_switch
*ds
, int port
,
1899 struct dsa_mall_mirror_tc_entry
*mirror
)
1902 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1903 int ctrl_reg
, dpm_reg
, spm_reg
;
1905 pr_debug("In %s\n", __func__
);
1906 for (group
= 0; group
< 4; group
++) {
1907 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1913 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1914 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1915 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1917 mutex_lock(&priv
->reg_mutex
);
1918 if (mirror
->ingress
) {
1919 /* Ingress, clear source port matrix */
1920 priv
->r
->mask_port_reg_be(1ULL << port
, 0, spm_reg
);
1922 /* Egress, clear destination port matrix */
1923 priv
->r
->mask_port_reg_be(1ULL << port
, 0, dpm_reg
);
1926 if (!(sw_r32(spm_reg
) || sw_r32(dpm_reg
))) {
1927 priv
->mirror_group_ports
[group
] = -1;
1928 sw_w32(0, ctrl_reg
);
1931 mutex_unlock(&priv
->reg_mutex
);
1934 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch
*ds
, int port
, struct switchdev_brport_flags flags
, struct netlink_ext_ack
*extack
)
1936 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1937 unsigned long features
= 0;
1938 pr_debug("%s: %d %lX\n", __func__
, port
, flags
.val
);
1939 if (priv
->r
->enable_learning
)
1940 features
|= BR_LEARNING
;
1941 if (priv
->r
->enable_flood
)
1942 features
|= BR_FLOOD
;
1943 if (priv
->r
->enable_mcast_flood
)
1944 features
|= BR_MCAST_FLOOD
;
1945 if (priv
->r
->enable_bcast_flood
)
1946 features
|= BR_BCAST_FLOOD
;
1947 if (flags
.mask
& ~(features
))
1953 static int rtl83xx_port_bridge_flags(struct dsa_switch
*ds
, int port
, struct switchdev_brport_flags flags
, struct netlink_ext_ack
*extack
)
1955 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1957 pr_debug("%s: %d %lX\n", __func__
, port
, flags
.val
);
1958 if (priv
->r
->enable_learning
&& (flags
.mask
& BR_LEARNING
))
1959 priv
->r
->enable_learning(port
, !!(flags
.val
& BR_LEARNING
));
1961 if (priv
->r
->enable_flood
&& (flags
.mask
& BR_FLOOD
))
1962 priv
->r
->enable_flood(port
, !!(flags
.val
& BR_FLOOD
));
1964 if (priv
->r
->enable_mcast_flood
&& (flags
.mask
& BR_MCAST_FLOOD
))
1965 priv
->r
->enable_mcast_flood(port
, !!(flags
.val
& BR_MCAST_FLOOD
));
1967 if (priv
->r
->enable_bcast_flood
&& (flags
.mask
& BR_BCAST_FLOOD
))
1968 priv
->r
->enable_bcast_flood(port
, !!(flags
.val
& BR_BCAST_FLOOD
));
1973 static bool rtl83xx_lag_can_offload(struct dsa_switch
*ds
,
1974 struct net_device
*lag
,
1975 struct netdev_lag_upper_info
*info
)
1979 id
= dsa_lag_id(ds
->dst
, lag
);
1980 if (id
< 0 || id
>= ds
->num_lag_ids
)
1983 if (info
->tx_type
!= NETDEV_LAG_TX_TYPE_HASH
) {
1986 if (info
->hash_type
!= NETDEV_LAG_HASH_L2
&& info
->hash_type
!= NETDEV_LAG_HASH_L23
)
1992 static int rtl83xx_port_lag_change(struct dsa_switch
*ds
, int port
)
1994 pr_debug("%s: %d\n", __func__
, port
);
1995 /* Nothing to be done... */
2000 static int rtl83xx_port_lag_join(struct dsa_switch
*ds
, int port
,
2001 struct net_device
*lag
,
2002 struct netdev_lag_upper_info
*info
)
2004 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2007 if (!rtl83xx_lag_can_offload(ds
, lag
, info
))
2010 mutex_lock(&priv
->reg_mutex
);
2012 for (i
= 0; i
< priv
->n_lags
; i
++) {
2013 if ((!priv
->lag_devs
[i
]) || (priv
->lag_devs
[i
] == lag
))
2016 if (port
>= priv
->cpu_port
) {
2020 pr_info("port_lag_join: group %d, port %d\n",i
, port
);
2021 if (!priv
->lag_devs
[i
])
2022 priv
->lag_devs
[i
] = lag
;
2024 if (priv
->lag_primary
[i
] == -1) {
2025 priv
->lag_primary
[i
] = port
;
2027 priv
->is_lagmember
[port
] = 1;
2029 priv
->lagmembers
|= (1ULL << port
);
2031 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2032 err
= rtl83xx_lag_add(priv
->ds
, i
, port
, info
);
2039 mutex_unlock(&priv
->reg_mutex
);
2044 static int rtl83xx_port_lag_leave(struct dsa_switch
*ds
, int port
,
2045 struct net_device
*lag
)
2047 int i
, group
= -1, err
;
2048 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2050 mutex_lock(&priv
->reg_mutex
);
2051 for (i
= 0; i
< priv
->n_lags
; i
++) {
2052 if (priv
->lags_port_members
[i
] & BIT_ULL(port
)) {
2059 pr_info("port_lag_leave: port %d is not a member\n", port
);
2064 if (port
>= priv
->cpu_port
) {
2068 pr_info("port_lag_del: group %d, port %d\n",group
, port
);
2069 priv
->lagmembers
&=~ (1ULL << port
);
2070 priv
->lag_primary
[i
] = -1;
2071 priv
->is_lagmember
[port
] = 0;
2072 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2073 err
= rtl83xx_lag_del(priv
->ds
, group
, port
);
2078 if (!priv
->lags_port_members
[i
])
2079 priv
->lag_devs
[i
] = NULL
;
2082 mutex_unlock(&priv
->reg_mutex
);
2086 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
2090 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2092 if ((phy_addr
>= 24) &&
2094 (priv
->ports
[24].phy
== PHY_RTL838X_SDS
)) {
2097 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
2101 read_phy(phy_addr
, 0, phy_reg
, &val
);
2105 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
2108 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2110 if ((phy_addr
>= 24) &&
2112 (priv
->ports
[24].phy
== PHY_RTL838X_SDS
)) {
2115 sw_w32(val
, RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2));
2118 return write_phy(phy_addr
, 0, phy_reg
, val
);
2121 const struct dsa_switch_ops rtl83xx_switch_ops
= {
2122 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2123 .setup
= rtl83xx_setup
,
2125 .phy_read
= dsa_phy_read
,
2126 .phy_write
= dsa_phy_write
,
2128 .phylink_validate
= rtl83xx_phylink_validate
,
2129 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
2130 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
2131 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
2132 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
2134 .get_strings
= rtl83xx_get_strings
,
2135 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2136 .get_sset_count
= rtl83xx_get_sset_count
,
2138 .port_enable
= rtl83xx_port_enable
,
2139 .port_disable
= rtl83xx_port_disable
,
2141 .get_mac_eee
= rtl83xx_get_mac_eee
,
2142 .set_mac_eee
= rtl83xx_set_mac_eee
,
2144 .set_ageing_time
= rtl83xx_set_ageing_time
,
2145 .port_bridge_join
= rtl83xx_port_bridge_join
,
2146 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2147 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2148 .port_fast_age
= rtl83xx_fast_age
,
2150 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2151 .port_vlan_add
= rtl83xx_vlan_add
,
2152 .port_vlan_del
= rtl83xx_vlan_del
,
2154 .port_fdb_add
= rtl83xx_port_fdb_add
,
2155 .port_fdb_del
= rtl83xx_port_fdb_del
,
2156 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2158 .port_mdb_add
= rtl83xx_port_mdb_add
,
2159 .port_mdb_del
= rtl83xx_port_mdb_del
,
2161 .port_mirror_add
= rtl83xx_port_mirror_add
,
2162 .port_mirror_del
= rtl83xx_port_mirror_del
,
2164 .port_lag_change
= rtl83xx_port_lag_change
,
2165 .port_lag_join
= rtl83xx_port_lag_join
,
2166 .port_lag_leave
= rtl83xx_port_lag_leave
,
2168 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2169 .port_bridge_flags
= rtl83xx_port_bridge_flags
,
2172 const struct dsa_switch_ops rtl930x_switch_ops
= {
2173 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2174 .setup
= rtl93xx_setup
,
2176 .phy_read
= dsa_phy_read
,
2177 .phy_write
= dsa_phy_write
,
2179 .phylink_validate
= rtl93xx_phylink_validate
,
2180 .phylink_mac_link_state
= rtl93xx_phylink_mac_link_state
,
2181 .phylink_mac_config
= rtl93xx_phylink_mac_config
,
2182 .phylink_mac_link_down
= rtl93xx_phylink_mac_link_down
,
2183 .phylink_mac_link_up
= rtl93xx_phylink_mac_link_up
,
2185 .get_strings
= rtl83xx_get_strings
,
2186 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2187 .get_sset_count
= rtl83xx_get_sset_count
,
2189 .port_enable
= rtl83xx_port_enable
,
2190 .port_disable
= rtl83xx_port_disable
,
2192 .get_mac_eee
= rtl93xx_get_mac_eee
,
2193 .set_mac_eee
= rtl83xx_set_mac_eee
,
2195 .set_ageing_time
= rtl83xx_set_ageing_time
,
2196 .port_bridge_join
= rtl83xx_port_bridge_join
,
2197 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2198 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2199 .port_fast_age
= rtl930x_fast_age
,
2201 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2202 .port_vlan_add
= rtl83xx_vlan_add
,
2203 .port_vlan_del
= rtl83xx_vlan_del
,
2205 .port_fdb_add
= rtl83xx_port_fdb_add
,
2206 .port_fdb_del
= rtl83xx_port_fdb_del
,
2207 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2209 .port_mdb_add
= rtl83xx_port_mdb_add
,
2210 .port_mdb_del
= rtl83xx_port_mdb_del
,
2212 .port_lag_change
= rtl83xx_port_lag_change
,
2213 .port_lag_join
= rtl83xx_port_lag_join
,
2214 .port_lag_leave
= rtl83xx_port_lag_leave
,
2216 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2217 .port_bridge_flags
= rtl83xx_port_bridge_flags
,