1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
10 extern struct rtl83xx_soc_info soc_info
;
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv
*priv
)
15 mutex_lock(&priv
->reg_mutex
);
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
20 if (priv
->family_id
== RTL8380_FAMILY_ID
)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
26 mutex_unlock(&priv
->reg_mutex
);
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i
= 0; i
< priv
->cpu_port
; i
++) {
37 if (priv
->ports
[i
].phy
)
41 pr_info("%s: %16llx\n", __func__
, v
);
42 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv
->family_id
== RTL8390_FAMILY_ID
)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL
);
47 else if(priv
->family_id
== RTL9300_FAMILY_ID
)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
51 const struct rtl83xx_mib_desc rtl83xx_mib
[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
104 static enum dsa_tag_protocol
rtl83xx_get_tag_protocol(struct dsa_switch
*ds
,
106 enum dsa_tag_protocol mprot
)
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
111 return DSA_TAG_PROTO_TRAILER
;
115 * Initialize all VLANS
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv
*priv
)
119 struct rtl838x_vlan_info info
;
122 pr_info("In %s\n", __func__
);
124 priv
->r
->vlan_profile_setup(0);
125 priv
->r
->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv
->r
->read_mcast_pmask(UNKNOWN_MC_PMASK
));
127 priv
->r
->vlan_profile_dump(0);
129 info
.fid
= 0; // Default Forwarding ID / MSTI
130 info
.hash_uc_fid
= false; // Do not build the L2 lookup hash with FID, but VID
131 info
.hash_mc_fid
= false; // Do the same for Multicast packets
132 info
.profile_id
= 0; // Use default Vlan Profile 0
133 info
.tagged_ports
= 0; // Initially no port members
134 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
136 info
.multicast_grp_mask
= 0;
137 info
.l2_tunnel_list_id
= -1;
140 // Initialize all vlans 0-4095
141 for (i
= 0; i
< MAX_VLANS
; i
++)
142 priv
->r
->vlan_set_tagged(i
, &info
);
144 // reset PVIDs; defaults to 1 on reset
145 for (i
= 0; i
<= priv
->ds
->num_ports
; i
++) {
146 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_INNER
, 0);
147 priv
->r
->vlan_port_pvid_set(i
, PBVLAN_TYPE_OUTER
, 0);
148 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_INNER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
149 priv
->r
->vlan_port_pvidmode_set(i
, PBVLAN_TYPE_OUTER
, PBVLAN_MODE_UNTAG_AND_PRITAG
);
152 // Set forwarding action based on inner VLAN tag
153 for (i
= 0; i
< priv
->cpu_port
; i
++)
154 priv
->r
->vlan_fwd_on_inner(i
, true);
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv
*priv
)
161 for (i
= 0; i
< priv
->cpu_port
; i
++)
162 priv
->r
->set_receive_management_action(i
, BPDU
, COPY2CPU
);
165 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv
*priv
,
166 int port
, bool enable
)
168 int shift
= SALRN_PORT_SHIFT(port
);
169 int val
= enable
? SALRN_MODE_HARDWARE
: SALRN_MODE_DISABLED
;
171 sw_w32_mask(SALRN_MODE_MASK
<< shift
, val
<< shift
,
172 priv
->r
->l2_port_new_salrn(port
));
175 static int rtl83xx_setup(struct dsa_switch
*ds
)
178 struct rtl838x_switch_priv
*priv
= ds
->priv
;
179 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
);
181 pr_debug("%s called\n", __func__
);
183 /* Disable MAC polling the PHY so that we can start configuration */
184 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
186 for (i
= 0; i
< ds
->num_ports
; i
++)
187 priv
->ports
[i
].enable
= false;
188 priv
->ports
[priv
->cpu_port
].enable
= true;
190 /* Isolate ports from each other: traffic only CPU <-> port */
191 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
192 * traffic from source port i to destination port j
194 for (i
= 0; i
< priv
->cpu_port
; i
++) {
195 if (priv
->ports
[i
].phy
) {
196 priv
->r
->set_port_reg_be(BIT_ULL(priv
->cpu_port
) | BIT_ULL(i
),
197 priv
->r
->port_iso_ctrl(i
));
198 port_bitmap
|= BIT_ULL(i
);
201 priv
->r
->set_port_reg_be(port_bitmap
, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
203 if (priv
->family_id
== RTL8380_FAMILY_ID
)
204 rtl838x_print_matrix();
206 rtl839x_print_matrix();
208 rtl83xx_init_stats(priv
);
210 rtl83xx_vlan_setup(priv
);
212 rtl83xx_setup_bpdu_traps(priv
);
214 ds
->configure_vlan_while_not_filtering
= true;
216 priv
->r
->l2_learning_setup();
218 rtl83xx_port_set_salrn(priv
, priv
->cpu_port
, false);
219 ds
->assisted_learning_on_cpu_port
= true;
222 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
223 * 0: FWD, 1: DROP, 2: TRAP2CPU
225 if (priv
->family_id
== RTL8380_FAMILY_ID
)
226 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL
);
228 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL
);
230 /* Enable MAC Polling PHY again */
231 rtl83xx_enable_phy_polling(priv
);
232 pr_debug("Please wait until PHY is settled\n");
234 priv
->r
->pie_init(priv
);
239 static int rtl93xx_setup(struct dsa_switch
*ds
)
242 struct rtl838x_switch_priv
*priv
= ds
->priv
;
243 u32 port_bitmap
= BIT(priv
->cpu_port
);
245 pr_info("%s called\n", __func__
);
247 /* Disable MAC polling the PHY so that we can start configuration */
248 if (priv
->family_id
== RTL9300_FAMILY_ID
)
249 sw_w32(0, RTL930X_SMI_POLL_CTRL
);
251 if (priv
->family_id
== RTL9310_FAMILY_ID
) {
252 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
);
253 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
256 // Disable all ports except CPU port
257 for (i
= 0; i
< ds
->num_ports
; i
++)
258 priv
->ports
[i
].enable
= false;
259 priv
->ports
[priv
->cpu_port
].enable
= true;
261 for (i
= 0; i
< priv
->cpu_port
; i
++) {
262 if (priv
->ports
[i
].phy
) {
263 priv
->r
->traffic_set(i
, BIT_ULL(priv
->cpu_port
) | BIT_ULL(i
));
264 port_bitmap
|= BIT_ULL(i
);
267 priv
->r
->traffic_set(priv
->cpu_port
, port_bitmap
);
269 rtl930x_print_matrix();
271 // TODO: Initialize statistics
273 rtl83xx_vlan_setup(priv
);
275 ds
->configure_vlan_while_not_filtering
= true;
277 priv
->r
->l2_learning_setup();
279 rtl83xx_port_set_salrn(priv
, priv
->cpu_port
, false);
280 ds
->assisted_learning_on_cpu_port
= true;
282 rtl83xx_enable_phy_polling(priv
);
284 priv
->r
->pie_init(priv
);
286 priv
->r
->led_init(priv
);
291 static int rtl93xx_get_sds(struct phy_device
*phydev
)
293 struct device
*dev
= &phydev
->mdio
.dev
;
294 struct device_node
*dn
;
301 if (of_property_read_u32(dn
, "sds", &sds_num
))
304 dev_err(dev
, "No DT node.\n");
311 static void rtl83xx_phylink_validate(struct dsa_switch
*ds
, int port
,
312 unsigned long *supported
,
313 struct phylink_link_state
*state
)
315 struct rtl838x_switch_priv
*priv
= ds
->priv
;
316 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
318 pr_debug("In %s port %d, state is %d", __func__
, port
, state
->interface
);
320 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
321 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
322 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
323 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
324 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
325 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
326 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
327 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
328 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
329 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
331 "Unsupported interface: %d for port %d\n",
332 state
->interface
, port
);
336 /* Allow all the expected bits */
337 phylink_set(mask
, Autoneg
);
338 phylink_set_port_modes(mask
);
339 phylink_set(mask
, Pause
);
340 phylink_set(mask
, Asym_Pause
);
342 /* With the exclusion of MII and Reverse MII, we support Gigabit,
343 * including Half duplex
345 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
346 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
347 phylink_set(mask
, 1000baseT_Full
);
348 phylink_set(mask
, 1000baseT_Half
);
351 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
352 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
353 phylink_set(mask
, 1000baseX_Full
);
355 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
356 if (port
>= 48 && port
<= 51 && priv
->family_id
== RTL8390_FAMILY_ID
)
357 phylink_set(mask
, 1000baseX_Full
);
359 phylink_set(mask
, 10baseT_Half
);
360 phylink_set(mask
, 10baseT_Full
);
361 phylink_set(mask
, 100baseT_Half
);
362 phylink_set(mask
, 100baseT_Full
);
364 bitmap_and(supported
, supported
, mask
,
365 __ETHTOOL_LINK_MODE_MASK_NBITS
);
366 bitmap_and(state
->advertising
, state
->advertising
, mask
,
367 __ETHTOOL_LINK_MODE_MASK_NBITS
);
370 static void rtl93xx_phylink_validate(struct dsa_switch
*ds
, int port
,
371 unsigned long *supported
,
372 struct phylink_link_state
*state
)
374 struct rtl838x_switch_priv
*priv
= ds
->priv
;
375 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
377 pr_debug("In %s port %d, state is %d (%s)", __func__
, port
, state
->interface
,
378 phy_modes(state
->interface
));
380 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
381 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
382 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
383 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
384 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
385 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
386 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
387 state
->interface
!= PHY_INTERFACE_MODE_XGMII
&&
388 state
->interface
!= PHY_INTERFACE_MODE_HSGMII
&&
389 state
->interface
!= PHY_INTERFACE_MODE_10GBASER
&&
390 state
->interface
!= PHY_INTERFACE_MODE_10GKR
&&
391 state
->interface
!= PHY_INTERFACE_MODE_USXGMII
&&
392 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
393 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
394 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
396 "Unsupported interface: %d for port %d\n",
397 state
->interface
, port
);
401 /* Allow all the expected bits */
402 phylink_set(mask
, Autoneg
);
403 phylink_set_port_modes(mask
);
404 phylink_set(mask
, Pause
);
405 phylink_set(mask
, Asym_Pause
);
407 /* With the exclusion of MII and Reverse MII, we support Gigabit,
408 * including Half duplex
410 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
411 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
412 phylink_set(mask
, 1000baseT_Full
);
413 phylink_set(mask
, 1000baseT_Half
);
416 // Internal phys of the RTL93xx family provide 10G
417 if (priv
->ports
[port
].phy_is_integrated
418 && state
->interface
== PHY_INTERFACE_MODE_1000BASEX
) {
419 phylink_set(mask
, 1000baseX_Full
);
420 } else if (priv
->ports
[port
].phy_is_integrated
) {
421 phylink_set(mask
, 1000baseX_Full
);
422 phylink_set(mask
, 10000baseKR_Full
);
423 phylink_set(mask
, 10000baseSR_Full
);
424 phylink_set(mask
, 10000baseCR_Full
);
426 if (state
->interface
== PHY_INTERFACE_MODE_INTERNAL
) {
427 phylink_set(mask
, 1000baseX_Full
);
428 phylink_set(mask
, 1000baseT_Full
);
429 phylink_set(mask
, 10000baseKR_Full
);
430 phylink_set(mask
, 10000baseT_Full
);
431 phylink_set(mask
, 10000baseSR_Full
);
432 phylink_set(mask
, 10000baseCR_Full
);
435 if (state
->interface
== PHY_INTERFACE_MODE_USXGMII
)
436 phylink_set(mask
, 10000baseT_Full
);
438 phylink_set(mask
, 10baseT_Half
);
439 phylink_set(mask
, 10baseT_Full
);
440 phylink_set(mask
, 100baseT_Half
);
441 phylink_set(mask
, 100baseT_Full
);
443 bitmap_and(supported
, supported
, mask
,
444 __ETHTOOL_LINK_MODE_MASK_NBITS
);
445 bitmap_and(state
->advertising
, state
->advertising
, mask
,
446 __ETHTOOL_LINK_MODE_MASK_NBITS
);
447 pr_debug("%s leaving supported: %*pb", __func__
, __ETHTOOL_LINK_MODE_MASK_NBITS
, supported
);
450 static int rtl83xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
451 struct phylink_link_state
*state
)
453 struct rtl838x_switch_priv
*priv
= ds
->priv
;
457 if (port
< 0 || port
> priv
->cpu_port
)
461 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
462 if (link
& BIT_ULL(port
))
464 pr_debug("%s: link state port %d: %llx\n", __func__
, port
, link
& BIT_ULL(port
));
467 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
470 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
471 speed
>>= (port
% 16) << 1;
472 switch (speed
& 0x3) {
474 state
->speed
= SPEED_10
;
477 state
->speed
= SPEED_100
;
480 state
->speed
= SPEED_1000
;
483 if (priv
->family_id
== RTL9300_FAMILY_ID
484 && (port
== 24 || port
== 26)) /* Internal serdes */
485 state
->speed
= SPEED_2500
;
487 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
490 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
491 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
492 state
->pause
|= MLO_PAUSE_RX
;
493 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
494 state
->pause
|= MLO_PAUSE_TX
;
498 static int rtl93xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
499 struct phylink_link_state
*state
)
501 struct rtl838x_switch_priv
*priv
= ds
->priv
;
506 if (port
< 0 || port
> priv
->cpu_port
)
510 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
511 * state needs to be read twice in order to read a correct result.
512 * This would not be necessary for ports connected e.g. to RTL8218D
516 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
517 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
518 if (link
& BIT_ULL(port
))
521 if (priv
->family_id
== RTL9310_FAMILY_ID
)
522 media
= priv
->r
->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS
);
524 if (priv
->family_id
== RTL9300_FAMILY_ID
)
525 media
= sw_r32(RTL930X_MAC_LINK_MEDIA_STS
);
527 if (media
& BIT_ULL(port
))
530 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__
, port
,
531 link
& BIT_ULL(port
), media
);
534 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
537 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
538 speed
>>= (port
% 8) << 2;
539 switch (speed
& 0xf) {
541 state
->speed
= SPEED_10
;
544 state
->speed
= SPEED_100
;
548 state
->speed
= SPEED_1000
;
551 state
->speed
= SPEED_10000
;
555 state
->speed
= SPEED_2500
;
558 state
->speed
= SPEED_5000
;
561 pr_err("%s: unknown speed: %d\n", __func__
, (u32
)speed
& 0xf);
564 if (priv
->family_id
== RTL9310_FAMILY_ID
565 && (port
>= 52 || port
<= 55)) { /* Internal serdes */
566 state
->speed
= SPEED_10000
;
571 pr_debug("%s: speed is: %d %d\n", __func__
, (u32
)speed
& 0xf, state
->speed
);
572 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
573 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
574 state
->pause
|= MLO_PAUSE_RX
;
575 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
576 state
->pause
|= MLO_PAUSE_TX
;
580 static void rtl83xx_config_interface(int port
, phy_interface_t interface
)
582 u32 old
, int_shift
, sds_shift
;
597 old
= sw_r32(RTL838X_SDS_MODE_SEL
);
599 case PHY_INTERFACE_MODE_1000BASEX
:
600 if ((old
>> sds_shift
& 0x1f) == 4)
602 sw_w32_mask(0x7 << int_shift
, 1 << int_shift
, RTL838X_INT_MODE_CTRL
);
603 sw_w32_mask(0x1f << sds_shift
, 4 << sds_shift
, RTL838X_SDS_MODE_SEL
);
605 case PHY_INTERFACE_MODE_SGMII
:
606 if ((old
>> sds_shift
& 0x1f) == 2)
608 sw_w32_mask(0x7 << int_shift
, 2 << int_shift
, RTL838X_INT_MODE_CTRL
);
609 sw_w32_mask(0x1f << sds_shift
, 2 << sds_shift
, RTL838X_SDS_MODE_SEL
);
614 pr_debug("configured port %d for interface %s\n", port
, phy_modes(interface
));
617 static void rtl83xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
619 const struct phylink_link_state
*state
)
621 struct rtl838x_switch_priv
*priv
= ds
->priv
;
623 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
625 pr_debug("%s port %d, mode %x\n", __func__
, port
, mode
);
627 if (port
== priv
->cpu_port
) {
628 /* Set Speed, duplex, flow control
629 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
630 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
633 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
634 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
635 /* allow CRC errors on CPU-port */
636 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
638 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
643 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
644 /* Auto-Negotiation does not work for MAC in RTL8390 */
645 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
646 if (mode
== MLO_AN_PHY
|| phylink_autoneg_inband(mode
)) {
647 pr_debug("PHY autonegotiates\n");
648 reg
|= RTL838X_NWAY_EN
;
649 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
650 rtl83xx_config_interface(port
, state
->interface
);
655 if (mode
!= MLO_AN_FIXED
)
656 pr_debug("Fixed state.\n");
658 /* Clear id_mode_dis bit, and the existing port mode, let
659 * RGMII_MODE_EN bet set by mac_link_{up,down} */
660 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
661 reg
&= ~(RTL838X_RX_PAUSE_EN
| RTL838X_TX_PAUSE_EN
);
662 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
663 if (state
->pause
& MLO_PAUSE_TX
)
664 reg
|= RTL838X_TX_PAUSE_EN
;
665 reg
|= RTL838X_RX_PAUSE_EN
;
667 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
668 reg
&= ~(RTL839X_RX_PAUSE_EN
| RTL839X_TX_PAUSE_EN
);
669 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
670 if (state
->pause
& MLO_PAUSE_TX
)
671 reg
|= RTL839X_TX_PAUSE_EN
;
672 reg
|= RTL839X_RX_PAUSE_EN
;
677 reg
&= ~(3 << speed_bit
);
678 switch (state
->speed
) {
680 reg
|= 2 << speed_bit
;
683 reg
|= 1 << speed_bit
;
686 break; // Ignore, including 10MBit which has a speed value of 0
689 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
690 reg
&= ~(RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
692 reg
|= RTL838X_FORCE_LINK_EN
;
693 if (state
->duplex
== RTL838X_DUPLEX_MODE
)
694 reg
|= RTL838X_DUPLEX_MODE
;
695 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
696 reg
&= ~(RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
698 reg
|= RTL839X_FORCE_LINK_EN
;
699 if (state
->duplex
== RTL839X_DUPLEX_MODE
)
700 reg
|= RTL839X_DUPLEX_MODE
;
703 // LAG members must use DUPLEX and we need to enable the link
704 if (priv
->lagmembers
& BIT_ULL(port
)) {
705 switch(priv
->family_id
) {
706 case RTL8380_FAMILY_ID
:
707 reg
|= (RTL838X_DUPLEX_MODE
| RTL838X_FORCE_LINK_EN
);
709 case RTL8390_FAMILY_ID
:
710 reg
|= (RTL839X_DUPLEX_MODE
| RTL839X_FORCE_LINK_EN
);
716 if (priv
->family_id
== RTL8380_FAMILY_ID
)
717 reg
&= ~RTL838X_NWAY_EN
;
718 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
721 static void rtl931x_phylink_mac_config(struct dsa_switch
*ds
, int port
,
723 const struct phylink_link_state
*state
)
725 struct rtl838x_switch_priv
*priv
= ds
->priv
;
729 sds_num
= priv
->ports
[port
].sds_num
;
730 pr_info("%s: speed %d sds_num %d\n", __func__
, state
->speed
, sds_num
);
732 switch (state
->interface
) {
733 case PHY_INTERFACE_MODE_HSGMII
:
734 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__
);
735 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
736 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_HSGMII
);
737 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_HSGMII
);
739 case PHY_INTERFACE_MODE_1000BASEX
:
740 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
741 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_1000BASEX
);
743 case PHY_INTERFACE_MODE_XGMII
:
744 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_XGMII
);
745 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_XGMII
);
747 case PHY_INTERFACE_MODE_10GBASER
:
748 case PHY_INTERFACE_MODE_10GKR
:
749 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
750 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
752 case PHY_INTERFACE_MODE_USXGMII
:
753 // Translates to MII_USXGMII_10GSXGMII
754 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
755 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_USXGMII
);
757 case PHY_INTERFACE_MODE_SGMII
:
758 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__
);
759 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_SGMII
);
760 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_SGMII
);
761 band
= rtl931x_sds_cmu_band_set(sds_num
, true, 62, PHY_INTERFACE_MODE_SGMII
);
763 case PHY_INTERFACE_MODE_QSGMII
:
764 band
= rtl931x_sds_cmu_band_get(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
765 rtl931x_sds_init(sds_num
, PHY_INTERFACE_MODE_QSGMII
);
768 pr_err("%s: unknown serdes mode: %s\n",
769 __func__
, phy_modes(state
->interface
));
773 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
774 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__
, reg
);
776 reg
&= ~(RTL931X_DUPLEX_MODE
| RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
);
779 reg
|= 0x2 << 12; // Set SMI speed to 0x2
781 reg
|= RTL931X_TX_PAUSE_EN
| RTL931X_RX_PAUSE_EN
;
783 if (priv
->lagmembers
& BIT_ULL(port
))
784 reg
|= RTL931X_DUPLEX_MODE
;
786 if (state
->duplex
== DUPLEX_FULL
)
787 reg
|= RTL931X_DUPLEX_MODE
;
789 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
793 static void rtl93xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
795 const struct phylink_link_state
*state
)
797 struct rtl838x_switch_priv
*priv
= ds
->priv
;
798 int sds_num
, sds_mode
;
801 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__
,
802 port
, mode
, phy_modes(state
->interface
), state
->speed
, state
->link
);
804 // Nothing to be done for the CPU-port
805 if (port
== priv
->cpu_port
)
808 if (priv
->family_id
== RTL9310_FAMILY_ID
)
809 return rtl931x_phylink_mac_config(ds
, port
, mode
, state
);
811 sds_num
= priv
->ports
[port
].sds_num
;
812 pr_info("%s SDS is %d\n", __func__
, sds_num
);
814 switch (state
->interface
) {
815 case PHY_INTERFACE_MODE_HSGMII
:
818 case PHY_INTERFACE_MODE_1000BASEX
:
821 case PHY_INTERFACE_MODE_XGMII
:
824 case PHY_INTERFACE_MODE_10GBASER
:
825 case PHY_INTERFACE_MODE_10GKR
:
826 sds_mode
= 0x1b; // 10G 1000X Auto
828 case PHY_INTERFACE_MODE_USXGMII
:
832 pr_err("%s: unknown serdes mode: %s\n",
833 __func__
, phy_modes(state
->interface
));
836 if (state
->interface
== PHY_INTERFACE_MODE_10GBASER
)
837 rtl9300_serdes_setup(sds_num
, state
->interface
);
840 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
843 switch (state
->speed
) {
862 reg
|= RTL930X_FORCE_LINK_EN
;
864 if (priv
->lagmembers
& BIT_ULL(port
))
865 reg
|= RTL930X_DUPLEX_MODE
| RTL930X_FORCE_LINK_EN
;
867 if (state
->duplex
== DUPLEX_FULL
)
868 reg
|= RTL930X_DUPLEX_MODE
;
870 if (priv
->ports
[port
].phy_is_integrated
)
871 reg
&= ~RTL930X_FORCE_EN
; // Clear MAC_FORCE_EN to allow SDS-MAC link
873 reg
|= RTL930X_FORCE_EN
;
875 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
878 static void rtl83xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
880 phy_interface_t interface
)
882 struct rtl838x_switch_priv
*priv
= ds
->priv
;
884 /* Stop TX/RX to port */
885 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
887 // No longer force link
888 sw_w32_mask(0x3, 0, priv
->r
->mac_force_mode_ctrl(port
));
891 static void rtl93xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
893 phy_interface_t interface
)
895 struct rtl838x_switch_priv
*priv
= ds
->priv
;
898 /* Stop TX/RX to port */
899 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
901 // No longer force link
902 if (priv
->family_id
== RTL9300_FAMILY_ID
)
903 v
= RTL930X_FORCE_EN
| RTL930X_FORCE_LINK_EN
;
904 else if (priv
->family_id
== RTL9310_FAMILY_ID
)
905 v
= RTL931X_FORCE_EN
| RTL931X_FORCE_LINK_EN
;
906 sw_w32_mask(v
, 0, priv
->r
->mac_force_mode_ctrl(port
));
909 static void rtl83xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
911 phy_interface_t interface
,
912 struct phy_device
*phydev
,
913 int speed
, int duplex
,
914 bool tx_pause
, bool rx_pause
)
916 struct rtl838x_switch_priv
*priv
= ds
->priv
;
917 /* Restart TX/RX to port */
918 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
919 // TODO: Set speed/duplex/pauses
922 static void rtl93xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
924 phy_interface_t interface
,
925 struct phy_device
*phydev
,
926 int speed
, int duplex
,
927 bool tx_pause
, bool rx_pause
)
929 struct rtl838x_switch_priv
*priv
= ds
->priv
;
931 /* Restart TX/RX to port */
932 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
933 // TODO: Set speed/duplex/pauses
936 static void rtl83xx_get_strings(struct dsa_switch
*ds
,
937 int port
, u32 stringset
, u8
*data
)
941 if (stringset
!= ETH_SS_STATS
)
944 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++)
945 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl83xx_mib
[i
].name
,
949 static void rtl83xx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
952 struct rtl838x_switch_priv
*priv
= ds
->priv
;
953 const struct rtl83xx_mib_desc
*mib
;
957 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++) {
958 mib
= &rtl83xx_mib
[i
];
960 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 252 - mib
->offset
);
961 if (mib
->size
== 2) {
962 h
= sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 248 - mib
->offset
);
968 static int rtl83xx_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
970 if (sset
!= ETH_SS_STATS
)
973 return ARRAY_SIZE(rtl83xx_mib
);
976 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv
*priv
, int port
)
978 int mc_group
= find_first_zero_bit(priv
->mc_group_bm
, MAX_MC_GROUPS
- 1);
981 if (mc_group
>= MAX_MC_GROUPS
- 1)
984 if (priv
->is_lagmember
[port
]) {
985 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
989 set_bit(mc_group
, priv
->mc_group_bm
);
990 mc_group
++; // We cannot use group 0, as this is used for lookup miss flooding
991 portmask
= BIT_ULL(port
) | BIT_ULL(priv
->cpu_port
);
992 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
997 static u64
rtl83xx_mc_group_add_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
999 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
1001 pr_debug("%s: %d\n", __func__
, port
);
1002 if (priv
->is_lagmember
[port
]) {
1003 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1006 portmask
|= BIT_ULL(port
);
1007 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1012 static u64
rtl83xx_mc_group_del_port(struct rtl838x_switch_priv
*priv
, int mc_group
, int port
)
1014 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
1016 pr_debug("%s: %d\n", __func__
, port
);
1017 if (priv
->is_lagmember
[port
]) {
1018 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1021 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1022 if (portmask
== BIT_ULL(priv
->cpu_port
)) {
1023 portmask
&= ~BIT_ULL(priv
->cpu_port
);
1024 priv
->r
->write_mcast_pmask(mc_group
, portmask
);
1025 clear_bit(mc_group
, priv
->mc_group_bm
);
1031 static void store_mcgroups(struct rtl838x_switch_priv
*priv
, int port
)
1035 for (mc_group
= 0; mc_group
< MAX_MC_GROUPS
; mc_group
++) {
1036 u64 portmask
= priv
->r
->read_mcast_pmask(mc_group
);
1037 if (portmask
& BIT_ULL(port
)) {
1038 priv
->mc_group_saves
[mc_group
] = port
;
1039 rtl83xx_mc_group_del_port(priv
, mc_group
, port
);
1044 static void load_mcgroups(struct rtl838x_switch_priv
*priv
, int port
)
1048 for (mc_group
= 0; mc_group
< MAX_MC_GROUPS
; mc_group
++) {
1049 if (priv
->mc_group_saves
[mc_group
] == port
) {
1050 rtl83xx_mc_group_add_port(priv
, mc_group
, port
);
1051 priv
->mc_group_saves
[mc_group
] = -1;
1056 static int rtl83xx_port_enable(struct dsa_switch
*ds
, int port
,
1057 struct phy_device
*phydev
)
1059 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1062 pr_debug("%s: %x %d", __func__
, (u32
) priv
, port
);
1063 priv
->ports
[port
].enable
= true;
1065 /* enable inner tagging on egress, do not keep any tags */
1066 priv
->r
->vlan_port_keep_tag_set(port
, 0, 1);
1068 if (dsa_is_cpu_port(ds
, port
))
1071 /* add port to switch mask of CPU_PORT */
1072 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1074 load_mcgroups(priv
, port
);
1076 if (priv
->is_lagmember
[port
]) {
1077 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1081 /* add all other ports in the same bridge to switch mask of port */
1082 v
= priv
->r
->traffic_get(port
);
1083 v
|= priv
->ports
[port
].pm
;
1084 priv
->r
->traffic_set(port
, v
);
1086 // TODO: Figure out if this is necessary
1087 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
1088 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_SABLK_CTRL
);
1089 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_DABLK_CTRL
);
1092 if (priv
->ports
[port
].sds_num
< 0)
1093 priv
->ports
[port
].sds_num
= rtl93xx_get_sds(phydev
);
1098 static void rtl83xx_port_disable(struct dsa_switch
*ds
, int port
)
1100 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1103 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1104 /* you can only disable user ports */
1105 if (!dsa_is_user_port(ds
, port
))
1108 // BUG: This does not work on RTL931X
1109 /* remove port from switch mask of CPU_PORT */
1110 priv
->r
->traffic_disable(priv
->cpu_port
, port
);
1111 store_mcgroups(priv
, port
);
1113 /* remove all other ports in the same bridge from switch mask of port */
1114 v
= priv
->r
->traffic_get(port
);
1115 v
&= ~priv
->ports
[port
].pm
;
1116 priv
->r
->traffic_set(port
, v
);
1118 priv
->ports
[port
].enable
= false;
1121 static int rtl83xx_set_mac_eee(struct dsa_switch
*ds
, int port
,
1122 struct ethtool_eee
*e
)
1124 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1126 if (e
->eee_enabled
&& !priv
->eee_enabled
) {
1127 pr_info("Globally enabling EEE\n");
1128 priv
->r
->init_eee(priv
, true);
1131 priv
->r
->port_eee_set(priv
, port
, e
->eee_enabled
);
1134 pr_info("Enabled EEE for port %d\n", port
);
1136 pr_info("Disabled EEE for port %d\n", port
);
1140 static int rtl83xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1141 struct ethtool_eee
*e
)
1143 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1145 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
1147 priv
->r
->eee_port_ability(priv
, e
, port
);
1149 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1151 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1156 static int rtl93xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
1157 struct ethtool_eee
*e
)
1159 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1161 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
1162 | SUPPORTED_2500baseX_Full
;
1164 priv
->r
->eee_port_ability(priv
, e
, port
);
1166 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
1168 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
1173 static int rtl83xx_set_ageing_time(struct dsa_switch
*ds
, unsigned int msec
)
1175 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1177 priv
->r
->set_ageing_time(msec
);
1181 static int rtl83xx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1182 struct net_device
*bridge
)
1184 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1185 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
), v
;
1188 pr_debug("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
1190 if (priv
->is_lagmember
[port
]) {
1191 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1195 mutex_lock(&priv
->reg_mutex
);
1196 for (i
= 0; i
< ds
->num_ports
; i
++) {
1197 /* Add this port to the port matrix of the other ports in the
1198 * same bridge. If the port is disabled, port matrix is kept
1199 * and not being setup until the port becomes enabled.
1201 if (dsa_is_user_port(ds
, i
) && !priv
->is_lagmember
[i
] && i
!= port
) {
1202 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1204 if (priv
->ports
[i
].enable
)
1205 priv
->r
->traffic_enable(i
, port
);
1207 priv
->ports
[i
].pm
|= BIT_ULL(port
);
1208 port_bitmap
|= BIT_ULL(i
);
1211 load_mcgroups(priv
, port
);
1213 /* Add all other ports to this port matrix. */
1214 if (priv
->ports
[port
].enable
) {
1215 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
1216 v
= priv
->r
->traffic_get(port
);
1218 priv
->r
->traffic_set(port
, v
);
1220 priv
->ports
[port
].pm
|= port_bitmap
;
1221 mutex_unlock(&priv
->reg_mutex
);
1226 static void rtl83xx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1227 struct net_device
*bridge
)
1229 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1230 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
), v
;
1233 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
1234 mutex_lock(&priv
->reg_mutex
);
1235 for (i
= 0; i
< ds
->num_ports
; i
++) {
1236 /* Remove this port from the port matrix of the other ports
1237 * in the same bridge. If the port is disabled, port matrix
1238 * is kept and not being setup until the port becomes enabled.
1239 * And the other port's port matrix cannot be broken when the
1240 * other port is still a VLAN-aware port.
1242 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
1243 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
1245 if (priv
->ports
[i
].enable
)
1246 priv
->r
->traffic_disable(i
, port
);
1248 priv
->ports
[i
].pm
|= BIT_ULL(port
);
1249 port_bitmap
&= ~BIT_ULL(i
);
1252 store_mcgroups(priv
, port
);
1254 /* Add all other ports to this port matrix. */
1255 if (priv
->ports
[port
].enable
) {
1256 v
= priv
->r
->traffic_get(port
);
1258 priv
->r
->traffic_set(port
, v
);
1260 priv
->ports
[port
].pm
&= ~port_bitmap
;
1262 mutex_unlock(&priv
->reg_mutex
);
1265 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1271 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1272 int n
= priv
->port_width
<< 1;
1274 /* Ports above or equal CPU port can never be configured */
1275 if (port
>= priv
->cpu_port
)
1278 mutex_lock(&priv
->reg_mutex
);
1280 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1281 * have 64 bit fields, 839x and 931x have 128 bit fields
1283 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1285 if (priv
->family_id
== RTL9300_FAMILY_ID
)
1287 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1290 index
= n
- (pos
>> 4) - 1;
1291 bit
= (pos
<< 1) % 32;
1293 priv
->r
->stp_get(priv
, msti
, port_state
);
1295 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
1296 port_state
[index
] &= ~(3 << bit
);
1299 case BR_STATE_DISABLED
: /* 0 */
1300 port_state
[index
] |= (0 << bit
);
1302 case BR_STATE_BLOCKING
: /* 4 */
1303 case BR_STATE_LISTENING
: /* 1 */
1304 port_state
[index
] |= (1 << bit
);
1306 case BR_STATE_LEARNING
: /* 2 */
1307 port_state
[index
] |= (2 << bit
);
1309 case BR_STATE_FORWARDING
: /* 3*/
1310 port_state
[index
] |= (3 << bit
);
1315 priv
->r
->stp_set(priv
, msti
, port_state
);
1317 mutex_unlock(&priv
->reg_mutex
);
1320 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
)
1322 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1323 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
1325 pr_debug("FAST AGE port %d\n", port
);
1326 mutex_lock(&priv
->reg_mutex
);
1327 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1329 * 0-4: Replacing port
1330 * 5-9: Flushed/replaced port
1332 * 22: Entry types: 1: dynamic, 0: also static
1333 * 23: Match flush port
1335 * 25: Flush (0) or replace (1) L2 entries
1336 * 26: Status of action (1: Start, 0: Done)
1338 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
1340 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(26 + s
));
1342 mutex_unlock(&priv
->reg_mutex
);
1345 void rtl931x_fast_age(struct dsa_switch
*ds
, int port
)
1347 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1349 pr_info("%s port %d\n", __func__
, port
);
1350 mutex_lock(&priv
->reg_mutex
);
1351 sw_w32(port
<< 11, RTL931X_L2_TBL_FLUSH_CTRL
+ 4);
1353 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL
);
1355 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL
) & BIT (28));
1357 mutex_unlock(&priv
->reg_mutex
);
1360 void rtl930x_fast_age(struct dsa_switch
*ds
, int port
)
1362 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1364 if (priv
->family_id
== RTL9310_FAMILY_ID
)
1365 return rtl931x_fast_age(ds
, port
);
1367 pr_debug("FAST AGE port %d\n", port
);
1368 mutex_lock(&priv
->reg_mutex
);
1369 sw_w32(port
<< 11, RTL930X_L2_TBL_FLUSH_CTRL
+ 4);
1371 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL
);
1373 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(30));
1375 mutex_unlock(&priv
->reg_mutex
);
1378 static int rtl83xx_vlan_filtering(struct dsa_switch
*ds
, int port
,
1379 bool vlan_filtering
,
1380 struct netlink_ext_ack
*extack
)
1382 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1384 pr_debug("%s: port %d\n", __func__
, port
);
1385 mutex_lock(&priv
->reg_mutex
);
1387 if (vlan_filtering
) {
1388 /* Enable ingress and egress filtering
1389 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1390 * the filter action:
1393 * 2: Trap packet to CPU port
1394 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1396 if (port
!= priv
->cpu_port
)
1397 priv
->r
->set_vlan_igr_filter(port
, IGR_DROP
);
1399 priv
->r
->set_vlan_egr_filter(port
, EGR_ENABLE
);
1401 /* Disable ingress and egress filtering */
1402 if (port
!= priv
->cpu_port
)
1403 priv
->r
->set_vlan_igr_filter(port
, IGR_FORWARD
);
1405 priv
->r
->set_vlan_egr_filter(port
, EGR_DISABLE
);
1408 /* Do we need to do something to the CPU-Port, too? */
1409 mutex_unlock(&priv
->reg_mutex
);
1414 static int rtl83xx_vlan_prepare(struct dsa_switch
*ds
, int port
,
1415 const struct switchdev_obj_port_vlan
*vlan
)
1417 struct rtl838x_vlan_info info
;
1418 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1420 priv
->r
->vlan_tables_read(0, &info
);
1422 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1423 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1424 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1426 priv
->r
->vlan_tables_read(1, &info
);
1427 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1428 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1429 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
1430 priv
->r
->vlan_set_untagged(1, info
.untagged_ports
);
1431 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info
.untagged_ports
);
1433 priv
->r
->vlan_set_tagged(1, &info
);
1434 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info
.tagged_ports
);
1439 static int rtl83xx_vlan_add(struct dsa_switch
*ds
, int port
,
1440 const struct switchdev_obj_port_vlan
*vlan
,
1441 struct netlink_ext_ack
*extack
)
1443 struct rtl838x_vlan_info info
;
1444 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1447 pr_debug("%s port %d, vid %d, flags %x\n",
1448 __func__
, port
, vlan
->vid
, vlan
->flags
);
1450 if (vlan
->vid
> 4095) {
1451 dev_err(priv
->dev
, "VLAN out of range: %d", vlan
->vid
);
1455 err
= rtl83xx_vlan_prepare(ds
, port
, vlan
);
1459 mutex_lock(&priv
->reg_mutex
);
1461 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
&& vlan
->vid
) {
1462 /* Set both inner and outer PVID of the port */
1463 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_INNER
, vlan
->vid
);
1464 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_OUTER
, vlan
->vid
);
1465 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_INNER
,
1466 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1467 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_OUTER
,
1468 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1470 priv
->ports
[port
].pvid
= vlan
->vid
;
1473 /* Get port memberships of this vlan */
1474 priv
->r
->vlan_tables_read(vlan
->vid
, &info
);
1477 if (!info
.tagged_ports
) {
1479 info
.hash_mc_fid
= false;
1480 info
.hash_uc_fid
= false;
1481 info
.profile_id
= 0;
1484 /* sanitize untagged_ports - must be a subset */
1485 if (info
.untagged_ports
& ~info
.tagged_ports
)
1486 info
.untagged_ports
= 0;
1488 info
.tagged_ports
|= BIT_ULL(port
);
1489 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
1490 info
.untagged_ports
|= BIT_ULL(port
);
1492 priv
->r
->vlan_set_untagged(vlan
->vid
, info
.untagged_ports
);
1493 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.untagged_ports
);
1495 priv
->r
->vlan_set_tagged(vlan
->vid
, &info
);
1496 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.tagged_ports
);
1498 mutex_unlock(&priv
->reg_mutex
);
1503 static int rtl83xx_vlan_del(struct dsa_switch
*ds
, int port
,
1504 const struct switchdev_obj_port_vlan
*vlan
)
1506 struct rtl838x_vlan_info info
;
1507 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1510 pr_debug("%s: port %d, vid %d, flags %x\n",
1511 __func__
, port
, vlan
->vid
, vlan
->flags
);
1513 if (vlan
->vid
> 4095) {
1514 dev_err(priv
->dev
, "VLAN out of range: %d", vlan
->vid
);
1518 mutex_lock(&priv
->reg_mutex
);
1519 pvid
= priv
->ports
[port
].pvid
;
1521 /* Reset to default if removing the current PVID */
1522 if (vlan
->vid
== pvid
) {
1523 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_INNER
, 0);
1524 priv
->r
->vlan_port_pvid_set(port
, PBVLAN_TYPE_OUTER
, 0);
1525 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_INNER
,
1526 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1527 priv
->r
->vlan_port_pvidmode_set(port
, PBVLAN_TYPE_OUTER
,
1528 PBVLAN_MODE_UNTAG_AND_PRITAG
);
1530 /* Get port memberships of this vlan */
1531 priv
->r
->vlan_tables_read(vlan
->vid
, &info
);
1533 /* remove port from both tables */
1534 info
.untagged_ports
&= (~BIT_ULL(port
));
1535 info
.tagged_ports
&= (~BIT_ULL(port
));
1537 priv
->r
->vlan_set_untagged(vlan
->vid
, info
.untagged_ports
);
1538 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.untagged_ports
);
1540 priv
->r
->vlan_set_tagged(vlan
->vid
, &info
);
1541 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan
->vid
, info
.tagged_ports
);
1543 mutex_unlock(&priv
->reg_mutex
);
1548 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry
*e
, int port
, int vid
, u64 mac
)
1550 memset(e
, 0, sizeof(*e
));
1552 e
->type
= L2_UNICAST
;
1556 e
->is_static
= true;
1560 e
->rvid
= e
->vid
= vid
;
1561 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1562 u64_to_ether_addr(mac
, e
->mac
);
1565 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry
*e
, int vid
, u64 mac
, int mc_group
)
1567 memset(e
, 0, sizeof(*e
));
1569 e
->type
= L2_MULTICAST
;
1572 e
->mc_portmask_index
= mc_group
;
1574 e
->rvid
= e
->vid
= vid
;
1575 e
->is_ip_mc
= e
->is_ipv6_mc
= false;
1576 u64_to_ether_addr(mac
, e
->mac
);
1580 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1581 * over the entries in the bucket until either a matching entry is found or an empty slot
1582 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1583 * when an empty slot was found and must exist is false, the index of the slot is returned
1584 * when no slots are available returns -1
1586 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1587 bool must_exist
, struct rtl838x_l2_entry
*e
)
1590 u32 key
= priv
->r
->l2_hash_key(priv
, seed
);
1593 pr_debug("%s: using key %x, for seed %016llx\n", __func__
, key
, seed
);
1594 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1595 for (i
= 0; i
< priv
->l2_bucket_size
; i
++) {
1596 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, e
);
1597 pr_debug("valid %d, mac %016llx\n", e
->valid
, ether_addr_to_u64(&e
->mac
[0]));
1598 if (must_exist
&& !e
->valid
)
1600 if (!e
->valid
|| ((entry
& 0x0fffffffffffffffULL
) == seed
)) {
1601 idx
= i
> 3 ? ((key
>> 14) & 0xffff) | i
>> 1 : ((key
<< 2) | i
) & 0xffff;
1610 * Uses the seed to identify an entry in the CAM by looping over all its entries
1611 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1612 * when an empty slot was found the index of the slot is returned
1613 * when no slots are available returns -1
1615 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv
*priv
, u64 seed
,
1616 bool must_exist
, struct rtl838x_l2_entry
*e
)
1621 for (i
= 0; i
< 64; i
++) {
1622 entry
= priv
->r
->read_cam(i
, e
);
1623 if (!must_exist
&& !e
->valid
) {
1624 if (idx
< 0) /* First empty entry? */
1627 } else if ((entry
& 0x0fffffffffffffffULL
) == seed
) {
1628 pr_debug("Found entry in CAM\n");
1636 static int rtl83xx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1637 const unsigned char *addr
, u16 vid
)
1639 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1640 u64 mac
= ether_addr_to_u64(addr
);
1641 struct rtl838x_l2_entry e
;
1643 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1645 if (priv
->is_lagmember
[port
]) {
1646 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1650 mutex_lock(&priv
->reg_mutex
);
1652 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1654 // Found an existing or empty entry
1656 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1657 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1661 // Hash buckets full, try CAM
1662 rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1665 rtl83xx_setup_l2_uc_entry(&e
, port
, vid
, mac
);
1666 priv
->r
->write_cam(idx
, &e
);
1672 mutex_unlock(&priv
->reg_mutex
);
1676 static int rtl83xx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1677 const unsigned char *addr
, u16 vid
)
1679 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1680 u64 mac
= ether_addr_to_u64(addr
);
1681 struct rtl838x_l2_entry e
;
1683 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1685 pr_debug("In %s, mac %llx, vid: %d\n", __func__
, mac
, vid
);
1686 mutex_lock(&priv
->reg_mutex
);
1688 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1691 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1693 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1697 /* Check CAM for spillover from hash buckets */
1698 rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1702 priv
->r
->write_cam(idx
, &e
);
1707 mutex_unlock(&priv
->reg_mutex
);
1711 static int rtl83xx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1712 dsa_fdb_dump_cb_t
*cb
, void *data
)
1714 struct rtl838x_l2_entry e
;
1715 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1718 mutex_lock(&priv
->reg_mutex
);
1720 for (i
= 0; i
< priv
->fib_entries
; i
++) {
1721 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1726 if (e
.port
== port
|| e
.port
== RTL930X_PORT_IGNORE
)
1727 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1730 for (i
= 0; i
< 64; i
++) {
1731 priv
->r
->read_cam(i
, &e
);
1737 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1740 mutex_unlock(&priv
->reg_mutex
);
1744 static int rtl83xx_port_mdb_add(struct dsa_switch
*ds
, int port
,
1745 const struct switchdev_obj_port_mdb
*mdb
)
1747 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1748 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1749 struct rtl838x_l2_entry e
;
1752 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1755 if (priv
->id
>= 0x9300)
1758 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1760 if (priv
->is_lagmember
[port
]) {
1761 pr_debug("%s: %d is lag slave. ignore\n", __func__
, port
);
1765 mutex_lock(&priv
->reg_mutex
);
1767 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, false, &e
);
1769 // Found an existing or empty entry
1772 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1773 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1774 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1776 pr_debug("New entry for seed %016llx\n", seed
);
1777 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1782 rtl83xx_setup_l2_mc_entry(&e
, vid
, mac
, mc_group
);
1783 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1788 // Hash buckets full, try CAM
1789 rtl83xx_find_l2_cam_entry(priv
, seed
, false, &e
);
1793 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1794 ether_addr_to_u64(e
.mac
), e
.mc_portmask_index
);
1795 rtl83xx_mc_group_add_port(priv
, e
.mc_portmask_index
, port
);
1797 pr_debug("New entry\n");
1798 mc_group
= rtl83xx_mc_group_alloc(priv
, port
);
1803 rtl83xx_setup_l2_mc_entry(&e
, vid
, mac
, mc_group
);
1804 priv
->r
->write_cam(idx
, &e
);
1811 mutex_unlock(&priv
->reg_mutex
);
1813 dev_err(ds
->dev
, "failed to add MDB entry\n");
1818 int rtl83xx_port_mdb_del(struct dsa_switch
*ds
, int port
,
1819 const struct switchdev_obj_port_mdb
*mdb
)
1821 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1822 u64 mac
= ether_addr_to_u64(mdb
->addr
);
1823 struct rtl838x_l2_entry e
;
1826 u64 seed
= priv
->r
->l2_hash_seed(mac
, vid
);
1829 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__
, port
, mac
, vid
);
1831 if (priv
->is_lagmember
[port
]) {
1832 pr_info("%s: %d is lag slave. ignore\n", __func__
, port
);
1836 mutex_lock(&priv
->reg_mutex
);
1838 idx
= rtl83xx_find_l2_hash_entry(priv
, seed
, true, &e
);
1841 pr_debug("Found entry index %d, key %d and bucket %d\n", idx
, idx
>> 2, idx
& 3);
1842 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1845 priv
->r
->write_l2_entry_using_hash(idx
>> 2, idx
& 0x3, &e
);
1850 /* Check CAM for spillover from hash buckets */
1851 rtl83xx_find_l2_cam_entry(priv
, seed
, true, &e
);
1854 portmask
= rtl83xx_mc_group_del_port(priv
, e
.mc_portmask_index
, port
);
1857 priv
->r
->write_cam(idx
, &e
);
1861 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1863 mutex_unlock(&priv
->reg_mutex
);
1867 static int rtl83xx_port_mirror_add(struct dsa_switch
*ds
, int port
,
1868 struct dsa_mall_mirror_tc_entry
*mirror
,
1871 /* We support 4 mirror groups, one destination port per group */
1873 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1874 int ctrl_reg
, dpm_reg
, spm_reg
;
1876 pr_debug("In %s\n", __func__
);
1878 for (group
= 0; group
< 4; group
++) {
1879 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1883 for (group
= 0; group
< 4; group
++) {
1884 if (priv
->mirror_group_ports
[group
] < 0)
1892 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1893 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1894 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1896 pr_debug("Using group %d\n", group
);
1897 mutex_lock(&priv
->reg_mutex
);
1899 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1900 /* Enable mirroring to port across VLANs (bit 11) */
1901 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1903 /* Enable mirroring to destination port */
1904 sw_w32((mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1907 if (ingress
&& (priv
->r
->get_port_reg_be(spm_reg
) & (1ULL << port
))) {
1908 mutex_unlock(&priv
->reg_mutex
);
1911 if ((!ingress
) && (priv
->r
->get_port_reg_be(dpm_reg
) & (1ULL << port
))) {
1912 mutex_unlock(&priv
->reg_mutex
);
1917 priv
->r
->mask_port_reg_be(0, 1ULL << port
, spm_reg
);
1919 priv
->r
->mask_port_reg_be(0, 1ULL << port
, dpm_reg
);
1921 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1922 mutex_unlock(&priv
->reg_mutex
);
1926 static void rtl83xx_port_mirror_del(struct dsa_switch
*ds
, int port
,
1927 struct dsa_mall_mirror_tc_entry
*mirror
)
1930 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1931 int ctrl_reg
, dpm_reg
, spm_reg
;
1933 pr_debug("In %s\n", __func__
);
1934 for (group
= 0; group
< 4; group
++) {
1935 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1941 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1942 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1943 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1945 mutex_lock(&priv
->reg_mutex
);
1946 if (mirror
->ingress
) {
1947 /* Ingress, clear source port matrix */
1948 priv
->r
->mask_port_reg_be(1ULL << port
, 0, spm_reg
);
1950 /* Egress, clear destination port matrix */
1951 priv
->r
->mask_port_reg_be(1ULL << port
, 0, dpm_reg
);
1954 if (!(sw_r32(spm_reg
) || sw_r32(dpm_reg
))) {
1955 priv
->mirror_group_ports
[group
] = -1;
1956 sw_w32(0, ctrl_reg
);
1959 mutex_unlock(&priv
->reg_mutex
);
1962 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch
*ds
, int port
, struct switchdev_brport_flags flags
, struct netlink_ext_ack
*extack
)
1964 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1965 unsigned long features
= 0;
1966 pr_debug("%s: %d %lX\n", __func__
, port
, flags
.val
);
1967 if (priv
->r
->enable_learning
)
1968 features
|= BR_LEARNING
;
1969 if (priv
->r
->enable_flood
)
1970 features
|= BR_FLOOD
;
1971 if (priv
->r
->enable_mcast_flood
)
1972 features
|= BR_MCAST_FLOOD
;
1973 if (priv
->r
->enable_bcast_flood
)
1974 features
|= BR_BCAST_FLOOD
;
1975 if (flags
.mask
& ~(features
))
1981 static int rtl83xx_port_bridge_flags(struct dsa_switch
*ds
, int port
, struct switchdev_brport_flags flags
, struct netlink_ext_ack
*extack
)
1983 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1985 pr_debug("%s: %d %lX\n", __func__
, port
, flags
.val
);
1986 if (priv
->r
->enable_learning
&& (flags
.mask
& BR_LEARNING
))
1987 priv
->r
->enable_learning(port
, !!(flags
.val
& BR_LEARNING
));
1989 if (priv
->r
->enable_flood
&& (flags
.mask
& BR_FLOOD
))
1990 priv
->r
->enable_flood(port
, !!(flags
.val
& BR_FLOOD
));
1992 if (priv
->r
->enable_mcast_flood
&& (flags
.mask
& BR_MCAST_FLOOD
))
1993 priv
->r
->enable_mcast_flood(port
, !!(flags
.val
& BR_MCAST_FLOOD
));
1995 if (priv
->r
->enable_bcast_flood
&& (flags
.mask
& BR_BCAST_FLOOD
))
1996 priv
->r
->enable_bcast_flood(port
, !!(flags
.val
& BR_BCAST_FLOOD
));
2001 static bool rtl83xx_lag_can_offload(struct dsa_switch
*ds
,
2002 struct net_device
*lag
,
2003 struct netdev_lag_upper_info
*info
)
2007 id
= dsa_lag_id(ds
->dst
, lag
);
2008 if (id
< 0 || id
>= ds
->num_lag_ids
)
2011 if (info
->tx_type
!= NETDEV_LAG_TX_TYPE_HASH
) {
2014 if (info
->hash_type
!= NETDEV_LAG_HASH_L2
&& info
->hash_type
!= NETDEV_LAG_HASH_L23
)
2020 static int rtl83xx_port_lag_change(struct dsa_switch
*ds
, int port
)
2022 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2024 pr_debug("%s: %d\n", __func__
, port
);
2025 // Nothing to be done...
2030 static int rtl83xx_port_lag_join(struct dsa_switch
*ds
, int port
,
2031 struct net_device
*lag
,
2032 struct netdev_lag_upper_info
*info
)
2034 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2037 if (!rtl83xx_lag_can_offload(ds
, lag
, info
))
2040 mutex_lock(&priv
->reg_mutex
);
2042 for (i
= 0; i
< priv
->n_lags
; i
++) {
2043 if ((!priv
->lag_devs
[i
]) || (priv
->lag_devs
[i
] == lag
))
2046 if (port
>= priv
->cpu_port
) {
2050 pr_info("port_lag_join: group %d, port %d\n",i
, port
);
2051 if (!priv
->lag_devs
[i
])
2052 priv
->lag_devs
[i
] = lag
;
2054 if (priv
->lag_primary
[i
]==-1) {
2055 priv
->lag_primary
[i
]=port
;
2057 priv
->is_lagmember
[port
] = 1;
2059 priv
->lagmembers
|= (1ULL << port
);
2061 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2062 err
= rtl83xx_lag_add(priv
->ds
, i
, port
, info
);
2069 mutex_unlock(&priv
->reg_mutex
);
2074 static int rtl83xx_port_lag_leave(struct dsa_switch
*ds
, int port
,
2075 struct net_device
*lag
)
2077 int i
, group
= -1, err
;
2078 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2080 mutex_lock(&priv
->reg_mutex
);
2081 for (i
=0;i
<priv
->n_lags
;i
++) {
2082 if (priv
->lags_port_members
[i
] & BIT_ULL(port
)) {
2089 pr_info("port_lag_leave: port %d is not a member\n", port
);
2094 if (port
>= priv
->cpu_port
) {
2098 pr_info("port_lag_del: group %d, port %d\n",group
, port
);
2099 priv
->lagmembers
&=~ (1ULL << port
);
2100 priv
->lag_primary
[i
] = -1;
2101 priv
->is_lagmember
[port
] = 0;
2102 pr_debug("lag_members = %llX\n", priv
->lagmembers
);
2103 err
= rtl83xx_lag_del(priv
->ds
, group
, port
);
2108 if (!priv
->lags_port_members
[i
])
2109 priv
->lag_devs
[i
] = NULL
;
2112 mutex_unlock(&priv
->reg_mutex
);
2116 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
2120 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2122 if (phy_addr
>= 24 && phy_addr
<= 27
2123 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
2126 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
2130 read_phy(phy_addr
, 0, phy_reg
, &val
);
2134 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
2137 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2139 if (phy_addr
>= 24 && phy_addr
<= 27
2140 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
2143 sw_w32(val
, RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2));
2146 return write_phy(phy_addr
, 0, phy_reg
, val
);
2149 const struct dsa_switch_ops rtl83xx_switch_ops
= {
2150 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2151 .setup
= rtl83xx_setup
,
2153 .phy_read
= dsa_phy_read
,
2154 .phy_write
= dsa_phy_write
,
2156 .phylink_validate
= rtl83xx_phylink_validate
,
2157 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
2158 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
2159 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
2160 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
2162 .get_strings
= rtl83xx_get_strings
,
2163 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2164 .get_sset_count
= rtl83xx_get_sset_count
,
2166 .port_enable
= rtl83xx_port_enable
,
2167 .port_disable
= rtl83xx_port_disable
,
2169 .get_mac_eee
= rtl83xx_get_mac_eee
,
2170 .set_mac_eee
= rtl83xx_set_mac_eee
,
2172 .set_ageing_time
= rtl83xx_set_ageing_time
,
2173 .port_bridge_join
= rtl83xx_port_bridge_join
,
2174 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2175 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2176 .port_fast_age
= rtl83xx_fast_age
,
2178 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2179 .port_vlan_add
= rtl83xx_vlan_add
,
2180 .port_vlan_del
= rtl83xx_vlan_del
,
2182 .port_fdb_add
= rtl83xx_port_fdb_add
,
2183 .port_fdb_del
= rtl83xx_port_fdb_del
,
2184 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2186 .port_mdb_add
= rtl83xx_port_mdb_add
,
2187 .port_mdb_del
= rtl83xx_port_mdb_del
,
2189 .port_mirror_add
= rtl83xx_port_mirror_add
,
2190 .port_mirror_del
= rtl83xx_port_mirror_del
,
2192 .port_lag_change
= rtl83xx_port_lag_change
,
2193 .port_lag_join
= rtl83xx_port_lag_join
,
2194 .port_lag_leave
= rtl83xx_port_lag_leave
,
2196 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2197 .port_bridge_flags
= rtl83xx_port_bridge_flags
,
2200 const struct dsa_switch_ops rtl930x_switch_ops
= {
2201 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
2202 .setup
= rtl93xx_setup
,
2204 .phy_read
= dsa_phy_read
,
2205 .phy_write
= dsa_phy_write
,
2207 .phylink_validate
= rtl93xx_phylink_validate
,
2208 .phylink_mac_link_state
= rtl93xx_phylink_mac_link_state
,
2209 .phylink_mac_config
= rtl93xx_phylink_mac_config
,
2210 .phylink_mac_link_down
= rtl93xx_phylink_mac_link_down
,
2211 .phylink_mac_link_up
= rtl93xx_phylink_mac_link_up
,
2213 .get_strings
= rtl83xx_get_strings
,
2214 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
2215 .get_sset_count
= rtl83xx_get_sset_count
,
2217 .port_enable
= rtl83xx_port_enable
,
2218 .port_disable
= rtl83xx_port_disable
,
2220 .get_mac_eee
= rtl93xx_get_mac_eee
,
2221 .set_mac_eee
= rtl83xx_set_mac_eee
,
2223 .set_ageing_time
= rtl83xx_set_ageing_time
,
2224 .port_bridge_join
= rtl83xx_port_bridge_join
,
2225 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
2226 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
2227 .port_fast_age
= rtl930x_fast_age
,
2229 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
2230 .port_vlan_add
= rtl83xx_vlan_add
,
2231 .port_vlan_del
= rtl83xx_vlan_del
,
2233 .port_fdb_add
= rtl83xx_port_fdb_add
,
2234 .port_fdb_del
= rtl83xx_port_fdb_del
,
2235 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
2237 .port_mdb_add
= rtl83xx_port_mdb_add
,
2238 .port_mdb_del
= rtl83xx_port_mdb_del
,
2240 .port_lag_change
= rtl83xx_port_lag_change
,
2241 .port_lag_join
= rtl83xx_port_lag_join
,
2242 .port_lag_leave
= rtl83xx_port_lag_leave
,
2244 .port_pre_bridge_flags
= rtl83xx_port_pre_bridge_flags
,
2245 .port_bridge_flags
= rtl83xx_port_bridge_flags
,