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kernel: backport an upstream fix for ath10k splat
[openwrt/staging/xback.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7
8 #include "rtl83xx.h"
9
10 extern struct rtl83xx_soc_info soc_info;
11
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
13 {
14 mutex_lock(&priv->reg_mutex);
15
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
18 */
19 if (priv->family_id == RTL8380_FAMILY_ID)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
21
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv->r->stat_rst);
24
25 mutex_unlock(&priv->reg_mutex);
26 }
27
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
29 {
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
114 {
115 struct rtl838x_vlan_info info;
116
117 pr_info("In %s\n", __func__);
118
119 priv->r->vlan_profile_setup(0);
120 priv->r->vlan_profile_setup(1);
121 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
122 priv->r->vlan_profile_dump(0);
123
124 info.fid = 0; /* Default Forwarding ID / MSTI */
125 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
126 info.hash_mc_fid = false; /* Do the same for Multicast packets */
127 info.profile_id = 0; /* Use default Vlan Profile 0 */
128 info.tagged_ports = 0; /* Initially no port members */
129 if (priv->family_id == RTL9310_FAMILY_ID) {
130 info.if_id = 0;
131 info.multicast_grp_mask = 0;
132 info.l2_tunnel_list_id = -1;
133 }
134
135 /* Initialize all vlans 0-4095 */
136 for (int i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 /* reset PVIDs; defaults to 1 on reset */
140 for (int i = 0; i <= priv->cpu_port; i++) {
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 1);
142 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 1);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
145 }
146
147 /* Set forwarding action based on inner VLAN tag */
148 for (int i = 0; i < priv->cpu_port; i++)
149 priv->r->vlan_fwd_on_inner(i, true);
150 }
151
152 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
153 {
154 for (int i = 0; i < priv->cpu_port; i++)
155 priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
156 }
157
158 static void rtl83xx_setup_lldp_traps(struct rtl838x_switch_priv *priv)
159 {
160 for (int i = 0; i < priv->cpu_port; i++)
161 priv->r->set_receive_management_action(i, LLDP, TRAP2CPU);
162 }
163
164 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
165 int port, bool enable)
166 {
167 int shift = SALRN_PORT_SHIFT(port);
168 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
169
170 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
171 priv->r->l2_port_new_salrn(port));
172 }
173
174 static int rtl83xx_setup(struct dsa_switch *ds)
175 {
176 struct rtl838x_switch_priv *priv = ds->priv;
177
178 pr_debug("%s called\n", __func__);
179
180 /* Disable MAC polling the PHY so that we can start configuration */
181 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
182
183 for (int i = 0; i < ds->num_ports; i++)
184 priv->ports[i].enable = false;
185 priv->ports[priv->cpu_port].enable = true;
186
187 /* Configure ports so they are disabled by default, but once enabled
188 * they will work in isolated mode (only traffic between port and CPU).
189 */
190 for (int i = 0; i < priv->cpu_port; i++) {
191 if (priv->ports[i].phy) {
192 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
193 priv->r->traffic_set(i, BIT_ULL(i));
194 }
195 }
196 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
197
198 /* For standalone ports, forward packets even if a static fdb
199 * entry for the source address exists on another port.
200 */
201 if (priv->r->set_static_move_action) {
202 for (int i = 0; i <= priv->cpu_port; i++)
203 priv->r->set_static_move_action(i, true);
204 }
205
206 if (priv->family_id == RTL8380_FAMILY_ID)
207 rtl838x_print_matrix();
208 else
209 rtl839x_print_matrix();
210
211 rtl83xx_init_stats(priv);
212
213 rtl83xx_vlan_setup(priv);
214
215 rtl83xx_setup_bpdu_traps(priv);
216 rtl83xx_setup_lldp_traps(priv);
217
218 ds->configure_vlan_while_not_filtering = true;
219
220 priv->r->l2_learning_setup();
221
222 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
223 ds->assisted_learning_on_cpu_port = true;
224
225 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
226 * 0: FWD, 1: DROP, 2: TRAP2CPU
227 */
228 if (priv->family_id == RTL8380_FAMILY_ID)
229 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
230 else
231 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
232
233 /* Enable MAC Polling PHY again */
234 rtl83xx_enable_phy_polling(priv);
235 pr_debug("Please wait until PHY is settled\n");
236 msleep(1000);
237 priv->r->pie_init(priv);
238
239 return 0;
240 }
241
242 static int rtl93xx_setup(struct dsa_switch *ds)
243 {
244 struct rtl838x_switch_priv *priv = ds->priv;
245
246 pr_info("%s called\n", __func__);
247
248 /* Disable MAC polling the PHY so that we can start configuration */
249 if (priv->family_id == RTL9300_FAMILY_ID)
250 sw_w32(0, RTL930X_SMI_POLL_CTRL);
251
252 if (priv->family_id == RTL9310_FAMILY_ID) {
253 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
254 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
255 }
256
257 /* Disable all ports except CPU port */
258 for (int i = 0; i < ds->num_ports; i++)
259 priv->ports[i].enable = false;
260 priv->ports[priv->cpu_port].enable = true;
261
262 /* Configure ports so they are disabled by default, but once enabled
263 * they will work in isolated mode (only traffic between port and CPU).
264 */
265 for (int i = 0; i < priv->cpu_port; i++) {
266 if (priv->ports[i].phy) {
267 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
268 priv->r->traffic_set(i, BIT_ULL(i));
269 }
270 }
271 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
272
273 rtl930x_print_matrix();
274
275 /* TODO: Initialize statistics */
276
277 rtl83xx_vlan_setup(priv);
278
279 ds->configure_vlan_while_not_filtering = true;
280
281 priv->r->l2_learning_setup();
282
283 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
284 ds->assisted_learning_on_cpu_port = true;
285
286 rtl83xx_enable_phy_polling(priv);
287
288 priv->r->pie_init(priv);
289
290 priv->r->led_init(priv);
291
292 return 0;
293 }
294
295 static int rtl93xx_get_sds(struct phy_device *phydev)
296 {
297 struct device *dev = &phydev->mdio.dev;
298 struct device_node *dn;
299 u32 sds_num;
300
301 if (!dev)
302 return -1;
303 if (dev->of_node) {
304 dn = dev->of_node;
305 if (of_property_read_u32(dn, "sds", &sds_num))
306 sds_num = -1;
307 } else {
308 dev_err(dev, "No DT node.\n");
309 return -1;
310 }
311
312 return sds_num;
313 }
314
315 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
316 unsigned long *supported,
317 struct phylink_link_state *state)
318 {
319 struct rtl838x_switch_priv *priv = ds->priv;
320 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
321
322 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
323
324 if (!phy_interface_mode_is_rgmii(state->interface) &&
325 state->interface != PHY_INTERFACE_MODE_NA &&
326 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
327 state->interface != PHY_INTERFACE_MODE_MII &&
328 state->interface != PHY_INTERFACE_MODE_REVMII &&
329 state->interface != PHY_INTERFACE_MODE_GMII &&
330 state->interface != PHY_INTERFACE_MODE_QSGMII &&
331 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
332 state->interface != PHY_INTERFACE_MODE_SGMII) {
333 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
334 dev_err(ds->dev,
335 "Unsupported interface: %d for port %d\n",
336 state->interface, port);
337 return;
338 }
339
340 /* Allow all the expected bits */
341 phylink_set(mask, Autoneg);
342 phylink_set_port_modes(mask);
343 phylink_set(mask, Pause);
344 phylink_set(mask, Asym_Pause);
345
346 /* With the exclusion of MII and Reverse MII, we support Gigabit,
347 * including Half duplex
348 */
349 if (state->interface != PHY_INTERFACE_MODE_MII &&
350 state->interface != PHY_INTERFACE_MODE_REVMII) {
351 phylink_set(mask, 1000baseT_Full);
352 phylink_set(mask, 1000baseT_Half);
353 }
354
355 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
356 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
357 phylink_set(mask, 1000baseX_Full);
358
359 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
360 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
361 phylink_set(mask, 1000baseX_Full);
362
363 phylink_set(mask, 10baseT_Half);
364 phylink_set(mask, 10baseT_Full);
365 phylink_set(mask, 100baseT_Half);
366 phylink_set(mask, 100baseT_Full);
367
368 bitmap_and(supported, supported, mask,
369 __ETHTOOL_LINK_MODE_MASK_NBITS);
370 bitmap_and(state->advertising, state->advertising, mask,
371 __ETHTOOL_LINK_MODE_MASK_NBITS);
372 }
373
374 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
375 unsigned long *supported,
376 struct phylink_link_state *state)
377 {
378 struct rtl838x_switch_priv *priv = ds->priv;
379 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
380
381 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
382 phy_modes(state->interface));
383
384 if (!phy_interface_mode_is_rgmii(state->interface) &&
385 state->interface != PHY_INTERFACE_MODE_NA &&
386 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
387 state->interface != PHY_INTERFACE_MODE_MII &&
388 state->interface != PHY_INTERFACE_MODE_REVMII &&
389 state->interface != PHY_INTERFACE_MODE_GMII &&
390 state->interface != PHY_INTERFACE_MODE_QSGMII &&
391 state->interface != PHY_INTERFACE_MODE_XGMII &&
392 state->interface != PHY_INTERFACE_MODE_HSGMII &&
393 state->interface != PHY_INTERFACE_MODE_10GBASER &&
394 state->interface != PHY_INTERFACE_MODE_10GKR &&
395 state->interface != PHY_INTERFACE_MODE_USXGMII &&
396 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
397 state->interface != PHY_INTERFACE_MODE_SGMII) {
398 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
399 dev_err(ds->dev,
400 "Unsupported interface: %d for port %d\n",
401 state->interface, port);
402 return;
403 }
404
405 /* Allow all the expected bits */
406 phylink_set(mask, Autoneg);
407 phylink_set_port_modes(mask);
408 phylink_set(mask, Pause);
409 phylink_set(mask, Asym_Pause);
410
411 /* With the exclusion of MII and Reverse MII, we support Gigabit,
412 * including Half duplex
413 */
414 if (state->interface != PHY_INTERFACE_MODE_MII &&
415 state->interface != PHY_INTERFACE_MODE_REVMII) {
416 phylink_set(mask, 1000baseT_Full);
417 phylink_set(mask, 1000baseT_Half);
418 }
419
420 /* Internal phys of the RTL93xx family provide 10G */
421 if (priv->ports[port].phy_is_integrated &&
422 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
423 phylink_set(mask, 1000baseX_Full);
424 } else if (priv->ports[port].phy_is_integrated) {
425 phylink_set(mask, 1000baseX_Full);
426 phylink_set(mask, 10000baseKR_Full);
427 phylink_set(mask, 10000baseSR_Full);
428 phylink_set(mask, 10000baseCR_Full);
429 }
430 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
431 phylink_set(mask, 1000baseX_Full);
432 phylink_set(mask, 1000baseT_Full);
433 phylink_set(mask, 10000baseKR_Full);
434 phylink_set(mask, 10000baseT_Full);
435 phylink_set(mask, 10000baseSR_Full);
436 phylink_set(mask, 10000baseCR_Full);
437 }
438
439 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
440 phylink_set(mask, 2500baseT_Full);
441 phylink_set(mask, 5000baseT_Full);
442 phylink_set(mask, 10000baseT_Full);
443 }
444
445 phylink_set(mask, 10baseT_Half);
446 phylink_set(mask, 10baseT_Full);
447 phylink_set(mask, 100baseT_Half);
448 phylink_set(mask, 100baseT_Full);
449
450 bitmap_and(supported, supported, mask,
451 __ETHTOOL_LINK_MODE_MASK_NBITS);
452 bitmap_and(state->advertising, state->advertising, mask,
453 __ETHTOOL_LINK_MODE_MASK_NBITS);
454 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
455 }
456
457 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
458 struct phylink_link_state *state)
459 {
460 struct rtl838x_switch_priv *priv = ds->priv;
461 u64 speed;
462 u64 link;
463
464 if (port < 0 || port > priv->cpu_port)
465 return -EINVAL;
466
467 state->link = 0;
468 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
469 if (link & BIT_ULL(port))
470 state->link = 1;
471 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
472
473 state->duplex = 0;
474 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
475 state->duplex = 1;
476
477 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
478 speed >>= (port % 16) << 1;
479 switch (speed & 0x3) {
480 case 0:
481 state->speed = SPEED_10;
482 break;
483 case 1:
484 state->speed = SPEED_100;
485 break;
486 case 2:
487 state->speed = SPEED_1000;
488 break;
489 case 3:
490 if (priv->family_id == RTL9300_FAMILY_ID
491 && (port == 24 || port == 26)) /* Internal serdes */
492 state->speed = SPEED_2500;
493 else
494 state->speed = SPEED_100; /* Is in fact 500Mbit */
495 }
496
497 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
498 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
499 state->pause |= MLO_PAUSE_RX;
500 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
501 state->pause |= MLO_PAUSE_TX;
502
503 return 1;
504 }
505
506 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
507 struct phylink_link_state *state)
508 {
509 struct rtl838x_switch_priv *priv = ds->priv;
510 u64 speed;
511 u64 link;
512 u64 media;
513
514 if (port < 0 || port > priv->cpu_port)
515 return -EINVAL;
516
517 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
518 * state needs to be read twice in order to read a correct result.
519 * This would not be necessary for ports connected e.g. to RTL8218D
520 * PHYs.
521 */
522 state->link = 0;
523 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
524 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
525 if (link & BIT_ULL(port))
526 state->link = 1;
527
528 if (priv->family_id == RTL9310_FAMILY_ID)
529 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
530
531 if (priv->family_id == RTL9300_FAMILY_ID)
532 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
533
534 if (media & BIT_ULL(port))
535 state->link = 1;
536
537 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
538 link & BIT_ULL(port), media);
539
540 state->duplex = 0;
541 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
542 state->duplex = 1;
543
544 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
545 speed >>= (port % 8) << 2;
546 switch (speed & 0xf) {
547 case 0:
548 state->speed = SPEED_10;
549 break;
550 case 1:
551 state->speed = SPEED_100;
552 break;
553 case 2:
554 case 7:
555 state->speed = SPEED_1000;
556 break;
557 case 4:
558 state->speed = SPEED_10000;
559 break;
560 case 5:
561 case 8:
562 state->speed = SPEED_2500;
563 break;
564 case 6:
565 state->speed = SPEED_5000;
566 break;
567 default:
568 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
569 }
570
571 if (priv->family_id == RTL9310_FAMILY_ID
572 && (port >= 52 && port <= 55)) { /* Internal serdes */
573 state->speed = SPEED_10000;
574 state->link = 1;
575 state->duplex = 1;
576 }
577
578 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
579 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
580 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
581 state->pause |= MLO_PAUSE_RX;
582 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
583 state->pause |= MLO_PAUSE_TX;
584
585 return 1;
586 }
587
588 static void rtl83xx_config_interface(int port, phy_interface_t interface)
589 {
590 u32 old, int_shift, sds_shift;
591
592 switch (port) {
593 case 24:
594 int_shift = 0;
595 sds_shift = 5;
596 break;
597 case 26:
598 int_shift = 3;
599 sds_shift = 0;
600 break;
601 default:
602 return;
603 }
604
605 old = sw_r32(RTL838X_SDS_MODE_SEL);
606 switch (interface) {
607 case PHY_INTERFACE_MODE_1000BASEX:
608 if ((old >> sds_shift & 0x1f) == 4)
609 return;
610 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
611 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
612 break;
613 case PHY_INTERFACE_MODE_SGMII:
614 if ((old >> sds_shift & 0x1f) == 2)
615 return;
616 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
617 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
618 break;
619 default:
620 return;
621 }
622 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
623 }
624
625 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
626 unsigned int mode,
627 const struct phylink_link_state *state)
628 {
629 struct rtl838x_switch_priv *priv = ds->priv;
630 u32 reg;
631 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
632
633 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
634
635 if (port == priv->cpu_port) {
636 /* Set Speed, duplex, flow control
637 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
638 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
639 * | MEDIA_SEL
640 */
641 if (priv->family_id == RTL8380_FAMILY_ID) {
642 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
643 /* allow CRC errors on CPU-port */
644 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
645 } else {
646 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
647 }
648 return;
649 }
650
651 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
652 /* Auto-Negotiation does not work for MAC in RTL8390 */
653 if (priv->family_id == RTL8380_FAMILY_ID) {
654 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
655 pr_debug("PHY autonegotiates\n");
656 reg |= RTL838X_NWAY_EN;
657 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
658 rtl83xx_config_interface(port, state->interface);
659 return;
660 }
661 }
662
663 if (mode != MLO_AN_FIXED)
664 pr_debug("Fixed state.\n");
665
666 /* Clear id_mode_dis bit, and the existing port mode, let
667 * RGMII_MODE_EN bet set by mac_link_{up,down} */
668 if (priv->family_id == RTL8380_FAMILY_ID) {
669 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
670 if (state->pause & MLO_PAUSE_TXRX_MASK) {
671 if (state->pause & MLO_PAUSE_TX)
672 reg |= RTL838X_TX_PAUSE_EN;
673 reg |= RTL838X_RX_PAUSE_EN;
674 }
675 } else if (priv->family_id == RTL8390_FAMILY_ID) {
676 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
677 if (state->pause & MLO_PAUSE_TXRX_MASK) {
678 if (state->pause & MLO_PAUSE_TX)
679 reg |= RTL839X_TX_PAUSE_EN;
680 reg |= RTL839X_RX_PAUSE_EN;
681 }
682 }
683
684
685 reg &= ~(3 << speed_bit);
686 switch (state->speed) {
687 case SPEED_1000:
688 reg |= 2 << speed_bit;
689 break;
690 case SPEED_100:
691 reg |= 1 << speed_bit;
692 break;
693 default:
694 break; /* Ignore, including 10MBit which has a speed value of 0 */
695 }
696
697 if (priv->family_id == RTL8380_FAMILY_ID) {
698 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
699 if (state->link)
700 reg |= RTL838X_FORCE_LINK_EN;
701 if (state->duplex == RTL838X_DUPLEX_MODE)
702 reg |= RTL838X_DUPLEX_MODE;
703 } else if (priv->family_id == RTL8390_FAMILY_ID) {
704 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
705 if (state->link)
706 reg |= RTL839X_FORCE_LINK_EN;
707 if (state->duplex == RTL839X_DUPLEX_MODE)
708 reg |= RTL839X_DUPLEX_MODE;
709 }
710
711 /* LAG members must use DUPLEX and we need to enable the link */
712 if (priv->lagmembers & BIT_ULL(port)) {
713 switch(priv->family_id) {
714 case RTL8380_FAMILY_ID:
715 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
716 break;
717 case RTL8390_FAMILY_ID:
718 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
719 break;
720 }
721 }
722
723 /* Disable AN */
724 if (priv->family_id == RTL8380_FAMILY_ID)
725 reg &= ~RTL838X_NWAY_EN;
726 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
727 }
728
729 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
730 unsigned int mode,
731 const struct phylink_link_state *state)
732 {
733 struct rtl838x_switch_priv *priv = ds->priv;
734 int sds_num;
735 u32 reg, band;
736
737 sds_num = priv->ports[port].sds_num;
738 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
739
740 switch (state->interface) {
741 case PHY_INTERFACE_MODE_HSGMII:
742 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
743 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
744 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
745 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
746 break;
747 case PHY_INTERFACE_MODE_1000BASEX:
748 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
749 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
750 break;
751 case PHY_INTERFACE_MODE_XGMII:
752 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
753 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
754 break;
755 case PHY_INTERFACE_MODE_10GBASER:
756 case PHY_INTERFACE_MODE_10GKR:
757 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
758 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
759 break;
760 case PHY_INTERFACE_MODE_USXGMII:
761 /* Translates to MII_USXGMII_10GSXGMII */
762 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
763 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
764 break;
765 case PHY_INTERFACE_MODE_SGMII:
766 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
767 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
768 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
769 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
770 break;
771 case PHY_INTERFACE_MODE_QSGMII:
772 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
773 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
774 break;
775 default:
776 pr_err("%s: unknown serdes mode: %s\n",
777 __func__, phy_modes(state->interface));
778 return;
779 }
780
781 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
782 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
783
784 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
785
786 reg &= ~(0xf << 12);
787 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
788
789 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
790
791 if (priv->lagmembers & BIT_ULL(port))
792 reg |= RTL931X_DUPLEX_MODE;
793
794 if (state->duplex == DUPLEX_FULL)
795 reg |= RTL931X_DUPLEX_MODE;
796
797 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
798
799 }
800
801 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
802 unsigned int mode,
803 const struct phylink_link_state *state)
804 {
805 struct rtl838x_switch_priv *priv = ds->priv;
806 int sds_num;
807 u32 reg;
808
809 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
810 port, mode, phy_modes(state->interface), state->speed, state->link);
811
812 /* Nothing to be done for the CPU-port */
813 if (port == priv->cpu_port)
814 return;
815
816 if (priv->family_id == RTL9310_FAMILY_ID)
817 return rtl931x_phylink_mac_config(ds, port, mode, state);
818
819 sds_num = priv->ports[port].sds_num;
820 pr_info("%s SDS is %d\n", __func__, sds_num);
821 if (sds_num >= 0 &&
822 (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
823 state->interface == PHY_INTERFACE_MODE_10GBASER))
824 rtl9300_serdes_setup(port, sds_num, state->interface);
825
826 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
827 reg &= ~(0xf << 3);
828
829 switch (state->speed) {
830 case SPEED_10000:
831 reg |= 4 << 3;
832 break;
833 case SPEED_5000:
834 reg |= 6 << 3;
835 break;
836 case SPEED_2500:
837 reg |= 5 << 3;
838 break;
839 case SPEED_1000:
840 reg |= 2 << 3;
841 break;
842 case SPEED_100:
843 reg |= 1 << 3;
844 break;
845 default:
846 /* Also covers 10M */
847 break;
848 }
849
850 if (state->link)
851 reg |= RTL930X_FORCE_LINK_EN;
852
853 if (priv->lagmembers & BIT_ULL(port))
854 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
855
856 if (state->duplex == DUPLEX_FULL)
857 reg |= RTL930X_DUPLEX_MODE;
858 else
859 reg &= ~RTL930X_DUPLEX_MODE; /* Clear duplex bit otherwise */
860
861 if (priv->ports[port].phy_is_integrated)
862 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
863 else
864 reg |= RTL930X_FORCE_EN;
865
866 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
867 }
868
869 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
870 unsigned int mode,
871 phy_interface_t interface)
872 {
873 struct rtl838x_switch_priv *priv = ds->priv;
874
875 /* Stop TX/RX to port */
876 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
877
878 /* No longer force link */
879 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
880 }
881
882 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
883 unsigned int mode,
884 phy_interface_t interface)
885 {
886 struct rtl838x_switch_priv *priv = ds->priv;
887 u32 v = 0;
888
889 /* Stop TX/RX to port */
890 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
891
892 /* No longer force link */
893 if (priv->family_id == RTL9300_FAMILY_ID)
894 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
895 else if (priv->family_id == RTL9310_FAMILY_ID)
896 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
897 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
898 }
899
900 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
901 unsigned int mode,
902 phy_interface_t interface,
903 struct phy_device *phydev,
904 int speed, int duplex,
905 bool tx_pause, bool rx_pause)
906 {
907 struct rtl838x_switch_priv *priv = ds->priv;
908 /* Restart TX/RX to port */
909 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
910 /* TODO: Set speed/duplex/pauses */
911 }
912
913 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
914 unsigned int mode,
915 phy_interface_t interface,
916 struct phy_device *phydev,
917 int speed, int duplex,
918 bool tx_pause, bool rx_pause)
919 {
920 struct rtl838x_switch_priv *priv = ds->priv;
921
922 /* Restart TX/RX to port */
923 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
924 /* TODO: Set speed/duplex/pauses */
925 }
926
927 static void rtl83xx_get_strings(struct dsa_switch *ds,
928 int port, u32 stringset, u8 *data)
929 {
930 if (stringset != ETH_SS_STATS)
931 return;
932
933 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
934 ethtool_puts(&data, rtl83xx_mib[i].name);
935 }
936
937 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
938 uint64_t *data)
939 {
940 struct rtl838x_switch_priv *priv = ds->priv;
941 const struct rtl83xx_mib_desc *mib;
942 u64 h;
943
944 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
945 mib = &rtl83xx_mib[i];
946
947 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
948 if (mib->size == 2) {
949 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
950 data[i] |= h << 32;
951 }
952 }
953 }
954
955 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
956 {
957 if (sset != ETH_SS_STATS)
958 return 0;
959
960 return ARRAY_SIZE(rtl83xx_mib);
961 }
962
963 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
964 {
965 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
966 u64 portmask;
967
968 if (mc_group >= MAX_MC_GROUPS - 1)
969 return -1;
970
971 set_bit(mc_group, priv->mc_group_bm);
972 portmask = BIT_ULL(port);
973 priv->r->write_mcast_pmask(mc_group, portmask);
974
975 return mc_group;
976 }
977
978 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
979 {
980 u64 portmask = priv->r->read_mcast_pmask(mc_group);
981
982 pr_debug("%s: %d\n", __func__, port);
983
984 portmask |= BIT_ULL(port);
985 priv->r->write_mcast_pmask(mc_group, portmask);
986
987 return portmask;
988 }
989
990 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
991 {
992 u64 portmask = priv->r->read_mcast_pmask(mc_group);
993
994 pr_debug("%s: %d\n", __func__, port);
995
996 portmask &= ~BIT_ULL(port);
997 priv->r->write_mcast_pmask(mc_group, portmask);
998 if (!portmask)
999 clear_bit(mc_group, priv->mc_group_bm);
1000
1001 return portmask;
1002 }
1003
1004 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1005 struct phy_device *phydev)
1006 {
1007 struct rtl838x_switch_priv *priv = ds->priv;
1008 u64 v;
1009
1010 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1011 priv->ports[port].enable = true;
1012
1013 /* enable inner tagging on egress, do not keep any tags */
1014 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1015
1016 if (dsa_is_cpu_port(ds, port))
1017 return 0;
1018
1019 /* add port to switch mask of CPU_PORT */
1020 priv->r->traffic_enable(priv->cpu_port, port);
1021
1022 if (priv->is_lagmember[port]) {
1023 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1024 return 0;
1025 }
1026
1027 /* add all other ports in the same bridge to switch mask of port */
1028 v = priv->r->traffic_get(port);
1029 v |= priv->ports[port].pm;
1030 priv->r->traffic_set(port, v);
1031
1032 /* TODO: Figure out if this is necessary */
1033 if (priv->family_id == RTL9300_FAMILY_ID) {
1034 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1035 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1036 }
1037
1038 if (priv->ports[port].sds_num < 0)
1039 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1040
1041 return 0;
1042 }
1043
1044 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1045 {
1046 struct rtl838x_switch_priv *priv = ds->priv;
1047 u64 v;
1048
1049 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1050 /* you can only disable user ports */
1051 if (!dsa_is_user_port(ds, port))
1052 return;
1053
1054 /* BUG: This does not work on RTL931X */
1055 /* remove port from switch mask of CPU_PORT */
1056 priv->r->traffic_disable(priv->cpu_port, port);
1057
1058 /* remove all other ports in the same bridge from switch mask of port */
1059 v = priv->r->traffic_get(port);
1060 v &= ~priv->ports[port].pm;
1061 priv->r->traffic_set(port, v);
1062
1063 priv->ports[port].enable = false;
1064 }
1065
1066 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1067 struct ethtool_eee *e)
1068 {
1069 struct rtl838x_switch_priv *priv = ds->priv;
1070
1071 if (e->eee_enabled && !priv->eee_enabled) {
1072 pr_info("Globally enabling EEE\n");
1073 priv->r->init_eee(priv, true);
1074 }
1075
1076 priv->r->port_eee_set(priv, port, e->eee_enabled);
1077
1078 if (e->eee_enabled)
1079 pr_info("Enabled EEE for port %d\n", port);
1080 else
1081 pr_info("Disabled EEE for port %d\n", port);
1082
1083 return 0;
1084 }
1085
1086 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1087 struct ethtool_eee *e)
1088 {
1089 struct rtl838x_switch_priv *priv = ds->priv;
1090
1091 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1092
1093 priv->r->eee_port_ability(priv, e, port);
1094
1095 e->eee_enabled = priv->ports[port].eee_enabled;
1096
1097 e->eee_active = !!(e->advertised & e->lp_advertised);
1098
1099 return 0;
1100 }
1101
1102 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1103 struct ethtool_eee *e)
1104 {
1105 struct rtl838x_switch_priv *priv = ds->priv;
1106
1107 e->supported = SUPPORTED_100baseT_Full |
1108 SUPPORTED_1000baseT_Full |
1109 SUPPORTED_2500baseX_Full;
1110
1111 priv->r->eee_port_ability(priv, e, port);
1112
1113 e->eee_enabled = priv->ports[port].eee_enabled;
1114
1115 e->eee_active = !!(e->advertised & e->lp_advertised);
1116
1117 return 0;
1118 }
1119
1120 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1121 {
1122 struct rtl838x_switch_priv *priv = ds->priv;
1123
1124 priv->r->set_ageing_time(msec);
1125
1126 return 0;
1127 }
1128
1129 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1130 struct net_device *bridge)
1131 {
1132 struct rtl838x_switch_priv *priv = ds->priv;
1133 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1134
1135 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1136
1137 if (priv->is_lagmember[port]) {
1138 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1139 return 0;
1140 }
1141
1142 mutex_lock(&priv->reg_mutex);
1143 for (int i = 0; i < ds->num_ports; i++) {
1144 /* Add this port to the port matrix of the other ports in the
1145 * same bridge. If the port is disabled, port matrix is kept
1146 * and not being setup until the port becomes enabled.
1147 */
1148 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1149 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1150 continue;
1151 if (priv->ports[i].enable)
1152 priv->r->traffic_enable(i, port);
1153
1154 priv->ports[i].pm |= BIT_ULL(port);
1155 port_bitmap |= BIT_ULL(i);
1156 }
1157 }
1158
1159 /* Add all other ports to this port matrix. */
1160 if (priv->ports[port].enable) {
1161 priv->r->traffic_enable(priv->cpu_port, port);
1162 v = priv->r->traffic_get(port);
1163 v |= port_bitmap;
1164 priv->r->traffic_set(port, v);
1165 }
1166 priv->ports[port].pm |= port_bitmap;
1167
1168 if (priv->r->set_static_move_action)
1169 priv->r->set_static_move_action(port, false);
1170
1171 mutex_unlock(&priv->reg_mutex);
1172
1173 return 0;
1174 }
1175
1176 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1177 struct net_device *bridge)
1178 {
1179 struct rtl838x_switch_priv *priv = ds->priv;
1180 u64 port_bitmap = 0, v;
1181
1182 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1183 mutex_lock(&priv->reg_mutex);
1184 for (int i = 0; i < ds->num_ports; i++) {
1185 /* Remove this port from the port matrix of the other ports
1186 * in the same bridge. If the port is disabled, port matrix
1187 * is kept and not being setup until the port becomes enabled.
1188 * And the other port's port matrix cannot be broken when the
1189 * other port is still a VLAN-aware port.
1190 */
1191 if (dsa_is_user_port(ds, i) && i != port) {
1192 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1193 continue;
1194 if (priv->ports[i].enable)
1195 priv->r->traffic_disable(i, port);
1196
1197 priv->ports[i].pm &= ~BIT_ULL(port);
1198 port_bitmap |= BIT_ULL(i);
1199 }
1200 }
1201
1202 /* Remove all other ports from this port matrix. */
1203 if (priv->ports[port].enable) {
1204 v = priv->r->traffic_get(port);
1205 v &= ~port_bitmap;
1206 priv->r->traffic_set(port, v);
1207 }
1208 priv->ports[port].pm &= ~port_bitmap;
1209
1210 if (priv->r->set_static_move_action)
1211 priv->r->set_static_move_action(port, true);
1212
1213 mutex_unlock(&priv->reg_mutex);
1214 }
1215
1216 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1217 {
1218 u32 msti = 0;
1219 u32 port_state[4];
1220 int index, bit;
1221 int pos = port;
1222 struct rtl838x_switch_priv *priv = ds->priv;
1223 int n = priv->port_width << 1;
1224
1225 /* Ports above or equal CPU port can never be configured */
1226 if (port >= priv->cpu_port)
1227 return;
1228
1229 mutex_lock(&priv->reg_mutex);
1230
1231 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1232 * have 64 bit fields, 839x and 931x have 128 bit fields
1233 */
1234 if (priv->family_id == RTL8390_FAMILY_ID)
1235 pos += 12;
1236 if (priv->family_id == RTL9300_FAMILY_ID)
1237 pos += 3;
1238 if (priv->family_id == RTL9310_FAMILY_ID)
1239 pos += 8;
1240
1241 index = n - (pos >> 4) - 1;
1242 bit = (pos << 1) % 32;
1243
1244 priv->r->stp_get(priv, msti, port_state);
1245
1246 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1247 port_state[index] &= ~(3 << bit);
1248
1249 switch (state) {
1250 case BR_STATE_DISABLED: /* 0 */
1251 port_state[index] |= (0 << bit);
1252 break;
1253 case BR_STATE_BLOCKING: /* 4 */
1254 case BR_STATE_LISTENING: /* 1 */
1255 port_state[index] |= (1 << bit);
1256 break;
1257 case BR_STATE_LEARNING: /* 2 */
1258 port_state[index] |= (2 << bit);
1259 break;
1260 case BR_STATE_FORWARDING: /* 3 */
1261 port_state[index] |= (3 << bit);
1262 default:
1263 break;
1264 }
1265
1266 priv->r->stp_set(priv, msti, port_state);
1267
1268 mutex_unlock(&priv->reg_mutex);
1269 }
1270
1271 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1272 {
1273 struct rtl838x_switch_priv *priv = ds->priv;
1274 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1275
1276 pr_debug("FAST AGE port %d\n", port);
1277 mutex_lock(&priv->reg_mutex);
1278 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1279 * port fields:
1280 * 0-4: Replacing port
1281 * 5-9: Flushed/replaced port
1282 * 10-21: FVID
1283 * 22: Entry types: 1: dynamic, 0: also static
1284 * 23: Match flush port
1285 * 24: Match FVID
1286 * 25: Flush (0) or replace (1) L2 entries
1287 * 26: Status of action (1: Start, 0: Done)
1288 */
1289 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1290
1291 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1292
1293 mutex_unlock(&priv->reg_mutex);
1294 }
1295
1296 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1297 {
1298 struct rtl838x_switch_priv *priv = ds->priv;
1299
1300 pr_info("%s port %d\n", __func__, port);
1301 mutex_lock(&priv->reg_mutex);
1302 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1303
1304 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1305
1306 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1307
1308 mutex_unlock(&priv->reg_mutex);
1309 }
1310
1311 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1312 {
1313 struct rtl838x_switch_priv *priv = ds->priv;
1314
1315 if (priv->family_id == RTL9310_FAMILY_ID)
1316 return rtl931x_fast_age(ds, port);
1317
1318 pr_debug("FAST AGE port %d\n", port);
1319 mutex_lock(&priv->reg_mutex);
1320 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1321
1322 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1323
1324 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1325
1326 mutex_unlock(&priv->reg_mutex);
1327 }
1328
1329 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1330 bool vlan_filtering,
1331 struct netlink_ext_ack *extack)
1332 {
1333 struct rtl838x_switch_priv *priv = ds->priv;
1334
1335 pr_debug("%s: port %d\n", __func__, port);
1336 mutex_lock(&priv->reg_mutex);
1337
1338 if (vlan_filtering) {
1339 /* Enable ingress and egress filtering
1340 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1341 * the filter action:
1342 * 0: Always Forward
1343 * 1: Drop packet
1344 * 2: Trap packet to CPU port
1345 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1346 */
1347 if (port != priv->cpu_port) {
1348 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1349 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1350 }
1351 else {
1352 priv->r->set_vlan_igr_filter(port, IGR_TRAP);
1353 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1354 }
1355
1356 } else {
1357 /* Disable ingress and egress filtering */
1358 if (port != priv->cpu_port)
1359 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1360
1361 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1362 }
1363
1364 /* Do we need to do something to the CPU-Port, too? */
1365 mutex_unlock(&priv->reg_mutex);
1366
1367 return 0;
1368 }
1369
1370 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1371 const struct switchdev_obj_port_vlan *vlan)
1372 {
1373 struct rtl838x_vlan_info info;
1374 struct rtl838x_switch_priv *priv = ds->priv;
1375
1376 priv->r->vlan_tables_read(0, &info);
1377
1378 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1379 info.tagged_ports, info.untagged_ports, info.profile_id,
1380 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1381
1382 priv->r->vlan_tables_read(1, &info);
1383 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1384 info.tagged_ports, info.untagged_ports, info.profile_id,
1385 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1386 priv->r->vlan_set_untagged(1, info.untagged_ports);
1387 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1388
1389 priv->r->vlan_set_tagged(1, &info);
1390 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1391
1392 return 0;
1393 }
1394
1395 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1396 int port, int pvid)
1397 {
1398 /* Set both inner and outer PVID of the port */
1399 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1400 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1401 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1402 PBVLAN_MODE_UNTAG_AND_PRITAG);
1403 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1404 PBVLAN_MODE_UNTAG_AND_PRITAG);
1405
1406 priv->ports[port].pvid = pvid;
1407 }
1408
1409 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1410 const struct switchdev_obj_port_vlan *vlan,
1411 struct netlink_ext_ack *extack)
1412 {
1413 struct rtl838x_vlan_info info;
1414 struct rtl838x_switch_priv *priv = ds->priv;
1415 int err;
1416
1417 pr_debug("%s port %d, vid %d, flags %x\n",
1418 __func__, port, vlan->vid, vlan->flags);
1419
1420 if(!vlan->vid) return 0;
1421
1422 if (vlan->vid > 4095) {
1423 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1424 return -ENOTSUPP;
1425 }
1426
1427 err = rtl83xx_vlan_prepare(ds, port, vlan);
1428 if (err)
1429 return err;
1430
1431 mutex_lock(&priv->reg_mutex);
1432
1433 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1434 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1435 else if (priv->ports[port].pvid == vlan->vid)
1436 rtl83xx_vlan_set_pvid(priv, port, 0);
1437
1438 /* Get port memberships of this vlan */
1439 priv->r->vlan_tables_read(vlan->vid, &info);
1440
1441 /* new VLAN? */
1442 if (!info.tagged_ports) {
1443 info.fid = 0;
1444 info.hash_mc_fid = false;
1445 info.hash_uc_fid = false;
1446 info.profile_id = 0;
1447 }
1448
1449 /* sanitize untagged_ports - must be a subset */
1450 if (info.untagged_ports & ~info.tagged_ports)
1451 info.untagged_ports = 0;
1452
1453 info.tagged_ports |= BIT_ULL(port);
1454 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1455 info.untagged_ports |= BIT_ULL(port);
1456 else
1457 info.untagged_ports &= ~BIT_ULL(port);
1458
1459 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1460 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1461
1462 priv->r->vlan_set_tagged(vlan->vid, &info);
1463 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1464
1465 mutex_unlock(&priv->reg_mutex);
1466
1467 return 0;
1468 }
1469
1470 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1471 const struct switchdev_obj_port_vlan *vlan)
1472 {
1473 struct rtl838x_vlan_info info;
1474 struct rtl838x_switch_priv *priv = ds->priv;
1475 u16 pvid;
1476
1477 pr_debug("%s: port %d, vid %d, flags %x\n",
1478 __func__, port, vlan->vid, vlan->flags);
1479
1480 if (vlan->vid > 4095) {
1481 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1482 return -ENOTSUPP;
1483 }
1484
1485 mutex_lock(&priv->reg_mutex);
1486 pvid = priv->ports[port].pvid;
1487
1488 /* Reset to default if removing the current PVID */
1489 if (vlan->vid == pvid) {
1490 rtl83xx_vlan_set_pvid(priv, port, 0);
1491 }
1492 /* Get port memberships of this vlan */
1493 priv->r->vlan_tables_read(vlan->vid, &info);
1494
1495 /* remove port from both tables */
1496 info.untagged_ports &= (~BIT_ULL(port));
1497 info.tagged_ports &= (~BIT_ULL(port));
1498
1499 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1500 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1501
1502 priv->r->vlan_set_tagged(vlan->vid, &info);
1503 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1504
1505 mutex_unlock(&priv->reg_mutex);
1506
1507 return 0;
1508 }
1509
1510 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1511 {
1512 memset(e, 0, sizeof(*e));
1513
1514 e->type = L2_UNICAST;
1515 e->valid = true;
1516
1517 e->age = 3;
1518 e->is_static = true;
1519
1520 e->port = port;
1521
1522 e->rvid = e->vid = vid;
1523 e->is_ip_mc = e->is_ipv6_mc = false;
1524 u64_to_ether_addr(mac, e->mac);
1525 }
1526
1527 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1528 {
1529 memset(e, 0, sizeof(*e));
1530
1531 e->type = L2_MULTICAST;
1532 e->valid = true;
1533
1534 e->mc_portmask_index = mc_group;
1535
1536 e->rvid = e->vid = vid;
1537 e->is_ip_mc = e->is_ipv6_mc = false;
1538 u64_to_ether_addr(mac, e->mac);
1539 }
1540
1541 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1542 * over the entries in the bucket until either a matching entry is found or an empty slot
1543 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1544 * when an empty slot was found and must exist is false, the index of the slot is returned
1545 * when no slots are available returns -1
1546 */
1547 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1548 bool must_exist, struct rtl838x_l2_entry *e)
1549 {
1550 int idx = -1;
1551 u32 key = priv->r->l2_hash_key(priv, seed);
1552 u64 entry;
1553
1554 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1555 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1556 for (int i = 0; i < priv->l2_bucket_size; i++) {
1557 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1558 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1559 if (must_exist && !e->valid)
1560 continue;
1561 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1562 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1563 break;
1564 }
1565 }
1566
1567 return idx;
1568 }
1569
1570 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1571 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1572 * when an empty slot was found the index of the slot is returned
1573 * when no slots are available returns -1
1574 */
1575 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1576 bool must_exist, struct rtl838x_l2_entry *e)
1577 {
1578 int idx = -1;
1579 u64 entry;
1580
1581 for (int i = 0; i < 64; i++) {
1582 entry = priv->r->read_cam(i, e);
1583 if (!must_exist && !e->valid) {
1584 if (idx < 0) /* First empty entry? */
1585 idx = i;
1586 break;
1587 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1588 pr_debug("Found entry in CAM\n");
1589 idx = i;
1590 break;
1591 }
1592 }
1593
1594 return idx;
1595 }
1596
1597 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1598 const unsigned char *addr, u16 vid)
1599 {
1600 struct rtl838x_switch_priv *priv = ds->priv;
1601 u64 mac = ether_addr_to_u64(addr);
1602 struct rtl838x_l2_entry e;
1603 int err = 0, idx;
1604 u64 seed = priv->r->l2_hash_seed(mac, vid);
1605
1606 if (priv->is_lagmember[port]) {
1607 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1608 return 0;
1609 }
1610
1611 mutex_lock(&priv->reg_mutex);
1612
1613 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1614
1615 /* Found an existing or empty entry */
1616 if (idx >= 0) {
1617 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1618 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1619 goto out;
1620 }
1621
1622 /* Hash buckets full, try CAM */
1623 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1624
1625 if (idx >= 0) {
1626 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1627 priv->r->write_cam(idx, &e);
1628 goto out;
1629 }
1630
1631 err = -ENOTSUPP;
1632
1633 out:
1634 mutex_unlock(&priv->reg_mutex);
1635
1636 return err;
1637 }
1638
1639 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1640 const unsigned char *addr, u16 vid)
1641 {
1642 struct rtl838x_switch_priv *priv = ds->priv;
1643 u64 mac = ether_addr_to_u64(addr);
1644 struct rtl838x_l2_entry e;
1645 int err = 0, idx;
1646 u64 seed = priv->r->l2_hash_seed(mac, vid);
1647
1648 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1649 mutex_lock(&priv->reg_mutex);
1650
1651 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1652
1653 if (idx >= 0) {
1654 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1655 e.valid = false;
1656 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1657 goto out;
1658 }
1659
1660 /* Check CAM for spillover from hash buckets */
1661 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1662
1663 if (idx >= 0) {
1664 e.valid = false;
1665 priv->r->write_cam(idx, &e);
1666 goto out;
1667 }
1668 err = -ENOENT;
1669
1670 out:
1671 mutex_unlock(&priv->reg_mutex);
1672
1673 return err;
1674 }
1675
1676 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1677 dsa_fdb_dump_cb_t *cb, void *data)
1678 {
1679 struct rtl838x_l2_entry e;
1680 struct rtl838x_switch_priv *priv = ds->priv;
1681
1682 mutex_lock(&priv->reg_mutex);
1683
1684 for (int i = 0; i < priv->fib_entries; i++) {
1685 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1686
1687 if (!e.valid)
1688 continue;
1689
1690 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1691 cb(e.mac, e.vid, e.is_static, data);
1692
1693 if (!((i + 1) % 64))
1694 cond_resched();
1695 }
1696
1697 for (int i = 0; i < 64; i++) {
1698 priv->r->read_cam(i, &e);
1699
1700 if (!e.valid)
1701 continue;
1702
1703 if (e.port == port)
1704 cb(e.mac, e.vid, e.is_static, data);
1705 }
1706
1707 mutex_unlock(&priv->reg_mutex);
1708
1709 return 0;
1710 }
1711
1712 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1713 const struct switchdev_obj_port_mdb *mdb)
1714 {
1715 struct rtl838x_switch_priv *priv = ds->priv;
1716 u64 mac = ether_addr_to_u64(mdb->addr);
1717 struct rtl838x_l2_entry e;
1718 int err = 0, idx;
1719 int vid = mdb->vid;
1720 u64 seed = priv->r->l2_hash_seed(mac, vid);
1721 int mc_group;
1722
1723 if (priv->id >= 0x9300)
1724 return -EOPNOTSUPP;
1725
1726 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1727
1728 if (priv->is_lagmember[port]) {
1729 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1730 return -EINVAL;
1731 }
1732
1733 mutex_lock(&priv->reg_mutex);
1734
1735 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1736
1737 /* Found an existing or empty entry */
1738 if (idx >= 0) {
1739 if (e.valid) {
1740 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1741 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1742 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1743 } else {
1744 pr_debug("New entry for seed %016llx\n", seed);
1745 mc_group = rtl83xx_mc_group_alloc(priv, port);
1746 if (mc_group < 0) {
1747 err = -ENOTSUPP;
1748 goto out;
1749 }
1750 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1751 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1752 }
1753 goto out;
1754 }
1755
1756 /* Hash buckets full, try CAM */
1757 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1758
1759 if (idx >= 0) {
1760 if (e.valid) {
1761 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1762 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1763 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1764 } else {
1765 pr_debug("New entry\n");
1766 mc_group = rtl83xx_mc_group_alloc(priv, port);
1767 if (mc_group < 0) {
1768 err = -ENOTSUPP;
1769 goto out;
1770 }
1771 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1772 priv->r->write_cam(idx, &e);
1773 }
1774 goto out;
1775 }
1776
1777 err = -ENOTSUPP;
1778
1779 out:
1780 mutex_unlock(&priv->reg_mutex);
1781 if (err)
1782 dev_err(ds->dev, "failed to add MDB entry\n");
1783
1784 return err;
1785 }
1786
1787 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1788 const struct switchdev_obj_port_mdb *mdb)
1789 {
1790 struct rtl838x_switch_priv *priv = ds->priv;
1791 u64 mac = ether_addr_to_u64(mdb->addr);
1792 struct rtl838x_l2_entry e;
1793 int err = 0, idx;
1794 int vid = mdb->vid;
1795 u64 seed = priv->r->l2_hash_seed(mac, vid);
1796 u64 portmask;
1797
1798 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1799
1800 if (priv->is_lagmember[port]) {
1801 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1802 return 0;
1803 }
1804
1805 mutex_lock(&priv->reg_mutex);
1806
1807 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1808
1809 if (idx >= 0) {
1810 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1811 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1812 if (!portmask) {
1813 e.valid = false;
1814 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1815 }
1816 goto out;
1817 }
1818
1819 /* Check CAM for spillover from hash buckets */
1820 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1821
1822 if (idx >= 0) {
1823 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1824 if (!portmask) {
1825 e.valid = false;
1826 priv->r->write_cam(idx, &e);
1827 }
1828 goto out;
1829 }
1830 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1831
1832 out:
1833 mutex_unlock(&priv->reg_mutex);
1834
1835 return err;
1836 }
1837
1838 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1839 struct dsa_mall_mirror_tc_entry *mirror,
1840 bool ingress)
1841 {
1842 /* We support 4 mirror groups, one destination port per group */
1843 int group;
1844 struct rtl838x_switch_priv *priv = ds->priv;
1845 int ctrl_reg, dpm_reg, spm_reg;
1846
1847 pr_debug("In %s\n", __func__);
1848
1849 for (group = 0; group < 4; group++) {
1850 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1851 break;
1852 }
1853 if (group >= 4) {
1854 for (group = 0; group < 4; group++) {
1855 if (priv->mirror_group_ports[group] < 0)
1856 break;
1857 }
1858 }
1859
1860 if (group >= 4)
1861 return -ENOSPC;
1862
1863 ctrl_reg = priv->r->mir_ctrl + group * 4;
1864 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1865 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1866
1867 pr_debug("Using group %d\n", group);
1868 mutex_lock(&priv->reg_mutex);
1869
1870 if (priv->family_id == RTL8380_FAMILY_ID) {
1871 /* Enable mirroring to port across VLANs (bit 11) */
1872 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1873 } else {
1874 /* Enable mirroring to destination port */
1875 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1876 }
1877
1878 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1879 mutex_unlock(&priv->reg_mutex);
1880 return -EEXIST;
1881 }
1882 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1883 mutex_unlock(&priv->reg_mutex);
1884 return -EEXIST;
1885 }
1886
1887 if (ingress)
1888 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1889 else
1890 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1891
1892 priv->mirror_group_ports[group] = mirror->to_local_port;
1893 mutex_unlock(&priv->reg_mutex);
1894
1895 return 0;
1896 }
1897
1898 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1899 struct dsa_mall_mirror_tc_entry *mirror)
1900 {
1901 int group = 0;
1902 struct rtl838x_switch_priv *priv = ds->priv;
1903 int ctrl_reg, dpm_reg, spm_reg;
1904
1905 pr_debug("In %s\n", __func__);
1906 for (group = 0; group < 4; group++) {
1907 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1908 break;
1909 }
1910 if (group >= 4)
1911 return;
1912
1913 ctrl_reg = priv->r->mir_ctrl + group * 4;
1914 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1915 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1916
1917 mutex_lock(&priv->reg_mutex);
1918 if (mirror->ingress) {
1919 /* Ingress, clear source port matrix */
1920 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1921 } else {
1922 /* Egress, clear destination port matrix */
1923 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1924 }
1925
1926 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1927 priv->mirror_group_ports[group] = -1;
1928 sw_w32(0, ctrl_reg);
1929 }
1930
1931 mutex_unlock(&priv->reg_mutex);
1932 }
1933
1934 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1935 {
1936 struct rtl838x_switch_priv *priv = ds->priv;
1937 unsigned long features = 0;
1938 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1939 if (priv->r->enable_learning)
1940 features |= BR_LEARNING;
1941 if (priv->r->enable_flood)
1942 features |= BR_FLOOD;
1943 if (priv->r->enable_mcast_flood)
1944 features |= BR_MCAST_FLOOD;
1945 if (priv->r->enable_bcast_flood)
1946 features |= BR_BCAST_FLOOD;
1947 if (flags.mask & ~(features))
1948 return -EINVAL;
1949
1950 return 0;
1951 }
1952
1953 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1954 {
1955 struct rtl838x_switch_priv *priv = ds->priv;
1956
1957 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1958 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1959 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1960
1961 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1962 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1963
1964 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1965 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1966
1967 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1968 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1969
1970 return 0;
1971 }
1972
1973 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1974 struct net_device *lag,
1975 struct netdev_lag_upper_info *info)
1976 {
1977 int id;
1978
1979 id = dsa_lag_id(ds->dst, lag);
1980 if (id < 0 || id >= ds->num_lag_ids)
1981 return false;
1982
1983 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1984 return false;
1985 }
1986 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1987 return false;
1988
1989 return true;
1990 }
1991
1992 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
1993 {
1994 pr_debug("%s: %d\n", __func__, port);
1995 /* Nothing to be done... */
1996
1997 return 0;
1998 }
1999
2000 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2001 struct net_device *lag,
2002 struct netdev_lag_upper_info *info)
2003 {
2004 struct rtl838x_switch_priv *priv = ds->priv;
2005 int i, err = 0;
2006
2007 if (!rtl83xx_lag_can_offload(ds, lag, info))
2008 return -EOPNOTSUPP;
2009
2010 mutex_lock(&priv->reg_mutex);
2011
2012 for (i = 0; i < priv->n_lags; i++) {
2013 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2014 break;
2015 }
2016 if (port >= priv->cpu_port) {
2017 err = -EINVAL;
2018 goto out;
2019 }
2020 pr_info("port_lag_join: group %d, port %d\n",i, port);
2021 if (!priv->lag_devs[i])
2022 priv->lag_devs[i] = lag;
2023
2024 if (priv->lag_primary[i] == -1) {
2025 priv->lag_primary[i] = port;
2026 } else
2027 priv->is_lagmember[port] = 1;
2028
2029 priv->lagmembers |= (1ULL << port);
2030
2031 pr_debug("lag_members = %llX\n", priv->lagmembers);
2032 err = rtl83xx_lag_add(priv->ds, i, port, info);
2033 if (err) {
2034 err = -EINVAL;
2035 goto out;
2036 }
2037
2038 out:
2039 mutex_unlock(&priv->reg_mutex);
2040
2041 return err;
2042 }
2043
2044 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2045 struct net_device *lag)
2046 {
2047 int i, group = -1, err;
2048 struct rtl838x_switch_priv *priv = ds->priv;
2049
2050 mutex_lock(&priv->reg_mutex);
2051 for (i = 0; i < priv->n_lags; i++) {
2052 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2053 group = i;
2054 break;
2055 }
2056 }
2057
2058 if (group == -1) {
2059 pr_info("port_lag_leave: port %d is not a member\n", port);
2060 err = -EINVAL;
2061 goto out;
2062 }
2063
2064 if (port >= priv->cpu_port) {
2065 err = -EINVAL;
2066 goto out;
2067 }
2068 pr_info("port_lag_del: group %d, port %d\n",group, port);
2069 priv->lagmembers &=~ (1ULL << port);
2070 priv->lag_primary[i] = -1;
2071 priv->is_lagmember[port] = 0;
2072 pr_debug("lag_members = %llX\n", priv->lagmembers);
2073 err = rtl83xx_lag_del(priv->ds, group, port);
2074 if (err) {
2075 err = -EINVAL;
2076 goto out;
2077 }
2078 if (!priv->lags_port_members[i])
2079 priv->lag_devs[i] = NULL;
2080
2081 out:
2082 mutex_unlock(&priv->reg_mutex);
2083 return 0;
2084 }
2085
2086 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2087 {
2088 u32 val;
2089 u32 offset = 0;
2090 struct rtl838x_switch_priv *priv = ds->priv;
2091
2092 if ((phy_addr >= 24) &&
2093 (phy_addr <= 27) &&
2094 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2095 if (phy_addr == 26)
2096 offset = 0x100;
2097 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2098 return val;
2099 }
2100
2101 read_phy(phy_addr, 0, phy_reg, &val);
2102 return val;
2103 }
2104
2105 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2106 {
2107 u32 offset = 0;
2108 struct rtl838x_switch_priv *priv = ds->priv;
2109
2110 if ((phy_addr >= 24) &&
2111 (phy_addr <= 27) &&
2112 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2113 if (phy_addr == 26)
2114 offset = 0x100;
2115 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2116 return 0;
2117 }
2118 return write_phy(phy_addr, 0, phy_reg, val);
2119 }
2120
2121 const struct dsa_switch_ops rtl83xx_switch_ops = {
2122 .get_tag_protocol = rtl83xx_get_tag_protocol,
2123 .setup = rtl83xx_setup,
2124
2125 .phy_read = dsa_phy_read,
2126 .phy_write = dsa_phy_write,
2127
2128 .phylink_validate = rtl83xx_phylink_validate,
2129 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2130 .phylink_mac_config = rtl83xx_phylink_mac_config,
2131 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2132 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2133
2134 .get_strings = rtl83xx_get_strings,
2135 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2136 .get_sset_count = rtl83xx_get_sset_count,
2137
2138 .port_enable = rtl83xx_port_enable,
2139 .port_disable = rtl83xx_port_disable,
2140
2141 .get_mac_eee = rtl83xx_get_mac_eee,
2142 .set_mac_eee = rtl83xx_set_mac_eee,
2143
2144 .set_ageing_time = rtl83xx_set_ageing_time,
2145 .port_bridge_join = rtl83xx_port_bridge_join,
2146 .port_bridge_leave = rtl83xx_port_bridge_leave,
2147 .port_stp_state_set = rtl83xx_port_stp_state_set,
2148 .port_fast_age = rtl83xx_fast_age,
2149
2150 .port_vlan_filtering = rtl83xx_vlan_filtering,
2151 .port_vlan_add = rtl83xx_vlan_add,
2152 .port_vlan_del = rtl83xx_vlan_del,
2153
2154 .port_fdb_add = rtl83xx_port_fdb_add,
2155 .port_fdb_del = rtl83xx_port_fdb_del,
2156 .port_fdb_dump = rtl83xx_port_fdb_dump,
2157
2158 .port_mdb_add = rtl83xx_port_mdb_add,
2159 .port_mdb_del = rtl83xx_port_mdb_del,
2160
2161 .port_mirror_add = rtl83xx_port_mirror_add,
2162 .port_mirror_del = rtl83xx_port_mirror_del,
2163
2164 .port_lag_change = rtl83xx_port_lag_change,
2165 .port_lag_join = rtl83xx_port_lag_join,
2166 .port_lag_leave = rtl83xx_port_lag_leave,
2167
2168 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2169 .port_bridge_flags = rtl83xx_port_bridge_flags,
2170 };
2171
2172 const struct dsa_switch_ops rtl930x_switch_ops = {
2173 .get_tag_protocol = rtl83xx_get_tag_protocol,
2174 .setup = rtl93xx_setup,
2175
2176 .phy_read = dsa_phy_read,
2177 .phy_write = dsa_phy_write,
2178
2179 .phylink_validate = rtl93xx_phylink_validate,
2180 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2181 .phylink_mac_config = rtl93xx_phylink_mac_config,
2182 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2183 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2184
2185 .get_strings = rtl83xx_get_strings,
2186 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2187 .get_sset_count = rtl83xx_get_sset_count,
2188
2189 .port_enable = rtl83xx_port_enable,
2190 .port_disable = rtl83xx_port_disable,
2191
2192 .get_mac_eee = rtl93xx_get_mac_eee,
2193 .set_mac_eee = rtl83xx_set_mac_eee,
2194
2195 .set_ageing_time = rtl83xx_set_ageing_time,
2196 .port_bridge_join = rtl83xx_port_bridge_join,
2197 .port_bridge_leave = rtl83xx_port_bridge_leave,
2198 .port_stp_state_set = rtl83xx_port_stp_state_set,
2199 .port_fast_age = rtl930x_fast_age,
2200
2201 .port_vlan_filtering = rtl83xx_vlan_filtering,
2202 .port_vlan_add = rtl83xx_vlan_add,
2203 .port_vlan_del = rtl83xx_vlan_del,
2204
2205 .port_fdb_add = rtl83xx_port_fdb_add,
2206 .port_fdb_del = rtl83xx_port_fdb_del,
2207 .port_fdb_dump = rtl83xx_port_fdb_dump,
2208
2209 .port_mdb_add = rtl83xx_port_mdb_add,
2210 .port_mdb_del = rtl83xx_port_mdb_del,
2211
2212 .port_lag_change = rtl83xx_port_lag_change,
2213 .port_lag_join = rtl83xx_port_lag_join,
2214 .port_lag_leave = rtl83xx_port_lag_leave,
2215
2216 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2217 .port_bridge_flags = rtl83xx_port_bridge_flags,
2218 };
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