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df78aa3737fa0facf94e8dc76e82664424b381fc
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
12 {
13 mutex_lock(&priv->reg_mutex);
14
15 /* Enable statistics module: all counters plus debug.
16 * On RTL839x all counters are enabled by default
17 */
18 if (priv->family_id == RTL8380_FAMILY_ID)
19 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
20
21 /* Reset statistics counters */
22 sw_w32_mask(0, 1, priv->r->stat_rst);
23
24 mutex_unlock(&priv->reg_mutex);
25 }
26
27 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
28 {
29 u64 v = 0;
30
31 msleep(1000);
32 /* Enable all ports with a PHY, including the SFP-ports */
33 for (int i = 0; i < priv->cpu_port; i++) {
34 if (priv->ports[i].phy)
35 v |= BIT_ULL(i);
36 }
37
38 pr_info("%s: %16llx\n", __func__, v);
39 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
40
41 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
42 if (priv->family_id == RTL8390_FAMILY_ID)
43 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
44 else if(priv->family_id == RTL9300_FAMILY_ID)
45 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
46 }
47
48 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
49 MIB_DESC(2, 0xf8, "ifInOctets"),
50 MIB_DESC(2, 0xf0, "ifOutOctets"),
51 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
52 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
53 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
54 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
55 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
56 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
57 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
58 MIB_DESC(1, 0xd0, "ifOutDiscards"),
59 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
60 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
61 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
62 MIB_DESC(1, 0xc0, ".3LateCollisions"),
63 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
64 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
65 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
66 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
67 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
68 MIB_DESC(1, 0xa8, "DropEvents"),
69 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
70 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
71 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
72 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
73 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
74 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
75 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
76 MIB_DESC(1, 0x88, "rx_OversizePkts"),
77 MIB_DESC(1, 0x84, "Fragments"),
78 MIB_DESC(1, 0x80, "Jabbers"),
79 MIB_DESC(1, 0x7c, "Collisions"),
80 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
81 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
82 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
83 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
85 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
87 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
89 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
91 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
92 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
93 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x40, "rxMacDiscards")
95 };
96
97
98 /* DSA callbacks */
99
100
101 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
102 int port,
103 enum dsa_tag_protocol mprot)
104 {
105 /* The switch does not tag the frames, instead internally the header
106 * structure for each packet is tagged accordingly.
107 */
108 return DSA_TAG_PROTO_TRAILER;
109 }
110
111 /* Initialize all VLANS */
112 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
113 {
114 struct rtl838x_vlan_info info;
115
116 pr_info("In %s\n", __func__);
117
118 priv->r->vlan_profile_setup(0);
119 priv->r->vlan_profile_setup(1);
120 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
121 priv->r->vlan_profile_dump(0);
122
123 info.fid = 0; /* Default Forwarding ID / MSTI */
124 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
125 info.hash_mc_fid = false; /* Do the same for Multicast packets */
126 info.profile_id = 0; /* Use default Vlan Profile 0 */
127 info.tagged_ports = 0; /* Initially no port members */
128 if (priv->family_id == RTL9310_FAMILY_ID) {
129 info.if_id = 0;
130 info.multicast_grp_mask = 0;
131 info.l2_tunnel_list_id = -1;
132 }
133
134 /* Initialize all vlans 0-4095 */
135 for (int i = 0; i < MAX_VLANS; i ++)
136 priv->r->vlan_set_tagged(i, &info);
137
138 /* reset PVIDs; defaults to 1 on reset */
139 for (int i = 0; i <= priv->ds->num_ports; i++) {
140 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
142 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 }
145
146 /* Set forwarding action based on inner VLAN tag */
147 for (int i = 0; i < priv->cpu_port; i++)
148 priv->r->vlan_fwd_on_inner(i, true);
149 }
150
151 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
152 {
153 for (int i = 0; i < priv->cpu_port; i++)
154 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
155 }
156
157 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
158 int port, bool enable)
159 {
160 int shift = SALRN_PORT_SHIFT(port);
161 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
162
163 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
164 priv->r->l2_port_new_salrn(port));
165 }
166
167 static int rtl83xx_setup(struct dsa_switch *ds)
168 {
169 struct rtl838x_switch_priv *priv = ds->priv;
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (int i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Configure ports so they are disabled by default, but once enabled
181 * they will work in isolated mode (only traffic between port and CPU).
182 */
183 for (int i = 0; i < priv->cpu_port; i++) {
184 if (priv->ports[i].phy) {
185 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
186 priv->r->traffic_set(i, BIT_ULL(i));
187 }
188 }
189 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
190
191 /* For standalone ports, forward packets even if a static fdb
192 * entry for the source address exists on another port.
193 */
194 if (priv->r->set_static_move_action) {
195 for (int i = 0; i <= priv->cpu_port; i++)
196 priv->r->set_static_move_action(i, true);
197 }
198
199 if (priv->family_id == RTL8380_FAMILY_ID)
200 rtl838x_print_matrix();
201 else
202 rtl839x_print_matrix();
203
204 rtl83xx_init_stats(priv);
205
206 rtl83xx_vlan_setup(priv);
207
208 rtl83xx_setup_bpdu_traps(priv);
209
210 ds->configure_vlan_while_not_filtering = true;
211
212 priv->r->l2_learning_setup();
213
214 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
215 ds->assisted_learning_on_cpu_port = true;
216
217 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
218 * 0: FWD, 1: DROP, 2: TRAP2CPU
219 */
220 if (priv->family_id == RTL8380_FAMILY_ID)
221 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
222 else
223 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
224
225 /* Enable MAC Polling PHY again */
226 rtl83xx_enable_phy_polling(priv);
227 pr_debug("Please wait until PHY is settled\n");
228 msleep(1000);
229 priv->r->pie_init(priv);
230
231 return 0;
232 }
233
234 static int rtl93xx_setup(struct dsa_switch *ds)
235 {
236 struct rtl838x_switch_priv *priv = ds->priv;
237
238 pr_info("%s called\n", __func__);
239
240 /* Disable MAC polling the PHY so that we can start configuration */
241 if (priv->family_id == RTL9300_FAMILY_ID)
242 sw_w32(0, RTL930X_SMI_POLL_CTRL);
243
244 if (priv->family_id == RTL9310_FAMILY_ID) {
245 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
247 }
248
249 /* Disable all ports except CPU port */
250 for (int i = 0; i < ds->num_ports; i++)
251 priv->ports[i].enable = false;
252 priv->ports[priv->cpu_port].enable = true;
253
254 /* Configure ports so they are disabled by default, but once enabled
255 * they will work in isolated mode (only traffic between port and CPU).
256 */
257 for (int i = 0; i < priv->cpu_port; i++) {
258 if (priv->ports[i].phy) {
259 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
260 priv->r->traffic_set(i, BIT_ULL(i));
261 }
262 }
263 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
264
265 rtl930x_print_matrix();
266
267 /* TODO: Initialize statistics */
268
269 rtl83xx_vlan_setup(priv);
270
271 ds->configure_vlan_while_not_filtering = true;
272
273 priv->r->l2_learning_setup();
274
275 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
276 ds->assisted_learning_on_cpu_port = true;
277
278 rtl83xx_enable_phy_polling(priv);
279
280 priv->r->pie_init(priv);
281
282 priv->r->led_init(priv);
283
284 return 0;
285 }
286
287 static int rtl93xx_get_sds(struct phy_device *phydev)
288 {
289 struct device *dev = &phydev->mdio.dev;
290 struct device_node *dn;
291 u32 sds_num;
292
293 if (!dev)
294 return -1;
295 if (dev->of_node) {
296 dn = dev->of_node;
297 if (of_property_read_u32(dn, "sds", &sds_num))
298 sds_num = -1;
299 } else {
300 dev_err(dev, "No DT node.\n");
301 return -1;
302 }
303
304 return sds_num;
305 }
306
307 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
308 unsigned long *supported,
309 struct phylink_link_state *state)
310 {
311 struct rtl838x_switch_priv *priv = ds->priv;
312 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
313
314 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
315
316 if (!phy_interface_mode_is_rgmii(state->interface) &&
317 state->interface != PHY_INTERFACE_MODE_NA &&
318 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
319 state->interface != PHY_INTERFACE_MODE_MII &&
320 state->interface != PHY_INTERFACE_MODE_REVMII &&
321 state->interface != PHY_INTERFACE_MODE_GMII &&
322 state->interface != PHY_INTERFACE_MODE_QSGMII &&
323 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
324 state->interface != PHY_INTERFACE_MODE_SGMII) {
325 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
326 dev_err(ds->dev,
327 "Unsupported interface: %d for port %d\n",
328 state->interface, port);
329 return;
330 }
331
332 /* Allow all the expected bits */
333 phylink_set(mask, Autoneg);
334 phylink_set_port_modes(mask);
335 phylink_set(mask, Pause);
336 phylink_set(mask, Asym_Pause);
337
338 /* With the exclusion of MII and Reverse MII, we support Gigabit,
339 * including Half duplex
340 */
341 if (state->interface != PHY_INTERFACE_MODE_MII &&
342 state->interface != PHY_INTERFACE_MODE_REVMII) {
343 phylink_set(mask, 1000baseT_Full);
344 phylink_set(mask, 1000baseT_Half);
345 }
346
347 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
348 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
349 phylink_set(mask, 1000baseX_Full);
350
351 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
352 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
353 phylink_set(mask, 1000baseX_Full);
354
355 phylink_set(mask, 10baseT_Half);
356 phylink_set(mask, 10baseT_Full);
357 phylink_set(mask, 100baseT_Half);
358 phylink_set(mask, 100baseT_Full);
359
360 bitmap_and(supported, supported, mask,
361 __ETHTOOL_LINK_MODE_MASK_NBITS);
362 bitmap_and(state->advertising, state->advertising, mask,
363 __ETHTOOL_LINK_MODE_MASK_NBITS);
364 }
365
366 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
367 unsigned long *supported,
368 struct phylink_link_state *state)
369 {
370 struct rtl838x_switch_priv *priv = ds->priv;
371 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
372
373 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
374 phy_modes(state->interface));
375
376 if (!phy_interface_mode_is_rgmii(state->interface) &&
377 state->interface != PHY_INTERFACE_MODE_NA &&
378 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
379 state->interface != PHY_INTERFACE_MODE_MII &&
380 state->interface != PHY_INTERFACE_MODE_REVMII &&
381 state->interface != PHY_INTERFACE_MODE_GMII &&
382 state->interface != PHY_INTERFACE_MODE_QSGMII &&
383 state->interface != PHY_INTERFACE_MODE_XGMII &&
384 state->interface != PHY_INTERFACE_MODE_HSGMII &&
385 state->interface != PHY_INTERFACE_MODE_10GBASER &&
386 state->interface != PHY_INTERFACE_MODE_10GKR &&
387 state->interface != PHY_INTERFACE_MODE_USXGMII &&
388 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
389 state->interface != PHY_INTERFACE_MODE_SGMII) {
390 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
391 dev_err(ds->dev,
392 "Unsupported interface: %d for port %d\n",
393 state->interface, port);
394 return;
395 }
396
397 /* Allow all the expected bits */
398 phylink_set(mask, Autoneg);
399 phylink_set_port_modes(mask);
400 phylink_set(mask, Pause);
401 phylink_set(mask, Asym_Pause);
402
403 /* With the exclusion of MII and Reverse MII, we support Gigabit,
404 * including Half duplex
405 */
406 if (state->interface != PHY_INTERFACE_MODE_MII &&
407 state->interface != PHY_INTERFACE_MODE_REVMII) {
408 phylink_set(mask, 1000baseT_Full);
409 phylink_set(mask, 1000baseT_Half);
410 }
411
412 /* Internal phys of the RTL93xx family provide 10G */
413 if (priv->ports[port].phy_is_integrated &&
414 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
415 phylink_set(mask, 1000baseX_Full);
416 } else if (priv->ports[port].phy_is_integrated) {
417 phylink_set(mask, 1000baseX_Full);
418 phylink_set(mask, 10000baseKR_Full);
419 phylink_set(mask, 10000baseSR_Full);
420 phylink_set(mask, 10000baseCR_Full);
421 }
422 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
423 phylink_set(mask, 1000baseX_Full);
424 phylink_set(mask, 1000baseT_Full);
425 phylink_set(mask, 10000baseKR_Full);
426 phylink_set(mask, 10000baseT_Full);
427 phylink_set(mask, 10000baseSR_Full);
428 phylink_set(mask, 10000baseCR_Full);
429 }
430
431 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
432 phylink_set(mask, 10000baseT_Full);
433
434 phylink_set(mask, 10baseT_Half);
435 phylink_set(mask, 10baseT_Full);
436 phylink_set(mask, 100baseT_Half);
437 phylink_set(mask, 100baseT_Full);
438
439 bitmap_and(supported, supported, mask,
440 __ETHTOOL_LINK_MODE_MASK_NBITS);
441 bitmap_and(state->advertising, state->advertising, mask,
442 __ETHTOOL_LINK_MODE_MASK_NBITS);
443 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
444 }
445
446 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
447 struct phylink_link_state *state)
448 {
449 struct rtl838x_switch_priv *priv = ds->priv;
450 u64 speed;
451 u64 link;
452
453 if (port < 0 || port > priv->cpu_port)
454 return -EINVAL;
455
456 state->link = 0;
457 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
458 if (link & BIT_ULL(port))
459 state->link = 1;
460 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
461
462 state->duplex = 0;
463 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
464 state->duplex = 1;
465
466 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
467 speed >>= (port % 16) << 1;
468 switch (speed & 0x3) {
469 case 0:
470 state->speed = SPEED_10;
471 break;
472 case 1:
473 state->speed = SPEED_100;
474 break;
475 case 2:
476 state->speed = SPEED_1000;
477 break;
478 case 3:
479 if (priv->family_id == RTL9300_FAMILY_ID
480 && (port == 24 || port == 26)) /* Internal serdes */
481 state->speed = SPEED_2500;
482 else
483 state->speed = SPEED_100; /* Is in fact 500Mbit */
484 }
485
486 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
487 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
488 state->pause |= MLO_PAUSE_RX;
489 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
490 state->pause |= MLO_PAUSE_TX;
491
492 return 1;
493 }
494
495 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
496 struct phylink_link_state *state)
497 {
498 struct rtl838x_switch_priv *priv = ds->priv;
499 u64 speed;
500 u64 link;
501 u64 media;
502
503 if (port < 0 || port > priv->cpu_port)
504 return -EINVAL;
505
506 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
507 * state needs to be read twice in order to read a correct result.
508 * This would not be necessary for ports connected e.g. to RTL8218D
509 * PHYs.
510 */
511 state->link = 0;
512 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
513 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
514 if (link & BIT_ULL(port))
515 state->link = 1;
516
517 if (priv->family_id == RTL9310_FAMILY_ID)
518 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
519
520 if (priv->family_id == RTL9300_FAMILY_ID)
521 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
522
523 if (media & BIT_ULL(port))
524 state->link = 1;
525
526 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
527 link & BIT_ULL(port), media);
528
529 state->duplex = 0;
530 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
531 state->duplex = 1;
532
533 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
534 speed >>= (port % 8) << 2;
535 switch (speed & 0xf) {
536 case 0:
537 state->speed = SPEED_10;
538 break;
539 case 1:
540 state->speed = SPEED_100;
541 break;
542 case 2:
543 case 7:
544 state->speed = SPEED_1000;
545 break;
546 case 4:
547 state->speed = SPEED_10000;
548 break;
549 case 5:
550 case 8:
551 state->speed = SPEED_2500;
552 break;
553 case 6:
554 state->speed = SPEED_5000;
555 break;
556 default:
557 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
558 }
559
560 if (priv->family_id == RTL9310_FAMILY_ID
561 && (port >= 52 || port <= 55)) { /* Internal serdes */
562 state->speed = SPEED_10000;
563 state->link = 1;
564 state->duplex = 1;
565 }
566
567 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
568 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
569 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
570 state->pause |= MLO_PAUSE_RX;
571 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
572 state->pause |= MLO_PAUSE_TX;
573
574 return 1;
575 }
576
577 static void rtl83xx_config_interface(int port, phy_interface_t interface)
578 {
579 u32 old, int_shift, sds_shift;
580
581 switch (port) {
582 case 24:
583 int_shift = 0;
584 sds_shift = 5;
585 break;
586 case 26:
587 int_shift = 3;
588 sds_shift = 0;
589 break;
590 default:
591 return;
592 }
593
594 old = sw_r32(RTL838X_SDS_MODE_SEL);
595 switch (interface) {
596 case PHY_INTERFACE_MODE_1000BASEX:
597 if ((old >> sds_shift & 0x1f) == 4)
598 return;
599 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
600 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
601 break;
602 case PHY_INTERFACE_MODE_SGMII:
603 if ((old >> sds_shift & 0x1f) == 2)
604 return;
605 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
606 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
607 break;
608 default:
609 return;
610 }
611 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
612 }
613
614 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
615 unsigned int mode,
616 const struct phylink_link_state *state)
617 {
618 struct rtl838x_switch_priv *priv = ds->priv;
619 u32 reg;
620 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
621
622 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
623
624 if (port == priv->cpu_port) {
625 /* Set Speed, duplex, flow control
626 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
627 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
628 * | MEDIA_SEL
629 */
630 if (priv->family_id == RTL8380_FAMILY_ID) {
631 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
632 /* allow CRC errors on CPU-port */
633 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
634 } else {
635 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
636 }
637 return;
638 }
639
640 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
641 /* Auto-Negotiation does not work for MAC in RTL8390 */
642 if (priv->family_id == RTL8380_FAMILY_ID) {
643 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
644 pr_debug("PHY autonegotiates\n");
645 reg |= RTL838X_NWAY_EN;
646 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
647 rtl83xx_config_interface(port, state->interface);
648 return;
649 }
650 }
651
652 if (mode != MLO_AN_FIXED)
653 pr_debug("Fixed state.\n");
654
655 /* Clear id_mode_dis bit, and the existing port mode, let
656 * RGMII_MODE_EN bet set by mac_link_{up,down} */
657 if (priv->family_id == RTL8380_FAMILY_ID) {
658 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
659 if (state->pause & MLO_PAUSE_TXRX_MASK) {
660 if (state->pause & MLO_PAUSE_TX)
661 reg |= RTL838X_TX_PAUSE_EN;
662 reg |= RTL838X_RX_PAUSE_EN;
663 }
664 } else if (priv->family_id == RTL8390_FAMILY_ID) {
665 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
666 if (state->pause & MLO_PAUSE_TXRX_MASK) {
667 if (state->pause & MLO_PAUSE_TX)
668 reg |= RTL839X_TX_PAUSE_EN;
669 reg |= RTL839X_RX_PAUSE_EN;
670 }
671 }
672
673
674 reg &= ~(3 << speed_bit);
675 switch (state->speed) {
676 case SPEED_1000:
677 reg |= 2 << speed_bit;
678 break;
679 case SPEED_100:
680 reg |= 1 << speed_bit;
681 break;
682 default:
683 break; /* Ignore, including 10MBit which has a speed value of 0 */
684 }
685
686 if (priv->family_id == RTL8380_FAMILY_ID) {
687 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
688 if (state->link)
689 reg |= RTL838X_FORCE_LINK_EN;
690 if (state->duplex == RTL838X_DUPLEX_MODE)
691 reg |= RTL838X_DUPLEX_MODE;
692 } else if (priv->family_id == RTL8390_FAMILY_ID) {
693 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
694 if (state->link)
695 reg |= RTL839X_FORCE_LINK_EN;
696 if (state->duplex == RTL839X_DUPLEX_MODE)
697 reg |= RTL839X_DUPLEX_MODE;
698 }
699
700 /* LAG members must use DUPLEX and we need to enable the link */
701 if (priv->lagmembers & BIT_ULL(port)) {
702 switch(priv->family_id) {
703 case RTL8380_FAMILY_ID:
704 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
705 break;
706 case RTL8390_FAMILY_ID:
707 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
708 break;
709 }
710 }
711
712 /* Disable AN */
713 if (priv->family_id == RTL8380_FAMILY_ID)
714 reg &= ~RTL838X_NWAY_EN;
715 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
716 }
717
718 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
719 unsigned int mode,
720 const struct phylink_link_state *state)
721 {
722 struct rtl838x_switch_priv *priv = ds->priv;
723 int sds_num;
724 u32 reg, band;
725
726 sds_num = priv->ports[port].sds_num;
727 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
728
729 switch (state->interface) {
730 case PHY_INTERFACE_MODE_HSGMII:
731 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
732 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
733 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
734 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
735 break;
736 case PHY_INTERFACE_MODE_1000BASEX:
737 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
738 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
739 break;
740 case PHY_INTERFACE_MODE_XGMII:
741 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
742 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
743 break;
744 case PHY_INTERFACE_MODE_10GBASER:
745 case PHY_INTERFACE_MODE_10GKR:
746 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
747 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
748 break;
749 case PHY_INTERFACE_MODE_USXGMII:
750 /* Translates to MII_USXGMII_10GSXGMII */
751 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
752 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
753 break;
754 case PHY_INTERFACE_MODE_SGMII:
755 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
756 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
757 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
758 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
759 break;
760 case PHY_INTERFACE_MODE_QSGMII:
761 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
762 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
763 break;
764 default:
765 pr_err("%s: unknown serdes mode: %s\n",
766 __func__, phy_modes(state->interface));
767 return;
768 }
769
770 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
771 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
772
773 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
774
775 reg &= ~(0xf << 12);
776 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
777
778 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
779
780 if (priv->lagmembers & BIT_ULL(port))
781 reg |= RTL931X_DUPLEX_MODE;
782
783 if (state->duplex == DUPLEX_FULL)
784 reg |= RTL931X_DUPLEX_MODE;
785
786 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
787
788 }
789
790 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
791 unsigned int mode,
792 const struct phylink_link_state *state)
793 {
794 struct rtl838x_switch_priv *priv = ds->priv;
795 int sds_num, sds_mode;
796 u32 reg;
797
798 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
799 port, mode, phy_modes(state->interface), state->speed, state->link);
800
801 /* Nothing to be done for the CPU-port */
802 if (port == priv->cpu_port)
803 return;
804
805 if (priv->family_id == RTL9310_FAMILY_ID)
806 return rtl931x_phylink_mac_config(ds, port, mode, state);
807
808 sds_num = priv->ports[port].sds_num;
809 pr_info("%s SDS is %d\n", __func__, sds_num);
810 if (sds_num >= 0) {
811 switch (state->interface) {
812 case PHY_INTERFACE_MODE_HSGMII:
813 sds_mode = 0x12;
814 break;
815 case PHY_INTERFACE_MODE_1000BASEX:
816 sds_mode = 0x04;
817 break;
818 case PHY_INTERFACE_MODE_XGMII:
819 sds_mode = 0x10;
820 break;
821 case PHY_INTERFACE_MODE_10GBASER:
822 case PHY_INTERFACE_MODE_10GKR:
823 sds_mode = 0x1b; /* 10G 1000X Auto */
824 break;
825 case PHY_INTERFACE_MODE_USXGMII:
826 sds_mode = 0x0d;
827 break;
828 default:
829 pr_err("%s: unknown serdes mode: %s\n",
830 __func__, phy_modes(state->interface));
831 return;
832 }
833 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
834 rtl9300_serdes_setup(sds_num, state->interface);
835 }
836
837 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
838 reg &= ~(0xf << 3);
839
840 switch (state->speed) {
841 case SPEED_10000:
842 reg |= 4 << 3;
843 break;
844 case SPEED_5000:
845 reg |= 6 << 3;
846 break;
847 case SPEED_2500:
848 reg |= 5 << 3;
849 break;
850 case SPEED_1000:
851 reg |= 2 << 3;
852 break;
853 default:
854 reg |= 2 << 3;
855 break;
856 }
857
858 if (state->link)
859 reg |= RTL930X_FORCE_LINK_EN;
860
861 if (priv->lagmembers & BIT_ULL(port))
862 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
863
864 if (state->duplex == DUPLEX_FULL)
865 reg |= RTL930X_DUPLEX_MODE;
866
867 if (priv->ports[port].phy_is_integrated)
868 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
869 else
870 reg |= RTL930X_FORCE_EN;
871
872 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
873 }
874
875 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
876 unsigned int mode,
877 phy_interface_t interface)
878 {
879 struct rtl838x_switch_priv *priv = ds->priv;
880
881 /* Stop TX/RX to port */
882 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
883
884 /* No longer force link */
885 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
886 }
887
888 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
889 unsigned int mode,
890 phy_interface_t interface)
891 {
892 struct rtl838x_switch_priv *priv = ds->priv;
893 u32 v = 0;
894
895 /* Stop TX/RX to port */
896 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
897
898 /* No longer force link */
899 if (priv->family_id == RTL9300_FAMILY_ID)
900 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
901 else if (priv->family_id == RTL9310_FAMILY_ID)
902 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
903 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
904 }
905
906 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
907 unsigned int mode,
908 phy_interface_t interface,
909 struct phy_device *phydev,
910 int speed, int duplex,
911 bool tx_pause, bool rx_pause)
912 {
913 struct rtl838x_switch_priv *priv = ds->priv;
914 /* Restart TX/RX to port */
915 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
916 /* TODO: Set speed/duplex/pauses */
917 }
918
919 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
920 unsigned int mode,
921 phy_interface_t interface,
922 struct phy_device *phydev,
923 int speed, int duplex,
924 bool tx_pause, bool rx_pause)
925 {
926 struct rtl838x_switch_priv *priv = ds->priv;
927
928 /* Restart TX/RX to port */
929 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
930 /* TODO: Set speed/duplex/pauses */
931 }
932
933 static void rtl83xx_get_strings(struct dsa_switch *ds,
934 int port, u32 stringset, u8 *data)
935 {
936 if (stringset != ETH_SS_STATS)
937 return;
938
939 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
940 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
941 ETH_GSTRING_LEN);
942 }
943
944 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
945 uint64_t *data)
946 {
947 struct rtl838x_switch_priv *priv = ds->priv;
948 const struct rtl83xx_mib_desc *mib;
949 u64 h;
950
951 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
952 mib = &rtl83xx_mib[i];
953
954 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
955 if (mib->size == 2) {
956 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
957 data[i] |= h << 32;
958 }
959 }
960 }
961
962 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
963 {
964 if (sset != ETH_SS_STATS)
965 return 0;
966
967 return ARRAY_SIZE(rtl83xx_mib);
968 }
969
970 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
971 {
972 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
973 u64 portmask;
974
975 if (mc_group >= MAX_MC_GROUPS - 1)
976 return -1;
977
978 if (priv->is_lagmember[port]) {
979 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
980 return 0;
981 }
982
983 set_bit(mc_group, priv->mc_group_bm);
984 portmask = BIT_ULL(port);
985 priv->r->write_mcast_pmask(mc_group, portmask);
986
987 return mc_group;
988 }
989
990 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
991 {
992 u64 portmask = priv->r->read_mcast_pmask(mc_group);
993
994 pr_debug("%s: %d\n", __func__, port);
995 if (priv->is_lagmember[port]) {
996 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
997 return portmask;
998 }
999 portmask |= BIT_ULL(port);
1000 priv->r->write_mcast_pmask(mc_group, portmask);
1001
1002 return portmask;
1003 }
1004
1005 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1006 {
1007 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1008
1009 pr_debug("%s: %d\n", __func__, port);
1010 if (priv->is_lagmember[port]) {
1011 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1012 return portmask;
1013 }
1014 portmask &= ~BIT_ULL(port);
1015 priv->r->write_mcast_pmask(mc_group, portmask);
1016 if (!portmask)
1017 clear_bit(mc_group, priv->mc_group_bm);
1018
1019 return portmask;
1020 }
1021
1022 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1023 struct phy_device *phydev)
1024 {
1025 struct rtl838x_switch_priv *priv = ds->priv;
1026 u64 v;
1027
1028 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1029 priv->ports[port].enable = true;
1030
1031 /* enable inner tagging on egress, do not keep any tags */
1032 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1033
1034 if (dsa_is_cpu_port(ds, port))
1035 return 0;
1036
1037 /* add port to switch mask of CPU_PORT */
1038 priv->r->traffic_enable(priv->cpu_port, port);
1039
1040 if (priv->is_lagmember[port]) {
1041 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1042 return 0;
1043 }
1044
1045 /* add all other ports in the same bridge to switch mask of port */
1046 v = priv->r->traffic_get(port);
1047 v |= priv->ports[port].pm;
1048 priv->r->traffic_set(port, v);
1049
1050 /* TODO: Figure out if this is necessary */
1051 if (priv->family_id == RTL9300_FAMILY_ID) {
1052 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1053 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1054 }
1055
1056 if (priv->ports[port].sds_num < 0)
1057 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1058
1059 return 0;
1060 }
1061
1062 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1063 {
1064 struct rtl838x_switch_priv *priv = ds->priv;
1065 u64 v;
1066
1067 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1068 /* you can only disable user ports */
1069 if (!dsa_is_user_port(ds, port))
1070 return;
1071
1072 /* BUG: This does not work on RTL931X */
1073 /* remove port from switch mask of CPU_PORT */
1074 priv->r->traffic_disable(priv->cpu_port, port);
1075
1076 /* remove all other ports in the same bridge from switch mask of port */
1077 v = priv->r->traffic_get(port);
1078 v &= ~priv->ports[port].pm;
1079 priv->r->traffic_set(port, v);
1080
1081 priv->ports[port].enable = false;
1082 }
1083
1084 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1085 struct ethtool_eee *e)
1086 {
1087 struct rtl838x_switch_priv *priv = ds->priv;
1088
1089 if (e->eee_enabled && !priv->eee_enabled) {
1090 pr_info("Globally enabling EEE\n");
1091 priv->r->init_eee(priv, true);
1092 }
1093
1094 priv->r->port_eee_set(priv, port, e->eee_enabled);
1095
1096 if (e->eee_enabled)
1097 pr_info("Enabled EEE for port %d\n", port);
1098 else
1099 pr_info("Disabled EEE for port %d\n", port);
1100
1101 return 0;
1102 }
1103
1104 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1105 struct ethtool_eee *e)
1106 {
1107 struct rtl838x_switch_priv *priv = ds->priv;
1108
1109 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1110
1111 priv->r->eee_port_ability(priv, e, port);
1112
1113 e->eee_enabled = priv->ports[port].eee_enabled;
1114
1115 e->eee_active = !!(e->advertised & e->lp_advertised);
1116
1117 return 0;
1118 }
1119
1120 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1121 struct ethtool_eee *e)
1122 {
1123 struct rtl838x_switch_priv *priv = ds->priv;
1124
1125 e->supported = SUPPORTED_100baseT_Full |
1126 SUPPORTED_1000baseT_Full |
1127 SUPPORTED_2500baseX_Full;
1128
1129 priv->r->eee_port_ability(priv, e, port);
1130
1131 e->eee_enabled = priv->ports[port].eee_enabled;
1132
1133 e->eee_active = !!(e->advertised & e->lp_advertised);
1134
1135 return 0;
1136 }
1137
1138 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1139 {
1140 struct rtl838x_switch_priv *priv = ds->priv;
1141
1142 priv->r->set_ageing_time(msec);
1143
1144 return 0;
1145 }
1146
1147 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1148 struct net_device *bridge)
1149 {
1150 struct rtl838x_switch_priv *priv = ds->priv;
1151 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1152
1153 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1154
1155 if (priv->is_lagmember[port]) {
1156 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1157 return 0;
1158 }
1159
1160 mutex_lock(&priv->reg_mutex);
1161 for (int i = 0; i < ds->num_ports; i++) {
1162 /* Add this port to the port matrix of the other ports in the
1163 * same bridge. If the port is disabled, port matrix is kept
1164 * and not being setup until the port becomes enabled.
1165 */
1166 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1167 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1168 continue;
1169 if (priv->ports[i].enable)
1170 priv->r->traffic_enable(i, port);
1171
1172 priv->ports[i].pm |= BIT_ULL(port);
1173 port_bitmap |= BIT_ULL(i);
1174 }
1175 }
1176
1177 /* Add all other ports to this port matrix. */
1178 if (priv->ports[port].enable) {
1179 priv->r->traffic_enable(priv->cpu_port, port);
1180 v = priv->r->traffic_get(port);
1181 v |= port_bitmap;
1182 priv->r->traffic_set(port, v);
1183 }
1184 priv->ports[port].pm |= port_bitmap;
1185
1186 if (priv->r->set_static_move_action)
1187 priv->r->set_static_move_action(port, false);
1188
1189 mutex_unlock(&priv->reg_mutex);
1190
1191 return 0;
1192 }
1193
1194 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1195 struct net_device *bridge)
1196 {
1197 struct rtl838x_switch_priv *priv = ds->priv;
1198 u64 port_bitmap = 0, v;
1199
1200 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1201 mutex_lock(&priv->reg_mutex);
1202 for (int i = 0; i < ds->num_ports; i++) {
1203 /* Remove this port from the port matrix of the other ports
1204 * in the same bridge. If the port is disabled, port matrix
1205 * is kept and not being setup until the port becomes enabled.
1206 * And the other port's port matrix cannot be broken when the
1207 * other port is still a VLAN-aware port.
1208 */
1209 if (dsa_is_user_port(ds, i) && i != port) {
1210 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1211 continue;
1212 if (priv->ports[i].enable)
1213 priv->r->traffic_disable(i, port);
1214
1215 priv->ports[i].pm &= ~BIT_ULL(port);
1216 port_bitmap |= BIT_ULL(i);
1217 }
1218 }
1219
1220 /* Remove all other ports from this port matrix. */
1221 if (priv->ports[port].enable) {
1222 v = priv->r->traffic_get(port);
1223 v &= ~port_bitmap;
1224 priv->r->traffic_set(port, v);
1225 }
1226 priv->ports[port].pm &= ~port_bitmap;
1227
1228 if (priv->r->set_static_move_action)
1229 priv->r->set_static_move_action(port, true);
1230
1231 mutex_unlock(&priv->reg_mutex);
1232 }
1233
1234 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1235 {
1236 u32 msti = 0;
1237 u32 port_state[4];
1238 int index, bit;
1239 int pos = port;
1240 struct rtl838x_switch_priv *priv = ds->priv;
1241 int n = priv->port_width << 1;
1242
1243 /* Ports above or equal CPU port can never be configured */
1244 if (port >= priv->cpu_port)
1245 return;
1246
1247 mutex_lock(&priv->reg_mutex);
1248
1249 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1250 * have 64 bit fields, 839x and 931x have 128 bit fields
1251 */
1252 if (priv->family_id == RTL8390_FAMILY_ID)
1253 pos += 12;
1254 if (priv->family_id == RTL9300_FAMILY_ID)
1255 pos += 3;
1256 if (priv->family_id == RTL9310_FAMILY_ID)
1257 pos += 8;
1258
1259 index = n - (pos >> 4) - 1;
1260 bit = (pos << 1) % 32;
1261
1262 priv->r->stp_get(priv, msti, port_state);
1263
1264 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1265 port_state[index] &= ~(3 << bit);
1266
1267 switch (state) {
1268 case BR_STATE_DISABLED: /* 0 */
1269 port_state[index] |= (0 << bit);
1270 break;
1271 case BR_STATE_BLOCKING: /* 4 */
1272 case BR_STATE_LISTENING: /* 1 */
1273 port_state[index] |= (1 << bit);
1274 break;
1275 case BR_STATE_LEARNING: /* 2 */
1276 port_state[index] |= (2 << bit);
1277 break;
1278 case BR_STATE_FORWARDING: /* 3 */
1279 port_state[index] |= (3 << bit);
1280 default:
1281 break;
1282 }
1283
1284 priv->r->stp_set(priv, msti, port_state);
1285
1286 mutex_unlock(&priv->reg_mutex);
1287 }
1288
1289 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1290 {
1291 struct rtl838x_switch_priv *priv = ds->priv;
1292 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1293
1294 pr_debug("FAST AGE port %d\n", port);
1295 mutex_lock(&priv->reg_mutex);
1296 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1297 * port fields:
1298 * 0-4: Replacing port
1299 * 5-9: Flushed/replaced port
1300 * 10-21: FVID
1301 * 22: Entry types: 1: dynamic, 0: also static
1302 * 23: Match flush port
1303 * 24: Match FVID
1304 * 25: Flush (0) or replace (1) L2 entries
1305 * 26: Status of action (1: Start, 0: Done)
1306 */
1307 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1308
1309 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1310
1311 mutex_unlock(&priv->reg_mutex);
1312 }
1313
1314 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1315 {
1316 struct rtl838x_switch_priv *priv = ds->priv;
1317
1318 pr_info("%s port %d\n", __func__, port);
1319 mutex_lock(&priv->reg_mutex);
1320 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1321
1322 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1323
1324 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1325
1326 mutex_unlock(&priv->reg_mutex);
1327 }
1328
1329 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1330 {
1331 struct rtl838x_switch_priv *priv = ds->priv;
1332
1333 if (priv->family_id == RTL9310_FAMILY_ID)
1334 return rtl931x_fast_age(ds, port);
1335
1336 pr_debug("FAST AGE port %d\n", port);
1337 mutex_lock(&priv->reg_mutex);
1338 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1339
1340 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1341
1342 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1343
1344 mutex_unlock(&priv->reg_mutex);
1345 }
1346
1347 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1348 bool vlan_filtering,
1349 struct netlink_ext_ack *extack)
1350 {
1351 struct rtl838x_switch_priv *priv = ds->priv;
1352
1353 pr_debug("%s: port %d\n", __func__, port);
1354 mutex_lock(&priv->reg_mutex);
1355
1356 if (vlan_filtering) {
1357 /* Enable ingress and egress filtering
1358 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1359 * the filter action:
1360 * 0: Always Forward
1361 * 1: Drop packet
1362 * 2: Trap packet to CPU port
1363 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1364 */
1365 if (port != priv->cpu_port)
1366 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1367
1368 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1369 } else {
1370 /* Disable ingress and egress filtering */
1371 if (port != priv->cpu_port)
1372 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1373
1374 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1375 }
1376
1377 /* Do we need to do something to the CPU-Port, too? */
1378 mutex_unlock(&priv->reg_mutex);
1379
1380 return 0;
1381 }
1382
1383 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1384 const struct switchdev_obj_port_vlan *vlan)
1385 {
1386 struct rtl838x_vlan_info info;
1387 struct rtl838x_switch_priv *priv = ds->priv;
1388
1389 priv->r->vlan_tables_read(0, &info);
1390
1391 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1392 info.tagged_ports, info.untagged_ports, info.profile_id,
1393 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1394
1395 priv->r->vlan_tables_read(1, &info);
1396 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1397 info.tagged_ports, info.untagged_ports, info.profile_id,
1398 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1399 priv->r->vlan_set_untagged(1, info.untagged_ports);
1400 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1401
1402 priv->r->vlan_set_tagged(1, &info);
1403 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1404
1405 return 0;
1406 }
1407
1408 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1409 int port, int pvid)
1410 {
1411 /* Set both inner and outer PVID of the port */
1412 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1413 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1414 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1415 PBVLAN_MODE_UNTAG_AND_PRITAG);
1416 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1417 PBVLAN_MODE_UNTAG_AND_PRITAG);
1418
1419 priv->ports[port].pvid = pvid;
1420 }
1421
1422 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1423 const struct switchdev_obj_port_vlan *vlan,
1424 struct netlink_ext_ack *extack)
1425 {
1426 struct rtl838x_vlan_info info;
1427 struct rtl838x_switch_priv *priv = ds->priv;
1428 int err;
1429
1430 pr_debug("%s port %d, vid %d, flags %x\n",
1431 __func__, port, vlan->vid, vlan->flags);
1432
1433 if (vlan->vid > 4095) {
1434 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1435 return -ENOTSUPP;
1436 }
1437
1438 err = rtl83xx_vlan_prepare(ds, port, vlan);
1439 if (err)
1440 return err;
1441
1442 mutex_lock(&priv->reg_mutex);
1443
1444 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1445 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1446 else if (priv->ports[port].pvid == vlan->vid)
1447 rtl83xx_vlan_set_pvid(priv, port, 0);
1448
1449 /* Get port memberships of this vlan */
1450 priv->r->vlan_tables_read(vlan->vid, &info);
1451
1452 /* new VLAN? */
1453 if (!info.tagged_ports) {
1454 info.fid = 0;
1455 info.hash_mc_fid = false;
1456 info.hash_uc_fid = false;
1457 info.profile_id = 0;
1458 }
1459
1460 /* sanitize untagged_ports - must be a subset */
1461 if (info.untagged_ports & ~info.tagged_ports)
1462 info.untagged_ports = 0;
1463
1464 info.tagged_ports |= BIT_ULL(port);
1465 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1466 info.untagged_ports |= BIT_ULL(port);
1467 else
1468 info.untagged_ports &= ~BIT_ULL(port);
1469
1470 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1471 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1472
1473 priv->r->vlan_set_tagged(vlan->vid, &info);
1474 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1475
1476 mutex_unlock(&priv->reg_mutex);
1477
1478 return 0;
1479 }
1480
1481 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1482 const struct switchdev_obj_port_vlan *vlan)
1483 {
1484 struct rtl838x_vlan_info info;
1485 struct rtl838x_switch_priv *priv = ds->priv;
1486 u16 pvid;
1487
1488 pr_debug("%s: port %d, vid %d, flags %x\n",
1489 __func__, port, vlan->vid, vlan->flags);
1490
1491 if (vlan->vid > 4095) {
1492 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1493 return -ENOTSUPP;
1494 }
1495
1496 mutex_lock(&priv->reg_mutex);
1497 pvid = priv->ports[port].pvid;
1498
1499 /* Reset to default if removing the current PVID */
1500 if (vlan->vid == pvid) {
1501 rtl83xx_vlan_set_pvid(priv, port, 0);
1502 }
1503 /* Get port memberships of this vlan */
1504 priv->r->vlan_tables_read(vlan->vid, &info);
1505
1506 /* remove port from both tables */
1507 info.untagged_ports &= (~BIT_ULL(port));
1508 info.tagged_ports &= (~BIT_ULL(port));
1509
1510 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1511 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1512
1513 priv->r->vlan_set_tagged(vlan->vid, &info);
1514 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1515
1516 mutex_unlock(&priv->reg_mutex);
1517
1518 return 0;
1519 }
1520
1521 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1522 {
1523 memset(e, 0, sizeof(*e));
1524
1525 e->type = L2_UNICAST;
1526 e->valid = true;
1527
1528 e->age = 3;
1529 e->is_static = true;
1530
1531 e->port = port;
1532
1533 e->rvid = e->vid = vid;
1534 e->is_ip_mc = e->is_ipv6_mc = false;
1535 u64_to_ether_addr(mac, e->mac);
1536 }
1537
1538 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1539 {
1540 memset(e, 0, sizeof(*e));
1541
1542 e->type = L2_MULTICAST;
1543 e->valid = true;
1544
1545 e->mc_portmask_index = mc_group;
1546
1547 e->rvid = e->vid = vid;
1548 e->is_ip_mc = e->is_ipv6_mc = false;
1549 u64_to_ether_addr(mac, e->mac);
1550 }
1551
1552 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1553 * over the entries in the bucket until either a matching entry is found or an empty slot
1554 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1555 * when an empty slot was found and must exist is false, the index of the slot is returned
1556 * when no slots are available returns -1
1557 */
1558 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1559 bool must_exist, struct rtl838x_l2_entry *e)
1560 {
1561 int idx = -1;
1562 u32 key = priv->r->l2_hash_key(priv, seed);
1563 u64 entry;
1564
1565 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1566 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1567 for (int i = 0; i < priv->l2_bucket_size; i++) {
1568 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1569 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1570 if (must_exist && !e->valid)
1571 continue;
1572 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1573 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1574 break;
1575 }
1576 }
1577
1578 return idx;
1579 }
1580
1581 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1582 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1583 * when an empty slot was found the index of the slot is returned
1584 * when no slots are available returns -1
1585 */
1586 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1587 bool must_exist, struct rtl838x_l2_entry *e)
1588 {
1589 int idx = -1;
1590 u64 entry;
1591
1592 for (int i = 0; i < 64; i++) {
1593 entry = priv->r->read_cam(i, e);
1594 if (!must_exist && !e->valid) {
1595 if (idx < 0) /* First empty entry? */
1596 idx = i;
1597 break;
1598 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1599 pr_debug("Found entry in CAM\n");
1600 idx = i;
1601 break;
1602 }
1603 }
1604
1605 return idx;
1606 }
1607
1608 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1609 const unsigned char *addr, u16 vid)
1610 {
1611 struct rtl838x_switch_priv *priv = ds->priv;
1612 u64 mac = ether_addr_to_u64(addr);
1613 struct rtl838x_l2_entry e;
1614 int err = 0, idx;
1615 u64 seed = priv->r->l2_hash_seed(mac, vid);
1616
1617 if (priv->is_lagmember[port]) {
1618 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1619 return 0;
1620 }
1621
1622 mutex_lock(&priv->reg_mutex);
1623
1624 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1625
1626 /* Found an existing or empty entry */
1627 if (idx >= 0) {
1628 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1629 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1630 goto out;
1631 }
1632
1633 /* Hash buckets full, try CAM */
1634 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1635
1636 if (idx >= 0) {
1637 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1638 priv->r->write_cam(idx, &e);
1639 goto out;
1640 }
1641
1642 err = -ENOTSUPP;
1643
1644 out:
1645 mutex_unlock(&priv->reg_mutex);
1646
1647 return err;
1648 }
1649
1650 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1651 const unsigned char *addr, u16 vid)
1652 {
1653 struct rtl838x_switch_priv *priv = ds->priv;
1654 u64 mac = ether_addr_to_u64(addr);
1655 struct rtl838x_l2_entry e;
1656 int err = 0, idx;
1657 u64 seed = priv->r->l2_hash_seed(mac, vid);
1658
1659 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1660 mutex_lock(&priv->reg_mutex);
1661
1662 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1663
1664 if (idx >= 0) {
1665 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1666 e.valid = false;
1667 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1668 goto out;
1669 }
1670
1671 /* Check CAM for spillover from hash buckets */
1672 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1673
1674 if (idx >= 0) {
1675 e.valid = false;
1676 priv->r->write_cam(idx, &e);
1677 goto out;
1678 }
1679 err = -ENOENT;
1680
1681 out:
1682 mutex_unlock(&priv->reg_mutex);
1683
1684 return err;
1685 }
1686
1687 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1688 dsa_fdb_dump_cb_t *cb, void *data)
1689 {
1690 struct rtl838x_l2_entry e;
1691 struct rtl838x_switch_priv *priv = ds->priv;
1692
1693 mutex_lock(&priv->reg_mutex);
1694
1695 for (int i = 0; i < priv->fib_entries; i++) {
1696 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1697
1698 if (!e.valid)
1699 continue;
1700
1701 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1702 cb(e.mac, e.vid, e.is_static, data);
1703
1704 if (!((i + 1) % 64))
1705 cond_resched();
1706 }
1707
1708 for (int i = 0; i < 64; i++) {
1709 priv->r->read_cam(i, &e);
1710
1711 if (!e.valid)
1712 continue;
1713
1714 if (e.port == port)
1715 cb(e.mac, e.vid, e.is_static, data);
1716 }
1717
1718 mutex_unlock(&priv->reg_mutex);
1719
1720 return 0;
1721 }
1722
1723 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1724 const struct switchdev_obj_port_mdb *mdb)
1725 {
1726 struct rtl838x_switch_priv *priv = ds->priv;
1727 u64 mac = ether_addr_to_u64(mdb->addr);
1728 struct rtl838x_l2_entry e;
1729 int err = 0, idx;
1730 int vid = mdb->vid;
1731 u64 seed = priv->r->l2_hash_seed(mac, vid);
1732 int mc_group;
1733
1734 if (priv->id >= 0x9300)
1735 return -EOPNOTSUPP;
1736
1737 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1738
1739 if (priv->is_lagmember[port]) {
1740 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1741 return -EINVAL;
1742 }
1743
1744 mutex_lock(&priv->reg_mutex);
1745
1746 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1747
1748 /* Found an existing or empty entry */
1749 if (idx >= 0) {
1750 if (e.valid) {
1751 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1752 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1753 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1754 } else {
1755 pr_debug("New entry for seed %016llx\n", seed);
1756 mc_group = rtl83xx_mc_group_alloc(priv, port);
1757 if (mc_group < 0) {
1758 err = -ENOTSUPP;
1759 goto out;
1760 }
1761 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1762 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1763 }
1764 goto out;
1765 }
1766
1767 /* Hash buckets full, try CAM */
1768 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1769
1770 if (idx >= 0) {
1771 if (e.valid) {
1772 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1773 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1774 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1775 } else {
1776 pr_debug("New entry\n");
1777 mc_group = rtl83xx_mc_group_alloc(priv, port);
1778 if (mc_group < 0) {
1779 err = -ENOTSUPP;
1780 goto out;
1781 }
1782 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1783 priv->r->write_cam(idx, &e);
1784 }
1785 goto out;
1786 }
1787
1788 err = -ENOTSUPP;
1789
1790 out:
1791 mutex_unlock(&priv->reg_mutex);
1792 if (err)
1793 dev_err(ds->dev, "failed to add MDB entry\n");
1794
1795 return err;
1796 }
1797
1798 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1799 const struct switchdev_obj_port_mdb *mdb)
1800 {
1801 struct rtl838x_switch_priv *priv = ds->priv;
1802 u64 mac = ether_addr_to_u64(mdb->addr);
1803 struct rtl838x_l2_entry e;
1804 int err = 0, idx;
1805 int vid = mdb->vid;
1806 u64 seed = priv->r->l2_hash_seed(mac, vid);
1807 u64 portmask;
1808
1809 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1810
1811 if (priv->is_lagmember[port]) {
1812 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1813 return 0;
1814 }
1815
1816 mutex_lock(&priv->reg_mutex);
1817
1818 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1819
1820 if (idx >= 0) {
1821 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1822 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1823 if (!portmask) {
1824 e.valid = false;
1825 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1826 }
1827 goto out;
1828 }
1829
1830 /* Check CAM for spillover from hash buckets */
1831 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1832
1833 if (idx >= 0) {
1834 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1835 if (!portmask) {
1836 e.valid = false;
1837 priv->r->write_cam(idx, &e);
1838 }
1839 goto out;
1840 }
1841 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1842
1843 out:
1844 mutex_unlock(&priv->reg_mutex);
1845
1846 return err;
1847 }
1848
1849 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1850 struct dsa_mall_mirror_tc_entry *mirror,
1851 bool ingress)
1852 {
1853 /* We support 4 mirror groups, one destination port per group */
1854 int group;
1855 struct rtl838x_switch_priv *priv = ds->priv;
1856 int ctrl_reg, dpm_reg, spm_reg;
1857
1858 pr_debug("In %s\n", __func__);
1859
1860 for (group = 0; group < 4; group++) {
1861 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1862 break;
1863 }
1864 if (group >= 4) {
1865 for (group = 0; group < 4; group++) {
1866 if (priv->mirror_group_ports[group] < 0)
1867 break;
1868 }
1869 }
1870
1871 if (group >= 4)
1872 return -ENOSPC;
1873
1874 ctrl_reg = priv->r->mir_ctrl + group * 4;
1875 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1876 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1877
1878 pr_debug("Using group %d\n", group);
1879 mutex_lock(&priv->reg_mutex);
1880
1881 if (priv->family_id == RTL8380_FAMILY_ID) {
1882 /* Enable mirroring to port across VLANs (bit 11) */
1883 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1884 } else {
1885 /* Enable mirroring to destination port */
1886 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1887 }
1888
1889 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1890 mutex_unlock(&priv->reg_mutex);
1891 return -EEXIST;
1892 }
1893 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1894 mutex_unlock(&priv->reg_mutex);
1895 return -EEXIST;
1896 }
1897
1898 if (ingress)
1899 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1900 else
1901 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1902
1903 priv->mirror_group_ports[group] = mirror->to_local_port;
1904 mutex_unlock(&priv->reg_mutex);
1905
1906 return 0;
1907 }
1908
1909 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1910 struct dsa_mall_mirror_tc_entry *mirror)
1911 {
1912 int group = 0;
1913 struct rtl838x_switch_priv *priv = ds->priv;
1914 int ctrl_reg, dpm_reg, spm_reg;
1915
1916 pr_debug("In %s\n", __func__);
1917 for (group = 0; group < 4; group++) {
1918 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1919 break;
1920 }
1921 if (group >= 4)
1922 return;
1923
1924 ctrl_reg = priv->r->mir_ctrl + group * 4;
1925 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1926 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1927
1928 mutex_lock(&priv->reg_mutex);
1929 if (mirror->ingress) {
1930 /* Ingress, clear source port matrix */
1931 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1932 } else {
1933 /* Egress, clear destination port matrix */
1934 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1935 }
1936
1937 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1938 priv->mirror_group_ports[group] = -1;
1939 sw_w32(0, ctrl_reg);
1940 }
1941
1942 mutex_unlock(&priv->reg_mutex);
1943 }
1944
1945 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1946 {
1947 struct rtl838x_switch_priv *priv = ds->priv;
1948 unsigned long features = 0;
1949 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1950 if (priv->r->enable_learning)
1951 features |= BR_LEARNING;
1952 if (priv->r->enable_flood)
1953 features |= BR_FLOOD;
1954 if (priv->r->enable_mcast_flood)
1955 features |= BR_MCAST_FLOOD;
1956 if (priv->r->enable_bcast_flood)
1957 features |= BR_BCAST_FLOOD;
1958 if (flags.mask & ~(features))
1959 return -EINVAL;
1960
1961 return 0;
1962 }
1963
1964 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1965 {
1966 struct rtl838x_switch_priv *priv = ds->priv;
1967
1968 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1969 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1970 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1971
1972 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1973 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1974
1975 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1976 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1977
1978 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1979 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1980
1981 return 0;
1982 }
1983
1984 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1985 struct net_device *lag,
1986 struct netdev_lag_upper_info *info)
1987 {
1988 int id;
1989
1990 id = dsa_lag_id(ds->dst, lag);
1991 if (id < 0 || id >= ds->num_lag_ids)
1992 return false;
1993
1994 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1995 return false;
1996 }
1997 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1998 return false;
1999
2000 return true;
2001 }
2002
2003 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2004 {
2005 struct rtl838x_switch_priv *priv = ds->priv;
2006
2007 pr_debug("%s: %d\n", __func__, port);
2008 /* Nothing to be done... */
2009
2010 return 0;
2011 }
2012
2013 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2014 struct net_device *lag,
2015 struct netdev_lag_upper_info *info)
2016 {
2017 struct rtl838x_switch_priv *priv = ds->priv;
2018 int i, err = 0;
2019
2020 if (!rtl83xx_lag_can_offload(ds, lag, info))
2021 return -EOPNOTSUPP;
2022
2023 mutex_lock(&priv->reg_mutex);
2024
2025 for (i = 0; i < priv->n_lags; i++) {
2026 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2027 break;
2028 }
2029 if (port >= priv->cpu_port) {
2030 err = -EINVAL;
2031 goto out;
2032 }
2033 pr_info("port_lag_join: group %d, port %d\n",i, port);
2034 if (!priv->lag_devs[i])
2035 priv->lag_devs[i] = lag;
2036
2037 if (priv->lag_primary[i] == -1) {
2038 priv->lag_primary[i] = port;
2039 } else
2040 priv->is_lagmember[port] = 1;
2041
2042 priv->lagmembers |= (1ULL << port);
2043
2044 pr_debug("lag_members = %llX\n", priv->lagmembers);
2045 err = rtl83xx_lag_add(priv->ds, i, port, info);
2046 if (err) {
2047 err = -EINVAL;
2048 goto out;
2049 }
2050
2051 out:
2052 mutex_unlock(&priv->reg_mutex);
2053
2054 return err;
2055 }
2056
2057 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2058 struct net_device *lag)
2059 {
2060 int i, group = -1, err;
2061 struct rtl838x_switch_priv *priv = ds->priv;
2062
2063 mutex_lock(&priv->reg_mutex);
2064 for (i = 0; i < priv->n_lags; i++) {
2065 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2066 group = i;
2067 break;
2068 }
2069 }
2070
2071 if (group == -1) {
2072 pr_info("port_lag_leave: port %d is not a member\n", port);
2073 err = -EINVAL;
2074 goto out;
2075 }
2076
2077 if (port >= priv->cpu_port) {
2078 err = -EINVAL;
2079 goto out;
2080 }
2081 pr_info("port_lag_del: group %d, port %d\n",group, port);
2082 priv->lagmembers &=~ (1ULL << port);
2083 priv->lag_primary[i] = -1;
2084 priv->is_lagmember[port] = 0;
2085 pr_debug("lag_members = %llX\n", priv->lagmembers);
2086 err = rtl83xx_lag_del(priv->ds, group, port);
2087 if (err) {
2088 err = -EINVAL;
2089 goto out;
2090 }
2091 if (!priv->lags_port_members[i])
2092 priv->lag_devs[i] = NULL;
2093
2094 out:
2095 mutex_unlock(&priv->reg_mutex);
2096 return 0;
2097 }
2098
2099 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2100 {
2101 u32 val;
2102 u32 offset = 0;
2103 struct rtl838x_switch_priv *priv = ds->priv;
2104
2105 if ((phy_addr >= 24) &&
2106 (phy_addr <= 27) &&
2107 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2108 if (phy_addr == 26)
2109 offset = 0x100;
2110 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2111 return val;
2112 }
2113
2114 read_phy(phy_addr, 0, phy_reg, &val);
2115 return val;
2116 }
2117
2118 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2119 {
2120 u32 offset = 0;
2121 struct rtl838x_switch_priv *priv = ds->priv;
2122
2123 if ((phy_addr >= 24) &&
2124 (phy_addr <= 27) &&
2125 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2126 if (phy_addr == 26)
2127 offset = 0x100;
2128 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2129 return 0;
2130 }
2131 return write_phy(phy_addr, 0, phy_reg, val);
2132 }
2133
2134 const struct dsa_switch_ops rtl83xx_switch_ops = {
2135 .get_tag_protocol = rtl83xx_get_tag_protocol,
2136 .setup = rtl83xx_setup,
2137
2138 .phy_read = dsa_phy_read,
2139 .phy_write = dsa_phy_write,
2140
2141 .phylink_validate = rtl83xx_phylink_validate,
2142 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2143 .phylink_mac_config = rtl83xx_phylink_mac_config,
2144 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2145 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2146
2147 .get_strings = rtl83xx_get_strings,
2148 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2149 .get_sset_count = rtl83xx_get_sset_count,
2150
2151 .port_enable = rtl83xx_port_enable,
2152 .port_disable = rtl83xx_port_disable,
2153
2154 .get_mac_eee = rtl83xx_get_mac_eee,
2155 .set_mac_eee = rtl83xx_set_mac_eee,
2156
2157 .set_ageing_time = rtl83xx_set_ageing_time,
2158 .port_bridge_join = rtl83xx_port_bridge_join,
2159 .port_bridge_leave = rtl83xx_port_bridge_leave,
2160 .port_stp_state_set = rtl83xx_port_stp_state_set,
2161 .port_fast_age = rtl83xx_fast_age,
2162
2163 .port_vlan_filtering = rtl83xx_vlan_filtering,
2164 .port_vlan_add = rtl83xx_vlan_add,
2165 .port_vlan_del = rtl83xx_vlan_del,
2166
2167 .port_fdb_add = rtl83xx_port_fdb_add,
2168 .port_fdb_del = rtl83xx_port_fdb_del,
2169 .port_fdb_dump = rtl83xx_port_fdb_dump,
2170
2171 .port_mdb_add = rtl83xx_port_mdb_add,
2172 .port_mdb_del = rtl83xx_port_mdb_del,
2173
2174 .port_mirror_add = rtl83xx_port_mirror_add,
2175 .port_mirror_del = rtl83xx_port_mirror_del,
2176
2177 .port_lag_change = rtl83xx_port_lag_change,
2178 .port_lag_join = rtl83xx_port_lag_join,
2179 .port_lag_leave = rtl83xx_port_lag_leave,
2180
2181 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2182 .port_bridge_flags = rtl83xx_port_bridge_flags,
2183 };
2184
2185 const struct dsa_switch_ops rtl930x_switch_ops = {
2186 .get_tag_protocol = rtl83xx_get_tag_protocol,
2187 .setup = rtl93xx_setup,
2188
2189 .phy_read = dsa_phy_read,
2190 .phy_write = dsa_phy_write,
2191
2192 .phylink_validate = rtl93xx_phylink_validate,
2193 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2194 .phylink_mac_config = rtl93xx_phylink_mac_config,
2195 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2196 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2197
2198 .get_strings = rtl83xx_get_strings,
2199 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2200 .get_sset_count = rtl83xx_get_sset_count,
2201
2202 .port_enable = rtl83xx_port_enable,
2203 .port_disable = rtl83xx_port_disable,
2204
2205 .get_mac_eee = rtl93xx_get_mac_eee,
2206 .set_mac_eee = rtl83xx_set_mac_eee,
2207
2208 .set_ageing_time = rtl83xx_set_ageing_time,
2209 .port_bridge_join = rtl83xx_port_bridge_join,
2210 .port_bridge_leave = rtl83xx_port_bridge_leave,
2211 .port_stp_state_set = rtl83xx_port_stp_state_set,
2212 .port_fast_age = rtl930x_fast_age,
2213
2214 .port_vlan_filtering = rtl83xx_vlan_filtering,
2215 .port_vlan_add = rtl83xx_vlan_add,
2216 .port_vlan_del = rtl83xx_vlan_del,
2217
2218 .port_fdb_add = rtl83xx_port_fdb_add,
2219 .port_fdb_del = rtl83xx_port_fdb_del,
2220 .port_fdb_dump = rtl83xx_port_fdb_dump,
2221
2222 .port_mdb_add = rtl83xx_port_mdb_add,
2223 .port_mdb_del = rtl83xx_port_mdb_del,
2224
2225 .port_lag_change = rtl83xx_port_lag_change,
2226 .port_lag_join = rtl83xx_port_lag_join,
2227 .port_lag_leave = rtl83xx_port_lag_leave,
2228
2229 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2230 .port_bridge_flags = rtl83xx_port_bridge_flags,
2231 };
Staging tree of Jo-Philipp Wich