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realtek: Whitespace and codestyle cleanup
[openwrt/staging/dedeckeh.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
12 {
13 mutex_lock(&priv->reg_mutex);
14
15 /* Enable statistics module: all counters plus debug.
16 * On RTL839x all counters are enabled by default
17 */
18 if (priv->family_id == RTL8380_FAMILY_ID)
19 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
20
21 /* Reset statistics counters */
22 sw_w32_mask(0, 1, priv->r->stat_rst);
23
24 mutex_unlock(&priv->reg_mutex);
25 }
26
27 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
28 {
29 int i;
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
114 {
115 struct rtl838x_vlan_info info;
116 int i;
117
118 pr_info("In %s\n", __func__);
119
120 priv->r->vlan_profile_setup(0);
121 priv->r->vlan_profile_setup(1);
122 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
123 priv->r->vlan_profile_dump(0);
124
125 info.fid = 0; // Default Forwarding ID / MSTI
126 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
127 info.hash_mc_fid = false; // Do the same for Multicast packets
128 info.profile_id = 0; // Use default Vlan Profile 0
129 info.tagged_ports = 0; // Initially no port members
130 if (priv->family_id == RTL9310_FAMILY_ID) {
131 info.if_id = 0;
132 info.multicast_grp_mask = 0;
133 info.l2_tunnel_list_id = -1;
134 }
135
136 // Initialize all vlans 0-4095
137 for (i = 0; i < MAX_VLANS; i ++)
138 priv->r->vlan_set_tagged(i, &info);
139
140 // reset PVIDs; defaults to 1 on reset
141 for (i = 0; i <= priv->ds->num_ports; i++) {
142 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
143 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
144 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
145 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
146 }
147
148 // Set forwarding action based on inner VLAN tag
149 for (i = 0; i < priv->cpu_port; i++)
150 priv->r->vlan_fwd_on_inner(i, true);
151 }
152
153 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
154 {
155 int i;
156
157 for (i = 0; i < priv->cpu_port; i++)
158 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
159 }
160
161 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
162 int port, bool enable)
163 {
164 int shift = SALRN_PORT_SHIFT(port);
165 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
166
167 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
168 priv->r->l2_port_new_salrn(port));
169 }
170
171 static int rtl83xx_setup(struct dsa_switch *ds)
172 {
173 int i;
174 struct rtl838x_switch_priv *priv = ds->priv;
175 u64 port_bitmap = BIT_ULL(priv->cpu_port);
176
177 pr_debug("%s called\n", __func__);
178
179 /* Disable MAC polling the PHY so that we can start configuration */
180 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
181
182 for (i = 0; i < ds->num_ports; i++)
183 priv->ports[i].enable = false;
184 priv->ports[priv->cpu_port].enable = true;
185
186 /* Isolate ports from each other: traffic only CPU <-> port */
187 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
188 * traffic from source port i to destination port j
189 */
190 for (i = 0; i < priv->cpu_port; i++) {
191 if (priv->ports[i].phy) {
192 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
193 priv->r->port_iso_ctrl(i));
194 port_bitmap |= BIT_ULL(i);
195 }
196 }
197 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
198
199 if (priv->family_id == RTL8380_FAMILY_ID)
200 rtl838x_print_matrix();
201 else
202 rtl839x_print_matrix();
203
204 rtl83xx_init_stats(priv);
205
206 rtl83xx_vlan_setup(priv);
207
208 rtl83xx_setup_bpdu_traps(priv);
209
210 ds->configure_vlan_while_not_filtering = true;
211
212 priv->r->l2_learning_setup();
213
214 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
215 ds->assisted_learning_on_cpu_port = true;
216
217 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
218 * 0: FWD, 1: DROP, 2: TRAP2CPU
219 */
220 if (priv->family_id == RTL8380_FAMILY_ID)
221 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
222 else
223 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
224
225 /* Enable MAC Polling PHY again */
226 rtl83xx_enable_phy_polling(priv);
227 pr_debug("Please wait until PHY is settled\n");
228 msleep(1000);
229 priv->r->pie_init(priv);
230
231 return 0;
232 }
233
234 static int rtl93xx_setup(struct dsa_switch *ds)
235 {
236 int i;
237 struct rtl838x_switch_priv *priv = ds->priv;
238 u32 port_bitmap = BIT(priv->cpu_port);
239
240 pr_info("%s called\n", __func__);
241
242 /* Disable MAC polling the PHY so that we can start configuration */
243 if (priv->family_id == RTL9300_FAMILY_ID)
244 sw_w32(0, RTL930X_SMI_POLL_CTRL);
245
246 if (priv->family_id == RTL9310_FAMILY_ID) {
247 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
248 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
249 }
250
251 // Disable all ports except CPU port
252 for (i = 0; i < ds->num_ports; i++)
253 priv->ports[i].enable = false;
254 priv->ports[priv->cpu_port].enable = true;
255
256 for (i = 0; i < priv->cpu_port; i++) {
257 if (priv->ports[i].phy) {
258 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
259 port_bitmap |= BIT_ULL(i);
260 }
261 }
262 priv->r->traffic_set(priv->cpu_port, port_bitmap);
263
264 rtl930x_print_matrix();
265
266 // TODO: Initialize statistics
267
268 rtl83xx_vlan_setup(priv);
269
270 ds->configure_vlan_while_not_filtering = true;
271
272 priv->r->l2_learning_setup();
273
274 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
275 ds->assisted_learning_on_cpu_port = true;
276
277 rtl83xx_enable_phy_polling(priv);
278
279 priv->r->pie_init(priv);
280
281 priv->r->led_init(priv);
282
283 return 0;
284 }
285
286 static int rtl93xx_get_sds(struct phy_device *phydev)
287 {
288 struct device *dev = &phydev->mdio.dev;
289 struct device_node *dn;
290 u32 sds_num;
291
292 if (!dev)
293 return -1;
294 if (dev->of_node) {
295 dn = dev->of_node;
296 if (of_property_read_u32(dn, "sds", &sds_num))
297 sds_num = -1;
298 } else {
299 dev_err(dev, "No DT node.\n");
300 return -1;
301 }
302
303 return sds_num;
304 }
305
306 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
307 unsigned long *supported,
308 struct phylink_link_state *state)
309 {
310 struct rtl838x_switch_priv *priv = ds->priv;
311 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
312
313 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
314
315 if (!phy_interface_mode_is_rgmii(state->interface) &&
316 state->interface != PHY_INTERFACE_MODE_NA &&
317 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
318 state->interface != PHY_INTERFACE_MODE_MII &&
319 state->interface != PHY_INTERFACE_MODE_REVMII &&
320 state->interface != PHY_INTERFACE_MODE_GMII &&
321 state->interface != PHY_INTERFACE_MODE_QSGMII &&
322 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
323 state->interface != PHY_INTERFACE_MODE_SGMII) {
324 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
325 dev_err(ds->dev,
326 "Unsupported interface: %d for port %d\n",
327 state->interface, port);
328 return;
329 }
330
331 /* Allow all the expected bits */
332 phylink_set(mask, Autoneg);
333 phylink_set_port_modes(mask);
334 phylink_set(mask, Pause);
335 phylink_set(mask, Asym_Pause);
336
337 /* With the exclusion of MII and Reverse MII, we support Gigabit,
338 * including Half duplex
339 */
340 if (state->interface != PHY_INTERFACE_MODE_MII &&
341 state->interface != PHY_INTERFACE_MODE_REVMII) {
342 phylink_set(mask, 1000baseT_Full);
343 phylink_set(mask, 1000baseT_Half);
344 }
345
346 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
347 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
348 phylink_set(mask, 1000baseX_Full);
349
350 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
351 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
352 phylink_set(mask, 1000baseX_Full);
353
354 phylink_set(mask, 10baseT_Half);
355 phylink_set(mask, 10baseT_Full);
356 phylink_set(mask, 100baseT_Half);
357 phylink_set(mask, 100baseT_Full);
358
359 bitmap_and(supported, supported, mask,
360 __ETHTOOL_LINK_MODE_MASK_NBITS);
361 bitmap_and(state->advertising, state->advertising, mask,
362 __ETHTOOL_LINK_MODE_MASK_NBITS);
363 }
364
365 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
366 unsigned long *supported,
367 struct phylink_link_state *state)
368 {
369 struct rtl838x_switch_priv *priv = ds->priv;
370 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
371
372 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
373 phy_modes(state->interface));
374
375 if (!phy_interface_mode_is_rgmii(state->interface) &&
376 state->interface != PHY_INTERFACE_MODE_NA &&
377 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
378 state->interface != PHY_INTERFACE_MODE_MII &&
379 state->interface != PHY_INTERFACE_MODE_REVMII &&
380 state->interface != PHY_INTERFACE_MODE_GMII &&
381 state->interface != PHY_INTERFACE_MODE_QSGMII &&
382 state->interface != PHY_INTERFACE_MODE_XGMII &&
383 state->interface != PHY_INTERFACE_MODE_HSGMII &&
384 state->interface != PHY_INTERFACE_MODE_10GBASER &&
385 state->interface != PHY_INTERFACE_MODE_10GKR &&
386 state->interface != PHY_INTERFACE_MODE_USXGMII &&
387 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
388 state->interface != PHY_INTERFACE_MODE_SGMII) {
389 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
390 dev_err(ds->dev,
391 "Unsupported interface: %d for port %d\n",
392 state->interface, port);
393 return;
394 }
395
396 /* Allow all the expected bits */
397 phylink_set(mask, Autoneg);
398 phylink_set_port_modes(mask);
399 phylink_set(mask, Pause);
400 phylink_set(mask, Asym_Pause);
401
402 /* With the exclusion of MII and Reverse MII, we support Gigabit,
403 * including Half duplex
404 */
405 if (state->interface != PHY_INTERFACE_MODE_MII &&
406 state->interface != PHY_INTERFACE_MODE_REVMII) {
407 phylink_set(mask, 1000baseT_Full);
408 phylink_set(mask, 1000baseT_Half);
409 }
410
411 // Internal phys of the RTL93xx family provide 10G
412 if (priv->ports[port].phy_is_integrated &&
413 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
414 phylink_set(mask, 1000baseX_Full);
415 } else if (priv->ports[port].phy_is_integrated) {
416 phylink_set(mask, 1000baseX_Full);
417 phylink_set(mask, 10000baseKR_Full);
418 phylink_set(mask, 10000baseSR_Full);
419 phylink_set(mask, 10000baseCR_Full);
420 }
421 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
422 phylink_set(mask, 1000baseX_Full);
423 phylink_set(mask, 1000baseT_Full);
424 phylink_set(mask, 10000baseKR_Full);
425 phylink_set(mask, 10000baseT_Full);
426 phylink_set(mask, 10000baseSR_Full);
427 phylink_set(mask, 10000baseCR_Full);
428 }
429
430 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
431 phylink_set(mask, 10000baseT_Full);
432
433 phylink_set(mask, 10baseT_Half);
434 phylink_set(mask, 10baseT_Full);
435 phylink_set(mask, 100baseT_Half);
436 phylink_set(mask, 100baseT_Full);
437
438 bitmap_and(supported, supported, mask,
439 __ETHTOOL_LINK_MODE_MASK_NBITS);
440 bitmap_and(state->advertising, state->advertising, mask,
441 __ETHTOOL_LINK_MODE_MASK_NBITS);
442 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
443 }
444
445 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
446 struct phylink_link_state *state)
447 {
448 struct rtl838x_switch_priv *priv = ds->priv;
449 u64 speed;
450 u64 link;
451
452 if (port < 0 || port > priv->cpu_port)
453 return -EINVAL;
454
455 state->link = 0;
456 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
457 if (link & BIT_ULL(port))
458 state->link = 1;
459 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
460
461 state->duplex = 0;
462 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
463 state->duplex = 1;
464
465 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
466 speed >>= (port % 16) << 1;
467 switch (speed & 0x3) {
468 case 0:
469 state->speed = SPEED_10;
470 break;
471 case 1:
472 state->speed = SPEED_100;
473 break;
474 case 2:
475 state->speed = SPEED_1000;
476 break;
477 case 3:
478 if (priv->family_id == RTL9300_FAMILY_ID
479 && (port == 24 || port == 26)) /* Internal serdes */
480 state->speed = SPEED_2500;
481 else
482 state->speed = SPEED_100; /* Is in fact 500Mbit */
483 }
484
485 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
486 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
487 state->pause |= MLO_PAUSE_RX;
488 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
489 state->pause |= MLO_PAUSE_TX;
490
491 return 1;
492 }
493
494 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
495 struct phylink_link_state *state)
496 {
497 struct rtl838x_switch_priv *priv = ds->priv;
498 u64 speed;
499 u64 link;
500 u64 media;
501
502 if (port < 0 || port > priv->cpu_port)
503 return -EINVAL;
504
505 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
506 * state needs to be read twice in order to read a correct result.
507 * This would not be necessary for ports connected e.g. to RTL8218D
508 * PHYs.
509 */
510 state->link = 0;
511 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
512 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
513 if (link & BIT_ULL(port))
514 state->link = 1;
515
516 if (priv->family_id == RTL9310_FAMILY_ID)
517 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
518
519 if (priv->family_id == RTL9300_FAMILY_ID)
520 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
521
522 if (media & BIT_ULL(port))
523 state->link = 1;
524
525 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
526 link & BIT_ULL(port), media);
527
528 state->duplex = 0;
529 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
530 state->duplex = 1;
531
532 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
533 speed >>= (port % 8) << 2;
534 switch (speed & 0xf) {
535 case 0:
536 state->speed = SPEED_10;
537 break;
538 case 1:
539 state->speed = SPEED_100;
540 break;
541 case 2:
542 case 7:
543 state->speed = SPEED_1000;
544 break;
545 case 4:
546 state->speed = SPEED_10000;
547 break;
548 case 5:
549 case 8:
550 state->speed = SPEED_2500;
551 break;
552 case 6:
553 state->speed = SPEED_5000;
554 break;
555 default:
556 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
557 }
558
559 if (priv->family_id == RTL9310_FAMILY_ID
560 && (port >= 52 || port <= 55)) { /* Internal serdes */
561 state->speed = SPEED_10000;
562 state->link = 1;
563 state->duplex = 1;
564 }
565
566 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
567 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
568 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
569 state->pause |= MLO_PAUSE_RX;
570 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
571 state->pause |= MLO_PAUSE_TX;
572
573 return 1;
574 }
575
576 static void rtl83xx_config_interface(int port, phy_interface_t interface)
577 {
578 u32 old, int_shift, sds_shift;
579
580 switch (port) {
581 case 24:
582 int_shift = 0;
583 sds_shift = 5;
584 break;
585 case 26:
586 int_shift = 3;
587 sds_shift = 0;
588 break;
589 default:
590 return;
591 }
592
593 old = sw_r32(RTL838X_SDS_MODE_SEL);
594 switch (interface) {
595 case PHY_INTERFACE_MODE_1000BASEX:
596 if ((old >> sds_shift & 0x1f) == 4)
597 return;
598 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
599 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
600 break;
601 case PHY_INTERFACE_MODE_SGMII:
602 if ((old >> sds_shift & 0x1f) == 2)
603 return;
604 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
605 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
606 break;
607 default:
608 return;
609 }
610 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
611 }
612
613 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
614 unsigned int mode,
615 const struct phylink_link_state *state)
616 {
617 struct rtl838x_switch_priv *priv = ds->priv;
618 u32 reg;
619 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
620
621 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
622
623 if (port == priv->cpu_port) {
624 /* Set Speed, duplex, flow control
625 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
626 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
627 * | MEDIA_SEL
628 */
629 if (priv->family_id == RTL8380_FAMILY_ID) {
630 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
631 /* allow CRC errors on CPU-port */
632 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
633 } else {
634 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
635 }
636 return;
637 }
638
639 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
640 /* Auto-Negotiation does not work for MAC in RTL8390 */
641 if (priv->family_id == RTL8380_FAMILY_ID) {
642 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
643 pr_debug("PHY autonegotiates\n");
644 reg |= RTL838X_NWAY_EN;
645 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
646 rtl83xx_config_interface(port, state->interface);
647 return;
648 }
649 }
650
651 if (mode != MLO_AN_FIXED)
652 pr_debug("Fixed state.\n");
653
654 /* Clear id_mode_dis bit, and the existing port mode, let
655 * RGMII_MODE_EN bet set by mac_link_{up,down} */
656 if (priv->family_id == RTL8380_FAMILY_ID) {
657 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
658 if (state->pause & MLO_PAUSE_TXRX_MASK) {
659 if (state->pause & MLO_PAUSE_TX)
660 reg |= RTL838X_TX_PAUSE_EN;
661 reg |= RTL838X_RX_PAUSE_EN;
662 }
663 } else if (priv->family_id == RTL8390_FAMILY_ID) {
664 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
665 if (state->pause & MLO_PAUSE_TXRX_MASK) {
666 if (state->pause & MLO_PAUSE_TX)
667 reg |= RTL839X_TX_PAUSE_EN;
668 reg |= RTL839X_RX_PAUSE_EN;
669 }
670 }
671
672
673 reg &= ~(3 << speed_bit);
674 switch (state->speed) {
675 case SPEED_1000:
676 reg |= 2 << speed_bit;
677 break;
678 case SPEED_100:
679 reg |= 1 << speed_bit;
680 break;
681 default:
682 break; // Ignore, including 10MBit which has a speed value of 0
683 }
684
685 if (priv->family_id == RTL8380_FAMILY_ID) {
686 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
687 if (state->link)
688 reg |= RTL838X_FORCE_LINK_EN;
689 if (state->duplex == RTL838X_DUPLEX_MODE)
690 reg |= RTL838X_DUPLEX_MODE;
691 } else if (priv->family_id == RTL8390_FAMILY_ID) {
692 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
693 if (state->link)
694 reg |= RTL839X_FORCE_LINK_EN;
695 if (state->duplex == RTL839X_DUPLEX_MODE)
696 reg |= RTL839X_DUPLEX_MODE;
697 }
698
699 // LAG members must use DUPLEX and we need to enable the link
700 if (priv->lagmembers & BIT_ULL(port)) {
701 switch(priv->family_id) {
702 case RTL8380_FAMILY_ID:
703 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
704 break;
705 case RTL8390_FAMILY_ID:
706 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
707 break;
708 }
709 }
710
711 // Disable AN
712 if (priv->family_id == RTL8380_FAMILY_ID)
713 reg &= ~RTL838X_NWAY_EN;
714 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
715 }
716
717 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
718 unsigned int mode,
719 const struct phylink_link_state *state)
720 {
721 struct rtl838x_switch_priv *priv = ds->priv;
722 int sds_num;
723 u32 reg, band;
724
725 sds_num = priv->ports[port].sds_num;
726 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
727
728 switch (state->interface) {
729 case PHY_INTERFACE_MODE_HSGMII:
730 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
731 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
732 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
733 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
734 break;
735 case PHY_INTERFACE_MODE_1000BASEX:
736 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
737 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
738 break;
739 case PHY_INTERFACE_MODE_XGMII:
740 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
741 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
742 break;
743 case PHY_INTERFACE_MODE_10GBASER:
744 case PHY_INTERFACE_MODE_10GKR:
745 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
746 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
747 break;
748 case PHY_INTERFACE_MODE_USXGMII:
749 // Translates to MII_USXGMII_10GSXGMII
750 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
751 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
752 break;
753 case PHY_INTERFACE_MODE_SGMII:
754 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
755 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
756 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
757 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
758 break;
759 case PHY_INTERFACE_MODE_QSGMII:
760 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
761 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
762 break;
763 default:
764 pr_err("%s: unknown serdes mode: %s\n",
765 __func__, phy_modes(state->interface));
766 return;
767 }
768
769 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
770 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
771
772 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
773
774 reg &= ~(0xf << 12);
775 reg |= 0x2 << 12; // Set SMI speed to 0x2
776
777 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
778
779 if (priv->lagmembers & BIT_ULL(port))
780 reg |= RTL931X_DUPLEX_MODE;
781
782 if (state->duplex == DUPLEX_FULL)
783 reg |= RTL931X_DUPLEX_MODE;
784
785 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
786
787 }
788
789 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
790 unsigned int mode,
791 const struct phylink_link_state *state)
792 {
793 struct rtl838x_switch_priv *priv = ds->priv;
794 int sds_num, sds_mode;
795 u32 reg;
796
797 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
798 port, mode, phy_modes(state->interface), state->speed, state->link);
799
800 // Nothing to be done for the CPU-port
801 if (port == priv->cpu_port)
802 return;
803
804 if (priv->family_id == RTL9310_FAMILY_ID)
805 return rtl931x_phylink_mac_config(ds, port, mode, state);
806
807 sds_num = priv->ports[port].sds_num;
808 pr_info("%s SDS is %d\n", __func__, sds_num);
809 if (sds_num >= 0) {
810 switch (state->interface) {
811 case PHY_INTERFACE_MODE_HSGMII:
812 sds_mode = 0x12;
813 break;
814 case PHY_INTERFACE_MODE_1000BASEX:
815 sds_mode = 0x04;
816 break;
817 case PHY_INTERFACE_MODE_XGMII:
818 sds_mode = 0x10;
819 break;
820 case PHY_INTERFACE_MODE_10GBASER:
821 case PHY_INTERFACE_MODE_10GKR:
822 sds_mode = 0x1b; // 10G 1000X Auto
823 break;
824 case PHY_INTERFACE_MODE_USXGMII:
825 sds_mode = 0x0d;
826 break;
827 default:
828 pr_err("%s: unknown serdes mode: %s\n",
829 __func__, phy_modes(state->interface));
830 return;
831 }
832 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
833 rtl9300_serdes_setup(sds_num, state->interface);
834 }
835
836 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
837 reg &= ~(0xf << 3);
838
839 switch (state->speed) {
840 case SPEED_10000:
841 reg |= 4 << 3;
842 break;
843 case SPEED_5000:
844 reg |= 6 << 3;
845 break;
846 case SPEED_2500:
847 reg |= 5 << 3;
848 break;
849 case SPEED_1000:
850 reg |= 2 << 3;
851 break;
852 default:
853 reg |= 2 << 3;
854 break;
855 }
856
857 if (state->link)
858 reg |= RTL930X_FORCE_LINK_EN;
859
860 if (priv->lagmembers & BIT_ULL(port))
861 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
862
863 if (state->duplex == DUPLEX_FULL)
864 reg |= RTL930X_DUPLEX_MODE;
865
866 if (priv->ports[port].phy_is_integrated)
867 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
868 else
869 reg |= RTL930X_FORCE_EN;
870
871 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
872 }
873
874 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
875 unsigned int mode,
876 phy_interface_t interface)
877 {
878 struct rtl838x_switch_priv *priv = ds->priv;
879
880 /* Stop TX/RX to port */
881 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
882
883 // No longer force link
884 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
885 }
886
887 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
888 unsigned int mode,
889 phy_interface_t interface)
890 {
891 struct rtl838x_switch_priv *priv = ds->priv;
892 u32 v = 0;
893
894 /* Stop TX/RX to port */
895 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
896
897 // No longer force link
898 if (priv->family_id == RTL9300_FAMILY_ID)
899 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
900 else if (priv->family_id == RTL9310_FAMILY_ID)
901 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
902 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
903 }
904
905 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
906 unsigned int mode,
907 phy_interface_t interface,
908 struct phy_device *phydev,
909 int speed, int duplex,
910 bool tx_pause, bool rx_pause)
911 {
912 struct rtl838x_switch_priv *priv = ds->priv;
913 /* Restart TX/RX to port */
914 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
915 // TODO: Set speed/duplex/pauses
916 }
917
918 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
919 unsigned int mode,
920 phy_interface_t interface,
921 struct phy_device *phydev,
922 int speed, int duplex,
923 bool tx_pause, bool rx_pause)
924 {
925 struct rtl838x_switch_priv *priv = ds->priv;
926
927 /* Restart TX/RX to port */
928 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
929 // TODO: Set speed/duplex/pauses
930 }
931
932 static void rtl83xx_get_strings(struct dsa_switch *ds,
933 int port, u32 stringset, u8 *data)
934 {
935 int i;
936
937 if (stringset != ETH_SS_STATS)
938 return;
939
940 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
941 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
942 ETH_GSTRING_LEN);
943 }
944
945 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
946 uint64_t *data)
947 {
948 struct rtl838x_switch_priv *priv = ds->priv;
949 const struct rtl83xx_mib_desc *mib;
950 int i;
951 u64 h;
952
953 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
954 mib = &rtl83xx_mib[i];
955
956 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
957 if (mib->size == 2) {
958 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
959 data[i] |= h << 32;
960 }
961 }
962 }
963
964 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
965 {
966 if (sset != ETH_SS_STATS)
967 return 0;
968
969 return ARRAY_SIZE(rtl83xx_mib);
970 }
971
972 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
973 {
974 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
975 u64 portmask;
976
977 if (mc_group >= MAX_MC_GROUPS - 1)
978 return -1;
979
980 if (priv->is_lagmember[port]) {
981 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
982 return 0;
983 }
984
985 set_bit(mc_group, priv->mc_group_bm);
986 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
987 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
988 priv->r->write_mcast_pmask(mc_group, portmask);
989
990 return mc_group;
991 }
992
993 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
994 {
995 u64 portmask = priv->r->read_mcast_pmask(mc_group);
996
997 pr_debug("%s: %d\n", __func__, port);
998 if (priv->is_lagmember[port]) {
999 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1000 return portmask;
1001 }
1002 portmask |= BIT_ULL(port);
1003 priv->r->write_mcast_pmask(mc_group, portmask);
1004
1005 return portmask;
1006 }
1007
1008 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1009 {
1010 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1011
1012 pr_debug("%s: %d\n", __func__, port);
1013 if (priv->is_lagmember[port]) {
1014 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1015 return portmask;
1016 }
1017 priv->r->write_mcast_pmask(mc_group, portmask);
1018 if (portmask == BIT_ULL(priv->cpu_port)) {
1019 portmask &= ~BIT_ULL(priv->cpu_port);
1020 priv->r->write_mcast_pmask(mc_group, portmask);
1021 clear_bit(mc_group, priv->mc_group_bm);
1022 }
1023
1024 return portmask;
1025 }
1026
1027 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1028 {
1029 int mc_group;
1030
1031 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1032 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1033 if (portmask & BIT_ULL(port)) {
1034 priv->mc_group_saves[mc_group] = port;
1035 rtl83xx_mc_group_del_port(priv, mc_group, port);
1036 }
1037 }
1038 }
1039
1040 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1041 {
1042 int mc_group;
1043
1044 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1045 if (priv->mc_group_saves[mc_group] == port) {
1046 rtl83xx_mc_group_add_port(priv, mc_group, port);
1047 priv->mc_group_saves[mc_group] = -1;
1048 }
1049 }
1050 }
1051
1052 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1053 struct phy_device *phydev)
1054 {
1055 struct rtl838x_switch_priv *priv = ds->priv;
1056 u64 v;
1057
1058 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1059 priv->ports[port].enable = true;
1060
1061 /* enable inner tagging on egress, do not keep any tags */
1062 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1063
1064 if (dsa_is_cpu_port(ds, port))
1065 return 0;
1066
1067 /* add port to switch mask of CPU_PORT */
1068 priv->r->traffic_enable(priv->cpu_port, port);
1069
1070 load_mcgroups(priv, port);
1071
1072 if (priv->is_lagmember[port]) {
1073 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1074 return 0;
1075 }
1076
1077 /* add all other ports in the same bridge to switch mask of port */
1078 v = priv->r->traffic_get(port);
1079 v |= priv->ports[port].pm;
1080 priv->r->traffic_set(port, v);
1081
1082 // TODO: Figure out if this is necessary
1083 if (priv->family_id == RTL9300_FAMILY_ID) {
1084 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1085 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1086 }
1087
1088 if (priv->ports[port].sds_num < 0)
1089 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1090
1091 return 0;
1092 }
1093
1094 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1095 {
1096 struct rtl838x_switch_priv *priv = ds->priv;
1097 u64 v;
1098
1099 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1100 /* you can only disable user ports */
1101 if (!dsa_is_user_port(ds, port))
1102 return;
1103
1104 // BUG: This does not work on RTL931X
1105 /* remove port from switch mask of CPU_PORT */
1106 priv->r->traffic_disable(priv->cpu_port, port);
1107 store_mcgroups(priv, port);
1108
1109 /* remove all other ports in the same bridge from switch mask of port */
1110 v = priv->r->traffic_get(port);
1111 v &= ~priv->ports[port].pm;
1112 priv->r->traffic_set(port, v);
1113
1114 priv->ports[port].enable = false;
1115 }
1116
1117 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1118 struct ethtool_eee *e)
1119 {
1120 struct rtl838x_switch_priv *priv = ds->priv;
1121
1122 if (e->eee_enabled && !priv->eee_enabled) {
1123 pr_info("Globally enabling EEE\n");
1124 priv->r->init_eee(priv, true);
1125 }
1126
1127 priv->r->port_eee_set(priv, port, e->eee_enabled);
1128
1129 if (e->eee_enabled)
1130 pr_info("Enabled EEE for port %d\n", port);
1131 else
1132 pr_info("Disabled EEE for port %d\n", port);
1133
1134 return 0;
1135 }
1136
1137 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1138 struct ethtool_eee *e)
1139 {
1140 struct rtl838x_switch_priv *priv = ds->priv;
1141
1142 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1143
1144 priv->r->eee_port_ability(priv, e, port);
1145
1146 e->eee_enabled = priv->ports[port].eee_enabled;
1147
1148 e->eee_active = !!(e->advertised & e->lp_advertised);
1149
1150 return 0;
1151 }
1152
1153 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1154 struct ethtool_eee *e)
1155 {
1156 struct rtl838x_switch_priv *priv = ds->priv;
1157
1158 e->supported = SUPPORTED_100baseT_Full |
1159 SUPPORTED_1000baseT_Full |
1160 SUPPORTED_2500baseX_Full;
1161
1162 priv->r->eee_port_ability(priv, e, port);
1163
1164 e->eee_enabled = priv->ports[port].eee_enabled;
1165
1166 e->eee_active = !!(e->advertised & e->lp_advertised);
1167
1168 return 0;
1169 }
1170
1171 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1172 {
1173 struct rtl838x_switch_priv *priv = ds->priv;
1174
1175 priv->r->set_ageing_time(msec);
1176
1177 return 0;
1178 }
1179
1180 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1181 struct net_device *bridge)
1182 {
1183 struct rtl838x_switch_priv *priv = ds->priv;
1184 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1185 int i;
1186
1187 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1188
1189 if (priv->is_lagmember[port]) {
1190 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1191 return 0;
1192 }
1193
1194 mutex_lock(&priv->reg_mutex);
1195 for (i = 0; i < ds->num_ports; i++) {
1196 /* Add this port to the port matrix of the other ports in the
1197 * same bridge. If the port is disabled, port matrix is kept
1198 * and not being setup until the port becomes enabled.
1199 */
1200 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1201 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1202 continue;
1203 if (priv->ports[i].enable)
1204 priv->r->traffic_enable(i, port);
1205
1206 priv->ports[i].pm |= BIT_ULL(port);
1207 port_bitmap |= BIT_ULL(i);
1208 }
1209 }
1210 load_mcgroups(priv, port);
1211
1212 /* Add all other ports to this port matrix. */
1213 if (priv->ports[port].enable) {
1214 priv->r->traffic_enable(priv->cpu_port, port);
1215 v = priv->r->traffic_get(port);
1216 v |= port_bitmap;
1217 priv->r->traffic_set(port, v);
1218 }
1219 priv->ports[port].pm |= port_bitmap;
1220 mutex_unlock(&priv->reg_mutex);
1221
1222 return 0;
1223 }
1224
1225 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1226 struct net_device *bridge)
1227 {
1228 struct rtl838x_switch_priv *priv = ds->priv;
1229 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1230 int i;
1231
1232 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1233 mutex_lock(&priv->reg_mutex);
1234 for (i = 0; i < ds->num_ports; i++) {
1235 /* Remove this port from the port matrix of the other ports
1236 * in the same bridge. If the port is disabled, port matrix
1237 * is kept and not being setup until the port becomes enabled.
1238 * And the other port's port matrix cannot be broken when the
1239 * other port is still a VLAN-aware port.
1240 */
1241 if (dsa_is_user_port(ds, i) && i != port) {
1242 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1243 continue;
1244 if (priv->ports[i].enable)
1245 priv->r->traffic_disable(i, port);
1246
1247 priv->ports[i].pm |= BIT_ULL(port);
1248 port_bitmap &= ~BIT_ULL(i);
1249 }
1250 }
1251 store_mcgroups(priv, port);
1252
1253 /* Add all other ports to this port matrix. */
1254 if (priv->ports[port].enable) {
1255 v = priv->r->traffic_get(port);
1256 v |= port_bitmap;
1257 priv->r->traffic_set(port, v);
1258 }
1259 priv->ports[port].pm &= ~port_bitmap;
1260
1261 mutex_unlock(&priv->reg_mutex);
1262 }
1263
1264 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1265 {
1266 u32 msti = 0;
1267 u32 port_state[4];
1268 int index, bit;
1269 int pos = port;
1270 struct rtl838x_switch_priv *priv = ds->priv;
1271 int n = priv->port_width << 1;
1272
1273 /* Ports above or equal CPU port can never be configured */
1274 if (port >= priv->cpu_port)
1275 return;
1276
1277 mutex_lock(&priv->reg_mutex);
1278
1279 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1280 * have 64 bit fields, 839x and 931x have 128 bit fields
1281 */
1282 if (priv->family_id == RTL8390_FAMILY_ID)
1283 pos += 12;
1284 if (priv->family_id == RTL9300_FAMILY_ID)
1285 pos += 3;
1286 if (priv->family_id == RTL9310_FAMILY_ID)
1287 pos += 8;
1288
1289 index = n - (pos >> 4) - 1;
1290 bit = (pos << 1) % 32;
1291
1292 priv->r->stp_get(priv, msti, port_state);
1293
1294 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1295 port_state[index] &= ~(3 << bit);
1296
1297 switch (state) {
1298 case BR_STATE_DISABLED: /* 0 */
1299 port_state[index] |= (0 << bit);
1300 break;
1301 case BR_STATE_BLOCKING: /* 4 */
1302 case BR_STATE_LISTENING: /* 1 */
1303 port_state[index] |= (1 << bit);
1304 break;
1305 case BR_STATE_LEARNING: /* 2 */
1306 port_state[index] |= (2 << bit);
1307 break;
1308 case BR_STATE_FORWARDING: /* 3 */
1309 port_state[index] |= (3 << bit);
1310 default:
1311 break;
1312 }
1313
1314 priv->r->stp_set(priv, msti, port_state);
1315
1316 mutex_unlock(&priv->reg_mutex);
1317 }
1318
1319 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1320 {
1321 struct rtl838x_switch_priv *priv = ds->priv;
1322 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1323
1324 pr_debug("FAST AGE port %d\n", port);
1325 mutex_lock(&priv->reg_mutex);
1326 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1327 * port fields:
1328 * 0-4: Replacing port
1329 * 5-9: Flushed/replaced port
1330 * 10-21: FVID
1331 * 22: Entry types: 1: dynamic, 0: also static
1332 * 23: Match flush port
1333 * 24: Match FVID
1334 * 25: Flush (0) or replace (1) L2 entries
1335 * 26: Status of action (1: Start, 0: Done)
1336 */
1337 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1338
1339 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1340
1341 mutex_unlock(&priv->reg_mutex);
1342 }
1343
1344 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1345 {
1346 struct rtl838x_switch_priv *priv = ds->priv;
1347
1348 pr_info("%s port %d\n", __func__, port);
1349 mutex_lock(&priv->reg_mutex);
1350 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1351
1352 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1353
1354 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1355
1356 mutex_unlock(&priv->reg_mutex);
1357 }
1358
1359 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1360 {
1361 struct rtl838x_switch_priv *priv = ds->priv;
1362
1363 if (priv->family_id == RTL9310_FAMILY_ID)
1364 return rtl931x_fast_age(ds, port);
1365
1366 pr_debug("FAST AGE port %d\n", port);
1367 mutex_lock(&priv->reg_mutex);
1368 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1369
1370 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1371
1372 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1373
1374 mutex_unlock(&priv->reg_mutex);
1375 }
1376
1377 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1378 bool vlan_filtering,
1379 struct netlink_ext_ack *extack)
1380 {
1381 struct rtl838x_switch_priv *priv = ds->priv;
1382
1383 pr_debug("%s: port %d\n", __func__, port);
1384 mutex_lock(&priv->reg_mutex);
1385
1386 if (vlan_filtering) {
1387 /* Enable ingress and egress filtering
1388 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1389 * the filter action:
1390 * 0: Always Forward
1391 * 1: Drop packet
1392 * 2: Trap packet to CPU port
1393 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1394 */
1395 if (port != priv->cpu_port)
1396 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1397
1398 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1399 } else {
1400 /* Disable ingress and egress filtering */
1401 if (port != priv->cpu_port)
1402 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1403
1404 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1405 }
1406
1407 /* Do we need to do something to the CPU-Port, too? */
1408 mutex_unlock(&priv->reg_mutex);
1409
1410 return 0;
1411 }
1412
1413 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1414 const struct switchdev_obj_port_vlan *vlan)
1415 {
1416 struct rtl838x_vlan_info info;
1417 struct rtl838x_switch_priv *priv = ds->priv;
1418
1419 priv->r->vlan_tables_read(0, &info);
1420
1421 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1422 info.tagged_ports, info.untagged_ports, info.profile_id,
1423 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1424
1425 priv->r->vlan_tables_read(1, &info);
1426 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1427 info.tagged_ports, info.untagged_ports, info.profile_id,
1428 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1429 priv->r->vlan_set_untagged(1, info.untagged_ports);
1430 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1431
1432 priv->r->vlan_set_tagged(1, &info);
1433 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1434
1435 return 0;
1436 }
1437
1438 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1439 const struct switchdev_obj_port_vlan *vlan,
1440 struct netlink_ext_ack *extack)
1441 {
1442 struct rtl838x_vlan_info info;
1443 struct rtl838x_switch_priv *priv = ds->priv;
1444 int err;
1445
1446 pr_debug("%s port %d, vid %d, flags %x\n",
1447 __func__, port, vlan->vid, vlan->flags);
1448
1449 if (vlan->vid > 4095) {
1450 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1451 return -ENOTSUPP;
1452 }
1453
1454 err = rtl83xx_vlan_prepare(ds, port, vlan);
1455 if (err)
1456 return err;
1457
1458 mutex_lock(&priv->reg_mutex);
1459
1460 if (vlan->flags & BRIDGE_VLAN_INFO_PVID && vlan->vid) {
1461 /* Set both inner and outer PVID of the port */
1462 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, vlan->vid);
1463 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, vlan->vid);
1464 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1465 PBVLAN_MODE_UNTAG_AND_PRITAG);
1466 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1467 PBVLAN_MODE_UNTAG_AND_PRITAG);
1468
1469 priv->ports[port].pvid = vlan->vid;
1470 }
1471
1472 /* Get port memberships of this vlan */
1473 priv->r->vlan_tables_read(vlan->vid, &info);
1474
1475 /* new VLAN? */
1476 if (!info.tagged_ports) {
1477 info.fid = 0;
1478 info.hash_mc_fid = false;
1479 info.hash_uc_fid = false;
1480 info.profile_id = 0;
1481 }
1482
1483 /* sanitize untagged_ports - must be a subset */
1484 if (info.untagged_ports & ~info.tagged_ports)
1485 info.untagged_ports = 0;
1486
1487 info.tagged_ports |= BIT_ULL(port);
1488 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1489 info.untagged_ports |= BIT_ULL(port);
1490
1491 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1492 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1493
1494 priv->r->vlan_set_tagged(vlan->vid, &info);
1495 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1496
1497 mutex_unlock(&priv->reg_mutex);
1498
1499 return 0;
1500 }
1501
1502 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1503 const struct switchdev_obj_port_vlan *vlan)
1504 {
1505 struct rtl838x_vlan_info info;
1506 struct rtl838x_switch_priv *priv = ds->priv;
1507 u16 pvid;
1508
1509 pr_debug("%s: port %d, vid %d, flags %x\n",
1510 __func__, port, vlan->vid, vlan->flags);
1511
1512 if (vlan->vid > 4095) {
1513 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1514 return -ENOTSUPP;
1515 }
1516
1517 mutex_lock(&priv->reg_mutex);
1518 pvid = priv->ports[port].pvid;
1519
1520 /* Reset to default if removing the current PVID */
1521 if (vlan->vid == pvid) {
1522 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1523 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1524 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1525 PBVLAN_MODE_UNTAG_AND_PRITAG);
1526 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1527 PBVLAN_MODE_UNTAG_AND_PRITAG);
1528 }
1529 /* Get port memberships of this vlan */
1530 priv->r->vlan_tables_read(vlan->vid, &info);
1531
1532 /* remove port from both tables */
1533 info.untagged_ports &= (~BIT_ULL(port));
1534 info.tagged_ports &= (~BIT_ULL(port));
1535
1536 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1537 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1538
1539 priv->r->vlan_set_tagged(vlan->vid, &info);
1540 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1541
1542 mutex_unlock(&priv->reg_mutex);
1543
1544 return 0;
1545 }
1546
1547 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1548 {
1549 memset(e, 0, sizeof(*e));
1550
1551 e->type = L2_UNICAST;
1552 e->valid = true;
1553
1554 e->age = 3;
1555 e->is_static = true;
1556
1557 e->port = port;
1558
1559 e->rvid = e->vid = vid;
1560 e->is_ip_mc = e->is_ipv6_mc = false;
1561 u64_to_ether_addr(mac, e->mac);
1562 }
1563
1564 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1565 {
1566 memset(e, 0, sizeof(*e));
1567
1568 e->type = L2_MULTICAST;
1569 e->valid = true;
1570
1571 e->mc_portmask_index = mc_group;
1572
1573 e->rvid = e->vid = vid;
1574 e->is_ip_mc = e->is_ipv6_mc = false;
1575 u64_to_ether_addr(mac, e->mac);
1576 }
1577
1578 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1579 * over the entries in the bucket until either a matching entry is found or an empty slot
1580 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1581 * when an empty slot was found and must exist is false, the index of the slot is returned
1582 * when no slots are available returns -1
1583 */
1584 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1585 bool must_exist, struct rtl838x_l2_entry *e)
1586 {
1587 int i, idx = -1;
1588 u32 key = priv->r->l2_hash_key(priv, seed);
1589 u64 entry;
1590
1591 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1592 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1593 for (i = 0; i < priv->l2_bucket_size; i++) {
1594 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1595 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1596 if (must_exist && !e->valid)
1597 continue;
1598 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1599 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1600 break;
1601 }
1602 }
1603
1604 return idx;
1605 }
1606
1607 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1608 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1609 * when an empty slot was found the index of the slot is returned
1610 * when no slots are available returns -1
1611 */
1612 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1613 bool must_exist, struct rtl838x_l2_entry *e)
1614 {
1615 int i, idx = -1;
1616 u64 entry;
1617
1618 for (i = 0; i < 64; i++) {
1619 entry = priv->r->read_cam(i, e);
1620 if (!must_exist && !e->valid) {
1621 if (idx < 0) /* First empty entry? */
1622 idx = i;
1623 break;
1624 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1625 pr_debug("Found entry in CAM\n");
1626 idx = i;
1627 break;
1628 }
1629 }
1630
1631 return idx;
1632 }
1633
1634 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1635 const unsigned char *addr, u16 vid)
1636 {
1637 struct rtl838x_switch_priv *priv = ds->priv;
1638 u64 mac = ether_addr_to_u64(addr);
1639 struct rtl838x_l2_entry e;
1640 int err = 0, idx;
1641 u64 seed = priv->r->l2_hash_seed(mac, vid);
1642
1643 if (priv->is_lagmember[port]) {
1644 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1645 return 0;
1646 }
1647
1648 mutex_lock(&priv->reg_mutex);
1649
1650 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1651
1652 // Found an existing or empty entry
1653 if (idx >= 0) {
1654 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1655 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1656 goto out;
1657 }
1658
1659 // Hash buckets full, try CAM
1660 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1661
1662 if (idx >= 0) {
1663 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1664 priv->r->write_cam(idx, &e);
1665 goto out;
1666 }
1667
1668 err = -ENOTSUPP;
1669
1670 out:
1671 mutex_unlock(&priv->reg_mutex);
1672
1673 return err;
1674 }
1675
1676 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1677 const unsigned char *addr, u16 vid)
1678 {
1679 struct rtl838x_switch_priv *priv = ds->priv;
1680 u64 mac = ether_addr_to_u64(addr);
1681 struct rtl838x_l2_entry e;
1682 int err = 0, idx;
1683 u64 seed = priv->r->l2_hash_seed(mac, vid);
1684
1685 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1686 mutex_lock(&priv->reg_mutex);
1687
1688 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1689
1690 if (idx >= 0) {
1691 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1692 e.valid = false;
1693 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1694 goto out;
1695 }
1696
1697 /* Check CAM for spillover from hash buckets */
1698 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1699
1700 if (idx >= 0) {
1701 e.valid = false;
1702 priv->r->write_cam(idx, &e);
1703 goto out;
1704 }
1705 err = -ENOENT;
1706
1707 out:
1708 mutex_unlock(&priv->reg_mutex);
1709
1710 return err;
1711 }
1712
1713 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1714 dsa_fdb_dump_cb_t *cb, void *data)
1715 {
1716 struct rtl838x_l2_entry e;
1717 struct rtl838x_switch_priv *priv = ds->priv;
1718 int i;
1719
1720 mutex_lock(&priv->reg_mutex);
1721
1722 for (i = 0; i < priv->fib_entries; i++) {
1723 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1724
1725 if (!e.valid)
1726 continue;
1727
1728 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1729 cb(e.mac, e.vid, e.is_static, data);
1730
1731 if (!((i + 1) % 64))
1732 cond_resched();
1733 }
1734
1735 for (i = 0; i < 64; i++) {
1736 priv->r->read_cam(i, &e);
1737
1738 if (!e.valid)
1739 continue;
1740
1741 if (e.port == port)
1742 cb(e.mac, e.vid, e.is_static, data);
1743 }
1744
1745 mutex_unlock(&priv->reg_mutex);
1746
1747 return 0;
1748 }
1749
1750 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1751 const struct switchdev_obj_port_mdb *mdb)
1752 {
1753 struct rtl838x_switch_priv *priv = ds->priv;
1754 u64 mac = ether_addr_to_u64(mdb->addr);
1755 struct rtl838x_l2_entry e;
1756 int err = 0, idx;
1757 int vid = mdb->vid;
1758 u64 seed = priv->r->l2_hash_seed(mac, vid);
1759 int mc_group;
1760
1761 if (priv->id >= 0x9300)
1762 return -EOPNOTSUPP;
1763
1764 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1765
1766 if (priv->is_lagmember[port]) {
1767 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1768 return -EINVAL;
1769 }
1770
1771 mutex_lock(&priv->reg_mutex);
1772
1773 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1774
1775 // Found an existing or empty entry
1776 if (idx >= 0) {
1777 if (e.valid) {
1778 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1779 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1780 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1781 } else {
1782 pr_debug("New entry for seed %016llx\n", seed);
1783 mc_group = rtl83xx_mc_group_alloc(priv, port);
1784 if (mc_group < 0) {
1785 err = -ENOTSUPP;
1786 goto out;
1787 }
1788 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1789 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1790 }
1791 goto out;
1792 }
1793
1794 // Hash buckets full, try CAM
1795 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1796
1797 if (idx >= 0) {
1798 if (e.valid) {
1799 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1800 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1801 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1802 } else {
1803 pr_debug("New entry\n");
1804 mc_group = rtl83xx_mc_group_alloc(priv, port);
1805 if (mc_group < 0) {
1806 err = -ENOTSUPP;
1807 goto out;
1808 }
1809 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1810 priv->r->write_cam(idx, &e);
1811 }
1812 goto out;
1813 }
1814
1815 err = -ENOTSUPP;
1816
1817 out:
1818 mutex_unlock(&priv->reg_mutex);
1819 if (err)
1820 dev_err(ds->dev, "failed to add MDB entry\n");
1821
1822 return err;
1823 }
1824
1825 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1826 const struct switchdev_obj_port_mdb *mdb)
1827 {
1828 struct rtl838x_switch_priv *priv = ds->priv;
1829 u64 mac = ether_addr_to_u64(mdb->addr);
1830 struct rtl838x_l2_entry e;
1831 int err = 0, idx;
1832 int vid = mdb->vid;
1833 u64 seed = priv->r->l2_hash_seed(mac, vid);
1834 u64 portmask;
1835
1836 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1837
1838 if (priv->is_lagmember[port]) {
1839 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1840 return 0;
1841 }
1842
1843 mutex_lock(&priv->reg_mutex);
1844
1845 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1846
1847 if (idx >= 0) {
1848 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1849 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1850 if (!portmask) {
1851 e.valid = false;
1852 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1853 }
1854 goto out;
1855 }
1856
1857 /* Check CAM for spillover from hash buckets */
1858 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1859
1860 if (idx >= 0) {
1861 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1862 if (!portmask) {
1863 e.valid = false;
1864 priv->r->write_cam(idx, &e);
1865 }
1866 goto out;
1867 }
1868 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1869
1870 out:
1871 mutex_unlock(&priv->reg_mutex);
1872
1873 return err;
1874 }
1875
1876 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1877 struct dsa_mall_mirror_tc_entry *mirror,
1878 bool ingress)
1879 {
1880 /* We support 4 mirror groups, one destination port per group */
1881 int group;
1882 struct rtl838x_switch_priv *priv = ds->priv;
1883 int ctrl_reg, dpm_reg, spm_reg;
1884
1885 pr_debug("In %s\n", __func__);
1886
1887 for (group = 0; group < 4; group++) {
1888 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1889 break;
1890 }
1891 if (group >= 4) {
1892 for (group = 0; group < 4; group++) {
1893 if (priv->mirror_group_ports[group] < 0)
1894 break;
1895 }
1896 }
1897
1898 if (group >= 4)
1899 return -ENOSPC;
1900
1901 ctrl_reg = priv->r->mir_ctrl + group * 4;
1902 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1903 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1904
1905 pr_debug("Using group %d\n", group);
1906 mutex_lock(&priv->reg_mutex);
1907
1908 if (priv->family_id == RTL8380_FAMILY_ID) {
1909 /* Enable mirroring to port across VLANs (bit 11) */
1910 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1911 } else {
1912 /* Enable mirroring to destination port */
1913 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1914 }
1915
1916 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1917 mutex_unlock(&priv->reg_mutex);
1918 return -EEXIST;
1919 }
1920 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1921 mutex_unlock(&priv->reg_mutex);
1922 return -EEXIST;
1923 }
1924
1925 if (ingress)
1926 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1927 else
1928 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1929
1930 priv->mirror_group_ports[group] = mirror->to_local_port;
1931 mutex_unlock(&priv->reg_mutex);
1932
1933 return 0;
1934 }
1935
1936 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1937 struct dsa_mall_mirror_tc_entry *mirror)
1938 {
1939 int group = 0;
1940 struct rtl838x_switch_priv *priv = ds->priv;
1941 int ctrl_reg, dpm_reg, spm_reg;
1942
1943 pr_debug("In %s\n", __func__);
1944 for (group = 0; group < 4; group++) {
1945 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1946 break;
1947 }
1948 if (group >= 4)
1949 return;
1950
1951 ctrl_reg = priv->r->mir_ctrl + group * 4;
1952 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1953 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1954
1955 mutex_lock(&priv->reg_mutex);
1956 if (mirror->ingress) {
1957 /* Ingress, clear source port matrix */
1958 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1959 } else {
1960 /* Egress, clear destination port matrix */
1961 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1962 }
1963
1964 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1965 priv->mirror_group_ports[group] = -1;
1966 sw_w32(0, ctrl_reg);
1967 }
1968
1969 mutex_unlock(&priv->reg_mutex);
1970 }
1971
1972 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1973 {
1974 struct rtl838x_switch_priv *priv = ds->priv;
1975 unsigned long features = 0;
1976 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1977 if (priv->r->enable_learning)
1978 features |= BR_LEARNING;
1979 if (priv->r->enable_flood)
1980 features |= BR_FLOOD;
1981 if (priv->r->enable_mcast_flood)
1982 features |= BR_MCAST_FLOOD;
1983 if (priv->r->enable_bcast_flood)
1984 features |= BR_BCAST_FLOOD;
1985 if (flags.mask & ~(features))
1986 return -EINVAL;
1987
1988 return 0;
1989 }
1990
1991 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1992 {
1993 struct rtl838x_switch_priv *priv = ds->priv;
1994
1995 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1996 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1997 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1998
1999 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
2000 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
2001
2002 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
2003 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
2004
2005 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
2006 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
2007
2008 return 0;
2009 }
2010
2011 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2012 struct net_device *lag,
2013 struct netdev_lag_upper_info *info)
2014 {
2015 int id;
2016
2017 id = dsa_lag_id(ds->dst, lag);
2018 if (id < 0 || id >= ds->num_lag_ids)
2019 return false;
2020
2021 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2022 return false;
2023 }
2024 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2025 return false;
2026
2027 return true;
2028 }
2029
2030 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2031 {
2032 struct rtl838x_switch_priv *priv = ds->priv;
2033
2034 pr_debug("%s: %d\n", __func__, port);
2035 // Nothing to be done...
2036
2037 return 0;
2038 }
2039
2040 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2041 struct net_device *lag,
2042 struct netdev_lag_upper_info *info)
2043 {
2044 struct rtl838x_switch_priv *priv = ds->priv;
2045 int i, err = 0;
2046
2047 if (!rtl83xx_lag_can_offload(ds, lag, info))
2048 return -EOPNOTSUPP;
2049
2050 mutex_lock(&priv->reg_mutex);
2051
2052 for (i = 0; i < priv->n_lags; i++) {
2053 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2054 break;
2055 }
2056 if (port >= priv->cpu_port) {
2057 err = -EINVAL;
2058 goto out;
2059 }
2060 pr_info("port_lag_join: group %d, port %d\n",i, port);
2061 if (!priv->lag_devs[i])
2062 priv->lag_devs[i] = lag;
2063
2064 if (priv->lag_primary[i] == -1) {
2065 priv->lag_primary[i] = port;
2066 } else
2067 priv->is_lagmember[port] = 1;
2068
2069 priv->lagmembers |= (1ULL << port);
2070
2071 pr_debug("lag_members = %llX\n", priv->lagmembers);
2072 err = rtl83xx_lag_add(priv->ds, i, port, info);
2073 if (err) {
2074 err = -EINVAL;
2075 goto out;
2076 }
2077
2078 out:
2079 mutex_unlock(&priv->reg_mutex);
2080
2081 return err;
2082 }
2083
2084 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2085 struct net_device *lag)
2086 {
2087 int i, group = -1, err;
2088 struct rtl838x_switch_priv *priv = ds->priv;
2089
2090 mutex_lock(&priv->reg_mutex);
2091 for (i = 0; i < priv->n_lags; i++) {
2092 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2093 group = i;
2094 break;
2095 }
2096 }
2097
2098 if (group == -1) {
2099 pr_info("port_lag_leave: port %d is not a member\n", port);
2100 err = -EINVAL;
2101 goto out;
2102 }
2103
2104 if (port >= priv->cpu_port) {
2105 err = -EINVAL;
2106 goto out;
2107 }
2108 pr_info("port_lag_del: group %d, port %d\n",group, port);
2109 priv->lagmembers &=~ (1ULL << port);
2110 priv->lag_primary[i] = -1;
2111 priv->is_lagmember[port] = 0;
2112 pr_debug("lag_members = %llX\n", priv->lagmembers);
2113 err = rtl83xx_lag_del(priv->ds, group, port);
2114 if (err) {
2115 err = -EINVAL;
2116 goto out;
2117 }
2118 if (!priv->lags_port_members[i])
2119 priv->lag_devs[i] = NULL;
2120
2121 out:
2122 mutex_unlock(&priv->reg_mutex);
2123 return 0;
2124 }
2125
2126 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2127 {
2128 u32 val;
2129 u32 offset = 0;
2130 struct rtl838x_switch_priv *priv = ds->priv;
2131
2132 if ((phy_addr >= 24) &&
2133 (phy_addr <= 27) &&
2134 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2135 if (phy_addr == 26)
2136 offset = 0x100;
2137 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2138 return val;
2139 }
2140
2141 read_phy(phy_addr, 0, phy_reg, &val);
2142 return val;
2143 }
2144
2145 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2146 {
2147 u32 offset = 0;
2148 struct rtl838x_switch_priv *priv = ds->priv;
2149
2150 if ((phy_addr >= 24) &&
2151 (phy_addr <= 27) &&
2152 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2153 if (phy_addr == 26)
2154 offset = 0x100;
2155 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2156 return 0;
2157 }
2158 return write_phy(phy_addr, 0, phy_reg, val);
2159 }
2160
2161 const struct dsa_switch_ops rtl83xx_switch_ops = {
2162 .get_tag_protocol = rtl83xx_get_tag_protocol,
2163 .setup = rtl83xx_setup,
2164
2165 .phy_read = dsa_phy_read,
2166 .phy_write = dsa_phy_write,
2167
2168 .phylink_validate = rtl83xx_phylink_validate,
2169 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2170 .phylink_mac_config = rtl83xx_phylink_mac_config,
2171 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2172 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2173
2174 .get_strings = rtl83xx_get_strings,
2175 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2176 .get_sset_count = rtl83xx_get_sset_count,
2177
2178 .port_enable = rtl83xx_port_enable,
2179 .port_disable = rtl83xx_port_disable,
2180
2181 .get_mac_eee = rtl83xx_get_mac_eee,
2182 .set_mac_eee = rtl83xx_set_mac_eee,
2183
2184 .set_ageing_time = rtl83xx_set_ageing_time,
2185 .port_bridge_join = rtl83xx_port_bridge_join,
2186 .port_bridge_leave = rtl83xx_port_bridge_leave,
2187 .port_stp_state_set = rtl83xx_port_stp_state_set,
2188 .port_fast_age = rtl83xx_fast_age,
2189
2190 .port_vlan_filtering = rtl83xx_vlan_filtering,
2191 .port_vlan_add = rtl83xx_vlan_add,
2192 .port_vlan_del = rtl83xx_vlan_del,
2193
2194 .port_fdb_add = rtl83xx_port_fdb_add,
2195 .port_fdb_del = rtl83xx_port_fdb_del,
2196 .port_fdb_dump = rtl83xx_port_fdb_dump,
2197
2198 .port_mdb_add = rtl83xx_port_mdb_add,
2199 .port_mdb_del = rtl83xx_port_mdb_del,
2200
2201 .port_mirror_add = rtl83xx_port_mirror_add,
2202 .port_mirror_del = rtl83xx_port_mirror_del,
2203
2204 .port_lag_change = rtl83xx_port_lag_change,
2205 .port_lag_join = rtl83xx_port_lag_join,
2206 .port_lag_leave = rtl83xx_port_lag_leave,
2207
2208 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2209 .port_bridge_flags = rtl83xx_port_bridge_flags,
2210 };
2211
2212 const struct dsa_switch_ops rtl930x_switch_ops = {
2213 .get_tag_protocol = rtl83xx_get_tag_protocol,
2214 .setup = rtl93xx_setup,
2215
2216 .phy_read = dsa_phy_read,
2217 .phy_write = dsa_phy_write,
2218
2219 .phylink_validate = rtl93xx_phylink_validate,
2220 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2221 .phylink_mac_config = rtl93xx_phylink_mac_config,
2222 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2223 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2224
2225 .get_strings = rtl83xx_get_strings,
2226 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2227 .get_sset_count = rtl83xx_get_sset_count,
2228
2229 .port_enable = rtl83xx_port_enable,
2230 .port_disable = rtl83xx_port_disable,
2231
2232 .get_mac_eee = rtl93xx_get_mac_eee,
2233 .set_mac_eee = rtl83xx_set_mac_eee,
2234
2235 .set_ageing_time = rtl83xx_set_ageing_time,
2236 .port_bridge_join = rtl83xx_port_bridge_join,
2237 .port_bridge_leave = rtl83xx_port_bridge_leave,
2238 .port_stp_state_set = rtl83xx_port_stp_state_set,
2239 .port_fast_age = rtl930x_fast_age,
2240
2241 .port_vlan_filtering = rtl83xx_vlan_filtering,
2242 .port_vlan_add = rtl83xx_vlan_add,
2243 .port_vlan_del = rtl83xx_vlan_del,
2244
2245 .port_fdb_add = rtl83xx_port_fdb_add,
2246 .port_fdb_del = rtl83xx_port_fdb_del,
2247 .port_fdb_dump = rtl83xx_port_fdb_dump,
2248
2249 .port_mdb_add = rtl83xx_port_mdb_add,
2250 .port_mdb_del = rtl83xx_port_mdb_del,
2251
2252 .port_lag_change = rtl83xx_port_lag_change,
2253 .port_lag_join = rtl83xx_port_lag_join,
2254 .port_lag_leave = rtl83xx_port_lag_leave,
2255
2256 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2257 .port_bridge_flags = rtl83xx_port_bridge_flags,
2258 };
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