19049e4c957a069212b4521d39592004571eb011
[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl838x.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef _RTL838X_H
4 #define _RTL838X_H
5
6 #include <net/dsa.h>
7
8 /*
9 * Register definition
10 */
11 #define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
12 #define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
13 #define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6)))
14 #define RTL931X_MAC_PORT_CTRL (0x6004)
15
16 #define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6)))
17 #define RTL931X_MAC_L2_PORT_CTRL (0x6000)
18
19 #define RTL838X_RST_GLB_CTRL_0 (0x003c)
20
21 #define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
22 #define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
23 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
24 #define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC)
25
26 #define RTL838X_DMY_REG31 (0x3b28)
27 #define RTL838X_SDS_MODE_SEL (0x0028)
28 #define RTL838X_SDS_CFG_REG (0x0034)
29 #define RTL838X_INT_MODE_CTRL (0x005c)
30 #define RTL838X_CHIP_INFO (0x00d8)
31 #define RTL839X_CHIP_INFO (0x0ff4)
32 #define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
33 #define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
34
35 /* Packet statistics */
36 #define RTL838X_STAT_PORT_STD_MIB (0x1200)
37 #define RTL839X_STAT_PORT_STD_MIB (0xC000)
38 #define RTL930X_STAT_PORT_MIB_CNTR (0x0664)
39 #define RTL838X_STAT_RST (0x3100)
40 #define RTL839X_STAT_RST (0xF504)
41 #define RTL930X_STAT_RST (0x3240)
42 #define RTL931X_STAT_RST (0x7ef4)
43 #define RTL838X_STAT_PORT_RST (0x3104)
44 #define RTL839X_STAT_PORT_RST (0xF508)
45 #define RTL930X_STAT_PORT_RST (0x3244)
46 #define RTL931X_STAT_PORT_RST (0x7ef8)
47 #define RTL838X_STAT_CTRL (0x3108)
48 #define RTL839X_STAT_CTRL (0x04cc)
49 #define RTL930X_STAT_CTRL (0x3248)
50 #define RTL931X_STAT_CTRL (0x5720)
51
52 /* Registers of the internal Serdes of the 8390 */
53 #define RTL8390_SDS0_1_XSG0 (0xA000)
54 #define RTL8390_SDS0_1_XSG1 (0xA100)
55 #define RTL839X_SDS12_13_XSG0 (0xB800)
56 #define RTL839X_SDS12_13_XSG1 (0xB900)
57 #define RTL839X_SDS12_13_PWR0 (0xb880)
58 #define RTL839X_SDS12_13_PWR1 (0xb980)
59
60 /* Registers of the internal Serdes of the 8380 */
61 #define RTL838X_SDS4_FIB_REG0 (0xF800)
62 #define RTL838X_SDS4_REG28 (0xef80)
63 #define RTL838X_SDS4_DUMMY0 (0xef8c)
64 #define RTL838X_SDS5_EXT_REG6 (0xf18c)
65
66 /* VLAN registers */
67 #define RTL838X_VLAN_CTRL (0x3A74)
68 #define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
69 #define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
70 #define RTL838X_VLAN_PORT_PB_VLAN (0x3C00)
71 #define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C)
72
73 #define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3)))
74 #define RTL839X_VLAN_CTRL (0x26D4)
75 #define RTL839X_VLAN_PORT_PB_VLAN (0x26D8)
76 #define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4)
77 #define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4)
78
79 #define RTL930X_VLAN_PROFILE_SET(idx) (0x9c60 + (((idx) * 20)))
80 #define RTL930X_VLAN_CTRL (0x82D4)
81 #define RTL930X_VLAN_PORT_PB_VLAN (0x82D8)
82 #define RTL930X_VLAN_PORT_IGR_FLTR (0x83C0)
83 #define RTL930X_VLAN_PORT_EGR_FLTR (0x83C8)
84
85 #define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28)))
86 #define RTL931X_VLAN_CTRL (0x94E4)
87 #define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8)
88 #define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4)
89 #define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4)
90
91 /* Table access registers */
92 #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
93 #define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
94 #define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
95 #define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
96
97 #define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
98 #define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2))
99 #define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
100 #define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
101 #define RTL839X_TBL_ACCESS_CTRL_2 (0x611C)
102 #define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2)))
103
104 #define RTL930X_TBL_ACCESS_CTRL_0 (0xB340)
105 #define RTL930X_TBL_ACCESS_DATA_0(idx) (0xB344 + ((idx) << 2))
106 #define RTL930X_TBL_ACCESS_CTRL_1 (0xB3A0)
107 #define RTL930X_TBL_ACCESS_DATA_1(idx) (0xB3A4 + ((idx) << 2))
108 #define RTL930X_TBL_ACCESS_CTRL_2 (0xCE04)
109 #define RTL930X_TBL_ACCESS_DATA_2(i) (0xCE08 + (((i) << 2)))
110
111 #define RTL931X_TBL_ACCESS_CTRL_0 (0x8500)
112 #define RTL931X_TBL_ACCESS_DATA_0(idx) (0x8508 + ((idx) << 2))
113 #define RTL931X_TBL_ACCESS_CTRL_1 (0x40C0)
114 #define RTL931X_TBL_ACCESS_DATA_1(idx) (0x40C4 + ((idx) << 2))
115 #define RTL931X_TBL_ACCESS_CTRL_2 (0x8528)
116 #define RTL931X_TBL_ACCESS_DATA_2(i) (0x852C + (((i) << 2)))
117 #define RTL931X_TBL_ACCESS_CTRL_3 (0x0200)
118 #define RTL931X_TBL_ACCESS_DATA_3(i) (0x0204 + (((i) << 2)))
119 #define RTL931X_TBL_ACCESS_CTRL_4 (0x20DC)
120 #define RTL931X_TBL_ACCESS_DATA_4(i) (0x20E0 + (((i) << 2)))
121 #define RTL931X_TBL_ACCESS_CTRL_5 (0x7E1C)
122 #define RTL931X_TBL_ACCESS_DATA_5(i) (0x7E20 + (((i) << 2)))
123
124 /* MAC handling */
125 #define RTL838X_MAC_LINK_STS (0xa188)
126 #define RTL839X_MAC_LINK_STS (0x0390)
127 #define RTL930X_MAC_LINK_STS (0xCB10)
128 #define RTL931X_MAC_LINK_STS (0x0EC0)
129 #define RTL838X_MAC_LINK_SPD_STS(p) (0xa190 + (((p >> 4) << 2)))
130 #define RTL839X_MAC_LINK_SPD_STS(p) (0x03a0 + (((p >> 4) << 2)))
131 #define RTL930X_MAC_LINK_SPD_STS(p) (0xCB18 + (((p >> 3) << 2)))
132 #define RTL931X_MAC_LINK_SPD_STS (0x0ED0)
133 #define RTL838X_MAC_LINK_DUP_STS (0xa19c)
134 #define RTL839X_MAC_LINK_DUP_STS (0x03b0)
135 #define RTL930X_MAC_LINK_DUP_STS (0xCB28)
136 #define RTL931X_MAC_LINK_DUP_STS (0x0EF0)
137 #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
138 #define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
139 #define RTL930X_MAC_TX_PAUSE_STS (0xCB2C)
140 #define RTL931X_MAC_TX_PAUSE_STS (0x0EF8)
141 #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
142 #define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
143 #define RTL930X_MAC_RX_PAUSE_STS (0xCB30)
144 #define RTL931X_MAC_RX_PAUSE_STS (0x0F00)
145 #define RTL930X_MAC_LINK_MEDIA_STS (0xCB14)
146 #define RTL931X_MAC_LINK_MEDIA_STS (0x0EC8)
147
148 /* MAC link state bits */
149 #define RTL838X_FORCE_EN (1 << 0)
150 #define RTL838X_FORCE_LINK_EN (1 << 1)
151 #define RTL838X_NWAY_EN (1 << 2)
152 #define RTL838X_DUPLEX_MODE (1 << 3)
153 #define RTL838X_TX_PAUSE_EN (1 << 6)
154 #define RTL838X_RX_PAUSE_EN (1 << 7)
155 #define RTL838X_MAC_FORCE_FC_EN (1 << 8)
156
157 #define RTL839X_FORCE_EN (1 << 0)
158 #define RTL839X_FORCE_LINK_EN (1 << 1)
159 #define RTL839X_DUPLEX_MODE (1 << 2)
160 #define RTL839X_TX_PAUSE_EN (1 << 5)
161 #define RTL839X_RX_PAUSE_EN (1 << 6)
162 #define RTL839X_MAC_FORCE_FC_EN (1 << 7)
163
164 #define RTL930X_FORCE_EN (1 << 0)
165 #define RTL930X_FORCE_LINK_EN (1 << 1)
166 #define RTL930X_DUPLEX_MODE (1 << 2)
167 #define RTL930X_TX_PAUSE_EN (1 << 7)
168 #define RTL930X_RX_PAUSE_EN (1 << 8)
169 #define RTL930X_MAC_FORCE_FC_EN (1 << 9)
170
171 #define RTL931X_FORCE_EN (1 << 9)
172 #define RTL931X_FORCE_LINK_EN (1 << 0)
173 #define RTL931X_DUPLEX_MODE (1 << 2)
174 #define RTL931X_MAC_FORCE_FC_EN (1 << 4)
175 #define RTL931X_TX_PAUSE_EN (1 << 16)
176 #define RTL931X_RX_PAUSE_EN (1 << 17)
177
178 /* EEE */
179 #define RTL838X_MAC_EEE_ABLTY (0xa1a8)
180 #define RTL838X_EEE_PORT_TX_EN (0x014c)
181 #define RTL838X_EEE_PORT_RX_EN (0x0150)
182 #define RTL838X_EEE_CLK_STOP_CTRL (0x0148)
183 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
184 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
185
186 #define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C)
187 #define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430)
188 #define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434)
189 #define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7))
190 #define RTL839X_MAC_EEE_ABLTY (0x03C8)
191
192 #define RTL930X_MAC_EEE_ABLTY (0xCB34)
193 #define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6))
194 #define RTL930X_EEEP_PORT_CTRL(p) (0x3278 + ((p) << 6))
195
196 /* L2 functionality */
197 #define RTL838X_L2_CTRL_0 (0x3200)
198 #define RTL839X_L2_CTRL_0 (0x3800)
199 #define RTL930X_L2_CTRL (0x8FD8)
200 #define RTL931X_L2_CTRL (0xC800)
201 #define RTL838X_L2_CTRL_1 (0x3204)
202 #define RTL839X_L2_CTRL_1 (0x3804)
203 #define RTL930X_L2_AGE_CTRL (0x8FDC)
204 #define RTL931X_L2_AGE_CTRL (0xC804)
205 #define RTL838X_L2_PORT_AGING_OUT (0x3358)
206 #define RTL839X_L2_PORT_AGING_OUT (0x3b74)
207 #define RTL930X_L2_PORT_AGE_CTRL (0x8FE0)
208 #define RTL931X_L2_PORT_AGE_CTRL (0xc808)
209 #define RTL838X_TBL_ACCESS_L2_CTRL (0x6900)
210 #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
211 #define RTL930X_TBL_ACCESS_L2_CTRL (0xB320)
212 #define RTL930X_TBL_ACCESS_L2_METHOD_CTRL (0xB324)
213 #define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
214 #define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
215 #define RTL930X_TBL_ACCESS_L2_DATA(idx) (0xab08 + ((idx) << 2))
216
217 #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
218 #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
219 #define RTL930X_L2_TBL_FLUSH_CTRL (0x9404)
220 #define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C)
221
222 #define RTL838X_L2_LRN_CONSTRT (0x329C)
223 #define RTL839X_L2_LRN_CONSTRT (0x3910)
224 #define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c)
225 #define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964)
226
227 #define RTL838X_L2_FLD_PMSK (0x3288)
228 #define RTL839X_L2_FLD_PMSK (0x38EC)
229 #define RTL930X_L2_BC_FLD_PMSK (0x9068)
230 #define RTL931X_L2_BC_FLD_PMSK (0xC8FC)
231
232 #define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064)
233 #define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4)
234
235 #define RTL838X_L2_LRN_CONSTRT_EN (0x3368)
236 #define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0)
237 #define RTL839X_L2_PORT_LRN_CONSTRT (0x3914)
238
239 #define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2)))
240 #define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
241 #define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2)))
242 #define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2)))
243
244 #define SALRN_PORT_SHIFT(p) ((p % 16) * 2)
245 #define SALRN_MODE_MASK 0x3
246 #define SALRN_MODE_HARDWARE 0
247 #define SALRN_MODE_DISABLED 2
248
249 #define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2)))
250 #define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2)))
251 #define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2)))
252 #define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2)))
253
254 #define RTL930X_ST_CTRL (0x8798)
255
256 #define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
257 #define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
258
259 #define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2))
260 #define RTL838X_VLAN_PORT_FWD (0x3A78)
261 #define RTL839X_VLAN_PORT_FWD (0x27AC)
262 #define RTL930X_VLAN_PORT_FWD (0x834C)
263 #define RTL931X_VLAN_PORT_FWD (0x95CC)
264 #define RTL838X_VLAN_FID_CTRL (0x3aa8)
265
266 /* Port Mirroring */
267 #define RTL838X_MIR_CTRL (0x5D00)
268 #define RTL838X_MIR_DPM_CTRL (0x5D20)
269 #define RTL838X_MIR_SPM_CTRL (0x5D10)
270
271 #define RTL839X_MIR_CTRL (0x2500)
272 #define RTL839X_MIR_DPM_CTRL (0x2530)
273 #define RTL839X_MIR_SPM_CTRL (0x2510)
274
275 #define RTL930X_MIR_CTRL (0xA2A0)
276 #define RTL930X_MIR_DPM_CTRL (0xA2C0)
277 #define RTL930X_MIR_SPM_CTRL (0xA2B0)
278
279 #define RTL931X_MIR_CTRL (0xAF00)
280 #define RTL931X_MIR_DPM_CTRL (0xAF30)
281 #define RTL931X_MIR_SPM_CTRL (0xAF10)
282
283 /* Storm/rate control and scheduling */
284 #define RTL838X_STORM_CTRL (0x4700)
285 #define RTL839X_STORM_CTRL (0x1800)
286 #define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2)))
287 #define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874)
288 #define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878)
289 #define RTL838X_STORM_CTRL_BURST_0 (0x487c)
290 #define RTL838X_STORM_CTRL_BURST_1 (0x4880)
291 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0 (0x1804)
292 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1 (0x1808)
293 #define RTL838X_SCHED_CTRL (0xB980)
294 #define RTL839X_SCHED_CTRL (0x60F4)
295 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58)
296 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C)
297 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804)
298 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808)
299 #define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000)
300 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0 (0x1604)
301 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1 (0x1608)
302 #define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60F8)
303 #define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL (0x6200)
304 #define RTL838X_SCHED_LB_THR (0xB984)
305 #define RTL839X_SCHED_LB_THR (0x60FC)
306 #define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7)))
307 #define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q) (0xC00C + (p << 7) + (((q) << 2)))
308 #define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
309 #define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
310 #define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
311 #define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2)))
312 #define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2)))
313 #define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2)))
314 #define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2)))
315 #define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2)))
316 #define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2)))
317 #define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3)))
318 #define RTL839X_STORM_CTRL_PORT_UC_1(p) (0x1860 + (((p) << 3)))
319 #define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3)))
320 #define RTL839X_STORM_CTRL_PORT_MC_1(p) (0x1a00 + (((p) << 3)))
321 #define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3)))
322 #define RTL839X_STORM_CTRL_PORT_BC_1(p) (0x1BA0 + (((p) << 3)))
323 #define RTL839X_TBL_ACCESS_CTRL_2 (0x611C)
324 #define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2)))
325 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p) (0x1618 + (((p) << 3)))
326 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p) (0x161C + (((p) << 3)))
327 #define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p) (0x1640 + (((p) << 3)))
328 #define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p) (0x1644 + (((p) << 3)))
329 #define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614)
330
331 /* Link aggregation (Trunking) */
332 #define TRUNK_DISTRIBUTION_ALGO_SPA_BIT 0x01
333 #define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT 0x02
334 #define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT 0x04
335 #define TRUNK_DISTRIBUTION_ALGO_SIP_BIT 0x08
336 #define TRUNK_DISTRIBUTION_ALGO_DIP_BIT 0x10
337 #define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT 0x20
338 #define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT 0x40
339 #define TRUNK_DISTRIBUTION_ALGO_MASKALL 0x7F
340
341 #define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01
342 #define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02
343 #define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04
344 #define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08
345 #define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF
346
347 #define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01
348 #define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02
349 #define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04
350 #define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08
351 #define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10
352 #define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20
353 #define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT 0x40
354 #define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT 0x80
355 #define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100
356 #define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT 0x200
357 #define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF
358
359 #define RTL838X_TRK_MBR_CTR (0x3E00)
360 #define RTL838X_TRK_HASH_IDX_CTRL (0x3E20)
361 #define RTL838X_TRK_HASH_CTRL (0x3E24)
362
363 #define RTL839X_TRK_MBR_CTR (0x2200)
364 #define RTL839X_TRK_HASH_IDX_CTRL (0x2280)
365 #define RTL839X_TRK_HASH_CTRL (0x2284)
366
367 #define RTL930X_TRK_MBR_CTRL (0xA41C)
368 #define RTL930X_TRK_HASH_CTRL (0x9F80)
369
370 #define RTL931X_TRK_MBR_CTRL (0xB8D0)
371 #define RTL931X_TRK_HASH_CTRL (0xBA70)
372
373 /* Attack prevention */
374 #define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
375 #define RTL838X_ATK_PRVNT_CTRL (0x5B04)
376 #define RTL838X_ATK_PRVNT_ACT (0x5B08)
377 #define RTL838X_ATK_PRVNT_STS (0x5B1C)
378
379 /* 802.1X */
380 #define RTL838X_RMA_BPDU_FLD_PMSK (0x4348)
381 #define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18)
382 #define RTL931X_RMA_BPDU_FLD_PMSK (0x8950)
383 #define RTL839X_RMA_BPDU_FLD_PMSK (0x125C)
384
385 #define RTL838X_SPCL_TRAP_CTRL (0x6980)
386 #define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988)
387 #define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C)
388 #define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
389 #define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994)
390 #define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998)
391
392 #define RTL839X_SPCL_TRAP_CTRL (0x1054)
393 #define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C)
394 #define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060)
395 #define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
396 #define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064)
397 #define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068)
398 #define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C)
399 #define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070)
400 /* special port action controls */
401 /*
402 values:
403 0 = FORWARD (default)
404 1 = DROP
405 2 = TRAP2CPU
406 3 = FLOOD IN ALL PORT
407
408 Register encoding.
409 offset = CTRL + (port >> 4) << 2
410 value/mask = 3 << ((port&0xF) << 1)
411 */
412
413 typedef enum {
414 BPDU = 0,
415 PTP,
416 PTP_UDP,
417 PTP_ETH2,
418 LLTP,
419 EAPOL,
420 GRATARP,
421 } rma_ctrl_t;
422
423 typedef enum {
424 FORWARD = 0,
425 DROP,
426 TRAP2CPU,
427 FLOODALL,
428 TRAP2MASTERCPU,
429 COPY2CPU,
430 } action_type_t;
431
432 #define RTL838X_RMA_BPDU_CTRL (0x4330)
433 #define RTL839X_RMA_BPDU_CTRL (0x122C)
434 #define RTL930X_RMA_BPDU_CTRL (0x9E7C)
435 #define RTL931X_RMA_BPDU_CTRL (0x881C)
436
437 #define RTL838X_RMA_PTP_CTRL (0x4338)
438 #define RTL839X_RMA_PTP_CTRL (0x123C)
439 #define RTL930X_RMA_PTP_CTRL (0x9E88)
440 #define RTL931X_RMA_PTP_CTRL (0x8834)
441
442 #define RTL838X_RMA_LLTP_CTRL (0x4340)
443 #define RTL839X_RMA_LLTP_CTRL (0x124C)
444 #define RTL930X_RMA_LLTP_CTRL (0x9EFC)
445 #define RTL931X_RMA_LLTP_CTRL (0x8918)
446
447 #define RTL930X_RMA_EAPOL_CTRL (0x9F08)
448 #define RTL931X_RMA_EAPOL_CTRL (0x8930)
449 #define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04)
450
451 /* QoS */
452 #define RTL838X_QM_INTPRI2QID_CTRL (0x5F00)
453 #define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2))
454 #define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2)))
455 #define RTL838X_PRI_SEL_PORT_PRI(p) (0x5FB8 + (((p / 10) << 2)))
456 #define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2)))
457 #define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10)
458 #define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
459 #define RTL838X_PRI_SEL_CTRL (0x10E0)
460 #define RTL839X_PRI_SEL_CTRL (0x10E0)
461 #define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2)))
462 #define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2)))
463 #define RTL838X_QM_PKT2CPU_INTPRI_0 (0x5F04)
464 #define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08)
465 #define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C)
466 #define RTL839X_OAM_CTRL (0x2100)
467 #define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2)))
468 #define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2)))
469 #define RTL839X_PRI_SEL_IPRI_REMAP (0x1080)
470 #define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C)
471 #define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC)
472 #define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2)))
473 #define RTL839X_RMK_DEI_CTRL (0x6AA4)
474 #define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2))
475 #define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2))
476 #define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8)
477 #define RTL838X_RMK_IPRI_CTRL (0xA460)
478 #define RTL838X_RMK_OPRI_CTRL (0xA464)
479 #define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7)))
480 #define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7)))
481 #define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2)))
482
483 /* Debug features */
484 #define RTL930X_STAT_PRVTE_DROP_COUNTER0 (0xB5B8)
485
486 /* Packet Inspection Engine */
487 #define RTL838X_METER_GLB_CTRL (0x4B08)
488 #define RTL839X_METER_GLB_CTRL (0x1300)
489 #define RTL930X_METER_GLB_CTRL (0xa0a0)
490 #define RTL931X_METER_GLB_CTRL (0x411C)
491
492 #define RTL839X_ACL_CTRL (0x1288)
493
494 #define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100)
495 #define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280)
496 #define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0)
497 #define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180)
498
499 #define RTL838X_ACL_BLK_PWR_CTRL (0x6104)
500 #define RTL839X_PS_ACL_PWR_CTRL (0x049c)
501
502 #define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2))
503 #define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2))
504 #define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2))
505 #define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2))
506
507 #define RTL838X_ACL_BLK_GROUP_CTRL (0x615C)
508 #define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec)
509
510 #define RTL838X_ACL_CLR_CTRL (0x6168)
511 #define RTL839X_ACL_CLR_CTRL (0x12fc)
512 #define RTL930X_PIE_CLR_CTRL (0xa66c)
513 #define RTL931X_PIE_CLR_CTRL (0x42D8)
514
515 #define RTL838X_DMY_REG27 (0x3378)
516
517 #define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2)))
518 #define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2)))
519 #define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2)))
520
521 #define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4)
522 #define RTL931X_PIE_BLK_PHASE_CTRL (0x4184)
523
524 // PIE actions
525 #define PIE_ACT_COPY_TO_PORT 2
526 #define PIE_ACT_REDIRECT_TO_PORT 4
527 #define PIE_ACT_ROUTE_UC 6
528 #define PIE_ACT_VID_ASSIGN 0
529
530 // L3 actions
531 #define L3_FORWARD 0
532 #define L3_DROP 1
533 #define L3_TRAP2CPU 2
534 #define L3_COPY2CPU 3
535 #define L3_TRAP2MASTERCPU 4
536 #define L3_COPY2MASTERCPU 5
537 #define L3_HARDDROP 6
538
539 // Route actions
540 #define ROUTE_ACT_FORWARD 0
541 #define ROUTE_ACT_TRAP2CPU 1
542 #define ROUTE_ACT_COPY2CPU 2
543 #define ROUTE_ACT_DROP 3
544
545 /* L3 Routing */
546 #define RTL839X_ROUTING_SA_CTRL 0x6afc
547 #define RTL930X_L3_HOST_TBL_CTRL (0xAB48)
548 #define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C)
549 #define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50)
550 #define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54)
551 #define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58)
552 #define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2))
553 #define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2))
554 #define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C)
555 #define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0)
556 #define RTL930X_L3_HW_LU_CTRL (0xACC0)
557 #define RTL930X_L3_IP_ROUTE_CTRL 0xab44
558
559 /* Port LED Control */
560 #define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2)))
561 #define RTL930X_LED_SET0_0_CTRL (0xCC28)
562 #define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2)))
563 #define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2)))
564 #define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C)
565 #define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40)
566 #define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44)
567
568 #define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2)))
569 #define RTL931X_LED_SET0_0_CTRL (0x0630)
570 #define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2)))
571 #define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2)))
572 #define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654)
573 #define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c)
574 #define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664)
575
576 #define MAX_VLANS 4096
577 #define MAX_LAGS 16
578 #define MAX_PRIOS 8
579 #define RTL930X_PORT_IGNORE 0x3f
580 #define MAX_MC_GROUPS 512
581 #define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1)
582 #define PIE_BLOCK_SIZE 128
583 #define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE)
584 #define N_FIXED_FIELDS 12
585 #define N_FIXED_FIELDS_RTL931X 14
586 #define MAX_COUNTERS 2048
587 #define MAX_ROUTES 512
588 #define MAX_HOST_ROUTES 1536
589 #define MAX_INTF_MTUS 8
590 #define DEFAULT_MTU 1536
591 #define MAX_INTERFACES 100
592 #define MAX_ROUTER_MACS 64
593 #define L3_EGRESS_DMACS 2048
594 #define MAX_SMACS 64
595
596 enum phy_type {
597 PHY_NONE = 0,
598 PHY_RTL838X_SDS = 1,
599 PHY_RTL8218B_INT = 2,
600 PHY_RTL8218B_EXT = 3,
601 PHY_RTL8214FC = 4,
602 PHY_RTL839X_SDS = 5,
603 PHY_RTL930X_SDS = 6,
604 };
605
606 enum pbvlan_type {
607 PBVLAN_TYPE_INNER = 0,
608 PBVLAN_TYPE_OUTER,
609 };
610
611 enum pbvlan_mode {
612 PBVLAN_MODE_UNTAG_AND_PRITAG = 0,
613 PBVLAN_MODE_UNTAG_ONLY,
614 PBVLAN_MODE_ALL_PKT,
615 };
616
617 struct rtl838x_port {
618 bool enable;
619 u64 pm;
620 u16 pvid;
621 bool eee_enabled;
622 enum phy_type phy;
623 bool phy_is_integrated;
624 bool is10G;
625 bool is2G5;
626 int sds_num;
627 int led_set;
628 const struct dsa_port *dp;
629 };
630
631 struct rtl838x_vlan_info {
632 u64 untagged_ports;
633 u64 tagged_ports;
634 u8 profile_id;
635 bool hash_mc_fid;
636 bool hash_uc_fid;
637 u8 fid; // AKA MSTI
638
639 // The following fields are used only by the RTL931X
640 int if_id; // Interface (index in L3_EGR_INTF_IDX)
641 u16 multicast_grp_mask;
642 int l2_tunnel_list_id;
643 };
644
645 enum l2_entry_type {
646 L2_INVALID = 0,
647 L2_UNICAST = 1,
648 L2_MULTICAST = 2,
649 IP4_MULTICAST = 3,
650 IP6_MULTICAST = 4,
651 };
652
653 struct rtl838x_l2_entry {
654 u8 mac[6];
655 u16 vid;
656 u16 rvid;
657 u8 port;
658 bool valid;
659 enum l2_entry_type type;
660 bool is_static;
661 bool is_ip_mc;
662 bool is_ipv6_mc;
663 bool block_da;
664 bool block_sa;
665 bool suspended;
666 bool next_hop;
667 int age;
668 u8 trunk;
669 bool is_trunk;
670 u8 stack_dev;
671 u16 mc_portmask_index;
672 u32 mc_gip;
673 u32 mc_sip;
674 u16 mc_mac_index;
675 u16 nh_route_id;
676 bool nh_vlan_target; // Only RTL83xx: VLAN used for next hop
677
678 // The following is only valid on RTL931x
679 bool is_open_flow;
680 bool is_pe_forward;
681 bool is_local_forward;
682 bool is_remote_forward;
683 bool is_l2_tunnel;
684 int l2_tunnel_id;
685 int l2_tunnel_list_id;
686 };
687
688 enum fwd_rule_action {
689 FWD_RULE_ACTION_NONE = 0,
690 FWD_RULE_ACTION_FWD = 1,
691 };
692
693 enum pie_phase {
694 PHASE_VACL = 0,
695 PHASE_IACL = 1,
696 };
697
698 enum igr_filter {
699 IGR_FORWARD = 0,
700 IGR_DROP = 1,
701 IGR_TRAP = 2,
702 };
703
704 enum egr_filter {
705 EGR_DISABLE = 0,
706 EGR_ENABLE = 1,
707 };
708
709 /* Intermediate representation of a Packet Inspection Engine Rule
710 * as suggested by the Kernel's tc flower offload subsystem
711 * Field meaning is universal across SoC families, but data content is specific
712 * to SoC family (e.g. because of different port ranges) */
713 struct pie_rule {
714 int id;
715 enum pie_phase phase; // Phase in which this template is applied
716 int packet_cntr; // ID of a packet counter assigned to this rule
717 int octet_cntr; // ID of a byte counter assigned to this rule
718 u32 last_packet_cnt;
719 u64 last_octet_cnt;
720
721 // The following are requirements for the pie template
722 bool is_egress;
723 bool is_ipv6; // This is a rule with IPv6 fields
724
725 // Fixed fields that are always matched against on RTL8380
726 u8 spmmask_fix;
727 u8 spn; // Source port number
728 bool stacking_port; // Source port is stacking port
729 bool mgnt_vlan; // Packet arrived on management VLAN
730 bool dmac_hit_sw; // The packet's destination MAC matches one of the device's
731 bool content_too_deep; // The content of the packet cannot be parsed: too many layers
732 bool not_first_frag; // Not the first IP fragment
733 u8 frame_type_l4; // 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP
734 u8 frame_type; // 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6
735 bool otag_fmt; // 0: outer tag packet, 1: outer priority tag or untagged
736 bool itag_fmt; // 0: inner tag packet, 1: inner priority tag or untagged
737 bool otag_exist; // packet with outer tag
738 bool itag_exist; // packet with inner tag
739 bool frame_type_l2; // 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved
740 bool igr_normal_port; // Ingress port is not cpu or stacking port
741 u8 tid; // The template ID defining the what the templated fields mean
742
743 // Masks for the fields that are always matched against on RTL8380
744 u8 spmmask_fix_m;
745 u8 spn_m;
746 bool stacking_port_m;
747 bool mgnt_vlan_m;
748 bool dmac_hit_sw_m;
749 bool content_too_deep_m;
750 bool not_first_frag_m;
751 u8 frame_type_l4_m;
752 u8 frame_type_m;
753 bool otag_fmt_m;
754 bool itag_fmt_m;
755 bool otag_exist_m;
756 bool itag_exist_m;
757 bool frame_type_l2_m;
758 bool igr_normal_port_m;
759 u8 tid_m;
760
761 // Logical operations between rules, special rules for rule numbers apply
762 bool valid;
763 bool cond_not; // Matches when conditions not match
764 bool cond_and1; // And this rule 2n with the next rule 2n+1 in same block
765 bool cond_and2; // And this rule m in block 2n with rule m in block 2n+1
766 bool ivalid;
767
768 // Actions to be performed
769 bool drop; // Drop the packet
770 bool fwd_sel; // Forward packet: to port, portmask, dest route, next rule, drop
771 bool ovid_sel; // So something to outer vlan-id: shift, re-assign
772 bool ivid_sel; // Do something to inner vlan-id: shift, re-assign
773 bool flt_sel; // Filter the packet when sending to certain ports
774 bool log_sel; // Log the packet in one of the LOG-table counters
775 bool rmk_sel; // Re-mark the packet, i.e. change the priority-tag
776 bool meter_sel; // Meter the packet, i.e. limit rate of this type of packet
777 bool tagst_sel; // Change the ergress tag
778 bool mir_sel; // Mirror the packet to a Link Aggregation Group
779 bool nopri_sel; // Change the normal priority
780 bool cpupri_sel; // Change the CPU priority
781 bool otpid_sel; // Change Outer Tag Protocol Identifier (802.1q)
782 bool itpid_sel; // Change Inner Tag Protocol Identifier (802.1q)
783 bool shaper_sel; // Apply traffic shaper
784 bool mpls_sel; // MPLS actions
785 bool bypass_sel; // Bypass actions
786 bool fwd_sa_lrn; // Learn the source address when forwarding
787 bool fwd_mod_to_cpu; // Forward the modified VLAN tag format to CPU-port
788
789 // Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300
790 u64 spm; // Source Port Matrix
791 u16 otag; // Outer VLAN-ID
792 u8 smac[ETH_ALEN]; // Source MAC address
793 u8 dmac[ETH_ALEN]; // Destination MAC address
794 u16 ethertype; // Ethernet frame type field in ethernet header
795 u16 itag; // Inner VLAN-ID
796 u16 field_range_check;
797 u32 sip; // Source IP
798 struct in6_addr sip6; // IPv6 Source IP
799 u32 dip; // Destination IP
800 struct in6_addr dip6; // IPv6 Destination IP
801 u16 tos_proto; // IPv4: TOS + Protocol fields, IPv6: Traffic class + next header
802 u16 sport; // TCP/UDP source port
803 u16 dport; // TCP/UDP destination port
804 u16 icmp_igmp;
805 u16 tcp_info;
806 u16 dsap_ssap; // Destination / Source Service Access Point bytes (802.3)
807
808 u64 spm_m;
809 u16 otag_m;
810 u8 smac_m[ETH_ALEN];
811 u8 dmac_m[ETH_ALEN];
812 u8 ethertype_m;
813 u16 itag_m;
814 u16 field_range_check_m;
815 u32 sip_m;
816 struct in6_addr sip6_m; // IPv6 Source IP mask
817 u32 dip_m;
818 struct in6_addr dip6_m; // IPv6 Destination IP mask
819 u16 tos_proto_m;
820 u16 sport_m;
821 u16 dport_m;
822 u16 icmp_igmp_m;
823 u16 tcp_info_m;
824 u16 dsap_ssap_m;
825
826 // Data associated with actions
827 u8 fwd_act; // Type of forwarding action
828 // 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask
829 // 4: redirect to portid, 5: redirect to portmask
830 // 6: route, 7: vlan leaky (only 8380)
831 u16 fwd_data; // Additional data for forwarding action, e.g. destination port
832 u8 ovid_act;
833 u16 ovid_data; // Outer VLAN ID
834 u8 ivid_act;
835 u16 ivid_data; // Inner VLAN ID
836 u16 flt_data; // Filtering data
837 u16 log_data; // ID of packet or octet counter in LOG table, on RTL93xx
838 // unnecessary since PIE-Rule-ID == LOG-counter-ID
839 bool log_octets;
840 u8 mpls_act; // MPLS action type
841 u16 mpls_lib_idx; // MPLS action data
842
843 u16 rmk_data; // Data for remarking
844 u16 meter_data; // ID of meter for bandwidth control
845 u16 tagst_data;
846 u16 mir_data;
847 u16 nopri_data;
848 u16 cpupri_data;
849 u16 otpid_data;
850 u16 itpid_data;
851 u16 shaper_data;
852
853 // Bypass actions, ignored on RTL8380
854 bool bypass_all; // Not clear
855 bool bypass_igr_stp; // Bypass Ingress STP state
856 bool bypass_ibc_sc; // Bypass Ingress Bandwidth Control and Storm Control
857 };
858
859 struct rtl838x_l3_intf {
860 u16 vid;
861 u8 smac_idx;
862 u8 ip4_mtu_id;
863 u8 ip6_mtu_id;
864 u16 ip4_mtu;
865 u16 ip6_mtu;
866 u8 ttl_scope;
867 u8 hl_scope;
868 u8 ip4_icmp_redirect;
869 u8 ip6_icmp_redirect;
870 u8 ip4_pbr_icmp_redirect;
871 u8 ip6_pbr_icmp_redirect;
872 };
873
874 /*
875 * An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point
876 * for the L3 routing system. Packets arriving and matching an entry in this table
877 * will be considered for routing.
878 * Mask fields state whether the corresponding data fields matter for matching
879 */
880 struct rtl93xx_rt_mac {
881 bool valid; // Valid or not
882 bool p_type; // Individual (0) or trunk (1) port
883 bool p_mask; // Whether the port type is used
884 u8 p_id;
885 u8 p_id_mask; // Mask for the port
886 u8 action; // Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU
887 // 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP
888 u16 vid;
889 u16 vid_mask;
890 u64 mac; // MAC address used as source MAC in the routed packet
891 u64 mac_mask;
892 };
893
894 struct rtl83xx_nexthop {
895 u16 id; // ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP
896 u32 dev_id;
897 u16 port;
898 u16 vid; // VLAN-ID for L2 table entry (saved from L2-UC entry)
899 u16 rvid; // Relay VID/FID for the L2 table entry
900 u64 mac; // The MAC address of the entry in the L2_NEXT_HOP table
901 u16 mac_id;
902 u16 l2_id; // Index of this next hop forwarding entry in L2 FIB table
903 u64 gw; // The gateway MAC address packets are forwarded to
904 int if_id; // Interface (into L3_EGR_INTF_IDX)
905 };
906
907 struct rtl838x_switch_priv;
908
909 struct rtl83xx_flow {
910 unsigned long cookie;
911 struct rhash_head node;
912 struct rcu_head rcu_head;
913 struct rtl838x_switch_priv *priv;
914 struct pie_rule rule;
915 u32 flags;
916 };
917
918 struct rtl93xx_route_attr {
919 bool valid;
920 bool hit;
921 bool ttl_dec;
922 bool ttl_check;
923 bool dst_null;
924 bool qos_as;
925 u8 qos_prio;
926 u8 type;
927 u8 action;
928 };
929
930 struct rtl83xx_route {
931 u32 gw_ip; // IP of the route's gateway
932 u32 dst_ip; // IP of the destination net
933 struct in6_addr dst_ip6;
934 int prefix_len; // Network prefix len of the destination net
935 bool is_host_route;
936 int id; // ID number of this route
937 struct rhlist_head linkage;
938 u16 switch_mac_id; // Index into switch's own MACs, RTL839X only
939 struct rtl83xx_nexthop nh;
940 struct pie_rule pr;
941 struct rtl93xx_route_attr attr;
942 };
943
944 struct rtl838x_reg {
945 void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
946 void (*set_port_reg_be)(u64 set, int reg);
947 u64 (*get_port_reg_be)(int reg);
948 void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
949 void (*set_port_reg_le)(u64 set, int reg);
950 u64 (*get_port_reg_le)(int reg);
951 int stat_port_rst;
952 int stat_rst;
953 int stat_port_std_mib;
954 int (*port_iso_ctrl)(int p);
955 void (*traffic_enable)(int source, int dest);
956 void (*traffic_disable)(int source, int dest);
957 void (*traffic_set)(int source, u64 dest_matrix);
958 u64 (*traffic_get)(int source);
959 int l2_ctrl_0;
960 int l2_ctrl_1;
961 int smi_poll_ctrl;
962 u32 l2_port_aging_out;
963 int l2_tbl_flush_ctrl;
964 void (*exec_tbl0_cmd)(u32 cmd);
965 void (*exec_tbl1_cmd)(u32 cmd);
966 int (*tbl_access_data_0)(int i);
967 int isr_glb_src;
968 int isr_port_link_sts_chg;
969 int imr_port_link_sts_chg;
970 int imr_glb;
971 void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
972 void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
973 void (*vlan_set_untagged)(u32 vlan, u64 portmask);
974 void (*vlan_profile_dump)(int index);
975 void (*vlan_profile_setup)(int profile);
976 void (*vlan_port_pvidmode_set)(int port, enum pbvlan_type type, enum pbvlan_mode mode);
977 void (*vlan_port_pvid_set)(int port, enum pbvlan_type type, int pvid);
978 void (*vlan_port_keep_tag_set)(int port, bool keep_outer, bool keep_inner);
979 void (*set_vlan_igr_filter)(int port, enum igr_filter state);
980 void (*set_vlan_egr_filter)(int port, enum egr_filter state);
981 void (*enable_learning)(int port, bool enable);
982 void (*enable_flood)(int port, bool enable);
983 void (*enable_mcast_flood)(int port, bool enable);
984 void (*enable_bcast_flood)(int port, bool enable);
985 void (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);
986 void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);
987 int (*mac_force_mode_ctrl)(int port);
988 int (*mac_port_ctrl)(int port);
989 int (*l2_port_new_salrn)(int port);
990 int (*l2_port_new_sa_fwd)(int port);
991 int (*set_ageing_time)(unsigned long msec);
992 int mir_ctrl;
993 int mir_dpm;
994 int mir_spm;
995 int mac_link_sts;
996 int mac_link_dup_sts;
997 int (*mac_link_spd_sts)(int port);
998 int mac_rx_pause_sts;
999 int mac_tx_pause_sts;
1000 u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
1001 void (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e);
1002 u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
1003 void (*write_cam)(int idx, struct rtl838x_l2_entry *e);
1004 int (*trk_mbr_ctr)(int group);
1005 int rma_bpdu_fld_pmask;
1006 int spcl_trap_eapol_ctrl;
1007 void (*init_eee)(struct rtl838x_switch_priv *priv, bool enable);
1008 void (*port_eee_set)(struct rtl838x_switch_priv *priv, int port, bool enable);
1009 int (*eee_port_ability)(struct rtl838x_switch_priv *priv,
1010 struct ethtool_eee *e, int port);
1011 u64 (*l2_hash_seed)(u64 mac, u32 vid);
1012 u32 (*l2_hash_key)(struct rtl838x_switch_priv *priv, u64 seed);
1013 u64 (*read_mcast_pmask)(int idx);
1014 void (*write_mcast_pmask)(int idx, u64 portmask);
1015 void (*vlan_fwd_on_inner)(int port, bool is_set);
1016 void (*pie_init)(struct rtl838x_switch_priv *priv);
1017 int (*pie_rule_read)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr);
1018 int (*pie_rule_write)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr);
1019 int (*pie_rule_add)(struct rtl838x_switch_priv *priv, struct pie_rule *rule);
1020 void (*pie_rule_rm)(struct rtl838x_switch_priv *priv, struct pie_rule *rule);
1021 void (*l2_learning_setup)(void);
1022 u32 (*packet_cntr_read)(int counter);
1023 void (*packet_cntr_clear)(int counter);
1024 void (*route_read)(int idx, struct rtl83xx_route *rt);
1025 void (*route_write)(int idx, struct rtl83xx_route *rt);
1026 void (*host_route_write)(int idx, struct rtl83xx_route *rt);
1027 int (*l3_setup)(struct rtl838x_switch_priv *priv);
1028 void (*set_l3_nexthop)(int idx, u16 dmac_id, u16 interface);
1029 void (*get_l3_nexthop)(int idx, u16 *dmac_id, u16 *interface);
1030 u64 (*get_l3_egress_mac)(u32 idx);
1031 void (*set_l3_egress_mac)(u32 idx, u64 mac);
1032 int (*find_l3_slot)(struct rtl83xx_route *rt, bool must_exist);
1033 int (*route_lookup_hw)(struct rtl83xx_route *rt);
1034 void (*get_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m);
1035 void (*set_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m);
1036 void (*set_l3_egress_intf)(int idx, struct rtl838x_l3_intf *intf);
1037 void (*set_distribution_algorithm)(int group, int algoidx, u32 algomask);
1038 void (*set_receive_management_action)(int port, rma_ctrl_t type, action_type_t action);
1039 void (*led_init)(struct rtl838x_switch_priv *priv);
1040 };
1041
1042 struct rtl838x_switch_priv {
1043 /* Switch operation */
1044 struct dsa_switch *ds;
1045 struct device *dev;
1046 u16 id;
1047 u16 family_id;
1048 char version;
1049 struct rtl838x_port ports[57];
1050 struct mutex reg_mutex; // Mutex for individual register manipulations
1051 struct mutex pie_mutex; // Mutex for Packet Inspection Engine
1052 int link_state_irq;
1053 int mirror_group_ports[4];
1054 struct mii_bus *mii_bus;
1055 const struct rtl838x_reg *r;
1056 u8 cpu_port;
1057 u8 port_mask;
1058 u8 port_width;
1059 u8 port_ignore;
1060 u64 irq_mask;
1061 u32 fib_entries;
1062 int l2_bucket_size;
1063 struct dentry *dbgfs_dir;
1064 int n_lags;
1065 u64 lags_port_members[MAX_LAGS];
1066 struct net_device *lag_devs[MAX_LAGS];
1067 u32 lag_primary[MAX_LAGS];
1068 u32 is_lagmember[57];
1069 u64 lagmembers;
1070 struct notifier_block nb; // TODO: change to different name
1071 struct notifier_block ne_nb;
1072 struct notifier_block fib_nb;
1073 bool eee_enabled;
1074 unsigned long int mc_group_bm[MAX_MC_GROUPS >> 5];
1075 int mc_group_saves[MAX_MC_GROUPS];
1076 int n_pie_blocks;
1077 struct rhashtable tc_ht;
1078 unsigned long int pie_use_bm[MAX_PIE_ENTRIES >> 5];
1079 int n_counters;
1080 unsigned long int octet_cntr_use_bm[MAX_COUNTERS >> 5];
1081 unsigned long int packet_cntr_use_bm[MAX_COUNTERS >> 4];
1082 struct rhltable routes;
1083 unsigned long int route_use_bm[MAX_ROUTES >> 5];
1084 unsigned long int host_route_use_bm[MAX_HOST_ROUTES >> 5];
1085 struct rtl838x_l3_intf *interfaces[MAX_INTERFACES];
1086 u16 intf_mtus[MAX_INTF_MTUS];
1087 int intf_mtu_count[MAX_INTF_MTUS];
1088 };
1089
1090 void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
1091 void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv);
1092
1093 #endif /* _RTL838X_H */