1 /* SPDX-License-Identifier: GPL-2.0-only */
8 /* Register definition */
9 #define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
10 #define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
11 #define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6)))
12 #define RTL931X_MAC_PORT_CTRL (0x6004)
14 #define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6)))
15 #define RTL931X_MAC_L2_PORT_CTRL (0x6000)
17 #define RTL838X_RST_GLB_CTRL_0 (0x003c)
19 #define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
20 #define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
21 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
22 #define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC)
24 #define RTL838X_DMY_REG31 (0x3b28)
25 #define RTL838X_SDS_MODE_SEL (0x0028)
26 #define RTL838X_SDS_CFG_REG (0x0034)
27 #define RTL838X_INT_MODE_CTRL (0x005c)
28 #define RTL838X_CHIP_INFO (0x00d8)
29 #define RTL839X_CHIP_INFO (0x0ff4)
30 #define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
31 #define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
33 /* Packet statistics */
34 #define RTL838X_STAT_PORT_STD_MIB (0x1200)
35 #define RTL839X_STAT_PORT_STD_MIB (0xC000)
36 #define RTL930X_STAT_PORT_MIB_CNTR (0x0664)
37 #define RTL838X_STAT_RST (0x3100)
38 #define RTL839X_STAT_RST (0xF504)
39 #define RTL930X_STAT_RST (0x3240)
40 #define RTL931X_STAT_RST (0x7ef4)
41 #define RTL838X_STAT_PORT_RST (0x3104)
42 #define RTL839X_STAT_PORT_RST (0xF508)
43 #define RTL930X_STAT_PORT_RST (0x3244)
44 #define RTL931X_STAT_PORT_RST (0x7ef8)
45 #define RTL838X_STAT_CTRL (0x3108)
46 #define RTL839X_STAT_CTRL (0x04cc)
47 #define RTL930X_STAT_CTRL (0x3248)
48 #define RTL931X_STAT_CTRL (0x5720)
50 /* Registers of the internal Serdes of the 8390 */
51 #define RTL8390_SDS0_1_XSG0 (0xA000)
52 #define RTL8390_SDS0_1_XSG1 (0xA100)
53 #define RTL839X_SDS12_13_XSG0 (0xB800)
54 #define RTL839X_SDS12_13_XSG1 (0xB900)
55 #define RTL839X_SDS12_13_PWR0 (0xb880)
56 #define RTL839X_SDS12_13_PWR1 (0xb980)
58 /* Registers of the internal Serdes of the 8380 */
59 #define RTL838X_SDS4_FIB_REG0 (0xF800)
60 #define RTL838X_SDS4_REG28 (0xef80)
61 #define RTL838X_SDS4_DUMMY0 (0xef8c)
62 #define RTL838X_SDS5_EXT_REG6 (0xf18c)
65 #define RTL838X_VLAN_CTRL (0x3A74)
66 #define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
67 #define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
68 #define RTL838X_VLAN_PORT_PB_VLAN (0x3C00)
69 #define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C)
71 #define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3)))
72 #define RTL839X_VLAN_CTRL (0x26D4)
73 #define RTL839X_VLAN_PORT_PB_VLAN (0x26D8)
74 #define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4)
75 #define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4)
77 #define RTL930X_VLAN_PROFILE_SET(idx) (0x9c60 + (((idx) * 20)))
78 #define RTL930X_VLAN_CTRL (0x82D4)
79 #define RTL930X_VLAN_PORT_PB_VLAN (0x82D8)
80 #define RTL930X_VLAN_PORT_IGR_FLTR (0x83C0)
81 #define RTL930X_VLAN_PORT_EGR_FLTR (0x83C8)
83 #define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28)))
84 #define RTL931X_VLAN_CTRL (0x94E4)
85 #define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8)
86 #define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4)
87 #define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4)
89 /* Table access registers */
90 #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
91 #define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
92 #define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
93 #define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
95 #define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
96 #define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2))
97 #define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
98 #define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
99 #define RTL839X_TBL_ACCESS_CTRL_2 (0x611C)
100 #define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2)))
102 #define RTL930X_TBL_ACCESS_CTRL_0 (0xB340)
103 #define RTL930X_TBL_ACCESS_DATA_0(idx) (0xB344 + ((idx) << 2))
104 #define RTL930X_TBL_ACCESS_CTRL_1 (0xB3A0)
105 #define RTL930X_TBL_ACCESS_DATA_1(idx) (0xB3A4 + ((idx) << 2))
106 #define RTL930X_TBL_ACCESS_CTRL_2 (0xCE04)
107 #define RTL930X_TBL_ACCESS_DATA_2(i) (0xCE08 + (((i) << 2)))
109 #define RTL931X_TBL_ACCESS_CTRL_0 (0x8500)
110 #define RTL931X_TBL_ACCESS_DATA_0(idx) (0x8508 + ((idx) << 2))
111 #define RTL931X_TBL_ACCESS_CTRL_1 (0x40C0)
112 #define RTL931X_TBL_ACCESS_DATA_1(idx) (0x40C4 + ((idx) << 2))
113 #define RTL931X_TBL_ACCESS_CTRL_2 (0x8528)
114 #define RTL931X_TBL_ACCESS_DATA_2(i) (0x852C + (((i) << 2)))
115 #define RTL931X_TBL_ACCESS_CTRL_3 (0x0200)
116 #define RTL931X_TBL_ACCESS_DATA_3(i) (0x0204 + (((i) << 2)))
117 #define RTL931X_TBL_ACCESS_CTRL_4 (0x20DC)
118 #define RTL931X_TBL_ACCESS_DATA_4(i) (0x20E0 + (((i) << 2)))
119 #define RTL931X_TBL_ACCESS_CTRL_5 (0x7E1C)
120 #define RTL931X_TBL_ACCESS_DATA_5(i) (0x7E20 + (((i) << 2)))
123 #define RTL838X_MAC_LINK_STS (0xa188)
124 #define RTL839X_MAC_LINK_STS (0x0390)
125 #define RTL930X_MAC_LINK_STS (0xCB10)
126 #define RTL931X_MAC_LINK_STS (0x0EC0)
127 #define RTL838X_MAC_LINK_SPD_STS(p) (0xa190 + (((p >> 4) << 2)))
128 #define RTL839X_MAC_LINK_SPD_STS(p) (0x03a0 + (((p >> 4) << 2)))
129 #define RTL930X_MAC_LINK_SPD_STS(p) (0xCB18 + (((p >> 3) << 2)))
130 #define RTL931X_MAC_LINK_SPD_STS (0x0ED0)
131 #define RTL838X_MAC_LINK_DUP_STS (0xa19c)
132 #define RTL839X_MAC_LINK_DUP_STS (0x03b0)
133 #define RTL930X_MAC_LINK_DUP_STS (0xCB28)
134 #define RTL931X_MAC_LINK_DUP_STS (0x0EF0)
135 #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
136 #define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
137 #define RTL930X_MAC_TX_PAUSE_STS (0xCB2C)
138 #define RTL931X_MAC_TX_PAUSE_STS (0x0EF8)
139 #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
140 #define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
141 #define RTL930X_MAC_RX_PAUSE_STS (0xCB30)
142 #define RTL931X_MAC_RX_PAUSE_STS (0x0F00)
143 #define RTL930X_MAC_LINK_MEDIA_STS (0xCB14)
144 #define RTL931X_MAC_LINK_MEDIA_STS (0x0EC8)
146 /* MAC link state bits */
147 #define RTL838X_FORCE_EN (1 << 0)
148 #define RTL838X_FORCE_LINK_EN (1 << 1)
149 #define RTL838X_NWAY_EN (1 << 2)
150 #define RTL838X_DUPLEX_MODE (1 << 3)
151 #define RTL838X_TX_PAUSE_EN (1 << 6)
152 #define RTL838X_RX_PAUSE_EN (1 << 7)
153 #define RTL838X_MAC_FORCE_FC_EN (1 << 8)
155 #define RTL839X_FORCE_EN (1 << 0)
156 #define RTL839X_FORCE_LINK_EN (1 << 1)
157 #define RTL839X_DUPLEX_MODE (1 << 2)
158 #define RTL839X_TX_PAUSE_EN (1 << 5)
159 #define RTL839X_RX_PAUSE_EN (1 << 6)
160 #define RTL839X_MAC_FORCE_FC_EN (1 << 7)
162 #define RTL930X_FORCE_EN (1 << 0)
163 #define RTL930X_FORCE_LINK_EN (1 << 1)
164 #define RTL930X_DUPLEX_MODE (1 << 2)
165 #define RTL930X_TX_PAUSE_EN (1 << 7)
166 #define RTL930X_RX_PAUSE_EN (1 << 8)
167 #define RTL930X_MAC_FORCE_FC_EN (1 << 9)
169 #define RTL931X_FORCE_EN (1 << 9)
170 #define RTL931X_FORCE_LINK_EN (1 << 0)
171 #define RTL931X_DUPLEX_MODE (1 << 2)
172 #define RTL931X_MAC_FORCE_FC_EN (1 << 4)
173 #define RTL931X_TX_PAUSE_EN (1 << 16)
174 #define RTL931X_RX_PAUSE_EN (1 << 17)
177 #define RTL838X_MAC_EEE_ABLTY (0xa1a8)
178 #define RTL838X_EEE_PORT_TX_EN (0x014c)
179 #define RTL838X_EEE_PORT_RX_EN (0x0150)
180 #define RTL838X_EEE_CLK_STOP_CTRL (0x0148)
181 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
182 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
184 #define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C)
185 #define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430)
186 #define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434)
187 #define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7))
188 #define RTL839X_MAC_EEE_ABLTY (0x03C8)
190 #define RTL930X_MAC_EEE_ABLTY (0xCB34)
191 #define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6))
192 #define RTL930X_EEEP_PORT_CTRL(p) (0x3278 + ((p) << 6))
194 /* L2 functionality */
195 #define RTL838X_L2_CTRL_0 (0x3200)
196 #define RTL839X_L2_CTRL_0 (0x3800)
197 #define RTL930X_L2_CTRL (0x8FD8)
198 #define RTL931X_L2_CTRL (0xC800)
199 #define RTL838X_L2_CTRL_1 (0x3204)
200 #define RTL839X_L2_CTRL_1 (0x3804)
201 #define RTL930X_L2_AGE_CTRL (0x8FDC)
202 #define RTL931X_L2_AGE_CTRL (0xC804)
203 #define RTL838X_L2_PORT_AGING_OUT (0x3358)
204 #define RTL839X_L2_PORT_AGING_OUT (0x3b74)
205 #define RTL930X_L2_PORT_AGE_CTRL (0x8FE0)
206 #define RTL931X_L2_PORT_AGE_CTRL (0xc808)
207 #define RTL838X_TBL_ACCESS_L2_CTRL (0x6900)
208 #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
209 #define RTL930X_TBL_ACCESS_L2_CTRL (0xB320)
210 #define RTL930X_TBL_ACCESS_L2_METHOD_CTRL (0xB324)
211 #define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
212 #define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
213 #define RTL930X_TBL_ACCESS_L2_DATA(idx) (0xab08 + ((idx) << 2))
215 #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
216 #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
217 #define RTL930X_L2_TBL_FLUSH_CTRL (0x9404)
218 #define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C)
220 #define RTL838X_L2_LRN_CONSTRT (0x329C)
221 #define RTL839X_L2_LRN_CONSTRT (0x3910)
222 #define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c)
223 #define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964)
225 #define RTL838X_L2_FLD_PMSK (0x3288)
226 #define RTL839X_L2_FLD_PMSK (0x38EC)
227 #define RTL930X_L2_BC_FLD_PMSK (0x9068)
228 #define RTL931X_L2_BC_FLD_PMSK (0xC8FC)
230 #define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064)
231 #define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4)
233 #define RTL838X_L2_LRN_CONSTRT_EN (0x3368)
234 #define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0)
235 #define RTL839X_L2_PORT_LRN_CONSTRT (0x3914)
237 #define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2)))
238 #define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
239 #define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2)))
240 #define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2)))
242 #define SALRN_PORT_SHIFT(p) ((p % 16) * 2)
243 #define SALRN_MODE_MASK 0x3
244 #define SALRN_MODE_HARDWARE 0
245 #define SALRN_MODE_DISABLED 2
247 #define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2)))
248 #define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2)))
249 #define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2)))
250 #define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2)))
252 #define RTL930X_ST_CTRL (0x8798)
254 #define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
255 #define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
257 #define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2))
258 #define RTL838X_VLAN_PORT_FWD (0x3A78)
259 #define RTL839X_VLAN_PORT_FWD (0x27AC)
260 #define RTL930X_VLAN_PORT_FWD (0x834C)
261 #define RTL931X_VLAN_PORT_FWD (0x95CC)
262 #define RTL838X_VLAN_FID_CTRL (0x3aa8)
265 #define RTL838X_MIR_CTRL (0x5D00)
266 #define RTL838X_MIR_DPM_CTRL (0x5D20)
267 #define RTL838X_MIR_SPM_CTRL (0x5D10)
269 #define RTL839X_MIR_CTRL (0x2500)
270 #define RTL839X_MIR_DPM_CTRL (0x2530)
271 #define RTL839X_MIR_SPM_CTRL (0x2510)
273 #define RTL930X_MIR_CTRL (0xA2A0)
274 #define RTL930X_MIR_DPM_CTRL (0xA2C0)
275 #define RTL930X_MIR_SPM_CTRL (0xA2B0)
277 #define RTL931X_MIR_CTRL (0xAF00)
278 #define RTL931X_MIR_DPM_CTRL (0xAF30)
279 #define RTL931X_MIR_SPM_CTRL (0xAF10)
281 /* Storm/rate control and scheduling */
282 #define RTL838X_STORM_CTRL (0x4700)
283 #define RTL839X_STORM_CTRL (0x1800)
284 #define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2)))
285 #define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874)
286 #define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878)
287 #define RTL838X_STORM_CTRL_BURST_0 (0x487c)
288 #define RTL838X_STORM_CTRL_BURST_1 (0x4880)
289 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0 (0x1804)
290 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1 (0x1808)
291 #define RTL838X_SCHED_CTRL (0xB980)
292 #define RTL839X_SCHED_CTRL (0x60F4)
293 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58)
294 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C)
295 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804)
296 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808)
297 #define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000)
298 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0 (0x1604)
299 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1 (0x1608)
300 #define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60F8)
301 #define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL (0x6200)
302 #define RTL838X_SCHED_LB_THR (0xB984)
303 #define RTL839X_SCHED_LB_THR (0x60FC)
304 #define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7)))
305 #define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q) (0xC00C + (p << 7) + (((q) << 2)))
306 #define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
307 #define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
308 #define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
309 #define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2)))
310 #define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2)))
311 #define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2)))
312 #define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2)))
313 #define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2)))
314 #define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2)))
315 #define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3)))
316 #define RTL839X_STORM_CTRL_PORT_UC_1(p) (0x1860 + (((p) << 3)))
317 #define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3)))
318 #define RTL839X_STORM_CTRL_PORT_MC_1(p) (0x1a00 + (((p) << 3)))
319 #define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3)))
320 #define RTL839X_STORM_CTRL_PORT_BC_1(p) (0x1BA0 + (((p) << 3)))
321 #define RTL839X_TBL_ACCESS_CTRL_2 (0x611C)
322 #define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2)))
323 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p) (0x1618 + (((p) << 3)))
324 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p) (0x161C + (((p) << 3)))
325 #define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p) (0x1640 + (((p) << 3)))
326 #define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p) (0x1644 + (((p) << 3)))
327 #define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614)
329 /* Link aggregation (Trunking) */
330 #define TRUNK_DISTRIBUTION_ALGO_SPA_BIT 0x01
331 #define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT 0x02
332 #define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT 0x04
333 #define TRUNK_DISTRIBUTION_ALGO_SIP_BIT 0x08
334 #define TRUNK_DISTRIBUTION_ALGO_DIP_BIT 0x10
335 #define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT 0x20
336 #define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT 0x40
337 #define TRUNK_DISTRIBUTION_ALGO_MASKALL 0x7F
339 #define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01
340 #define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02
341 #define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04
342 #define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08
343 #define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF
345 #define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01
346 #define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02
347 #define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04
348 #define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08
349 #define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10
350 #define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20
351 #define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT 0x40
352 #define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT 0x80
353 #define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100
354 #define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT 0x200
355 #define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF
357 #define RTL838X_TRK_MBR_CTR (0x3E00)
358 #define RTL838X_TRK_HASH_IDX_CTRL (0x3E20)
359 #define RTL838X_TRK_HASH_CTRL (0x3E24)
361 #define RTL839X_TRK_MBR_CTR (0x2200)
362 #define RTL839X_TRK_HASH_IDX_CTRL (0x2280)
363 #define RTL839X_TRK_HASH_CTRL (0x2284)
365 #define RTL930X_TRK_MBR_CTRL (0xA41C)
366 #define RTL930X_TRK_HASH_CTRL (0x9F80)
368 #define RTL931X_TRK_MBR_CTRL (0xB8D0)
369 #define RTL931X_TRK_HASH_CTRL (0xBA70)
371 /* Attack prevention */
372 #define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
373 #define RTL838X_ATK_PRVNT_CTRL (0x5B04)
374 #define RTL838X_ATK_PRVNT_ACT (0x5B08)
375 #define RTL838X_ATK_PRVNT_STS (0x5B1C)
378 #define RTL838X_RMA_BPDU_FLD_PMSK (0x4348)
379 #define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18)
380 #define RTL931X_RMA_BPDU_FLD_PMSK (0x8950)
381 #define RTL839X_RMA_BPDU_FLD_PMSK (0x125C)
383 #define RTL838X_SPCL_TRAP_CTRL (0x6980)
384 #define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988)
385 #define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C)
386 #define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
387 #define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994)
388 #define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998)
390 #define RTL839X_SPCL_TRAP_CTRL (0x1054)
391 #define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C)
392 #define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060)
393 #define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
394 #define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064)
395 #define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068)
396 #define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C)
397 #define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070)
398 /* special port action controls */
400 * 0 = FORWARD (default)
403 * 3 = FLOOD IN ALL PORT
406 * offset = CTRL + (port >> 4) << 2
407 * value/mask = 3 << ((port & 0xF) << 1)
429 #define RTL838X_RMA_BPDU_CTRL (0x4330)
430 #define RTL839X_RMA_BPDU_CTRL (0x122C)
431 #define RTL930X_RMA_BPDU_CTRL (0x9E7C)
432 #define RTL931X_RMA_BPDU_CTRL (0x881C)
434 #define RTL838X_RMA_PTP_CTRL (0x4338)
435 #define RTL839X_RMA_PTP_CTRL (0x123C)
436 #define RTL930X_RMA_PTP_CTRL (0x9E88)
437 #define RTL931X_RMA_PTP_CTRL (0x8834)
439 #define RTL838X_RMA_LLTP_CTRL (0x4340)
440 #define RTL839X_RMA_LLTP_CTRL (0x124C)
441 #define RTL930X_RMA_LLTP_CTRL (0x9EFC)
442 #define RTL931X_RMA_LLTP_CTRL (0x8918)
444 #define RTL930X_RMA_EAPOL_CTRL (0x9F08)
445 #define RTL931X_RMA_EAPOL_CTRL (0x8930)
446 #define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04)
449 #define RTL838X_QM_INTPRI2QID_CTRL (0x5F00)
450 #define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2))
451 #define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2)))
452 #define RTL838X_PRI_SEL_PORT_PRI(p) (0x5FB8 + (((p / 10) << 2)))
453 #define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2)))
454 #define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10)
455 #define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
456 #define RTL838X_PRI_SEL_CTRL (0x10E0)
457 #define RTL839X_PRI_SEL_CTRL (0x10E0)
458 #define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2)))
459 #define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2)))
460 #define RTL838X_QM_PKT2CPU_INTPRI_0 (0x5F04)
461 #define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08)
462 #define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C)
463 #define RTL839X_OAM_CTRL (0x2100)
464 #define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2)))
465 #define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2)))
466 #define RTL839X_PRI_SEL_IPRI_REMAP (0x1080)
467 #define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C)
468 #define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC)
469 #define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2)))
470 #define RTL839X_RMK_DEI_CTRL (0x6AA4)
471 #define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2))
472 #define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2))
473 #define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8)
474 #define RTL838X_RMK_IPRI_CTRL (0xA460)
475 #define RTL838X_RMK_OPRI_CTRL (0xA464)
476 #define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7)))
477 #define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7)))
478 #define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2)))
481 #define RTL930X_STAT_PRVTE_DROP_COUNTER0 (0xB5B8)
483 /* Packet Inspection Engine */
484 #define RTL838X_METER_GLB_CTRL (0x4B08)
485 #define RTL839X_METER_GLB_CTRL (0x1300)
486 #define RTL930X_METER_GLB_CTRL (0xa0a0)
487 #define RTL931X_METER_GLB_CTRL (0x411C)
489 #define RTL839X_ACL_CTRL (0x1288)
491 #define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100)
492 #define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280)
493 #define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0)
494 #define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180)
496 #define RTL838X_ACL_BLK_PWR_CTRL (0x6104)
497 #define RTL839X_PS_ACL_PWR_CTRL (0x049c)
499 #define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2))
500 #define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2))
501 #define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2))
502 #define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2))
504 #define RTL838X_ACL_BLK_GROUP_CTRL (0x615C)
505 #define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec)
507 #define RTL838X_ACL_CLR_CTRL (0x6168)
508 #define RTL839X_ACL_CLR_CTRL (0x12fc)
509 #define RTL930X_PIE_CLR_CTRL (0xa66c)
510 #define RTL931X_PIE_CLR_CTRL (0x42D8)
512 #define RTL838X_DMY_REG27 (0x3378)
514 #define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2)))
515 #define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2)))
516 #define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2)))
518 #define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4)
519 #define RTL931X_PIE_BLK_PHASE_CTRL (0x4184)
522 #define PIE_ACT_COPY_TO_PORT 2
523 #define PIE_ACT_REDIRECT_TO_PORT 4
524 #define PIE_ACT_ROUTE_UC 6
525 #define PIE_ACT_VID_ASSIGN 0
530 #define L3_TRAP2CPU 2
531 #define L3_COPY2CPU 3
532 #define L3_TRAP2MASTERCPU 4
533 #define L3_COPY2MASTERCPU 5
534 #define L3_HARDDROP 6
537 #define ROUTE_ACT_FORWARD 0
538 #define ROUTE_ACT_TRAP2CPU 1
539 #define ROUTE_ACT_COPY2CPU 2
540 #define ROUTE_ACT_DROP 3
543 #define RTL839X_ROUTING_SA_CTRL 0x6afc
544 #define RTL930X_L3_HOST_TBL_CTRL (0xAB48)
545 #define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C)
546 #define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50)
547 #define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54)
548 #define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58)
549 #define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2))
550 #define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2))
551 #define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C)
552 #define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0)
553 #define RTL930X_L3_HW_LU_CTRL (0xACC0)
554 #define RTL930X_L3_IP_ROUTE_CTRL 0xab44
556 /* Port LED Control */
557 #define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2)))
558 #define RTL930X_LED_SET0_0_CTRL (0xCC28)
559 #define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2)))
560 #define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2)))
561 #define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C)
562 #define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40)
563 #define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44)
565 #define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2)))
566 #define RTL931X_LED_SET0_0_CTRL (0x0630)
567 #define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2)))
568 #define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2)))
569 #define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654)
570 #define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c)
571 #define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664)
573 #define MAX_VLANS 4096
576 #define RTL930X_PORT_IGNORE 0x3f
577 #define MAX_MC_GROUPS 512
578 #define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1)
579 #define PIE_BLOCK_SIZE 128
580 #define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE)
581 #define N_FIXED_FIELDS 12
582 #define N_FIXED_FIELDS_RTL931X 14
583 #define MAX_COUNTERS 2048
584 #define MAX_ROUTES 512
585 #define MAX_HOST_ROUTES 1536
586 #define MAX_INTF_MTUS 8
587 #define DEFAULT_MTU 1536
588 #define MAX_INTERFACES 100
589 #define MAX_ROUTER_MACS 64
590 #define L3_EGRESS_DMACS 2048
596 PHY_RTL8218B_INT
= 2,
597 PHY_RTL8218B_EXT
= 3,
604 PBVLAN_TYPE_INNER
= 0,
609 PBVLAN_MODE_UNTAG_AND_PRITAG
= 0,
610 PBVLAN_MODE_UNTAG_ONLY
,
614 struct rtl838x_port
{
620 bool phy_is_integrated
;
625 const struct dsa_port
*dp
;
628 struct rtl838x_vlan_info
{
636 // The following fields are used only by the RTL931X
637 int if_id
; // Interface (index in L3_EGR_INTF_IDX)
638 u16 multicast_grp_mask
;
639 int l2_tunnel_list_id
;
650 struct rtl838x_l2_entry
{
656 enum l2_entry_type type
;
668 u16 mc_portmask_index
;
673 bool nh_vlan_target
; // Only RTL83xx: VLAN used for next hop
675 // The following is only valid on RTL931x
678 bool is_local_forward
;
679 bool is_remote_forward
;
682 int l2_tunnel_list_id
;
685 enum fwd_rule_action
{
686 FWD_RULE_ACTION_NONE
= 0,
687 FWD_RULE_ACTION_FWD
= 1,
706 /* Intermediate representation of a Packet Inspection Engine Rule
707 * as suggested by the Kernel's tc flower offload subsystem
708 * Field meaning is universal across SoC families, but data content is specific
709 * to SoC family (e.g. because of different port ranges) */
712 enum pie_phase phase
; // Phase in which this template is applied
713 int packet_cntr
; // ID of a packet counter assigned to this rule
714 int octet_cntr
; // ID of a byte counter assigned to this rule
718 // The following are requirements for the pie template
720 bool is_ipv6
; // This is a rule with IPv6 fields
722 // Fixed fields that are always matched against on RTL8380
724 u8 spn
; // Source port number
725 bool stacking_port
; // Source port is stacking port
726 bool mgnt_vlan
; // Packet arrived on management VLAN
727 bool dmac_hit_sw
; // The packet's destination MAC matches one of the device's
728 bool content_too_deep
; // The content of the packet cannot be parsed: too many layers
729 bool not_first_frag
; // Not the first IP fragment
730 u8 frame_type_l4
; // 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP
731 u8 frame_type
; // 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6
732 bool otag_fmt
; // 0: outer tag packet, 1: outer priority tag or untagged
733 bool itag_fmt
; // 0: inner tag packet, 1: inner priority tag or untagged
734 bool otag_exist
; // packet with outer tag
735 bool itag_exist
; // packet with inner tag
736 bool frame_type_l2
; // 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved
737 bool igr_normal_port
; // Ingress port is not cpu or stacking port
738 u8 tid
; // The template ID defining the what the templated fields mean
740 // Masks for the fields that are always matched against on RTL8380
743 bool stacking_port_m
;
746 bool content_too_deep_m
;
747 bool not_first_frag_m
;
754 bool frame_type_l2_m
;
755 bool igr_normal_port_m
;
758 // Logical operations between rules, special rules for rule numbers apply
760 bool cond_not
; // Matches when conditions not match
761 bool cond_and1
; // And this rule 2n with the next rule 2n+1 in same block
762 bool cond_and2
; // And this rule m in block 2n with rule m in block 2n+1
765 // Actions to be performed
766 bool drop
; // Drop the packet
767 bool fwd_sel
; // Forward packet: to port, portmask, dest route, next rule, drop
768 bool ovid_sel
; // So something to outer vlan-id: shift, re-assign
769 bool ivid_sel
; // Do something to inner vlan-id: shift, re-assign
770 bool flt_sel
; // Filter the packet when sending to certain ports
771 bool log_sel
; // Log the packet in one of the LOG-table counters
772 bool rmk_sel
; // Re-mark the packet, i.e. change the priority-tag
773 bool meter_sel
; // Meter the packet, i.e. limit rate of this type of packet
774 bool tagst_sel
; // Change the ergress tag
775 bool mir_sel
; // Mirror the packet to a Link Aggregation Group
776 bool nopri_sel
; // Change the normal priority
777 bool cpupri_sel
; // Change the CPU priority
778 bool otpid_sel
; // Change Outer Tag Protocol Identifier (802.1q)
779 bool itpid_sel
; // Change Inner Tag Protocol Identifier (802.1q)
780 bool shaper_sel
; // Apply traffic shaper
781 bool mpls_sel
; // MPLS actions
782 bool bypass_sel
; // Bypass actions
783 bool fwd_sa_lrn
; // Learn the source address when forwarding
784 bool fwd_mod_to_cpu
; // Forward the modified VLAN tag format to CPU-port
786 // Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300
787 u64 spm
; // Source Port Matrix
788 u16 otag
; // Outer VLAN-ID
789 u8 smac
[ETH_ALEN
]; // Source MAC address
790 u8 dmac
[ETH_ALEN
]; // Destination MAC address
791 u16 ethertype
; // Ethernet frame type field in ethernet header
792 u16 itag
; // Inner VLAN-ID
793 u16 field_range_check
;
794 u32 sip
; // Source IP
795 struct in6_addr sip6
; // IPv6 Source IP
796 u32 dip
; // Destination IP
797 struct in6_addr dip6
; // IPv6 Destination IP
798 u16 tos_proto
; // IPv4: TOS + Protocol fields, IPv6: Traffic class + next header
799 u16 sport
; // TCP/UDP source port
800 u16 dport
; // TCP/UDP destination port
803 u16 dsap_ssap
; // Destination / Source Service Access Point bytes (802.3)
811 u16 field_range_check_m
;
813 struct in6_addr sip6_m
; // IPv6 Source IP mask
815 struct in6_addr dip6_m
; // IPv6 Destination IP mask
823 // Data associated with actions
824 u8 fwd_act
; // Type of forwarding action
825 // 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask
826 // 4: redirect to portid, 5: redirect to portmask
827 // 6: route, 7: vlan leaky (only 8380)
828 u16 fwd_data
; // Additional data for forwarding action, e.g. destination port
830 u16 ovid_data
; // Outer VLAN ID
832 u16 ivid_data
; // Inner VLAN ID
833 u16 flt_data
; // Filtering data
834 u16 log_data
; // ID of packet or octet counter in LOG table, on RTL93xx
835 // unnecessary since PIE-Rule-ID == LOG-counter-ID
837 u8 mpls_act
; // MPLS action type
838 u16 mpls_lib_idx
; // MPLS action data
840 u16 rmk_data
; // Data for remarking
841 u16 meter_data
; // ID of meter for bandwidth control
850 // Bypass actions, ignored on RTL8380
851 bool bypass_all
; // Not clear
852 bool bypass_igr_stp
; // Bypass Ingress STP state
853 bool bypass_ibc_sc
; // Bypass Ingress Bandwidth Control and Storm Control
856 struct rtl838x_l3_intf
{
865 u8 ip4_icmp_redirect
;
866 u8 ip6_icmp_redirect
;
867 u8 ip4_pbr_icmp_redirect
;
868 u8 ip6_pbr_icmp_redirect
;
871 /* An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point
872 * for the L3 routing system. Packets arriving and matching an entry in this table
873 * will be considered for routing.
874 * Mask fields state whether the corresponding data fields matter for matching
876 struct rtl93xx_rt_mac
{
877 bool valid
; // Valid or not
878 bool p_type
; // Individual (0) or trunk (1) port
879 bool p_mask
; // Whether the port type is used
881 u8 p_id_mask
; // Mask for the port
882 u8 action
; // Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU
883 // 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP
886 u64 mac
; // MAC address used as source MAC in the routed packet
890 struct rtl83xx_nexthop
{
891 u16 id
; // ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP
894 u16 vid
; // VLAN-ID for L2 table entry (saved from L2-UC entry)
895 u16 rvid
; // Relay VID/FID for the L2 table entry
896 u64 mac
; // The MAC address of the entry in the L2_NEXT_HOP table
898 u16 l2_id
; // Index of this next hop forwarding entry in L2 FIB table
899 u64 gw
; // The gateway MAC address packets are forwarded to
900 int if_id
; // Interface (into L3_EGR_INTF_IDX)
903 struct rtl838x_switch_priv
;
905 struct rtl83xx_flow
{
906 unsigned long cookie
;
907 struct rhash_head node
;
908 struct rcu_head rcu_head
;
909 struct rtl838x_switch_priv
*priv
;
910 struct pie_rule rule
;
914 struct rtl93xx_route_attr
{
926 struct rtl83xx_route
{
927 u32 gw_ip
; // IP of the route's gateway
928 u32 dst_ip
; // IP of the destination net
929 struct in6_addr dst_ip6
;
930 int prefix_len
; // Network prefix len of the destination net
932 int id
; // ID number of this route
933 struct rhlist_head linkage
;
934 u16 switch_mac_id
; // Index into switch's own MACs, RTL839X only
935 struct rtl83xx_nexthop nh
;
937 struct rtl93xx_route_attr attr
;
941 void (*mask_port_reg_be
)(u64 clear
, u64 set
, int reg
);
942 void (*set_port_reg_be
)(u64 set
, int reg
);
943 u64 (*get_port_reg_be
)(int reg
);
944 void (*mask_port_reg_le
)(u64 clear
, u64 set
, int reg
);
945 void (*set_port_reg_le
)(u64 set
, int reg
);
946 u64 (*get_port_reg_le
)(int reg
);
949 int stat_port_std_mib
;
950 int (*port_iso_ctrl
)(int p
);
951 void (*traffic_enable
)(int source
, int dest
);
952 void (*traffic_disable
)(int source
, int dest
);
953 void (*traffic_set
)(int source
, u64 dest_matrix
);
954 u64 (*traffic_get
)(int source
);
958 u32 l2_port_aging_out
;
959 int l2_tbl_flush_ctrl
;
960 void (*exec_tbl0_cmd
)(u32 cmd
);
961 void (*exec_tbl1_cmd
)(u32 cmd
);
962 int (*tbl_access_data_0
)(int i
);
964 int isr_port_link_sts_chg
;
965 int imr_port_link_sts_chg
;
967 void (*vlan_tables_read
)(u32 vlan
, struct rtl838x_vlan_info
*info
);
968 void (*vlan_set_tagged
)(u32 vlan
, struct rtl838x_vlan_info
*info
);
969 void (*vlan_set_untagged
)(u32 vlan
, u64 portmask
);
970 void (*vlan_profile_dump
)(int index
);
971 void (*vlan_profile_setup
)(int profile
);
972 void (*vlan_port_pvidmode_set
)(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
);
973 void (*vlan_port_pvid_set
)(int port
, enum pbvlan_type type
, int pvid
);
974 void (*vlan_port_keep_tag_set
)(int port
, bool keep_outer
, bool keep_inner
);
975 void (*set_vlan_igr_filter
)(int port
, enum igr_filter state
);
976 void (*set_vlan_egr_filter
)(int port
, enum egr_filter state
);
977 void (*enable_learning
)(int port
, bool enable
);
978 void (*enable_flood
)(int port
, bool enable
);
979 void (*enable_mcast_flood
)(int port
, bool enable
);
980 void (*enable_bcast_flood
)(int port
, bool enable
);
981 void (*stp_get
)(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[]);
982 void (*stp_set
)(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[]);
983 int (*mac_force_mode_ctrl
)(int port
);
984 int (*mac_port_ctrl
)(int port
);
985 int (*l2_port_new_salrn
)(int port
);
986 int (*l2_port_new_sa_fwd
)(int port
);
987 int (*set_ageing_time
)(unsigned long msec
);
992 int mac_link_dup_sts
;
993 int (*mac_link_spd_sts
)(int port
);
994 int mac_rx_pause_sts
;
995 int mac_tx_pause_sts
;
996 u64 (*read_l2_entry_using_hash
)(u32 hash
, u32 position
, struct rtl838x_l2_entry
*e
);
997 void (*write_l2_entry_using_hash
)(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
);
998 u64 (*read_cam
)(int idx
, struct rtl838x_l2_entry
*e
);
999 void (*write_cam
)(int idx
, struct rtl838x_l2_entry
*e
);
1000 int (*trk_mbr_ctr
)(int group
);
1001 int rma_bpdu_fld_pmask
;
1002 int spcl_trap_eapol_ctrl
;
1003 void (*init_eee
)(struct rtl838x_switch_priv
*priv
, bool enable
);
1004 void (*port_eee_set
)(struct rtl838x_switch_priv
*priv
, int port
, bool enable
);
1005 int (*eee_port_ability
)(struct rtl838x_switch_priv
*priv
,
1006 struct ethtool_eee
*e
, int port
);
1007 u64 (*l2_hash_seed
)(u64 mac
, u32 vid
);
1008 u32 (*l2_hash_key
)(struct rtl838x_switch_priv
*priv
, u64 seed
);
1009 u64 (*read_mcast_pmask
)(int idx
);
1010 void (*write_mcast_pmask
)(int idx
, u64 portmask
);
1011 void (*vlan_fwd_on_inner
)(int port
, bool is_set
);
1012 void (*pie_init
)(struct rtl838x_switch_priv
*priv
);
1013 int (*pie_rule_read
)(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
);
1014 int (*pie_rule_write
)(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
);
1015 int (*pie_rule_add
)(struct rtl838x_switch_priv
*priv
, struct pie_rule
*rule
);
1016 void (*pie_rule_rm
)(struct rtl838x_switch_priv
*priv
, struct pie_rule
*rule
);
1017 void (*l2_learning_setup
)(void);
1018 u32 (*packet_cntr_read
)(int counter
);
1019 void (*packet_cntr_clear
)(int counter
);
1020 void (*route_read
)(int idx
, struct rtl83xx_route
*rt
);
1021 void (*route_write
)(int idx
, struct rtl83xx_route
*rt
);
1022 void (*host_route_write
)(int idx
, struct rtl83xx_route
*rt
);
1023 int (*l3_setup
)(struct rtl838x_switch_priv
*priv
);
1024 void (*set_l3_nexthop
)(int idx
, u16 dmac_id
, u16 interface
);
1025 void (*get_l3_nexthop
)(int idx
, u16
*dmac_id
, u16
*interface
);
1026 u64 (*get_l3_egress_mac
)(u32 idx
);
1027 void (*set_l3_egress_mac
)(u32 idx
, u64 mac
);
1028 int (*find_l3_slot
)(struct rtl83xx_route
*rt
, bool must_exist
);
1029 int (*route_lookup_hw
)(struct rtl83xx_route
*rt
);
1030 void (*get_l3_router_mac
)(u32 idx
, struct rtl93xx_rt_mac
*m
);
1031 void (*set_l3_router_mac
)(u32 idx
, struct rtl93xx_rt_mac
*m
);
1032 void (*set_l3_egress_intf
)(int idx
, struct rtl838x_l3_intf
*intf
);
1033 void (*set_distribution_algorithm
)(int group
, int algoidx
, u32 algomask
);
1034 void (*set_receive_management_action
)(int port
, rma_ctrl_t type
, action_type_t action
);
1035 void (*led_init
)(struct rtl838x_switch_priv
*priv
);
1038 struct rtl838x_switch_priv
{
1039 /* Switch operation */
1040 struct dsa_switch
*ds
;
1045 struct rtl838x_port ports
[57];
1046 struct mutex reg_mutex
; // Mutex for individual register manipulations
1047 struct mutex pie_mutex
; // Mutex for Packet Inspection Engine
1049 int mirror_group_ports
[4];
1050 struct mii_bus
*mii_bus
;
1051 const struct rtl838x_reg
*r
;
1059 struct dentry
*dbgfs_dir
;
1061 u64 lags_port_members
[MAX_LAGS
];
1062 struct net_device
*lag_devs
[MAX_LAGS
];
1063 u32 lag_primary
[MAX_LAGS
];
1064 u32 is_lagmember
[57];
1066 struct notifier_block nb
; // TODO: change to different name
1067 struct notifier_block ne_nb
;
1068 struct notifier_block fib_nb
;
1070 unsigned long int mc_group_bm
[MAX_MC_GROUPS
>> 5];
1071 int mc_group_saves
[MAX_MC_GROUPS
];
1073 struct rhashtable tc_ht
;
1074 unsigned long int pie_use_bm
[MAX_PIE_ENTRIES
>> 5];
1076 unsigned long int octet_cntr_use_bm
[MAX_COUNTERS
>> 5];
1077 unsigned long int packet_cntr_use_bm
[MAX_COUNTERS
>> 4];
1078 struct rhltable routes
;
1079 unsigned long int route_use_bm
[MAX_ROUTES
>> 5];
1080 unsigned long int host_route_use_bm
[MAX_HOST_ROUTES
>> 5];
1081 struct rtl838x_l3_intf
*interfaces
[MAX_INTERFACES
];
1082 u16 intf_mtus
[MAX_INTF_MTUS
];
1083 int intf_mtu_count
[MAX_INTF_MTUS
];
1086 void rtl838x_dbgfs_init(struct rtl838x_switch_priv
*priv
);
1087 void rtl930x_dbgfs_init(struct rtl838x_switch_priv
*priv
);
1089 #endif /* _RTL838X_H */