projects / openwrt / staging / dedeckeh.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
realtek: Reduce variable scopes
[openwrt/staging/dedeckeh.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4
5 #include "rtl83xx.h"
6
7 #define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0
8 #define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1
9 #define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
10
11 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828
12 /* port 0-52 */
13 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \
14 RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
15 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7,6)
16 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5,4)
17 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
18 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
19 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
20 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
21
22 extern struct mutex smi_lock;
23 extern struct rtl83xx_soc_info soc_info;
24
25 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
26 enum template_field_id {
27 TEMPLATE_FIELD_SPMMASK = 0,
28 TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */
29 TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-31 */
30 TEMPLATE_FIELD_SPM2 = 3, /* Source portmask ports 32-47 */
31 TEMPLATE_FIELD_SPM3 = 4, /* Source portmask ports 48-56 */
32 TEMPLATE_FIELD_DMAC0 = 5, /* Destination MAC [15:0] */
33 TEMPLATE_FIELD_DMAC1 = 6, /* Destination MAC [31:16] */
34 TEMPLATE_FIELD_DMAC2 = 7, /* Destination MAC [47:32] */
35 TEMPLATE_FIELD_SMAC0 = 8, /* Source MAC [15:0] */
36 TEMPLATE_FIELD_SMAC1 = 9, /* Source MAC [31:16] */
37 TEMPLATE_FIELD_SMAC2 = 10, /* Source MAC [47:32] */
38 TEMPLATE_FIELD_ETHERTYPE = 11, /* Ethernet frame type field */
39 /* Field-ID 12 is not used */
40 TEMPLATE_FIELD_OTAG = 13,
41 TEMPLATE_FIELD_ITAG = 14,
42 TEMPLATE_FIELD_SIP0 = 15,
43 TEMPLATE_FIELD_SIP1 = 16,
44 TEMPLATE_FIELD_DIP0 = 17,
45 TEMPLATE_FIELD_DIP1 = 18,
46 TEMPLATE_FIELD_IP_TOS_PROTO = 19,
47 TEMPLATE_FIELD_IP_FLAG = 20,
48 TEMPLATE_FIELD_L4_SPORT = 21,
49 TEMPLATE_FIELD_L4_DPORT = 22,
50 TEMPLATE_FIELD_L34_HEADER = 23,
51 TEMPLATE_FIELD_ICMP_IGMP = 24,
52 TEMPLATE_FIELD_VID_RANG0 = 25,
53 TEMPLATE_FIELD_VID_RANG1 = 26,
54 TEMPLATE_FIELD_L4_PORT_RANG = 27,
55 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28,
56 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29,
57 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30,
58 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31,
59 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32,
60 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33,
61 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34,
62 TEMPLATE_FIELD_SIP2 = 35,
63 TEMPLATE_FIELD_SIP3 = 36,
64 TEMPLATE_FIELD_SIP4 = 37,
65 TEMPLATE_FIELD_SIP5 = 38,
66 TEMPLATE_FIELD_SIP6 = 39,
67 TEMPLATE_FIELD_SIP7 = 40,
68 TEMPLATE_FIELD_OLABEL = 41,
69 TEMPLATE_FIELD_ILABEL = 42,
70 TEMPLATE_FIELD_OILABEL = 43,
71 TEMPLATE_FIELD_DPMMASK = 44,
72 TEMPLATE_FIELD_DPM0 = 45,
73 TEMPLATE_FIELD_DPM1 = 46,
74 TEMPLATE_FIELD_DPM2 = 47,
75 TEMPLATE_FIELD_DPM3 = 48,
76 TEMPLATE_FIELD_L2DPM0 = 49,
77 TEMPLATE_FIELD_L2DPM1 = 50,
78 TEMPLATE_FIELD_L2DPM2 = 51,
79 TEMPLATE_FIELD_L2DPM3 = 52,
80 TEMPLATE_FIELD_IVLAN = 53,
81 TEMPLATE_FIELD_OVLAN = 54,
82 TEMPLATE_FIELD_FWD_VID = 55,
83 TEMPLATE_FIELD_DIP2 = 56,
84 TEMPLATE_FIELD_DIP3 = 57,
85 TEMPLATE_FIELD_DIP4 = 58,
86 TEMPLATE_FIELD_DIP5 = 59,
87 TEMPLATE_FIELD_DIP6 = 60,
88 TEMPLATE_FIELD_DIP7 = 61,
89 };
90
91 /* Number of fixed templates predefined in the SoC */
92 #define N_FIXED_TEMPLATES 5
93 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
94 {
95 {
96 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
97 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
98 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
99 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
100 }, {
101 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
102 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
103 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,
104 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
105 }, {
106 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
107 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
108 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
109 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
110 }, {
111 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
112 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
113 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
114 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
115 }, {
116 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
117 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
118 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0,
119 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
120 },
121 };
122
123 void rtl839x_print_matrix(void)
124 {
125 volatile u64 *ptr9;
126
127 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
128 for (int i = 0; i < 52; i += 4)
129 pr_debug("> %16llx %16llx %16llx %16llx\n",
130 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
131 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
132 }
133
134 static inline int rtl839x_port_iso_ctrl(int p)
135 {
136 return RTL839X_PORT_ISO_CTRL(p);
137 }
138
139 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
140 {
141 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
142 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
143 }
144
145 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
146 {
147 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
148 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
149 }
150
151 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
152 {
153 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
154 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
155 }
156
157 static inline int rtl839x_tbl_access_data_0(int i)
158 {
159 return RTL839X_TBL_ACCESS_DATA_0(i);
160 }
161
162 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
163 {
164 u32 u, v, w;
165 /* Read VLAN table (0) via register 0 */
166 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
167
168 rtl_table_read(r, vlan);
169 u = sw_r32(rtl_table_data(r, 0));
170 v = sw_r32(rtl_table_data(r, 1));
171 w = sw_r32(rtl_table_data(r, 2));
172 rtl_table_release(r);
173
174 info->tagged_ports = u;
175 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
176 info->profile_id = w >> 30 | ((v & 1) << 2);
177 info->hash_mc_fid = !!(w & BIT(2));
178 info->hash_uc_fid = !!(w & BIT(3));
179 info->fid = (v >> 3) & 0xff;
180
181 /* Read UNTAG table (0) via table register 1 */
182 r = rtl_table_get(RTL8390_TBL_1, 0);
183 rtl_table_read(r, vlan);
184 u = sw_r32(rtl_table_data(r, 0));
185 v = sw_r32(rtl_table_data(r, 1));
186 rtl_table_release(r);
187
188 info->untagged_ports = u;
189 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
190 }
191
192 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
193 {
194 u32 u, v, w;
195 /* Access VLAN table (0) via register 0 */
196 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
197
198 u = info->tagged_ports >> 21;
199 v = info->tagged_ports << 11;
200 v |= ((u32)info->fid) << 3;
201 v |= info->hash_uc_fid ? BIT(2) : 0;
202 v |= info->hash_mc_fid ? BIT(1) : 0;
203 v |= (info->profile_id & 0x4) ? 1 : 0;
204 w = ((u32)(info->profile_id & 3)) << 30;
205
206 sw_w32(u, rtl_table_data(r, 0));
207 sw_w32(v, rtl_table_data(r, 1));
208 sw_w32(w, rtl_table_data(r, 2));
209
210 rtl_table_write(r, vlan);
211 rtl_table_release(r);
212 }
213
214 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
215 {
216 u32 u, v;
217
218 /* Access UNTAG table (0) via table register 1 */
219 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
220
221 u = portmask >> 21;
222 v = portmask << 11;
223
224 sw_w32(u, rtl_table_data(r, 0));
225 sw_w32(v, rtl_table_data(r, 1));
226 rtl_table_write(r, vlan);
227
228 rtl_table_release(r);
229 }
230
231 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
232 static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
233 {
234 if (is_set)
235 rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
236 else
237 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
238 }
239
240 /* Hash seed is vid (actually rvid) concatenated with the MAC address */
241 static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)
242 {
243 u64 v = vid;
244
245 v <<= 48;
246 v |= mac;
247
248 return v;
249 }
250
251 /* Applies the same hash algorithm as the one used currently by the ASIC to the seed
252 * and returns a key into the L2 hash table
253 */
254 static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
255 {
256 u32 h1, h2, h;
257
258 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
259 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^
260 ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^
261 ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
262 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^
263 ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^
264 (seed & 0x3f));
265 h = (h1 << 6) | h2;
266 } else {
267 h = (seed >> 60) ^
268 ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) ^
269 ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) ^
270 ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
271 }
272
273 return h;
274 }
275
276 static inline int rtl839x_mac_force_mode_ctrl(int p)
277 {
278 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
279 }
280
281 static inline int rtl839x_mac_port_ctrl(int p)
282 {
283 return RTL839X_MAC_PORT_CTRL(p);
284 }
285
286 static inline int rtl839x_l2_port_new_salrn(int p)
287 {
288 return RTL839X_L2_PORT_NEW_SALRN(p);
289 }
290
291 static inline int rtl839x_l2_port_new_sa_fwd(int p)
292 {
293 return RTL839X_L2_PORT_NEW_SA_FWD(p);
294 }
295
296 static inline int rtl839x_mac_link_spd_sts(int p)
297 {
298 return RTL839X_MAC_LINK_SPD_STS(p);
299 }
300
301 static inline int rtl839x_trk_mbr_ctr(int group)
302 {
303 return RTL839X_TRK_MBR_CTR + (group << 3);
304 }
305
306 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
307 {
308 /* Table contains different entry types, we need to identify the right one:
309 * Check for MC entries, first
310 */
311 e->is_ip_mc = !!(r[2] & BIT(31));
312 e->is_ipv6_mc = !!(r[2] & BIT(30));
313 e->type = L2_INVALID;
314 if (!e->is_ip_mc && !e->is_ipv6_mc) {
315 e->mac[0] = (r[0] >> 12);
316 e->mac[1] = (r[0] >> 4);
317 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
318 e->mac[3] = (r[1] >> 20);
319 e->mac[4] = (r[1] >> 12);
320 e->mac[5] = (r[1] >> 4);
321
322 e->vid = (r[2] >> 4) & 0xfff;
323 e->rvid = (r[0] >> 20) & 0xfff;
324
325 /* Is it a unicast entry? check multicast bit */
326 if (!(e->mac[0] & 1)) {
327 e->is_static = !!((r[2] >> 18) & 1);
328 e->port = (r[2] >> 24) & 0x3f;
329 e->block_da = !!(r[2] & (1 << 19));
330 e->block_sa = !!(r[2] & (1 << 20));
331 e->suspended = !!(r[2] & (1 << 17));
332 e->next_hop = !!(r[2] & (1 << 16));
333 if (e->next_hop) {
334 pr_debug("Found next hop entry, need to read data\n");
335 e->nh_vlan_target = !!(r[2] & BIT(15));
336 e->nh_route_id = (r[2] >> 4) & 0x1ff;
337 e->vid = e->rvid;
338 }
339 e->age = (r[2] >> 21) & 3;
340 e->valid = true;
341 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
342 e->valid = false;
343 else
344 e->type = L2_UNICAST;
345 } else {
346 e->valid = true;
347 e->type = L2_MULTICAST;
348 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
349 e->vid = e->rvid;
350 }
351 } else { /* IPv4 and IPv6 multicast */
352 e->vid = e->rvid = (r[0] << 20) & 0xfff;
353 e->mc_gip = r[1];
354 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
355 }
356 if (e->is_ip_mc) {
357 e->valid = true;
358 e->type = IP4_MULTICAST;
359 }
360 if (e->is_ipv6_mc) {
361 e->valid = true;
362 e->type = IP6_MULTICAST;
363 }
364 /* pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */
365 }
366
367 /* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */
368 static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
369 {
370 if (!e->valid) {
371 r[0] = r[1] = r[2] = 0;
372 return;
373 }
374
375 r[2] = e->is_ip_mc ? BIT(31) : 0;
376 r[2] |= e->is_ipv6_mc ? BIT(30) : 0;
377
378 if (!e->is_ip_mc && !e->is_ipv6_mc) {
379 r[0] = ((u32)e->mac[0]) << 12;
380 r[0] |= ((u32)e->mac[1]) << 4;
381 r[0] |= ((u32)e->mac[2]) >> 4;
382 r[1] = ((u32)e->mac[2]) << 28;
383 r[1] |= ((u32)e->mac[3]) << 20;
384 r[1] |= ((u32)e->mac[4]) << 12;
385 r[1] |= ((u32)e->mac[5]) << 4;
386
387 if (!(e->mac[0] & 1)) { /* Not multicast */
388 r[2] |= e->is_static ? BIT(18) : 0;
389 r[0] |= ((u32)e->rvid) << 20;
390 r[2] |= e->port << 24;
391 r[2] |= e->block_da ? BIT(19) : 0;
392 r[2] |= e->block_sa ? BIT(20) : 0;
393 r[2] |= e->suspended ? BIT(17) : 0;
394 r[2] |= ((u32)e->age) << 21;
395 if (e->next_hop) {
396 r[2] |= BIT(16);
397 r[2] |= e->nh_vlan_target ? BIT(15) : 0;
398 r[2] |= (e->nh_route_id & 0x7ff) << 4;
399 } else {
400 r[2] |= e->vid << 4;
401 }
402 pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]);
403 } else { /* L2 Multicast */
404 r[0] |= ((u32)e->rvid) << 20;
405 r[2] |= ((u32)e->mc_portmask_index) << 6;
406 }
407 } else { /* IPv4 or IPv6 MC entry */
408 r[0] = ((u32)e->rvid) << 20;
409 r[1] = e->mc_gip;
410 r[2] |= ((u32)e->mc_portmask_index) << 6;
411 }
412 }
413
414 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
415 * hash is the id of the bucket and pos is the position of the entry in that bucket
416 * The data read from the SoC is filled into rtl838x_l2_entry
417 */
418 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
419 {
420 u32 r[3];
421 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
422 u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
423
424 rtl_table_read(q, idx);
425 for (int i = 0; i < 3; i++)
426 r[i] = sw_r32(rtl_table_data(q, i));
427
428 rtl_table_release(q);
429
430 rtl839x_fill_l2_entry(r, e);
431 if (!e->valid)
432 return 0;
433
434 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
435 }
436
437 static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
438 {
439 u32 r[3];
440 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
441
442 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
443
444 rtl839x_fill_l2_row(r, e);
445
446 for (int i = 0; i < 3; i++)
447 sw_w32(r[i], rtl_table_data(q, i));
448
449 rtl_table_write(q, idx);
450 rtl_table_release(q);
451 }
452
453 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
454 {
455 u32 r[3];
456 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */
457
458 rtl_table_read(q, idx);
459 for (int i = 0; i < 3; i++)
460 r[i] = sw_r32(rtl_table_data(q, i));
461
462 rtl_table_release(q);
463
464 rtl839x_fill_l2_entry(r, e);
465 if (!e->valid)
466 return 0;
467
468 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
469
470 /* Return MAC with concatenated VID ac concatenated ID */
471 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
472 }
473
474 static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)
475 {
476 u32 r[3];
477 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */
478
479 rtl839x_fill_l2_row(r, e);
480
481 for (int i = 0; i < 3; i++)
482 sw_w32(r[i], rtl_table_data(q, i));
483
484 rtl_table_write(q, idx);
485 rtl_table_release(q);
486 }
487
488 static u64 rtl839x_read_mcast_pmask(int idx)
489 {
490 u64 portmask;
491 /* Read MC_PMSK (2) via register RTL8390_TBL_L2 */
492 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
493
494 rtl_table_read(q, idx);
495 portmask = sw_r32(rtl_table_data(q, 0));
496 portmask <<= 32;
497 portmask |= sw_r32(rtl_table_data(q, 1));
498 portmask >>= 11; /* LSB is bit 11 in data registers */
499 rtl_table_release(q);
500
501 return portmask;
502 }
503
504 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
505 {
506 /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
507 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
508
509 portmask <<= 11; /* LSB is bit 11 in data registers */
510 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
511 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
512 rtl_table_write(q, idx);
513 rtl_table_release(q);
514 }
515
516 static void rtl839x_vlan_profile_setup(int profile)
517 {
518 u32 p[2];
519 u32 pmask_id = UNKNOWN_MC_PMASK;
520
521 p[0] = pmask_id; /* Use portmaks 0xfff for unknown IPv6 MC flooding */
522 /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding */
523 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
524
525 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
526 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
527
528 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);
529 }
530
531 u64 rtl839x_traffic_get(int source)
532 {
533 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
534 }
535
536 void rtl839x_traffic_set(int source, u64 dest_matrix)
537 {
538 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
539 }
540
541 void rtl839x_traffic_enable(int source, int dest)
542 {
543 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
544 }
545
546 void rtl839x_traffic_disable(int source, int dest)
547 {
548 rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));
549 }
550
551 static void rtl839x_l2_learning_setup(void)
552 {
553 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
554 * address flooding to the reserved entry in the portmask table used
555 * also for multicast flooding */
556 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);
557
558 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
559 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT);
560
561 /* Do not trap ARP packets to CPU_PORT */
562 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL);
563 }
564
565 static void rtl839x_enable_learning(int port, bool enable)
566 {
567 /* Limit learning to maximum: 32k entries */
568
569 sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0,
570 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
571 }
572
573 static void rtl839x_enable_flood(int port, bool enable)
574 {
575 /* 0: Forward
576 * 1: Disable
577 * 2: to CPU
578 * 3: Copy to CPU
579 */
580 sw_w32_mask(0x3, enable ? 0 : 1,
581 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
582 }
583
584 static void rtl839x_enable_mcast_flood(int port, bool enable)
585 {
586
587 }
588
589 static void rtl839x_enable_bcast_flood(int port, bool enable)
590 {
591
592 }
593 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
594 {
595 struct dsa_switch *ds = dev_id;
596 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
597 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
598 u64 link;
599
600 /* Clear status */
601 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
602 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
603
604 for (int i = 0; i < RTL839X_CPU_PORT; i++) {
605 if (ports & BIT_ULL(i)) {
606 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
607 if (link & BIT_ULL(i))
608 dsa_port_phylink_mac_change(ds, i, true);
609 else
610 dsa_port_phylink_mac_change(ds, i, false);
611 }
612 }
613
614 return IRQ_HANDLED;
615 }
616
617 /* TODO: unused */
618 int rtl8390_sds_power(int mac, int val)
619 {
620 u32 offset = (mac == 48) ? 0x0 : 0x100;
621 u32 mode = val ? 0 : 1;
622
623 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
624
625 if ((mac != 48) && (mac != 49)) {
626 pr_err("%s: not an SFP port: %d\n", __func__, mac);
627 return -1;
628 }
629
630 /* Set bit 1003. 1000 starts at 7c */
631 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
632
633 return 0;
634 }
635
636 static int rtl839x_smi_wait_op(int timeout)
637 {
638 int ret = 0;
639 u32 val;
640
641 ret = readx_poll_timeout(sw_r32, RTL839X_PHYREG_ACCESS_CTRL,
642 val, !(val & 0x1), 20, timeout);
643 if (ret)
644 pr_err("%s: timeout\n", __func__);
645
646 return ret;
647 }
648
649 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
650 {
651 u32 v;
652 int err = 0;
653
654 if (port > 63 || page > 4095 || reg > 31)
655 return -ENOTSUPP;
656
657 /* Take bug on RTL839x Rev <= C into account */
658 if (port >= RTL839X_CPU_PORT)
659 return -EIO;
660
661 mutex_lock(&smi_lock);
662
663 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
664 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
665 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
666
667 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
668
669 v |= 1;
670 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
671
672 err = rtl839x_smi_wait_op(100000);
673 if (err)
674 goto errout;
675
676 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
677
678 errout:
679 mutex_unlock(&smi_lock);
680
681 return err;
682 }
683
684 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
685 {
686 u32 v;
687 int err = 0;
688
689 val &= 0xffff;
690 if (port > 63 || page > 4095 || reg > 31)
691 return -ENOTSUPP;
692
693 /* Take bug on RTL839x Rev <= C into account */
694 if (port >= RTL839X_CPU_PORT)
695 return -EIO;
696
697 mutex_lock(&smi_lock);
698
699 /* Set PHY to access */
700 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
701
702 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
703
704 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
705 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
706
707 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
708
709 v |= BIT(3) | 1; /* Write operation and execute */
710 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
711
712 err = rtl839x_smi_wait_op(100000);
713 if (err)
714 goto errout;
715
716 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
717 err = -EIO;
718
719 errout:
720 mutex_unlock(&smi_lock);
721
722 return err;
723 }
724
725 /* Read an mmd register of the PHY */
726 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
727 {
728 int err = 0;
729 u32 v;
730
731 /* Take bug on RTL839x Rev <= C into account */
732 if (port >= RTL839X_CPU_PORT)
733 return -EIO;
734
735 mutex_lock(&smi_lock);
736
737 /* Set PHY to access */
738 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
739
740 /* Set MMD device number and register to write to */
741 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
742
743 v = BIT(2) | BIT(0); /* MMD-access | EXEC */
744 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
745
746 err = rtl839x_smi_wait_op(100000);
747 if (err)
748 goto errout;
749
750 /* There is no error-checking via BIT 1 of v, as it does not seem to be set correctly */
751 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
752 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
753
754 errout:
755 mutex_unlock(&smi_lock);
756
757 return err;
758 }
759
760 /* Write to an mmd register of the PHY */
761 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
762 {
763 int err = 0;
764 u32 v;
765
766 /* Take bug on RTL839x Rev <= C into account */
767 if (port >= RTL839X_CPU_PORT)
768 return -EIO;
769
770 mutex_lock(&smi_lock);
771
772 /* Set PHY to access */
773 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
774
775 /* Set data to write */
776 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
777
778 /* Set MMD device number and register to write to */
779 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
780
781 v = BIT(3) | BIT(2) | BIT(0); /* WRITE | MMD-access | EXEC */
782 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
783
784 err = rtl839x_smi_wait_op(100000);
785 if (err)
786 goto errout;
787
788 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
789
790 errout:
791 mutex_unlock(&smi_lock);
792
793 return err;
794 }
795
796 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
797 {
798 u32 info, model;
799
800 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
801 info = sw_r32(RTL839X_CHIP_INFO);
802
803 model = sw_r32(RTL839X_MODEL_NAME_INFO);
804 priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);
805
806 pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
807 }
808
809 void rtl839x_vlan_profile_dump(int profile)
810 {
811 u32 p[2];
812
813 if (profile < 0 || profile > 7)
814 return;
815
816 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
817 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
818
819 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
820 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
821 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
822 (p[0]) & 0xfff);
823 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
824 }
825
826 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
827 {
828 u32 cmd = 1 << 16 | /* Execute cmd */
829 0 << 15 | /* Read */
830 5 << 12 | /* Table type 0b101 */
831 (msti & 0xfff);
832 priv->r->exec_tbl0_cmd(cmd);
833
834 for (int i = 0; i < 4; i++)
835 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
836 }
837
838 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
839 {
840 u32 cmd = 1 << 16 | /* Execute cmd */
841 1 << 15 | /* Write */
842 5 << 12 | /* Table type 0b101 */
843 (msti & 0xfff);
844 for (int i = 0; i < 4; i++)
845 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
846 priv->r->exec_tbl0_cmd(cmd);
847 }
848
849 /* Enables or disables the EEE/EEEP capability of a port */
850 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
851 {
852 u32 v;
853
854 /* This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP */
855 if (port >= 48)
856 return;
857
858 enable = true;
859 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
860 v = enable ? 0xf : 0x0;
861
862 /* Set EEE for 100, 500, 1000MBit and 10GBit */
863 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
864
865 /* Set TX/RX EEE state */
866 v = enable ? 0x3 : 0x0;
867 sw_w32(v, RTL839X_EEE_CTRL(port));
868
869 priv->ports[port].eee_enabled = enable;
870 }
871
872 /* Get EEE own capabilities and negotiation result */
873 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
874 {
875 u64 link, a;
876
877 if (port >= 48)
878 return 0;
879
880 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
881 if (!(link & BIT_ULL(port)))
882 return 0;
883
884 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
885 e->advertised |= ADVERTISED_100baseT_Full;
886
887 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
888 e->advertised |= ADVERTISED_1000baseT_Full;
889
890 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
891 pr_info("Link partner: %016llx\n", a);
892 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
893 e->lp_advertised = ADVERTISED_100baseT_Full;
894 e->lp_advertised |= ADVERTISED_1000baseT_Full;
895 return 1;
896 }
897
898 return 0;
899 }
900
901 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
902 {
903 pr_info("Setting up EEE, state: %d\n", enable);
904
905 /* Set wake timer for TX and pause timer both to 0x21 */
906 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
907 /* Set pause wake timer for GIGA-EEE to 0x11 */
908 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
909 /* Set pause wake timer for 10GBit ports to 0x11 */
910 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
911
912 /* Setup EEE on all ports */
913 for (int i = 0; i < priv->cpu_port; i++) {
914 if (priv->ports[i].phy)
915 rtl839x_port_eee_set(priv, i, enable);
916 }
917 priv->eee_enabled = enable;
918 }
919
920 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
921 {
922 int block = index / PIE_BLOCK_SIZE;
923
924 sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL);
925 }
926
927 /* Delete a range of Packet Inspection Engine rules */
928 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
929 {
930 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
931
932 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
933 mutex_lock(&priv->reg_mutex);
934
935 /* Write from-to and execute bit into control register */
936 sw_w32(v, RTL839X_ACL_CLR_CTRL);
937
938 /* Wait until command has completed */
939 do {
940 } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0));
941
942 mutex_unlock(&priv->reg_mutex);
943
944 return 0;
945 }
946
947 /* Reads the intermediate representation of the templated match-fields of the
948 * PIE rule in the pie_rule structure and fills in the raw data fields in the
949 * raw register space r[].
950 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
951 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
952 * on all SoCs
953 * On the RTL8390 the template mask registers are not word-aligned!
954 */
955 static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
956 {
957 for (int i = 0; i < N_FIXED_FIELDS; i++) {
958 enum template_field_id field_type = t[i];
959 u16 data = 0, data_m = 0;
960
961 switch (field_type) {
962 case TEMPLATE_FIELD_SPM0:
963 data = pr->spm;
964 data_m = pr->spm_m;
965 break;
966 case TEMPLATE_FIELD_SPM1:
967 data = pr->spm >> 16;
968 data_m = pr->spm_m >> 16;
969 break;
970 case TEMPLATE_FIELD_SPM2:
971 data = pr->spm >> 32;
972 data_m = pr->spm_m >> 32;
973 break;
974 case TEMPLATE_FIELD_SPM3:
975 data = pr->spm >> 48;
976 data_m = pr->spm_m >> 48;
977 break;
978 case TEMPLATE_FIELD_OTAG:
979 data = pr->otag;
980 data_m = pr->otag_m;
981 break;
982 case TEMPLATE_FIELD_SMAC0:
983 data = pr->smac[4];
984 data = (data << 8) | pr->smac[5];
985 data_m = pr->smac_m[4];
986 data_m = (data_m << 8) | pr->smac_m[5];
987 break;
988 case TEMPLATE_FIELD_SMAC1:
989 data = pr->smac[2];
990 data = (data << 8) | pr->smac[3];
991 data_m = pr->smac_m[2];
992 data_m = (data_m << 8) | pr->smac_m[3];
993 break;
994 case TEMPLATE_FIELD_SMAC2:
995 data = pr->smac[0];
996 data = (data << 8) | pr->smac[1];
997 data_m = pr->smac_m[0];
998 data_m = (data_m << 8) | pr->smac_m[1];
999 break;
1000 case TEMPLATE_FIELD_DMAC0:
1001 data = pr->dmac[4];
1002 data = (data << 8) | pr->dmac[5];
1003 data_m = pr->dmac_m[4];
1004 data_m = (data_m << 8) | pr->dmac_m[5];
1005 break;
1006 case TEMPLATE_FIELD_DMAC1:
1007 data = pr->dmac[2];
1008 data = (data << 8) | pr->dmac[3];
1009 data_m = pr->dmac_m[2];
1010 data_m = (data_m << 8) | pr->dmac_m[3];
1011 break;
1012 case TEMPLATE_FIELD_DMAC2:
1013 data = pr->dmac[0];
1014 data = (data << 8) | pr->dmac[1];
1015 data_m = pr->dmac_m[0];
1016 data_m = (data_m << 8) | pr->dmac_m[1];
1017 break;
1018 case TEMPLATE_FIELD_ETHERTYPE:
1019 data = pr->ethertype;
1020 data_m = pr->ethertype_m;
1021 break;
1022 case TEMPLATE_FIELD_ITAG:
1023 data = pr->itag;
1024 data_m = pr->itag_m;
1025 break;
1026 case TEMPLATE_FIELD_SIP0:
1027 if (pr->is_ipv6) {
1028 data = pr->sip6.s6_addr16[7];
1029 data_m = pr->sip6_m.s6_addr16[7];
1030 } else {
1031 data = pr->sip;
1032 data_m = pr->sip_m;
1033 }
1034 break;
1035 case TEMPLATE_FIELD_SIP1:
1036 if (pr->is_ipv6) {
1037 data = pr->sip6.s6_addr16[6];
1038 data_m = pr->sip6_m.s6_addr16[6];
1039 } else {
1040 data = pr->sip >> 16;
1041 data_m = pr->sip_m >> 16;
1042 }
1043 break;
1044 case TEMPLATE_FIELD_SIP2:
1045 case TEMPLATE_FIELD_SIP3:
1046 case TEMPLATE_FIELD_SIP4:
1047 case TEMPLATE_FIELD_SIP5:
1048 case TEMPLATE_FIELD_SIP6:
1049 case TEMPLATE_FIELD_SIP7:
1050 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1051 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1052 break;
1053 case TEMPLATE_FIELD_DIP0:
1054 if (pr->is_ipv6) {
1055 data = pr->dip6.s6_addr16[7];
1056 data_m = pr->dip6_m.s6_addr16[7];
1057 } else {
1058 data = pr->dip;
1059 data_m = pr->dip_m;
1060 }
1061 break;
1062 case TEMPLATE_FIELD_DIP1:
1063 if (pr->is_ipv6) {
1064 data = pr->dip6.s6_addr16[6];
1065 data_m = pr->dip6_m.s6_addr16[6];
1066 } else {
1067 data = pr->dip >> 16;
1068 data_m = pr->dip_m >> 16;
1069 }
1070 break;
1071 case TEMPLATE_FIELD_DIP2:
1072 case TEMPLATE_FIELD_DIP3:
1073 case TEMPLATE_FIELD_DIP4:
1074 case TEMPLATE_FIELD_DIP5:
1075 case TEMPLATE_FIELD_DIP6:
1076 case TEMPLATE_FIELD_DIP7:
1077 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1078 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1079 break;
1080 case TEMPLATE_FIELD_IP_TOS_PROTO:
1081 data = pr->tos_proto;
1082 data_m = pr->tos_proto_m;
1083 break;
1084 case TEMPLATE_FIELD_L4_SPORT:
1085 data = pr->sport;
1086 data_m = pr->sport_m;
1087 break;
1088 case TEMPLATE_FIELD_L4_DPORT:
1089 data = pr->dport;
1090 data_m = pr->dport_m;
1091 break;
1092 case TEMPLATE_FIELD_ICMP_IGMP:
1093 data = pr->icmp_igmp;
1094 data_m = pr->icmp_igmp_m;
1095 break;
1096 default:
1097 pr_info("%s: unknown field %d\n", __func__, field_type);
1098 }
1099
1100 /* On the RTL8390, the mask fields are not word aligned! */
1101 if (!(i % 2)) {
1102 r[5 - i / 2] = data;
1103 r[12 - i / 2] |= ((u32)data_m << 8);
1104 } else {
1105 r[5 - i / 2] |= ((u32)data) << 16;
1106 r[12 - i / 2] |= ((u32)data_m) << 24;
1107 r[11 - i / 2] |= ((u32)data_m) >> 8;
1108 }
1109 }
1110 }
1111
1112 /* Creates the intermediate representation of the templated match-fields of the
1113 * PIE rule in the pie_rule structure by reading the raw data fields in the
1114 * raw register space r[].
1115 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1116 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1117 * On the RTL8390 the template mask registers are not word-aligned!
1118 */
1119 void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1120 {
1121 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1122 enum template_field_id field_type = t[i];
1123 u16 data, data_m;
1124
1125 if (!(i % 2)) {
1126 data = r[5 - i / 2];
1127 data_m = r[12 - i / 2];
1128 } else {
1129 data = r[5 - i / 2] >> 16;
1130 data_m = r[12 - i / 2] >> 16;
1131 }
1132
1133 switch (field_type) {
1134 case TEMPLATE_FIELD_SPM0:
1135 pr->spm = (pr->spn << 16) | data;
1136 pr->spm_m = (pr->spn << 16) | data_m;
1137 break;
1138 case TEMPLATE_FIELD_SPM1:
1139 pr->spm = data;
1140 pr->spm_m = data_m;
1141 break;
1142 case TEMPLATE_FIELD_OTAG:
1143 pr->otag = data;
1144 pr->otag_m = data_m;
1145 break;
1146 case TEMPLATE_FIELD_SMAC0:
1147 pr->smac[4] = data >> 8;
1148 pr->smac[5] = data;
1149 pr->smac_m[4] = data >> 8;
1150 pr->smac_m[5] = data;
1151 break;
1152 case TEMPLATE_FIELD_SMAC1:
1153 pr->smac[2] = data >> 8;
1154 pr->smac[3] = data;
1155 pr->smac_m[2] = data >> 8;
1156 pr->smac_m[3] = data;
1157 break;
1158 case TEMPLATE_FIELD_SMAC2:
1159 pr->smac[0] = data >> 8;
1160 pr->smac[1] = data;
1161 pr->smac_m[0] = data >> 8;
1162 pr->smac_m[1] = data;
1163 break;
1164 case TEMPLATE_FIELD_DMAC0:
1165 pr->dmac[4] = data >> 8;
1166 pr->dmac[5] = data;
1167 pr->dmac_m[4] = data >> 8;
1168 pr->dmac_m[5] = data;
1169 break;
1170 case TEMPLATE_FIELD_DMAC1:
1171 pr->dmac[2] = data >> 8;
1172 pr->dmac[3] = data;
1173 pr->dmac_m[2] = data >> 8;
1174 pr->dmac_m[3] = data;
1175 break;
1176 case TEMPLATE_FIELD_DMAC2:
1177 pr->dmac[0] = data >> 8;
1178 pr->dmac[1] = data;
1179 pr->dmac_m[0] = data >> 8;
1180 pr->dmac_m[1] = data;
1181 break;
1182 case TEMPLATE_FIELD_ETHERTYPE:
1183 pr->ethertype = data;
1184 pr->ethertype_m = data_m;
1185 break;
1186 case TEMPLATE_FIELD_ITAG:
1187 pr->itag = data;
1188 pr->itag_m = data_m;
1189 break;
1190 case TEMPLATE_FIELD_SIP0:
1191 pr->sip = data;
1192 pr->sip_m = data_m;
1193 break;
1194 case TEMPLATE_FIELD_SIP1:
1195 pr->sip = (pr->sip << 16) | data;
1196 pr->sip_m = (pr->sip << 16) | data_m;
1197 break;
1198 case TEMPLATE_FIELD_SIP2:
1199 pr->is_ipv6 = true;
1200 /* Make use of limitiations on the position of the match values */
1201 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
1202 r[4 - i / 2], r[3 - i / 2]);
1203 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
1204 r[4 - i / 2], r[3 - i / 2]);
1205 case TEMPLATE_FIELD_SIP3:
1206 case TEMPLATE_FIELD_SIP4:
1207 case TEMPLATE_FIELD_SIP5:
1208 case TEMPLATE_FIELD_SIP6:
1209 case TEMPLATE_FIELD_SIP7:
1210 break;
1211
1212 case TEMPLATE_FIELD_DIP0:
1213 pr->dip = data;
1214 pr->dip_m = data_m;
1215 break;
1216
1217 case TEMPLATE_FIELD_DIP1:
1218 pr->dip = (pr->dip << 16) | data;
1219 pr->dip_m = (pr->dip << 16) | data_m;
1220 break;
1221
1222 case TEMPLATE_FIELD_DIP2:
1223 pr->is_ipv6 = true;
1224 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1225 r[4 - i / 2], r[3 - i / 2]);
1226 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1227 r[4 - i / 2], r[3 - i / 2]);
1228 case TEMPLATE_FIELD_DIP3:
1229 case TEMPLATE_FIELD_DIP4:
1230 case TEMPLATE_FIELD_DIP5:
1231 case TEMPLATE_FIELD_DIP6:
1232 case TEMPLATE_FIELD_DIP7:
1233 break;
1234 case TEMPLATE_FIELD_IP_TOS_PROTO:
1235 pr->tos_proto = data;
1236 pr->tos_proto_m = data_m;
1237 break;
1238 case TEMPLATE_FIELD_L4_SPORT:
1239 pr->sport = data;
1240 pr->sport_m = data_m;
1241 break;
1242 case TEMPLATE_FIELD_L4_DPORT:
1243 pr->dport = data;
1244 pr->dport_m = data_m;
1245 break;
1246 case TEMPLATE_FIELD_ICMP_IGMP:
1247 pr->icmp_igmp = data;
1248 pr->icmp_igmp_m = data_m;
1249 break;
1250 default:
1251 pr_info("%s: unknown field %d\n", __func__, field_type);
1252 }
1253 }
1254 }
1255
1256 static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1257 {
1258 pr->spmmask_fix = (r[6] >> 30) & 0x3;
1259 pr->spn = (r[6] >> 24) & 0x3f;
1260 pr->mgnt_vlan = (r[6] >> 23) & 1;
1261 pr->dmac_hit_sw = (r[6] >> 22) & 1;
1262 pr->not_first_frag = (r[6] >> 21) & 1;
1263 pr->frame_type_l4 = (r[6] >> 18) & 7;
1264 pr->frame_type = (r[6] >> 16) & 3;
1265 pr->otag_fmt = (r[6] >> 15) & 1;
1266 pr->itag_fmt = (r[6] >> 14) & 1;
1267 pr->otag_exist = (r[6] >> 13) & 1;
1268 pr->itag_exist = (r[6] >> 12) & 1;
1269 pr->frame_type_l2 = (r[6] >> 10) & 3;
1270 pr->tid = (r[6] >> 8) & 3;
1271
1272 pr->spmmask_fix_m = (r[12] >> 6) & 0x3;
1273 pr->spn_m = r[12] & 0x3f;
1274 pr->mgnt_vlan_m = (r[13] >> 31) & 1;
1275 pr->dmac_hit_sw_m = (r[13] >> 30) & 1;
1276 pr->not_first_frag_m = (r[13] >> 29) & 1;
1277 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1278 pr->frame_type_m = (r[13] >> 24) & 3;
1279 pr->otag_fmt_m = (r[13] >> 23) & 1;
1280 pr->itag_fmt_m = (r[13] >> 22) & 1;
1281 pr->otag_exist_m = (r[13] >> 21) & 1;
1282 pr->itag_exist_m = (r[13] >> 20) & 1;
1283 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1284 pr->tid_m = (r[13] >> 16) & 3;
1285
1286 pr->valid = r[13] & BIT(15);
1287 pr->cond_not = r[13] & BIT(14);
1288 pr->cond_and1 = r[13] & BIT(13);
1289 pr->cond_and2 = r[13] & BIT(12);
1290 }
1291
1292 static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1293 {
1294 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;
1295 r[6] |= ((u32) (pr->spn & 0x3f)) << 24;
1296 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1297 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1298 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1299 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1300 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1301 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1302 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1303 r[6] |= pr->otag_exist ? BIT(13) : 0;
1304 r[6] |= pr->itag_exist ? BIT(12) : 0;
1305 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1306 r[6] |= ((u32) (pr->tid & 0x3)) << 8;
1307
1308 r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;
1309 r[12] |= (u32) (pr->spn_m & 0x3f);
1310 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1311 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1312 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1313 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1314 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1315 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1316 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1317 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1318 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1319 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1320 r[13] |= ((u32) (pr->tid_m & 0x3)) << 16;
1321
1322 r[13] |= pr->valid ? BIT(15) : 0;
1323 r[13] |= pr->cond_not ? BIT(14) : 0;
1324 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1325 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1326 }
1327
1328 static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr)
1329 {
1330 if (pr->drop) {
1331 r[13] |= 0x9; /* Set ACT_MASK_FWD & FWD_ACT = DROP */
1332 r[13] |= BIT(3);
1333 } else {
1334 r[13] |= pr->fwd_sel ? BIT(3) : 0;
1335 r[13] |= pr->fwd_act;
1336 }
1337 r[13] |= pr->bypass_sel ? BIT(11) : 0;
1338 r[13] |= pr->mpls_sel ? BIT(10) : 0;
1339 r[13] |= pr->nopri_sel ? BIT(9) : 0;
1340 r[13] |= pr->ovid_sel ? BIT(8) : 0;
1341 r[13] |= pr->ivid_sel ? BIT(7) : 0;
1342 r[13] |= pr->meter_sel ? BIT(6) : 0;
1343 r[13] |= pr->mir_sel ? BIT(5) : 0;
1344 r[13] |= pr->log_sel ? BIT(4) : 0;
1345
1346 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18;
1347 r[14] |= pr->log_octets ? BIT(17) : 0;
1348 r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4;
1349 r[14] |= (pr->mir_data & 0x3) << 3;
1350 r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7;
1351 r[15] |= (u32)(pr->meter_data) << 26;
1352 r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3;
1353 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1354 r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3;
1355 r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff;
1356 r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28;
1357 r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20;
1358 r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20;
1359 r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20;
1360 r[16] |= pr->bypass_all ? BIT(9) : 0;
1361 r[16] |= pr->bypass_igr_stp ? BIT(8) : 0;
1362 r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0;
1363 }
1364
1365 static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr)
1366 {
1367 if (r[13] & BIT(3)) { /* ACT_MASK_FWD set, is it a drop? */
1368 if ((r[14] & 0x7) == 1) {
1369 pr->drop = true;
1370 } else {
1371 pr->fwd_sel = true;
1372 pr->fwd_act = r[14] & 0x7;
1373 }
1374 }
1375
1376 pr->bypass_sel = r[13] & BIT(11);
1377 pr->mpls_sel = r[13] & BIT(10);
1378 pr->nopri_sel = r[13] & BIT(9);
1379 pr->ovid_sel = r[13] & BIT(8);
1380 pr->ivid_sel = r[13] & BIT(7);
1381 pr->meter_sel = r[13] & BIT(6);
1382 pr->mir_sel = r[13] & BIT(5);
1383 pr->log_sel = r[13] & BIT(4);
1384
1385 /* TODO: Read in data fields */
1386
1387 pr->bypass_all = r[16] & BIT(9);
1388 pr->bypass_igr_stp = r[16] & BIT(8);
1389 pr->bypass_ibc_sc = r[16] & BIT(7);
1390 }
1391
1392 void rtl839x_pie_rule_dump_raw(u32 r[])
1393 {
1394 pr_info("Raw IACL table entry:\n");
1395 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1396 pr_info("Fixed : %06x\n", r[6] >> 8);
1397 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1398 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1399 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1400 (r[11] << 24) | (r[12] >> 8));
1401 pr_info("R[13]: %08x\n", r[13]);
1402 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1403 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1404 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1405 }
1406
1407 void rtl839x_pie_rule_dump(struct pie_rule *pr)
1408 {
1409 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1410 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1411 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1412 if (pr->fwd_sel)
1413 pr_info("FWD: %08x\n", pr->fwd_data);
1414 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1415 }
1416
1417 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1418 {
1419 /* Read IACL table (2) via register 0 */
1420 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2);
1421 u32 r[17];
1422 int block = idx / PIE_BLOCK_SIZE;
1423 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1424
1425 memset(pr, 0, sizeof(*pr));
1426 rtl_table_read(q, idx);
1427 for (int i = 0; i < 17; i++)
1428 r[i] = sw_r32(rtl_table_data(q, i));
1429
1430 rtl_table_release(q);
1431
1432 rtl839x_read_pie_fixed_fields(r, pr);
1433 if (!pr->valid)
1434 return 0;
1435
1436 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1437 rtl839x_pie_rule_dump_raw(r);
1438
1439 rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1440
1441 rtl839x_read_pie_action(r, pr);
1442
1443 return 0;
1444 }
1445
1446 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1447 {
1448 /* Access IACL table (2) via register 0 */
1449 struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2);
1450 u32 r[17];
1451 int block = idx / PIE_BLOCK_SIZE;
1452 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1453
1454 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1455
1456 for (int i = 0; i < 17; i++)
1457 r[i] = 0;
1458
1459 if (!pr->valid) {
1460 rtl_table_write(q, idx);
1461 rtl_table_release(q);
1462 return 0;
1463 }
1464 rtl839x_write_pie_fixed_fields(r, pr);
1465
1466 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1467 rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1468
1469 rtl839x_write_pie_action(r, pr);
1470
1471 /* rtl839x_pie_rule_dump_raw(r); */
1472
1473 for (int i = 0; i < 17; i++)
1474 sw_w32(r[i], rtl_table_data(q, i));
1475
1476 rtl_table_write(q, idx);
1477 rtl_table_release(q);
1478
1479 return 0;
1480 }
1481
1482 static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)
1483 {
1484 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1485 enum template_field_id ft = fixed_templates[t][i];
1486 if (field_type == ft)
1487 return true;
1488 }
1489
1490 return false;
1491 }
1492
1493 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv,
1494 struct pie_rule *pr, int t, int block)
1495 {
1496 int i;
1497
1498 if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1499 return -1;
1500
1501 if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1502 return -1;
1503
1504 if (pr->is_ipv6) {
1505 if ((pr->sip6_m.s6_addr32[0] ||
1506 pr->sip6_m.s6_addr32[1] ||
1507 pr->sip6_m.s6_addr32[2] ||
1508 pr->sip6_m.s6_addr32[3]) &&
1509 !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1510 return -1;
1511 if ((pr->dip6_m.s6_addr32[0] ||
1512 pr->dip6_m.s6_addr32[1] ||
1513 pr->dip6_m.s6_addr32[2] ||
1514 pr->dip6_m.s6_addr32[3]) &&
1515 !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1516 return -1;
1517 }
1518
1519 if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1520 return -1;
1521
1522 if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1523 return -1;
1524
1525 /* TODO: Check more */
1526
1527 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1528
1529 if (i >= PIE_BLOCK_SIZE)
1530 return -1;
1531
1532 return i + PIE_BLOCK_SIZE * block;
1533 }
1534
1535 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1536 {
1537 int idx, block, j, t;
1538 int min_block = 0;
1539 int max_block = priv->n_pie_blocks / 2;
1540
1541 if (pr->is_egress) {
1542 min_block = max_block;
1543 max_block = priv->n_pie_blocks;
1544 }
1545
1546 mutex_lock(&priv->pie_mutex);
1547
1548 for (block = min_block; block < max_block; block++) {
1549 for (j = 0; j < 2; j++) {
1550 t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1551 idx = rtl839x_pie_verify_template(priv, pr, t, block);
1552 if (idx >= 0)
1553 break;
1554 }
1555 if (j < 2)
1556 break;
1557 }
1558
1559 if (block >= priv->n_pie_blocks) {
1560 mutex_unlock(&priv->pie_mutex);
1561 return -EOPNOTSUPP;
1562 }
1563
1564 set_bit(idx, priv->pie_use_bm);
1565
1566 pr->valid = true;
1567 pr->tid = j; /* Mapped to template number */
1568 pr->tid_m = 0x3;
1569 pr->id = idx;
1570
1571 rtl839x_pie_lookup_enable(priv, idx);
1572 rtl839x_pie_rule_write(priv, idx, pr);
1573
1574 mutex_unlock(&priv->pie_mutex);
1575
1576 return 0;
1577 }
1578
1579 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1580 {
1581 int idx = pr->id;
1582
1583 rtl839x_pie_rule_del(priv, idx, idx);
1584 clear_bit(idx, priv->pie_use_bm);
1585 }
1586
1587 static void rtl839x_pie_init(struct rtl838x_switch_priv *priv)
1588 {
1589 u32 template_selectors;
1590
1591 mutex_init(&priv->pie_mutex);
1592
1593 /* Power on all PIE blocks */
1594 for (int i = 0; i < priv->n_pie_blocks; i++)
1595 sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL);
1596
1597 /* Set ingress and egress ACL blocks to 50/50: first Egress block is 9 */
1598 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); /* Writes 9 to cutline field */
1599
1600 /* Include IPG in metering */
1601 sw_w32(1, RTL839X_METER_GLB_CTRL);
1602
1603 /* Delete all present rules */
1604 rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1605
1606 /* Enable predefined templates 0, 1 for blocks 0-2 */
1607 template_selectors = 0 | (1 << 3);
1608 for (int i = 0; i < 3; i++)
1609 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1610
1611 /* Enable predefined templates 2, 3 for blocks 3-5 */
1612 template_selectors = 2 | (3 << 3);
1613 for (int i = 3; i < 6; i++)
1614 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1615
1616 /* Enable predefined templates 1, 4 for blocks 6-8 */
1617 template_selectors = 2 | (3 << 3);
1618 for (int i = 6; i < 9; i++)
1619 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1620
1621 /* Enable predefined templates 0, 1 for blocks 9-11 */
1622 template_selectors = 0 | (1 << 3);
1623 for (int i = 9; i < 12; i++)
1624 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1625
1626 /* Enable predefined templates 2, 3 for blocks 12-14 */
1627 template_selectors = 2 | (3 << 3);
1628 for (int i = 12; i < 15; i++)
1629 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1630
1631 /* Enable predefined templates 1, 4 for blocks 15-17 */
1632 template_selectors = 2 | (3 << 3);
1633 for (int i = 15; i < 18; i++)
1634 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1635 }
1636
1637 static u32 rtl839x_packet_cntr_read(int counter)
1638 {
1639 u32 v;
1640
1641 /* Read LOG table (4) via register RTL8390_TBL_0 */
1642 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1643
1644 pr_debug("In %s, id %d\n", __func__, counter);
1645 rtl_table_read(r, counter / 2);
1646
1647 /* The table has a size of 2 registers */
1648 if (counter % 2)
1649 v = sw_r32(rtl_table_data(r, 0));
1650 else
1651 v = sw_r32(rtl_table_data(r, 1));
1652
1653 rtl_table_release(r);
1654
1655 return v;
1656 }
1657
1658 static void rtl839x_packet_cntr_clear(int counter)
1659 {
1660 /* Access LOG table (4) via register RTL8390_TBL_0 */
1661 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1662
1663 pr_debug("In %s, id %d\n", __func__, counter);
1664 /* The table has a size of 2 registers */
1665 if (counter % 2)
1666 sw_w32(0, rtl_table_data(r, 0));
1667 else
1668 sw_w32(0, rtl_table_data(r, 1));
1669
1670 rtl_table_write(r, counter / 2);
1671
1672 rtl_table_release(r);
1673 }
1674
1675 static void rtl839x_route_read(int idx, struct rtl83xx_route *rt)
1676 {
1677 u64 v;
1678 /* Read ROUTING table (2) via register RTL8390_TBL_1 */
1679 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1680
1681 pr_debug("In %s\n", __func__);
1682 rtl_table_read(r, idx);
1683
1684 /* The table has a size of 2 registers */
1685 v = sw_r32(rtl_table_data(r, 0));
1686 v <<= 32;
1687 v |= sw_r32(rtl_table_data(r, 1));
1688 rt->switch_mac_id = (v >> 12) & 0xf;
1689 rt->nh.gw = v >> 16;
1690
1691 rtl_table_release(r);
1692 }
1693
1694 static void rtl839x_route_write(int idx, struct rtl83xx_route *rt)
1695 {
1696 u32 v;
1697
1698 /* Read ROUTING table (2) via register RTL8390_TBL_1 */
1699 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1700
1701 pr_debug("In %s\n", __func__);
1702 sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0));
1703 v = rt->nh.gw << 16;
1704 v |= rt->switch_mac_id << 12;
1705 sw_w32(v, rtl_table_data(r, 1));
1706 rtl_table_write(r, idx);
1707
1708 rtl_table_release(r);
1709 }
1710
1711 /* Configure the switch's own MAC addresses used when routing packets */
1712 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)
1713 {
1714 struct net_device *dev;
1715 u64 mac;
1716
1717 pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp);
1718 dev = priv->ports[priv->cpu_port].dp->slave;
1719 mac = ether_addr_to_u64(dev->dev_addr);
1720
1721 for (int i = 0; i < 15; i++) {
1722 mac++; /* BUG: VRRP for testing */
1723 sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8);
1724 sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4);
1725 }
1726 }
1727
1728 int rtl839x_l3_setup(struct rtl838x_switch_priv *priv)
1729 {
1730 rtl839x_setup_port_macs(priv);
1731
1732 return 0;
1733 }
1734
1735 void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1736 {
1737 sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK,
1738 keep_outer ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG) |
1739 FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK,
1740 keep_inner ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG),
1741 RTL839X_VLAN_PORT_TAG_STS_CTRL(port));
1742 }
1743
1744 void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1745 {
1746 if (type == PBVLAN_TYPE_INNER)
1747 sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1748 else
1749 sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1750 }
1751
1752 void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1753 {
1754 if (type == PBVLAN_TYPE_INNER)
1755 sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1756 else
1757 sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1758 }
1759
1760 static int rtl839x_set_ageing_time(unsigned long msec)
1761 {
1762 int t = sw_r32(RTL839X_L2_CTRL_1);
1763
1764 t &= 0x1FFFFF;
1765 t = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1766 pr_debug("L2 AGING time: %d sec\n", t);
1767
1768 t = (msec * 5 + 2000) / 3000;
1769 t = t > 0x1FFFFF ? 0x1FFFFF : t;
1770 sw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1);
1771 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT));
1772
1773 return 0;
1774 }
1775
1776 static void rtl839x_set_igr_filter(int port, enum igr_filter state)
1777 {
1778 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1779 RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1780 }
1781
1782 static void rtl839x_set_egr_filter(int port, enum egr_filter state)
1783 {
1784 sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
1785 RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
1786 }
1787
1788 void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1789 {
1790 sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1),
1791 RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2));
1792 sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2));
1793 }
1794
1795 void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1796 {
1797 switch(type) {
1798 case BPDU:
1799 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1800 RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1801 break;
1802 case PTP:
1803 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1804 RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
1805 break;
1806 case LLTP:
1807 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1808 RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1809 break;
1810 default:
1811 break;
1812 }
1813 }
1814
1815 const struct rtl838x_reg rtl839x_reg = {
1816 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1817 .set_port_reg_be = rtl839x_set_port_reg_be,
1818 .get_port_reg_be = rtl839x_get_port_reg_be,
1819 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1820 .set_port_reg_le = rtl839x_set_port_reg_le,
1821 .get_port_reg_le = rtl839x_get_port_reg_le,
1822 .stat_port_rst = RTL839X_STAT_PORT_RST,
1823 .stat_rst = RTL839X_STAT_RST,
1824 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
1825 .traffic_enable = rtl839x_traffic_enable,
1826 .traffic_disable = rtl839x_traffic_disable,
1827 .traffic_get = rtl839x_traffic_get,
1828 .traffic_set = rtl839x_traffic_set,
1829 .port_iso_ctrl = rtl839x_port_iso_ctrl,
1830 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
1831 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
1832 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
1833 .set_ageing_time = rtl839x_set_ageing_time,
1834 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
1835 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
1836 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
1837 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
1838 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
1839 .isr_glb_src = RTL839X_ISR_GLB_SRC,
1840 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
1841 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
1842 .imr_glb = RTL839X_IMR_GLB,
1843 .vlan_tables_read = rtl839x_vlan_tables_read,
1844 .vlan_set_tagged = rtl839x_vlan_set_tagged,
1845 .vlan_set_untagged = rtl839x_vlan_set_untagged,
1846 .vlan_profile_dump = rtl839x_vlan_profile_dump,
1847 .vlan_profile_setup = rtl839x_vlan_profile_setup,
1848 .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
1849 .vlan_port_keep_tag_set = rtl839x_vlan_port_keep_tag_set,
1850 .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set,
1851 .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set,
1852 .set_vlan_igr_filter = rtl839x_set_igr_filter,
1853 .set_vlan_egr_filter = rtl839x_set_egr_filter,
1854 .enable_learning = rtl839x_enable_learning,
1855 .enable_flood = rtl839x_enable_flood,
1856 .enable_mcast_flood = rtl839x_enable_mcast_flood,
1857 .enable_bcast_flood = rtl839x_enable_bcast_flood,
1858 .stp_get = rtl839x_stp_get,
1859 .stp_set = rtl839x_stp_set,
1860 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
1861 .mac_port_ctrl = rtl839x_mac_port_ctrl,
1862 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
1863 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
1864 .mir_ctrl = RTL839X_MIR_CTRL,
1865 .mir_dpm = RTL839X_MIR_DPM_CTRL,
1866 .mir_spm = RTL839X_MIR_SPM_CTRL,
1867 .mac_link_sts = RTL839X_MAC_LINK_STS,
1868 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
1869 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
1870 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
1871 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
1872 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
1873 .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,
1874 .read_cam = rtl839x_read_cam,
1875 .write_cam = rtl839x_write_cam,
1876 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
1877 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
1878 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
1879 .init_eee = rtl839x_init_eee,
1880 .port_eee_set = rtl839x_port_eee_set,
1881 .eee_port_ability = rtl839x_eee_port_ability,
1882 .l2_hash_seed = rtl839x_l2_hash_seed,
1883 .l2_hash_key = rtl839x_l2_hash_key,
1884 .read_mcast_pmask = rtl839x_read_mcast_pmask,
1885 .write_mcast_pmask = rtl839x_write_mcast_pmask,
1886 .pie_init = rtl839x_pie_init,
1887 .pie_rule_read = rtl839x_pie_rule_read,
1888 .pie_rule_write = rtl839x_pie_rule_write,
1889 .pie_rule_add = rtl839x_pie_rule_add,
1890 .pie_rule_rm = rtl839x_pie_rule_rm,
1891 .l2_learning_setup = rtl839x_l2_learning_setup,
1892 .packet_cntr_read = rtl839x_packet_cntr_read,
1893 .packet_cntr_clear = rtl839x_packet_cntr_clear,
1894 .route_read = rtl839x_route_read,
1895 .route_write = rtl839x_route_write,
1896 .l3_setup = rtl839x_l3_setup,
1897 .set_distribution_algorithm = rtl839x_set_distribution_algorithm,
1898 .set_receive_management_action = rtl839x_set_receive_management_action,
1899 };
Staging tree of dedeckeh