1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef _NET_DSA_RTL83XX_H
4 #define _NET_DSA_RTL83XX_H
10 #define RTL8380_VERSION_A 'A'
11 #define RTL8390_VERSION_A 'A'
12 #define RTL8380_VERSION_B 'B'
14 struct fdb_update_work
{
15 struct work_struct work
;
16 struct net_device
*ndev
;
20 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
21 struct rtl83xx_mib_desc
{
27 /* API for switch table access */
39 #define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \
40 { .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \
41 .t_bit = _t_bit, .rmode = _rmode \
67 void rtl_table_init(void);
68 struct table_reg
*rtl_table_get(rtl838x_tbl_reg_t r
, int t
);
69 void rtl_table_release(struct table_reg
*r
);
70 int rtl_table_read(struct table_reg
*r
, int idx
);
71 int rtl_table_write(struct table_reg
*r
, int idx
);
72 inline u16
rtl_table_data(struct table_reg
*r
, int i
);
73 inline u32
rtl_table_data_r(struct table_reg
*r
, int i
);
74 inline void rtl_table_data_w(struct table_reg
*r
, u32 v
, int i
);
76 void __init
rtl83xx_setup_qos(struct rtl838x_switch_priv
*priv
);
78 int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv
*priv
);
80 int rtl83xx_port_is_under(const struct net_device
* dev
, struct rtl838x_switch_priv
*priv
);
82 int read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
);
83 int write_phy(u32 port
, u32 page
, u32 reg
, u32 val
);
85 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
86 void rtl839x_mask_port_reg_be(u64 clear
, u64 set
, int reg
);
87 u64
rtl839x_get_port_reg_be(int reg
);
88 void rtl839x_set_port_reg_be(u64 set
, int reg
);
89 void rtl839x_mask_port_reg_le(u64 clear
, u64 set
, int reg
);
90 void rtl839x_set_port_reg_le(u64 set
, int reg
);
91 u64
rtl839x_get_port_reg_le(int reg
);
93 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
94 void rtl838x_mask_port_reg(u64 clear
, u64 set
, int reg
);
95 void rtl838x_set_port_reg(u64 set
, int reg
);
96 u64
rtl838x_get_port_reg(int reg
);
98 /* RTL838x-specific */
99 u32
rtl838x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
);
100 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
);
101 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
);
102 void rtl838x_vlan_profile_dump(int index
);
103 int rtl83xx_dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
);
104 void rtl8380_sds_rst(int mac
);
105 int rtl8380_sds_power(int mac
, int val
);
106 void rtl838x_print_matrix(void);
108 /* RTL839x-specific */
109 u32
rtl839x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
);
110 irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
);
111 void rtl8390_get_version(struct rtl838x_switch_priv
*priv
);
112 void rtl839x_vlan_profile_dump(int index
);
113 int rtl83xx_dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
);
114 void rtl839x_exec_tbl2_cmd(u32 cmd
);
115 void rtl839x_print_matrix(void);
117 /* RTL930x-specific */
118 u32
rtl930x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
);
119 irqreturn_t
rtl930x_switch_irq(int irq
, void *dev_id
);
120 irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
);
121 void rtl930x_vlan_profile_dump(int index
);
122 int rtl9300_sds_power(int mac
, int val
);
123 void rtl9300_sds_rst(int sds_num
, u32 mode
);
124 int rtl9300_serdes_setup(int sds_num
, phy_interface_t phy_mode
);
125 void rtl930x_print_matrix(void);
127 /* RTL931x-specific */
128 irqreturn_t
rtl931x_switch_irq(int irq
, void *dev_id
);
129 int rtl931x_sds_cmu_band_get(int sds
, phy_interface_t mode
);
130 int rtl931x_sds_cmu_band_set(int sds
, bool enable
, u32 band
, phy_interface_t mode
);
131 void rtl931x_sds_init(u32 sds
, phy_interface_t mode
);
133 int rtl83xx_lag_add(struct dsa_switch
*ds
, int group
, int port
, struct netdev_lag_upper_info
*info
);
134 int rtl83xx_lag_del(struct dsa_switch
*ds
, int group
, int port
);
136 #endif /* _NET_DSA_RTL83XX_H */