1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/inetdevice.h>
8 #define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0
9 #define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1
10 #define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2
11 #define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
13 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24
15 #define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \
16 RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
17 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7,6)
18 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5,4)
19 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
20 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
21 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
22 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
24 extern struct mutex smi_lock
;
25 extern struct rtl83xx_soc_info soc_info
;
27 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
28 enum template_field_id
{
29 TEMPLATE_FIELD_SPM0
= 0, /* Source portmask ports 0-15 */
30 TEMPLATE_FIELD_SPM1
= 1, /* Source portmask ports 16-31 */
31 TEMPLATE_FIELD_DMAC0
= 2, /* Destination MAC [15:0] */
32 TEMPLATE_FIELD_DMAC1
= 3, /* Destination MAC [31:16] */
33 TEMPLATE_FIELD_DMAC2
= 4, /* Destination MAC [47:32] */
34 TEMPLATE_FIELD_SMAC0
= 5, /* Source MAC [15:0] */
35 TEMPLATE_FIELD_SMAC1
= 6, /* Source MAC [31:16] */
36 TEMPLATE_FIELD_SMAC2
= 7, /* Source MAC [47:32] */
37 TEMPLATE_FIELD_ETHERTYPE
= 8, /* Ethernet frame type field */
38 TEMPLATE_FIELD_OTAG
= 9,
39 TEMPLATE_FIELD_ITAG
= 10,
40 TEMPLATE_FIELD_SIP0
= 11,
41 TEMPLATE_FIELD_SIP1
= 12,
42 TEMPLATE_FIELD_DIP0
= 13,
43 TEMPLATE_FIELD_DIP1
= 14,
44 TEMPLATE_FIELD_IP_TOS_PROTO
= 15,
45 TEMPLATE_FIELD_L4_SPORT
= 16,
46 TEMPLATE_FIELD_L4_DPORT
= 17,
47 TEMPLATE_FIELD_L34_HEADER
= 18,
48 TEMPLATE_FIELD_TCP_INFO
= 19,
49 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 20,
50 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 21,
51 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 22,
52 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 23,
53 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 24,
54 TEMPLATE_FIELD_FIELD_SELECTOR_4
= 25,
55 TEMPLATE_FIELD_FIELD_SELECTOR_5
= 26,
56 TEMPLATE_FIELD_SIP2
= 27,
57 TEMPLATE_FIELD_SIP3
= 28,
58 TEMPLATE_FIELD_SIP4
= 29,
59 TEMPLATE_FIELD_SIP5
= 30,
60 TEMPLATE_FIELD_SIP6
= 31,
61 TEMPLATE_FIELD_SIP7
= 32,
62 TEMPLATE_FIELD_DIP2
= 33,
63 TEMPLATE_FIELD_DIP3
= 34,
64 TEMPLATE_FIELD_DIP4
= 35,
65 TEMPLATE_FIELD_DIP5
= 36,
66 TEMPLATE_FIELD_DIP6
= 37,
67 TEMPLATE_FIELD_DIP7
= 38,
68 TEMPLATE_FIELD_PKT_INFO
= 39,
69 TEMPLATE_FIELD_FLOW_LABEL
= 40,
70 TEMPLATE_FIELD_DSAP_SSAP
= 41,
71 TEMPLATE_FIELD_SNAP_OUI
= 42,
72 TEMPLATE_FIELD_FWD_VID
= 43,
73 TEMPLATE_FIELD_RANGE_CHK
= 44,
74 TEMPLATE_FIELD_VLAN_GMSK
= 45, /* VLAN Group Mask/IP range check */
75 TEMPLATE_FIELD_DLP
= 46,
76 TEMPLATE_FIELD_META_DATA
= 47,
77 TEMPLATE_FIELD_SRC_FWD_VID
= 48,
78 TEMPLATE_FIELD_SLP
= 49,
81 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
82 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
84 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
86 /* Number of fixed templates predefined in the RTL9300 SoC */
87 #define N_FIXED_TEMPLATES 5
88 /* RTL9300 specific predefined templates */
89 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
92 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
93 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
94 TEMPLATE_FIELD_VLAN
, TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_DSAP_SSAP
,
95 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
97 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
98 TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_TCP_INFO
,
99 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_VLAN
,
100 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
102 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
103 TEMPLATE_FIELD_VLAN
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
104 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
105 TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_L4_DPORT
107 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
108 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
109 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_IP_TOS_PROTO
,
110 TEMPLATE_FIELD_TCP_INFO
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_L4_DPORT
112 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
113 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
114 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_VLAN
,
115 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM1
119 void rtl930x_print_matrix(void)
121 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 6);
123 for (int i
= 0; i
< 29; i
++) {
124 rtl_table_read(r
, i
);
125 pr_debug("> %08x\n", sw_r32(rtl_table_data(r
, 0)));
127 rtl_table_release(r
);
130 inline void rtl930x_exec_tbl0_cmd(u32 cmd
)
132 sw_w32(cmd
, RTL930X_TBL_ACCESS_CTRL_0
);
133 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0
) & (1 << 17));
136 inline void rtl930x_exec_tbl1_cmd(u32 cmd
)
138 sw_w32(cmd
, RTL930X_TBL_ACCESS_CTRL_1
);
139 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1
) & (1 << 17));
142 inline int rtl930x_tbl_access_data_0(int i
)
144 return RTL930X_TBL_ACCESS_DATA_0(i
);
147 static inline int rtl930x_l2_port_new_salrn(int p
)
149 return RTL930X_L2_PORT_SALRN(p
);
152 static inline int rtl930x_l2_port_new_sa_fwd(int p
)
154 /* TODO: The definition of the fields changed, because of the master-cpu in a stack */
155 return RTL930X_L2_PORT_NEW_SA_FWD(p
);
158 inline static int rtl930x_trk_mbr_ctr(int group
)
160 return RTL930X_TRK_MBR_CTRL
+ (group
<< 2);
163 static void rtl930x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
166 /* Read VLAN table (1) via register 0 */
167 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 1);
169 rtl_table_read(r
, vlan
);
170 v
= sw_r32(rtl_table_data(r
, 0));
171 w
= sw_r32(rtl_table_data(r
, 1));
172 pr_debug("VLAN_READ %d: %08x %08x\n", vlan
, v
, w
);
173 rtl_table_release(r
);
175 info
->tagged_ports
= v
>> 3;
176 info
->profile_id
= (w
>> 24) & 7;
177 info
->hash_mc_fid
= !!(w
& BIT(27));
178 info
->hash_uc_fid
= !!(w
& BIT(28));
179 info
->fid
= ((v
& 0x7) << 3) | ((w
>> 29) & 0x7);
181 /* Read UNTAG table via table register 2 */
182 r
= rtl_table_get(RTL9300_TBL_2
, 0);
183 rtl_table_read(r
, vlan
);
184 v
= sw_r32(rtl_table_data(r
, 0));
185 rtl_table_release(r
);
187 info
->untagged_ports
= v
>> 3;
190 static void rtl930x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
193 /* Access VLAN table (1) via register 0 */
194 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 1);
196 v
= info
->tagged_ports
<< 3;
197 v
|= ((u32
)info
->fid
) >> 3;
199 w
= ((u32
)info
->fid
) << 29;
200 w
|= info
->hash_mc_fid
? BIT(27) : 0;
201 w
|= info
->hash_uc_fid
? BIT(28) : 0;
202 w
|= info
->profile_id
<< 24;
204 sw_w32(v
, rtl_table_data(r
, 0));
205 sw_w32(w
, rtl_table_data(r
, 1));
207 rtl_table_write(r
, vlan
);
208 rtl_table_release(r
);
211 void rtl930x_vlan_profile_dump(int profile
)
215 if (profile
< 0 || profile
> 7)
218 p
[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
));
219 p
[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
) + 4);
220 p
[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
) + 8) & 0x1FFFFFFF;
221 p
[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
) + 12) & 0x1FFFFFFF;
222 p
[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
) + 16) & 0x1FFFFFFF;
224 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
225 profile
, p
[0] & (3 << 21), p
[2], p
[3], p
[4]);
226 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
227 p
[0] & BIT(17) ? 'y' : 'n', p
[0] & BIT(16) ? 'y' : 'n',
228 p
[0] & BIT(13) ? 'y' : 'n', p
[0] & BIT(12) ? 'y' : 'n');
229 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
230 p
[0] & BIT(15) ? 'y' : 'n', p
[0] & BIT(14) ? 'y' : 'n');
231 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
232 profile
, p
[0], p
[1], p
[2], p
[3], p
[4]);
235 static void rtl930x_vlan_set_untagged(u32 vlan
, u64 portmask
)
237 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_2
, 0);
239 sw_w32(portmask
<< 3, rtl_table_data(r
, 0));
240 rtl_table_write(r
, vlan
);
241 rtl_table_release(r
);
244 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
245 static void rtl930x_vlan_fwd_on_inner(int port
, bool is_set
)
247 /* Always set all tag modes to fwd based on either inner or outer tag */
249 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD
+ (port
<< 2));
251 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD
+ (port
<< 2));
254 static void rtl930x_vlan_profile_setup(int profile
)
258 pr_info("In %s\n", __func__
);
259 p
[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
));
260 p
[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile
) + 4);
262 /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */
263 p
[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
264 p
[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */
265 p
[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */
266 p
[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */
268 sw_w32(p
[0], RTL930X_VLAN_PROFILE_SET(profile
));
269 sw_w32(p
[1], RTL930X_VLAN_PROFILE_SET(profile
) + 4);
270 sw_w32(p
[2], RTL930X_VLAN_PROFILE_SET(profile
) + 8);
271 sw_w32(p
[3], RTL930X_VLAN_PROFILE_SET(profile
) + 12);
272 sw_w32(p
[4], RTL930X_VLAN_PROFILE_SET(profile
) + 16);
275 static void rtl930x_l2_learning_setup(void)
277 /* Portmask for flooding broadcast traffic */
278 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK
);
280 /* Portmask for flooding unicast traffic with unknown destination */
281 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK
);
283 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
284 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL
);
287 static void rtl930x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
289 u32 cmd
= 1 << 17 | /* Execute cmd */
291 4 << 12 | /* Table type 0b10 */
293 priv
->r
->exec_tbl0_cmd(cmd
);
295 for (int i
= 0; i
< 2; i
++)
296 port_state
[i
] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i
));
297 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti
, port_state
[0], port_state
[1]);
300 static void rtl930x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
302 u32 cmd
= 1 << 17 | /* Execute cmd */
303 1 << 16 | /* Write */
304 4 << 12 | /* Table type 4 */
307 for (int i
= 0; i
< 2; i
++)
308 sw_w32(port_state
[i
], RTL930X_TBL_ACCESS_DATA_0(i
));
309 priv
->r
->exec_tbl0_cmd(cmd
);
312 static inline int rtl930x_mac_force_mode_ctrl(int p
)
314 return RTL930X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
317 static inline int rtl930x_mac_port_ctrl(int p
)
319 return RTL930X_MAC_L2_PORT_CTRL(p
);
322 static inline int rtl930x_mac_link_spd_sts(int p
)
324 return RTL930X_MAC_LINK_SPD_STS(p
);
327 static u64
rtl930x_l2_hash_seed(u64 mac
, u32 vid
)
337 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
338 * algorithm as the one used currently by the ASIC to the seed, and return
339 * both hashes in the lower and higher word of the return value since only 12 bit of
340 * the hash are significant
342 static u32
rtl930x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
344 u32 k0
, k1
, h1
, h2
, h
;
346 k0
= (u32
) (((seed
>> 55) & 0x1f) ^
347 ((seed
>> 44) & 0x7ff) ^
348 ((seed
>> 33) & 0x7ff) ^
349 ((seed
>> 22) & 0x7ff) ^
350 ((seed
>> 11) & 0x7ff) ^
353 h1
= (seed
>> 11) & 0x7ff;
354 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
356 h2
= (seed
>> 33) & 0x7ff;
357 h2
= ((h2
& 0x3f) << 5)| ((h2
>> 6) & 0x3f);
359 k1
= (u32
) (((seed
<< 55) & 0x1f) ^
360 ((seed
>> 44) & 0x7ff) ^
362 ((seed
>> 22) & 0x7ff) ^
366 /* Algorithm choice for block 0 */
367 if (sw_r32(RTL930X_L2_CTRL
) & BIT(0))
372 /* Algorithm choice for block 1
373 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
375 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
376 * divided by 2 to divide the hash space in 2
378 if (sw_r32(RTL930X_L2_CTRL
) & BIT(1))
379 h
|= (k1
+ 2048) << 16;
381 h
|= (k0
+ 2048) << 16;
386 /* Fills an L2 entry structure from the SoC registers */
387 static void rtl930x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
389 pr_debug("In %s valid?\n", __func__
);
390 e
->valid
= !!(r
[2] & BIT(31));
394 pr_debug("In %s is valid\n", __func__
);
396 e
->is_ipv6_mc
= false;
398 /* TODO: Is there not a function to copy directly MAC memory? */
399 e
->mac
[0] = (r
[0] >> 24);
400 e
->mac
[1] = (r
[0] >> 16);
401 e
->mac
[2] = (r
[0] >> 8);
403 e
->mac
[4] = (r
[1] >> 24);
404 e
->mac
[5] = (r
[1] >> 16);
406 e
->next_hop
= !!(r
[2] & BIT(12));
407 e
->rvid
= r
[1] & 0xfff;
409 /* Is it a unicast entry? check multicast bit */
410 if (!(e
->mac
[0] & 1)) {
411 e
->type
= L2_UNICAST
;
412 e
->is_static
= !!(r
[2] & BIT(14));
413 e
->port
= (r
[2] >> 20) & 0x3ff;
414 /* Check for trunk port */
415 if (r
[2] & BIT(30)) {
417 e
->stack_dev
= (e
->port
>> 9) & 1;
418 e
->trunk
= e
->port
& 0x3f;
421 e
->stack_dev
= (e
->port
>> 6) & 0xf;
422 e
->port
= e
->port
& 0x3f;
425 e
->block_da
= !!(r
[2] & BIT(15));
426 e
->block_sa
= !!(r
[2] & BIT(16));
427 e
->suspended
= !!(r
[2] & BIT(13));
428 e
->age
= (r
[2] >> 17) & 3;
430 /* the UC_VID field in hardware is used for the VID or for the route id */
432 e
->nh_route_id
= r
[2] & 0x7ff;
435 e
->vid
= r
[2] & 0xfff;
440 e
->type
= L2_MULTICAST
;
441 e
->mc_portmask_index
= (r
[2] >> 16) & 0x3ff;
445 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
446 static void rtl930x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
451 r
[0] = r
[1] = r
[2] = 0;
455 r
[2] = BIT(31); /* Set valid bit */
457 r
[0] = ((u32
)e
->mac
[0]) << 24 |
458 ((u32
)e
->mac
[1]) << 16 |
459 ((u32
)e
->mac
[2]) << 8 |
461 r
[1] = ((u32
)e
->mac
[4]) << 24 |
462 ((u32
)e
->mac
[5]) << 16;
464 r
[2] |= e
->next_hop
? BIT(12) : 0;
466 if (e
->type
== L2_UNICAST
) {
467 r
[2] |= e
->is_static
? BIT(14) : 0;
468 r
[1] |= e
->rvid
& 0xfff;
469 r
[2] |= (e
->port
& 0x3ff) << 20;
472 port
= e
->stack_dev
<< 9 | (e
->port
& 0x3f);
474 port
= (e
->stack_dev
& 0xf) << 6;
475 port
|= e
->port
& 0x3f;
478 r
[2] |= e
->block_da
? BIT(15) : 0;
479 r
[2] |= e
->block_sa
? BIT(17) : 0;
480 r
[2] |= e
->suspended
? BIT(13) : 0;
481 r
[2] |= (e
->age
& 0x3) << 17;
482 /* the UC_VID field in hardware is used for the VID or for the route id */
484 r
[2] |= e
->nh_route_id
& 0x7ff;
486 r
[2] |= e
->vid
& 0xfff;
487 } else { /* L2_MULTICAST */
488 r
[2] |= (e
->mc_portmask_index
& 0x3ff) << 16;
489 r
[2] |= e
->mc_mac_index
& 0x7ff;
493 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
494 * hash is the id of the bucket and pos is the position of the entry in that bucket
495 * The data read from the SoC is filled into rtl838x_l2_entry
497 static u64
rtl930x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
500 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_L2
, 0);
505 pr_debug("%s: hash %08x, pos: %d\n", __func__
, hash
, pos
);
507 /* On the RTL93xx, 2 different hash algorithms are used making it a
508 * total of 8 buckets that need to be searched, 4 for each hash-half
509 * Use second hash space when bucket is between 4 and 8
518 idx
= (0 << 14) | (hash
<< 2) | pos
; /* Search SRAM, with hash and at pos in bucket */
519 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__
, hash
, pos
);
521 rtl_table_read(q
, idx
);
522 for (int i
= 0; i
< 3; i
++)
523 r
[i
] = sw_r32(rtl_table_data(q
, i
));
525 rtl_table_release(q
);
527 rtl930x_fill_l2_entry(r
, e
);
529 pr_debug("%s: valid: %d, nh: %d\n", __func__
, e
->valid
, e
->next_hop
);
533 mac
= ((u64
)e
->mac
[0]) << 40 |
534 ((u64
)e
->mac
[1]) << 32 |
535 ((u64
)e
->mac
[2]) << 24 |
536 ((u64
)e
->mac
[3]) << 16 |
537 ((u64
)e
->mac
[4]) << 8 |
540 seed
= rtl930x_l2_hash_seed(mac
, e
->rvid
);
541 pr_debug("%s: mac %016llx, seed %016llx\n", __func__
, mac
, seed
);
543 /* return vid with concatenated mac as unique id */
547 static void rtl930x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
550 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_L2
, 0);
551 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; /* Access SRAM, with hash and at pos in bucket */
553 pr_debug("%s: hash %d, pos %d\n", __func__
, hash
, pos
);
554 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__
, idx
,
555 e
->mac
[0], e
->mac
[1], e
->mac
[2], e
->mac
[3],e
->mac
[4],e
->mac
[5]);
557 rtl930x_fill_l2_row(r
, e
);
559 for (int i
= 0; i
< 3; i
++)
560 sw_w32(r
[i
], rtl_table_data(q
, i
));
562 rtl_table_write(q
, idx
);
563 rtl_table_release(q
);
566 static u64
rtl930x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
569 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_L2
, 1);
571 rtl_table_read(q
, idx
);
572 for (int i
= 0; i
< 3; i
++)
573 r
[i
] = sw_r32(rtl_table_data(q
, i
));
575 rtl_table_release(q
);
577 rtl930x_fill_l2_entry(r
, e
);
581 /* return mac with concatenated vid as unique id */
582 return ((u64
)r
[0] << 28) | ((r
[1] & 0xffff0000) >> 4) | e
->vid
;
585 static void rtl930x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
588 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_L2
, 1); /* Access L2 Table 1 */
590 rtl930x_fill_l2_row(r
, e
);
592 for (int i
= 0; i
< 3; i
++)
593 sw_w32(r
[i
], rtl_table_data(q
, i
));
595 rtl_table_write(q
, idx
);
596 rtl_table_release(q
);
599 static u64
rtl930x_read_mcast_pmask(int idx
)
602 /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */
603 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_L2
, 2);
605 rtl_table_read(q
, idx
);
606 portmask
= sw_r32(rtl_table_data(q
, 0));
608 rtl_table_release(q
);
610 pr_debug("%s: Index idx %d has portmask %08x\n", __func__
, idx
, portmask
);
615 static void rtl930x_write_mcast_pmask(int idx
, u64 portmask
)
619 /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */
620 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_L2
, 2);
622 pr_debug("%s: Index idx %d has portmask %08x\n", __func__
, idx
, pm
);
624 sw_w32(pm
, rtl_table_data(q
, 0));
625 rtl_table_write(q
, idx
);
626 rtl_table_release(q
);
629 u64
rtl930x_traffic_get(int source
)
632 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 6);
634 rtl_table_read(r
, source
);
635 v
= sw_r32(rtl_table_data(r
, 0));
636 rtl_table_release(r
);
642 /* Enable traffic between a source port and a destination port matrix */
643 void rtl930x_traffic_set(int source
, u64 dest_matrix
)
645 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 6);
647 sw_w32((dest_matrix
<< 3), rtl_table_data(r
, 0));
648 rtl_table_write(r
, source
);
649 rtl_table_release(r
);
652 void rtl930x_traffic_enable(int source
, int dest
)
654 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 6);
655 rtl_table_read(r
, source
);
656 sw_w32_mask(0, BIT(dest
+ 3), rtl_table_data(r
, 0));
657 rtl_table_write(r
, source
);
658 rtl_table_release(r
);
661 void rtl930x_traffic_disable(int source
, int dest
)
663 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 6);
664 rtl_table_read(r
, source
);
665 sw_w32_mask(BIT(dest
+ 3), 0, rtl_table_data(r
, 0));
666 rtl_table_write(r
, source
);
667 rtl_table_release(r
);
670 void rtl9300_dump_debug(void)
672 u16 r
= RTL930X_STAT_PRVTE_DROP_COUNTER0
;
674 for (int i
= 0; i
< 10; i
++) {
675 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i
* 8,
676 sw_r32(r
), sw_r32(r
+ 4), sw_r32(r
+ 8), sw_r32(r
+ 12),
677 sw_r32(r
+ 16), sw_r32(r
+ 20), sw_r32(r
+ 24), sw_r32(r
+ 28));
680 pr_info("# %08x %08x %08x %08x %08x\n",
681 sw_r32(r
), sw_r32(r
+ 4), sw_r32(r
+ 8), sw_r32(r
+ 12), sw_r32(r
+ 16));
682 rtl930x_print_matrix();
683 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
684 sw_r32(RTL930X_L2_PORT_SABLK_CTRL
), sw_r32(RTL930X_L2_PORT_DABLK_CTRL
)
689 irqreturn_t
rtl930x_switch_irq(int irq
, void *dev_id
)
691 struct dsa_switch
*ds
= dev_id
;
692 u32 ports
= sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG
);
696 sw_w32(ports
, RTL930X_ISR_PORT_LINK_STS_CHG
);
698 for (int i
= 0; i
< 28; i
++) {
699 if (ports
& BIT(i
)) {
700 /* Read the register twice because of issues with latency at least
701 * with the external RTL8226 PHY on the XGS1210
703 link
= sw_r32(RTL930X_MAC_LINK_STS
);
704 link
= sw_r32(RTL930X_MAC_LINK_STS
);
706 dsa_port_phylink_mac_change(ds
, i
, true);
708 dsa_port_phylink_mac_change(ds
, i
, false);
715 int rtl930x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
720 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__
, port
, page
, reg
, val
);
722 if (port
> 63 || page
> 4095 || reg
> 31)
726 mutex_lock(&smi_lock
);
728 sw_w32(BIT(port
), RTL930X_SMI_ACCESS_PHY_CTRL_0
);
729 sw_w32_mask(0xffff << 16, val
<< 16, RTL930X_SMI_ACCESS_PHY_CTRL_2
);
730 v
= reg
<< 20 | page
<< 3 | 0x1f << 15 | BIT(2) | BIT(0);
731 sw_w32(v
, RTL930X_SMI_ACCESS_PHY_CTRL_1
);
734 v
= sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1
);
740 mutex_unlock(&smi_lock
);
745 int rtl930x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
750 if (port
> 63 || page
> 4095 || reg
> 31)
753 mutex_lock(&smi_lock
);
755 sw_w32_mask(0xffff << 16, port
<< 16, RTL930X_SMI_ACCESS_PHY_CTRL_2
);
756 v
= reg
<< 20 | page
<< 3 | 0x1f << 15 | 1;
757 sw_w32(v
, RTL930X_SMI_ACCESS_PHY_CTRL_1
);
760 v
= sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1
);
764 pr_debug("Error reading phy %d, register %d\n", port
, reg
);
767 *val
= (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff);
769 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__
, port
, page
, reg
, *val
);
771 mutex_unlock(&smi_lock
);
776 /* Write to an mmd register of the PHY */
777 int rtl930x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
)
782 mutex_lock(&smi_lock
);
784 /* Set PHY to access */
785 sw_w32(BIT(port
), RTL930X_SMI_ACCESS_PHY_CTRL_0
);
787 /* Set data to write */
788 sw_w32_mask(0xffff << 16, val
<< 16, RTL930X_SMI_ACCESS_PHY_CTRL_2
);
790 /* Set MMD device number and register to write to */
791 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3
);
793 v
= BIT(2) | BIT(1) | BIT(0); /* WRITE | MMD-access | EXEC */
794 sw_w32(v
, RTL930X_SMI_ACCESS_PHY_CTRL_1
);
797 v
= sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1
);
798 } while (v
& BIT(0));
800 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, val
, err
);
801 mutex_unlock(&smi_lock
);
805 /* Read an mmd register of the PHY */
806 int rtl930x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
811 mutex_lock(&smi_lock
);
813 /* Set PHY to access */
814 sw_w32_mask(0xffff << 16, port
<< 16, RTL930X_SMI_ACCESS_PHY_CTRL_2
);
816 /* Set MMD device number and register to write to */
817 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3
);
819 v
= BIT(1) | BIT(0); /* MMD-access | EXEC */
820 sw_w32(v
, RTL930X_SMI_ACCESS_PHY_CTRL_1
);
823 v
= sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1
);
824 } while (v
& BIT(0));
825 /* There is no error-checking via BIT 25 of v, as it does not seem to be set correctly */
826 *val
= (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff);
827 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, *val
, err
);
829 mutex_unlock(&smi_lock
);
834 /* Calculate both the block 0 and the block 1 hash, and return in
835 * lower and higher word of the return value since only 12 bit of
836 * the hash are significant
838 u32
rtl930x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
)
840 u32 k0
, k1
, h1
, h2
, h
;
842 k0
= (u32
) (((seed
>> 55) & 0x1f) ^
843 ((seed
>> 44) & 0x7ff) ^
844 ((seed
>> 33) & 0x7ff) ^
845 ((seed
>> 22) & 0x7ff) ^
846 ((seed
>> 11) & 0x7ff) ^
849 h1
= (seed
>> 11) & 0x7ff;
850 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
852 h2
= (seed
>> 33) & 0x7ff;
853 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x3f);
855 k1
= (u32
) (((seed
<< 55) & 0x1f) ^
856 ((seed
>> 44) & 0x7ff) ^
858 ((seed
>> 22) & 0x7ff) ^
862 /* Algorithm choice for block 0 */
863 if (sw_r32(RTL930X_L2_CTRL
) & BIT(0))
868 /* Algorithm choice for block 1
869 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
871 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
872 * divided by 2 to divide the hash space in 2
874 if (sw_r32(RTL930X_L2_CTRL
) & BIT(1))
875 h
|= (k1
+ 2048) << 16;
877 h
|= (k0
+ 2048) << 16;
882 /* Enables or disables the EEE/EEEP capability of a port */
883 void rtl930x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
887 /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */
891 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
892 v
= enable
? 0x3f : 0x0;
894 /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */
895 sw_w32_mask(0, v
<< 10, rtl930x_mac_force_mode_ctrl(port
));
897 /* Set TX/RX EEE state */
898 v
= enable
? 0x3 : 0x0;
899 sw_w32(v
, RTL930X_EEE_CTRL(port
));
901 priv
->ports
[port
].eee_enabled
= enable
;
904 /* Get EEE own capabilities and negotiation result */
905 int rtl930x_eee_port_ability(struct rtl838x_switch_priv
*priv
, struct ethtool_eee
*e
, int port
)
912 pr_info("In %s, port %d\n", __func__
, port
);
913 link
= sw_r32(RTL930X_MAC_LINK_STS
);
914 link
= sw_r32(RTL930X_MAC_LINK_STS
);
915 if (!(link
& BIT(port
)))
918 pr_info("Setting advertised\n");
919 if (sw_r32(rtl930x_mac_force_mode_ctrl(port
)) & BIT(10))
920 e
->advertised
|= ADVERTISED_100baseT_Full
;
922 if (sw_r32(rtl930x_mac_force_mode_ctrl(port
)) & BIT(12))
923 e
->advertised
|= ADVERTISED_1000baseT_Full
;
925 if (priv
->ports
[port
].is2G5
&& sw_r32(rtl930x_mac_force_mode_ctrl(port
)) & BIT(13)) {
926 pr_info("ADVERTISING 2.5G EEE\n");
927 e
->advertised
|= ADVERTISED_2500baseX_Full
;
930 if (priv
->ports
[port
].is10G
&& sw_r32(rtl930x_mac_force_mode_ctrl(port
)) & BIT(15))
931 e
->advertised
|= ADVERTISED_10000baseT_Full
;
933 a
= sw_r32(RTL930X_MAC_EEE_ABLTY
);
934 a
= sw_r32(RTL930X_MAC_EEE_ABLTY
);
935 pr_info("Link partner: %08x\n", a
);
937 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
938 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
939 if (priv
->ports
[port
].is2G5
)
940 e
->lp_advertised
|= ADVERTISED_2500baseX_Full
;
941 if (priv
->ports
[port
].is10G
)
942 e
->lp_advertised
|= ADVERTISED_10000baseT_Full
;
945 /* Read 2x to clear latched state */
946 a
= sw_r32(RTL930X_EEEP_PORT_CTRL(port
));
947 a
= sw_r32(RTL930X_EEEP_PORT_CTRL(port
));
948 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__
, a
);
953 static void rtl930x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
955 pr_info("Setting up EEE, state: %d\n", enable
);
957 /* Setup EEE on all ports */
958 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
959 if (priv
->ports
[i
].phy
)
960 rtl930x_port_eee_set(priv
, i
, enable
);
963 priv
->eee_enabled
= enable
;
965 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
967 static u32
rtl930x_l3_hash4(u32 ip
, int algorithm
, bool move_dip
)
973 memset(rows
, 0, sizeof(rows
));
975 rows
[0] = HASH_PICK(ip
, 27, 5);
976 rows
[1] = HASH_PICK(ip
, 18, 9);
977 rows
[2] = HASH_PICK(ip
, 9, 9);
980 rows
[3] = HASH_PICK(ip
, 0, 9);
983 hash
= rows
[0] ^ rows
[1] ^ rows
[2] ^ rows
[3];
985 s0
= rows
[0] + rows
[1] + rows
[2];
986 s1
= (s0
& 0x1ff) + ((s0
& (0x1ff << 9)) >> 9);
987 pH
= (s1
& 0x1ff) + ((s1
& (0x1ff << 9)) >> 9);
993 static u32
rtl930x_l3_hash6(struct in6_addr
*ip6
, int algorithm
, bool move_dip
)
999 rows
[0] = (HASH_PICK(ip6
->s6_addr
[0], 6, 2) << 0);
1000 rows
[1] = (HASH_PICK(ip6
->s6_addr
[0], 0, 6) << 3) | HASH_PICK(ip6
->s6_addr
[1], 5, 3);
1001 rows
[2] = (HASH_PICK(ip6
->s6_addr
[1], 0, 5) << 4) | HASH_PICK(ip6
->s6_addr
[2], 4, 4);
1002 rows
[3] = (HASH_PICK(ip6
->s6_addr
[2], 0, 4) << 5) | HASH_PICK(ip6
->s6_addr
[3], 3, 5);
1003 rows
[4] = (HASH_PICK(ip6
->s6_addr
[3], 0, 3) << 6) | HASH_PICK(ip6
->s6_addr
[4], 2, 6);
1004 rows
[5] = (HASH_PICK(ip6
->s6_addr
[4], 0, 2) << 7) | HASH_PICK(ip6
->s6_addr
[5], 1, 7);
1005 rows
[6] = (HASH_PICK(ip6
->s6_addr
[5], 0, 1) << 8) | HASH_PICK(ip6
->s6_addr
[6], 0, 8);
1006 rows
[7] = (HASH_PICK(ip6
->s6_addr
[7], 0, 8) << 1) | HASH_PICK(ip6
->s6_addr
[8], 7, 1);
1007 rows
[8] = (HASH_PICK(ip6
->s6_addr
[8], 0, 7) << 2) | HASH_PICK(ip6
->s6_addr
[9], 6, 2);
1008 rows
[9] = (HASH_PICK(ip6
->s6_addr
[9], 0, 6) << 3) | HASH_PICK(ip6
->s6_addr
[10], 5, 3);
1009 rows
[10] = (HASH_PICK(ip6
->s6_addr
[10], 0, 5) << 4) | HASH_PICK(ip6
->s6_addr
[11], 4, 4);
1011 rows
[11] = (HASH_PICK(ip6
->s6_addr
[11], 0, 4) << 5) |
1012 (HASH_PICK(ip6
->s6_addr
[12], 3, 5) << 0);
1013 rows
[12] = (HASH_PICK(ip6
->s6_addr
[12], 0, 3) << 6) |
1014 (HASH_PICK(ip6
->s6_addr
[13], 2, 6) << 0);
1015 rows
[13] = (HASH_PICK(ip6
->s6_addr
[13], 0, 2) << 7) |
1016 (HASH_PICK(ip6
->s6_addr
[14], 1, 7) << 0);
1018 rows
[14] = (HASH_PICK(ip6
->s6_addr
[14], 0, 1) << 8) |
1019 (HASH_PICK(ip6
->s6_addr
[15], 0, 8) << 0);
1021 hash
= rows
[0] ^ rows
[1] ^ rows
[2] ^ rows
[3] ^ rows
[4] ^
1022 rows
[5] ^ rows
[6] ^ rows
[7] ^ rows
[8] ^ rows
[9] ^
1023 rows
[10] ^ rows
[11] ^ rows
[12] ^ rows
[13] ^ rows
[14];
1025 rows
[11] = (HASH_PICK(ip6
->s6_addr
[11], 0, 4) << 5);
1026 rows
[12] = (HASH_PICK(ip6
->s6_addr
[12], 3, 5) << 0);
1027 rows
[13] = (HASH_PICK(ip6
->s6_addr
[12], 0, 3) << 6) |
1028 HASH_PICK(ip6
->s6_addr
[13], 2, 6);
1029 rows
[14] = (HASH_PICK(ip6
->s6_addr
[13], 0, 2) << 7) |
1030 HASH_PICK(ip6
->s6_addr
[14], 1, 7);
1032 rows
[15] = (HASH_PICK(ip6
->s6_addr
[14], 0, 1) << 8) |
1033 (HASH_PICK(ip6
->s6_addr
[15], 0, 8) << 0);
1035 s0
= rows
[12] + rows
[13] + rows
[14];
1036 s1
= (s0
& 0x1ff) + ((s0
& (0x1ff << 9)) >> 9);
1037 pH
= (s1
& 0x1ff) + ((s1
& (0x1ff << 9)) >> 9);
1038 hash
= rows
[0] ^ rows
[1] ^ rows
[2] ^ rows
[3] ^ rows
[4] ^
1039 rows
[5] ^ rows
[6] ^ rows
[7] ^ rows
[8] ^ rows
[9] ^
1040 rows
[10] ^ rows
[11] ^ pH
^ rows
[15];
1045 /* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1046 * We currently only support IPv4 and IPv6 unicast route
1048 static void rtl930x_route_read(int idx
, struct rtl83xx_route
*rt
)
1051 bool host_route
, default_route
;
1052 struct in6_addr ip6_m
;
1054 /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1055 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 2);
1057 rtl_table_read(r
, idx
);
1058 /* The table has a size of 11 registers */
1059 rt
->attr
.valid
= !!(sw_r32(rtl_table_data(r
, 0)) & BIT(31));
1060 if (!rt
->attr
.valid
)
1063 rt
->attr
.type
= (sw_r32(rtl_table_data(r
, 0)) >> 29) & 0x3;
1065 v
= sw_r32(rtl_table_data(r
, 10));
1066 host_route
= !!(v
& BIT(21));
1067 default_route
= !!(v
& BIT(20));
1068 rt
->prefix_len
= -1;
1069 pr_info("%s: host route %d, default_route %d\n", __func__
, host_route
, default_route
);
1071 switch (rt
->attr
.type
) {
1072 case 0: /* IPv4 Unicast route */
1073 rt
->dst_ip
= sw_r32(rtl_table_data(r
, 4));
1074 ip4_m
= sw_r32(rtl_table_data(r
, 9));
1075 pr_info("%s: Read ip4 mask: %08x\n", __func__
, ip4_m
);
1076 rt
->prefix_len
= host_route
? 32 : -1;
1077 rt
->prefix_len
= (rt
->prefix_len
< 0 && default_route
) ? 0 : -1;
1078 if (rt
->prefix_len
< 0)
1079 rt
->prefix_len
= inet_mask_len(ip4_m
);
1081 case 2: /* IPv6 Unicast route */
1082 ipv6_addr_set(&rt
->dst_ip6
,
1083 sw_r32(rtl_table_data(r
, 1)), sw_r32(rtl_table_data(r
, 2)),
1084 sw_r32(rtl_table_data(r
, 3)), sw_r32(rtl_table_data(r
, 4)));
1085 ipv6_addr_set(&ip6_m
,
1086 sw_r32(rtl_table_data(r
, 6)), sw_r32(rtl_table_data(r
, 7)),
1087 sw_r32(rtl_table_data(r
, 8)), sw_r32(rtl_table_data(r
, 9)));
1088 rt
->prefix_len
= host_route
? 128 : 0;
1089 rt
->prefix_len
= (rt
->prefix_len
< 0 && default_route
) ? 0 : -1;
1090 if (rt
->prefix_len
< 0)
1091 rt
->prefix_len
= find_last_bit((unsigned long int *)&ip6_m
.s6_addr32
,
1094 case 1: /* IPv4 Multicast route */
1095 case 3: /* IPv6 Multicast route */
1096 pr_warn("%s: route type not supported\n", __func__
);
1100 rt
->attr
.hit
= !!(v
& BIT(22));
1101 rt
->attr
.action
= (v
>> 18) & 3;
1102 rt
->nh
.id
= (v
>> 7) & 0x7ff;
1103 rt
->attr
.ttl_dec
= !!(v
& BIT(6));
1104 rt
->attr
.ttl_check
= !!(v
& BIT(5));
1105 rt
->attr
.dst_null
= !!(v
& BIT(4));
1106 rt
->attr
.qos_as
= !!(v
& BIT(3));
1107 rt
->attr
.qos_prio
= v
& 0x7;
1108 pr_info("%s: index %d is valid: %d\n", __func__
, idx
, rt
->attr
.valid
);
1109 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1110 __func__
, rt
->nh
.id
, rt
->attr
.hit
, rt
->attr
.action
,
1111 rt
->attr
.ttl_dec
, rt
->attr
.ttl_check
, rt
->attr
.dst_null
);
1112 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__
, &rt
->dst_ip
, rt
->prefix_len
);
1114 rtl_table_release(r
);
1117 static void rtl930x_net6_mask(int prefix_len
, struct in6_addr
*ip6_m
)
1120 /* Define network mask */
1121 o
= prefix_len
>> 3;
1122 b
= prefix_len
& 0x7;
1123 memset(ip6_m
->s6_addr
, 0xff, o
);
1124 ip6_m
->s6_addr
[o
] |= b
? 0xff00 >> b
: 0x00;
1127 /* Read a host route entry from the table using its index
1128 * We currently only support IPv4 and IPv6 unicast route
1130 static void rtl930x_host_route_read(int idx
, struct rtl83xx_route
*rt
)
1133 /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1134 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 1);
1136 idx
= ((idx
/ 6) * 8) + (idx
% 6);
1138 pr_debug("In %s, physical index %d\n", __func__
, idx
);
1139 rtl_table_read(r
, idx
);
1140 /* The table has a size of 5 (for UC, 11 for MC) registers */
1141 v
= sw_r32(rtl_table_data(r
, 0));
1142 rt
->attr
.valid
= !!(v
& BIT(31));
1143 if (!rt
->attr
.valid
)
1145 rt
->attr
.type
= (v
>> 29) & 0x3;
1146 switch (rt
->attr
.type
) {
1147 case 0: /* IPv4 Unicast route */
1148 rt
->dst_ip
= sw_r32(rtl_table_data(r
, 4));
1150 case 2: /* IPv6 Unicast route */
1151 ipv6_addr_set(&rt
->dst_ip6
,
1152 sw_r32(rtl_table_data(r
, 3)), sw_r32(rtl_table_data(r
, 2)),
1153 sw_r32(rtl_table_data(r
, 1)), sw_r32(rtl_table_data(r
, 0)));
1155 case 1: /* IPv4 Multicast route */
1156 case 3: /* IPv6 Multicast route */
1157 pr_warn("%s: route type not supported\n", __func__
);
1161 rt
->attr
.hit
= !!(v
& BIT(20));
1162 rt
->attr
.dst_null
= !!(v
& BIT(19));
1163 rt
->attr
.action
= (v
>> 17) & 3;
1164 rt
->nh
.id
= (v
>> 6) & 0x7ff;
1165 rt
->attr
.ttl_dec
= !!(v
& BIT(5));
1166 rt
->attr
.ttl_check
= !!(v
& BIT(4));
1167 rt
->attr
.qos_as
= !!(v
& BIT(3));
1168 rt
->attr
.qos_prio
= v
& 0x7;
1169 pr_debug("%s: index %d is valid: %d\n", __func__
, idx
, rt
->attr
.valid
);
1170 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1171 __func__
, rt
->nh
.id
, rt
->attr
.hit
, rt
->attr
.action
, rt
->attr
.ttl_dec
, rt
->attr
.ttl_check
,
1173 pr_debug("%s: Destination: %pI4\n", __func__
, &rt
->dst_ip
);
1176 rtl_table_release(r
);
1179 /* Write a host route entry from the table using its index
1180 * We currently only support IPv4 and IPv6 unicast route
1182 static void rtl930x_host_route_write(int idx
, struct rtl83xx_route
*rt
)
1185 /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1186 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 1);
1187 /* The table has a size of 5 (for UC, 11 for MC) registers */
1189 idx
= ((idx
/ 6) * 8) + (idx
% 6);
1191 pr_debug("%s: index %d is valid: %d\n", __func__
, idx
, rt
->attr
.valid
);
1192 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1193 __func__
, rt
->nh
.id
, rt
->attr
.hit
, rt
->attr
.action
, rt
->attr
.ttl_dec
, rt
->attr
.ttl_check
,
1195 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__
, &rt
->dst_ip
, rt
->prefix_len
);
1197 v
= BIT(31); /* Entry is valid */
1198 v
|= (rt
->attr
.type
& 0x3) << 29;
1199 v
|= rt
->attr
.hit
? BIT(20) : 0;
1200 v
|= rt
->attr
.dst_null
? BIT(19) : 0;
1201 v
|= (rt
->attr
.action
& 0x3) << 17;
1202 v
|= (rt
->nh
.id
& 0x7ff) << 6;
1203 v
|= rt
->attr
.ttl_dec
? BIT(5) : 0;
1204 v
|= rt
->attr
.ttl_check
? BIT(4) : 0;
1205 v
|= rt
->attr
.qos_as
? BIT(3) : 0;
1206 v
|= rt
->attr
.qos_prio
& 0x7;
1208 sw_w32(v
, rtl_table_data(r
, 0));
1209 switch (rt
->attr
.type
) {
1210 case 0: /* IPv4 Unicast route */
1211 sw_w32(0, rtl_table_data(r
, 1));
1212 sw_w32(0, rtl_table_data(r
, 2));
1213 sw_w32(0, rtl_table_data(r
, 3));
1214 sw_w32(rt
->dst_ip
, rtl_table_data(r
, 4));
1216 case 2: /* IPv6 Unicast route */
1217 sw_w32(rt
->dst_ip6
.s6_addr32
[0], rtl_table_data(r
, 1));
1218 sw_w32(rt
->dst_ip6
.s6_addr32
[1], rtl_table_data(r
, 2));
1219 sw_w32(rt
->dst_ip6
.s6_addr32
[2], rtl_table_data(r
, 3));
1220 sw_w32(rt
->dst_ip6
.s6_addr32
[3], rtl_table_data(r
, 4));
1222 case 1: /* IPv4 Multicast route */
1223 case 3: /* IPv6 Multicast route */
1224 pr_warn("%s: route type not supported\n", __func__
);
1228 rtl_table_write(r
, idx
);
1231 rtl_table_release(r
);
1234 /* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1235 * using hardware offload.
1237 static int rtl930x_route_lookup_hw(struct rtl83xx_route
*rt
)
1240 struct in6_addr ip6_m
;
1242 if (rt
->attr
.type
== 1 || rt
->attr
.type
== 3) /* Hardware only supports UC routes */
1245 sw_w32_mask(0x3 << 19, rt
->attr
.type
, RTL930X_L3_HW_LU_KEY_CTRL
);
1246 if (rt
->attr
.type
) { /* IPv6 */
1247 rtl930x_net6_mask(rt
->prefix_len
, &ip6_m
);
1248 for (int i
= 0; i
< 4; i
++)
1249 sw_w32(rt
->dst_ip6
.s6_addr32
[0] & ip6_m
.s6_addr32
[0],
1250 RTL930X_L3_HW_LU_KEY_IP_CTRL
+ (i
<< 2));
1252 ip4_m
= inet_make_mask(rt
->prefix_len
);
1253 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL
);
1254 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL
+ 4);
1255 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL
+ 8);
1256 v
= rt
->dst_ip
& ip4_m
;
1257 pr_info("%s: searching for %pI4\n", __func__
, &v
);
1258 sw_w32(v
, RTL930X_L3_HW_LU_KEY_IP_CTRL
+ 12);
1261 /* Execute CAM lookup in SoC */
1262 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL
);
1264 /* Wait until execute bit clears and result is ready */
1266 v
= sw_r32(RTL930X_L3_HW_LU_CTRL
);
1267 } while (v
& BIT(15));
1269 pr_info("%s: found: %d, index: %d\n", __func__
, !!(v
& BIT(14)), v
& 0x1ff);
1271 /* Test if search successful (BIT 14 set) */
1278 static int rtl930x_find_l3_slot(struct rtl83xx_route
*rt
, bool must_exist
)
1280 int slot_width
, algorithm
, addr
, idx
;
1282 struct rtl83xx_route route_entry
;
1284 /* IPv6 entries take up 3 slots */
1285 slot_width
= (rt
->attr
.type
== 0) || (rt
->attr
.type
== 2) ? 1 : 3;
1287 for (int t
= 0; t
< 2; t
++) {
1288 algorithm
= (sw_r32(RTL930X_L3_HOST_TBL_CTRL
) >> (2 + t
)) & 0x1;
1289 hash
= rtl930x_l3_hash4(rt
->dst_ip
, algorithm
, false);
1291 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__
, t
, algorithm
, hash
);
1293 for (int s
= 0; s
< 6; s
+= slot_width
) {
1294 addr
= (t
<< 12) | ((hash
& 0x1ff) << 3) | s
;
1295 pr_debug("%s physical address %d\n", __func__
, addr
);
1296 idx
= ((addr
/ 8) * 6) + (addr
% 8);
1297 pr_debug("%s logical address %d\n", __func__
, idx
);
1299 rtl930x_host_route_read(idx
, &route_entry
);
1300 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__
,
1301 rt
->attr
.valid
, &rt
->dst_ip
, rt
->attr
.hit
);
1302 if (!must_exist
&& rt
->attr
.valid
)
1304 if (must_exist
&& route_entry
.dst_ip
== rt
->dst_ip
)
1312 /* Write a prefix route into the routing table CAM at position idx
1313 * Currently only IPv4 and IPv6 unicast routes are supported
1315 static void rtl930x_route_write(int idx
, struct rtl83xx_route
*rt
)
1318 struct in6_addr ip6_m
;
1319 /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1320 /* The table has a size of 11 registers (20 for MC) */
1321 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 2);
1323 pr_debug("%s: index %d is valid: %d\n", __func__
, idx
, rt
->attr
.valid
);
1324 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1325 __func__
, rt
->nh
.id
, rt
->attr
.hit
, rt
->attr
.action
,
1326 rt
->attr
.ttl_dec
, rt
->attr
.ttl_check
, rt
->attr
.dst_null
);
1327 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__
, &rt
->dst_ip
, rt
->prefix_len
);
1329 v
= rt
->attr
.valid
? BIT(31) : 0;
1330 v
|= (rt
->attr
.type
& 0x3) << 29;
1331 sw_w32(v
, rtl_table_data(r
, 0));
1333 v
= rt
->attr
.hit
? BIT(22) : 0;
1334 v
|= (rt
->attr
.action
& 0x3) << 18;
1335 v
|= (rt
->nh
.id
& 0x7ff) << 7;
1336 v
|= rt
->attr
.ttl_dec
? BIT(6) : 0;
1337 v
|= rt
->attr
.ttl_check
? BIT(5) : 0;
1338 v
|= rt
->attr
.dst_null
? BIT(6) : 0;
1339 v
|= rt
->attr
.qos_as
? BIT(6) : 0;
1340 v
|= rt
->attr
.qos_prio
& 0x7;
1341 v
|= rt
->prefix_len
== 0 ? BIT(20) : 0; /* set default route bit */
1343 /* set bit mask for entry type always to 0x3 */
1344 sw_w32(0x3 << 29, rtl_table_data(r
, 5));
1346 switch (rt
->attr
.type
) {
1347 case 0: /* IPv4 Unicast route */
1348 sw_w32(0, rtl_table_data(r
, 1));
1349 sw_w32(0, rtl_table_data(r
, 2));
1350 sw_w32(0, rtl_table_data(r
, 3));
1351 sw_w32(rt
->dst_ip
, rtl_table_data(r
, 4));
1353 v
|= rt
->prefix_len
== 32 ? BIT(21) : 0; /* set host-route bit */
1354 ip4_m
= inet_make_mask(rt
->prefix_len
);
1355 sw_w32(0, rtl_table_data(r
, 6));
1356 sw_w32(0, rtl_table_data(r
, 7));
1357 sw_w32(0, rtl_table_data(r
, 8));
1358 sw_w32(ip4_m
, rtl_table_data(r
, 9));
1360 case 2: /* IPv6 Unicast route */
1361 sw_w32(rt
->dst_ip6
.s6_addr32
[0], rtl_table_data(r
, 1));
1362 sw_w32(rt
->dst_ip6
.s6_addr32
[1], rtl_table_data(r
, 2));
1363 sw_w32(rt
->dst_ip6
.s6_addr32
[2], rtl_table_data(r
, 3));
1364 sw_w32(rt
->dst_ip6
.s6_addr32
[3], rtl_table_data(r
, 4));
1366 v
|= rt
->prefix_len
== 128 ? BIT(21) : 0; /* set host-route bit */
1368 rtl930x_net6_mask(rt
->prefix_len
, &ip6_m
);
1370 sw_w32(ip6_m
.s6_addr32
[0], rtl_table_data(r
, 6));
1371 sw_w32(ip6_m
.s6_addr32
[1], rtl_table_data(r
, 7));
1372 sw_w32(ip6_m
.s6_addr32
[2], rtl_table_data(r
, 8));
1373 sw_w32(ip6_m
.s6_addr32
[3], rtl_table_data(r
, 9));
1375 case 1: /* IPv4 Multicast route */
1376 case 3: /* IPv6 Multicast route */
1377 pr_warn("%s: route type not supported\n", __func__
);
1378 rtl_table_release(r
);
1381 sw_w32(v
, rtl_table_data(r
, 10));
1383 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__
,
1384 sw_r32(rtl_table_data(r
, 0)), sw_r32(rtl_table_data(r
, 1)), sw_r32(rtl_table_data(r
, 2)),
1385 sw_r32(rtl_table_data(r
, 3)), sw_r32(rtl_table_data(r
, 4)), sw_r32(rtl_table_data(r
, 5)),
1386 sw_r32(rtl_table_data(r
, 6)), sw_r32(rtl_table_data(r
, 7)), sw_r32(rtl_table_data(r
, 8)),
1387 sw_r32(rtl_table_data(r
, 9)), sw_r32(rtl_table_data(r
, 10)));
1389 rtl_table_write(r
, idx
);
1390 rtl_table_release(r
);
1394 /* Get the destination MAC and L3 egress interface ID of a nexthop entry from
1395 * the SoC's L3_NEXTHOP table
1397 static void rtl930x_get_l3_nexthop(int idx
, u16
*dmac_id
, u16
*interface
)
1400 /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1401 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 3);
1403 rtl_table_read(r
, idx
);
1404 /* The table has a size of 1 register */
1405 v
= sw_r32(rtl_table_data(r
, 0));
1406 rtl_table_release(r
);
1408 *dmac_id
= (v
>> 7) & 0x7fff;
1409 *interface
= v
& 0x7f;
1412 static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv
*priv
, int mtu
)
1416 for (i
= 0; i
< MAX_INTF_MTUS
; i
++) {
1417 if (mtu
== priv
->intf_mtus
[i
])
1420 if (i
>= MAX_INTF_MTUS
|| !priv
->intf_mtu_count
[i
]) {
1421 pr_err("%s: No MTU slot found for MTU: %d\n", __func__
, mtu
);
1425 priv
->intf_mtu_count
[i
]--;
1428 static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv
*priv
, int mtu
)
1433 /* Try to find an existing mtu-value or a free slot */
1434 free_mtu
= MAX_INTF_MTUS
;
1435 for (i
= 0; i
< MAX_INTF_MTUS
&& priv
->intf_mtus
[i
] != mtu
; i
++) {
1436 if ((!priv
->intf_mtu_count
[i
]) && (free_mtu
== MAX_INTF_MTUS
))
1439 i
= (i
< MAX_INTF_MTUS
) ? i
: free_mtu
;
1440 if (i
< MAX_INTF_MTUS
) {
1443 pr_err("%s: No free MTU slot available!\n", __func__
);
1447 priv
->intf_mtus
[i
] = mtu
;
1448 pr_info("Writing MTU %d to slot %d\n", priv
->intf_mtus
[i
], i
);
1449 /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */
1450 sw_w32_mask(0xffff << ((i
% 2) * 16), priv
->intf_mtus
[i
] << ((i
% 2) * 16),
1451 RTL930X_L3_IP_MTU_CTRL(i
));
1452 sw_w32_mask(0xffff << ((i
% 2) * 16), priv
->intf_mtus
[i
] << ((i
% 2) * 16),
1453 RTL930X_L3_IP6_MTU_CTRL(i
));
1455 priv
->intf_mtu_count
[i
]++;
1460 /* Creates an interface for a route by setting up the HW tables in the SoC */
1461 static int rtl930x_l3_intf_add(struct rtl838x_switch_priv
*priv
, struct rtl838x_l3_intf
*intf
)
1463 int i
, intf_id
, mtu_id
;
1464 /* number of MTU-values < 16384 */
1466 /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */
1467 intf
->ip6_mtu
= intf
->ip6_mtu
? intf
->ip6_mtu
: intf
->ip4_mtu
;
1469 mtu_id
= rtl930x_l3_mtu_add(priv
, intf
->ip4_mtu
);
1470 pr_info("%s: added mtu %d with mtu-id %d\n", __func__
, intf
->ip4_mtu
, mtu_id
);
1473 intf
->ip4_mtu_id
= mtu_id
;
1474 intf
->ip6_mtu_id
= mtu_id
;
1476 for (i
= 0; i
< MAX_INTERFACES
; i
++) {
1477 if (!priv
->interfaces
[i
])
1480 if (i
>= MAX_INTERFACES
) {
1481 pr_err("%s: cannot find free interface entry\n", __func__
);
1485 priv
->interfaces
[i
] = kzalloc(sizeof(struct rtl838x_l3_intf
), GFP_KERNEL
);
1486 if (!priv
->interfaces
[i
]) {
1487 pr_err("%s: no memory to allocate new interface\n", __func__
);
1492 /* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1493 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1494 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1496 * 0x7ffd: TRAP2MASTERCPU
1497 * 0x7fff: DMAC_ID_DROP
1499 static void rtl930x_set_l3_nexthop(int idx
, u16 dmac_id
, u16 interface
)
1501 /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1502 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 3);
1504 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1505 __func__
, idx
, dmac_id
, interface
);
1506 sw_w32(((dmac_id
& 0x7fff) << 7) | (interface
& 0x7f), rtl_table_data(r
, 0));
1508 pr_info("%s: %08x\n", __func__
, sw_r32(rtl_table_data(r
,0)));
1509 rtl_table_write(r
, idx
);
1510 rtl_table_release(r
);
1513 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
1515 int block
= index
/ PIE_BLOCK_SIZE
;
1517 sw_w32_mask(0, BIT(block
), RTL930X_PIE_BLK_LOOKUP_CTRL
);
1520 /* Reads the intermediate representation of the templated match-fields of the
1521 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1522 * raw register space r[].
1523 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1524 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1526 * On the RTL9300 the mask fields are not word-aligend!
1528 static void rtl930x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
1530 for (int i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1531 enum template_field_id field_type
= t
[i
];
1532 u16 data
= 0, data_m
= 0;
1534 switch (field_type
) {
1535 case TEMPLATE_FIELD_SPM0
:
1539 case TEMPLATE_FIELD_SPM1
:
1540 data
= pr
->spm
>> 16;
1541 data_m
= pr
->spm_m
>> 16;
1543 case TEMPLATE_FIELD_OTAG
:
1545 data_m
= pr
->otag_m
;
1547 case TEMPLATE_FIELD_SMAC0
:
1549 data
= (data
<< 8) | pr
->smac
[5];
1550 data_m
= pr
->smac_m
[4];
1551 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
1553 case TEMPLATE_FIELD_SMAC1
:
1555 data
= (data
<< 8) | pr
->smac
[3];
1556 data_m
= pr
->smac_m
[2];
1557 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
1559 case TEMPLATE_FIELD_SMAC2
:
1561 data
= (data
<< 8) | pr
->smac
[1];
1562 data_m
= pr
->smac_m
[0];
1563 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
1565 case TEMPLATE_FIELD_DMAC0
:
1567 data
= (data
<< 8) | pr
->dmac
[5];
1568 data_m
= pr
->dmac_m
[4];
1569 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
1571 case TEMPLATE_FIELD_DMAC1
:
1573 data
= (data
<< 8) | pr
->dmac
[3];
1574 data_m
= pr
->dmac_m
[2];
1575 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
1577 case TEMPLATE_FIELD_DMAC2
:
1579 data
= (data
<< 8) | pr
->dmac
[1];
1580 data_m
= pr
->dmac_m
[0];
1581 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
1583 case TEMPLATE_FIELD_ETHERTYPE
:
1584 data
= pr
->ethertype
;
1585 data_m
= pr
->ethertype_m
;
1587 case TEMPLATE_FIELD_ITAG
:
1589 data_m
= pr
->itag_m
;
1591 case TEMPLATE_FIELD_SIP0
:
1593 data
= pr
->sip6
.s6_addr16
[7];
1594 data_m
= pr
->sip6_m
.s6_addr16
[7];
1600 case TEMPLATE_FIELD_SIP1
:
1602 data
= pr
->sip6
.s6_addr16
[6];
1603 data_m
= pr
->sip6_m
.s6_addr16
[6];
1605 data
= pr
->sip
>> 16;
1606 data_m
= pr
->sip_m
>> 16;
1609 case TEMPLATE_FIELD_SIP2
:
1610 case TEMPLATE_FIELD_SIP3
:
1611 case TEMPLATE_FIELD_SIP4
:
1612 case TEMPLATE_FIELD_SIP5
:
1613 case TEMPLATE_FIELD_SIP6
:
1614 case TEMPLATE_FIELD_SIP7
:
1615 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1616 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1618 case TEMPLATE_FIELD_DIP0
:
1620 data
= pr
->dip6
.s6_addr16
[7];
1621 data_m
= pr
->dip6_m
.s6_addr16
[7];
1627 case TEMPLATE_FIELD_DIP1
:
1629 data
= pr
->dip6
.s6_addr16
[6];
1630 data_m
= pr
->dip6_m
.s6_addr16
[6];
1632 data
= pr
->dip
>> 16;
1633 data_m
= pr
->dip_m
>> 16;
1636 case TEMPLATE_FIELD_DIP2
:
1637 case TEMPLATE_FIELD_DIP3
:
1638 case TEMPLATE_FIELD_DIP4
:
1639 case TEMPLATE_FIELD_DIP5
:
1640 case TEMPLATE_FIELD_DIP6
:
1641 case TEMPLATE_FIELD_DIP7
:
1642 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1643 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1645 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1646 data
= pr
->tos_proto
;
1647 data_m
= pr
->tos_proto_m
;
1649 case TEMPLATE_FIELD_L4_SPORT
:
1651 data_m
= pr
->sport_m
;
1653 case TEMPLATE_FIELD_L4_DPORT
:
1655 data_m
= pr
->dport_m
;
1657 case TEMPLATE_FIELD_DSAP_SSAP
:
1658 data
= pr
->dsap_ssap
;
1659 data_m
= pr
->dsap_ssap_m
;
1661 case TEMPLATE_FIELD_TCP_INFO
:
1662 data
= pr
->tcp_info
;
1663 data_m
= pr
->tcp_info_m
;
1665 case TEMPLATE_FIELD_RANGE_CHK
:
1666 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1669 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1672 /* On the RTL9300, the mask fields are not word aligned! */
1674 r
[5 - i
/ 2] = data
;
1675 r
[12 - i
/ 2] |= ((u32
)data_m
<< 8);
1677 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
1678 r
[12 - i
/ 2] |= ((u32
)data_m
) << 24;
1679 r
[11 - i
/ 2] |= ((u32
)data_m
) >> 8;
1684 static void rtl930x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1686 pr
->stacking_port
= r
[6] & BIT(31);
1687 pr
->spn
= (r
[6] >> 24) & 0x7f;
1688 pr
->mgnt_vlan
= r
[6] & BIT(23);
1689 if (pr
->phase
== PHASE_IACL
)
1690 pr
->dmac_hit_sw
= r
[6] & BIT(22);
1692 pr
->content_too_deep
= r
[6] & BIT(22);
1693 pr
->not_first_frag
= r
[6] & BIT(21);
1694 pr
->frame_type_l4
= (r
[6] >> 18) & 7;
1695 pr
->frame_type
= (r
[6] >> 16) & 3;
1696 pr
->otag_fmt
= (r
[6] >> 15) & 1;
1697 pr
->itag_fmt
= (r
[6] >> 14) & 1;
1698 pr
->otag_exist
= (r
[6] >> 13) & 1;
1699 pr
->itag_exist
= (r
[6] >> 12) & 1;
1700 pr
->frame_type_l2
= (r
[6] >> 10) & 3;
1701 pr
->igr_normal_port
= (r
[6] >> 9) & 1;
1702 pr
->tid
= (r
[6] >> 8) & 1;
1704 pr
->stacking_port_m
= r
[12] & BIT(7);
1705 pr
->spn_m
= r
[12] & 0x7f;
1706 pr
->mgnt_vlan_m
= r
[13] & BIT(31);
1707 if (pr
->phase
== PHASE_IACL
)
1708 pr
->dmac_hit_sw_m
= r
[13] & BIT(30);
1710 pr
->content_too_deep_m
= r
[13] & BIT(30);
1711 pr
->not_first_frag_m
= r
[13] & BIT(29);
1712 pr
->frame_type_l4_m
= (r
[13] >> 26) & 7;
1713 pr
->frame_type_m
= (r
[13] >> 24) & 3;
1714 pr
->otag_fmt_m
= r
[13] & BIT(23);
1715 pr
->itag_fmt_m
= r
[13] & BIT(22);
1716 pr
->otag_exist_m
= r
[13] & BIT(21);
1717 pr
->itag_exist_m
= r
[13] & BIT (20);
1718 pr
->frame_type_l2_m
= (r
[13] >> 18) & 3;
1719 pr
->igr_normal_port_m
= r
[13] & BIT(17);
1720 pr
->tid_m
= (r
[13] >> 16) & 1;
1722 pr
->valid
= r
[13] & BIT(15);
1723 pr
->cond_not
= r
[13] & BIT(14);
1724 pr
->cond_and1
= r
[13] & BIT(13);
1725 pr
->cond_and2
= r
[13] & BIT(12);
1728 static void rtl930x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1730 r
[6] = pr
->stacking_port
? BIT(31) : 0;
1731 r
[6] |= ((u32
) (pr
->spn
& 0x7f)) << 24;
1732 r
[6] |= pr
->mgnt_vlan
? BIT(23) : 0;
1733 if (pr
->phase
== PHASE_IACL
)
1734 r
[6] |= pr
->dmac_hit_sw
? BIT(22) : 0;
1736 r
[6] |= pr
->content_too_deep
? BIT(22) : 0;
1737 r
[6] |= pr
->not_first_frag
? BIT(21) : 0;
1738 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 18;
1739 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 16;
1740 r
[6] |= pr
->otag_fmt
? BIT(15) : 0;
1741 r
[6] |= pr
->itag_fmt
? BIT(14) : 0;
1742 r
[6] |= pr
->otag_exist
? BIT(13) : 0;
1743 r
[6] |= pr
->itag_exist
? BIT(12) : 0;
1744 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 10;
1745 r
[6] |= pr
->igr_normal_port
? BIT(9) : 0;
1746 r
[6] |= ((u32
) (pr
->tid
& 0x1)) << 8;
1748 r
[12] |= pr
->stacking_port_m
? BIT(7) : 0;
1749 r
[12] |= (u32
) (pr
->spn_m
& 0x7f);
1750 r
[13] |= pr
->mgnt_vlan_m
? BIT(31) : 0;
1751 if (pr
->phase
== PHASE_IACL
)
1752 r
[13] |= pr
->dmac_hit_sw_m
? BIT(30) : 0;
1754 r
[13] |= pr
->content_too_deep_m
? BIT(30) : 0;
1755 r
[13] |= pr
->not_first_frag_m
? BIT(29) : 0;
1756 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 26;
1757 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 24;
1758 r
[13] |= pr
->otag_fmt_m
? BIT(23) : 0;
1759 r
[13] |= pr
->itag_fmt_m
? BIT(22) : 0;
1760 r
[13] |= pr
->otag_exist_m
? BIT(21) : 0;
1761 r
[13] |= pr
->itag_exist_m
? BIT(20) : 0;
1762 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 18;
1763 r
[13] |= pr
->igr_normal_port_m
? BIT(17) : 0;
1764 r
[13] |= ((u32
) (pr
->tid_m
& 0x1)) << 16;
1766 r
[13] |= pr
->valid
? BIT(15) : 0;
1767 r
[13] |= pr
->cond_not
? BIT(14) : 0;
1768 r
[13] |= pr
->cond_and1
? BIT(13) : 0;
1769 r
[13] |= pr
->cond_and2
? BIT(12) : 0;
1772 static void rtl930x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1774 /* Either drop or forward */
1776 r
[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */
1777 /* Actually DROP, not PERMIT in Green / Yellow / Red */
1778 r
[14] |= BIT(23) | BIT(22) | BIT(20);
1780 r
[14] |= pr
->fwd_sel
? BIT(27) : 0;
1781 r
[14] |= pr
->fwd_act
<< 18;
1782 r
[14] |= BIT(14); /* We overwrite any drop */
1784 if (pr
->phase
== PHASE_VACL
)
1785 r
[14] |= pr
->fwd_sa_lrn
? BIT(15) : 0;
1786 r
[13] |= pr
->bypass_sel
? BIT(5) : 0;
1787 r
[13] |= pr
->nopri_sel
? BIT(4) : 0;
1788 r
[13] |= pr
->tagst_sel
? BIT(3) : 0;
1789 r
[13] |= pr
->ovid_sel
? BIT(1) : 0;
1790 r
[14] |= pr
->ivid_sel
? BIT(31) : 0;
1791 r
[14] |= pr
->meter_sel
? BIT(30) : 0;
1792 r
[14] |= pr
->mir_sel
? BIT(29) : 0;
1793 r
[14] |= pr
->log_sel
? BIT(28) : 0;
1795 r
[14] |= ((u32
)(pr
->fwd_data
& 0x3fff)) << 3;
1796 r
[15] |= pr
->log_octets
? BIT(31) : 0;
1797 r
[15] |= (u32
)(pr
->meter_data
) << 23;
1799 r
[15] |= ((u32
)(pr
->ivid_act
) << 21) & 0x3;
1800 r
[15] |= ((u32
)(pr
->ivid_data
) << 9) & 0xfff;
1801 r
[16] |= ((u32
)(pr
->ovid_act
) << 30) & 0x3;
1802 r
[16] |= ((u32
)(pr
->ovid_data
) & 0xfff) << 16;
1803 r
[16] |= (pr
->mir_data
& 0x3) << 6;
1804 r
[17] |= ((u32
)(pr
->tagst_data
) & 0xf) << 28;
1805 r
[17] |= ((u32
)(pr
->nopri_data
) & 0x7) << 25;
1806 r
[17] |= pr
->bypass_ibc_sc
? BIT(16) : 0;
1809 void rtl930x_pie_rule_dump_raw(u32 r
[])
1811 pr_info("Raw IACL table entry:\n");
1812 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1813 r
[0], r
[1], r
[2], r
[3], r
[4], r
[5], r
[6], r
[7]);
1814 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1815 r
[8], r
[9], r
[10], r
[11], r
[12], r
[13], r
[14], r
[15]);
1816 pr_info("r 16 - 18: %08x %08x %08x\n", r
[16], r
[17], r
[18]);
1817 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1818 pr_info("Fixed : %06x\n", r
[6] >> 8);
1819 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1820 (r
[6] << 24) | (r
[7] >> 8), (r
[7] << 24) | (r
[8] >> 8), (r
[8] << 24) | (r
[9] >> 8),
1821 (r
[9] << 24) | (r
[10] >> 8), (r
[10] << 24) | (r
[11] >> 8),
1822 (r
[11] << 24) | (r
[12] >> 8));
1823 pr_info("R[13]: %08x\n", r
[13]);
1824 pr_info("Fixed M: %06x\n", ((r
[12] << 16) | (r
[13] >> 16)) & 0xffffff);
1825 pr_info("Valid / not / and1 / and2 : %1x\n", (r
[13] >> 12) & 0xf);
1826 pr_info("r 13-16: %08x %08x %08x %08x\n", r
[13], r
[14], r
[15], r
[16]);
1829 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1831 /* Access IACL table (2) via register 0 */
1832 struct table_reg
*q
= rtl_table_get(RTL9300_TBL_0
, 2);
1834 int block
= idx
/ PIE_BLOCK_SIZE
;
1835 u32 t_select
= sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block
));
1837 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1839 for (int i
= 0; i
< 19; i
++)
1843 rtl_table_write(q
, idx
);
1844 rtl_table_release(q
);
1847 rtl930x_write_pie_fixed_fields(r
, pr
);
1849 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 4)) & 0xf);
1850 rtl930x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 4)) & 0xf]);
1852 rtl930x_write_pie_action(r
, pr
);
1854 /* rtl930x_pie_rule_dump_raw(r); */
1856 for (int i
= 0; i
< 19; i
++)
1857 sw_w32(r
[i
], rtl_table_data(q
, i
));
1859 rtl_table_write(q
, idx
);
1860 rtl_table_release(q
);
1865 static bool rtl930x_pie_templ_has(int t
, enum template_field_id field_type
)
1867 for (int i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1868 enum template_field_id ft
= fixed_templates
[t
][i
];
1869 if (field_type
== ft
)
1876 /* Verify that the rule pr is compatible with a given template t in block block
1877 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1880 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1881 struct pie_rule
*pr
, int t
, int block
)
1885 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl930x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1888 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl930x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1892 if ((pr
->sip6_m
.s6_addr32
[0] ||
1893 pr
->sip6_m
.s6_addr32
[1] ||
1894 pr
->sip6_m
.s6_addr32
[2] ||
1895 pr
->sip6_m
.s6_addr32
[3]) &&
1896 !rtl930x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1898 if ((pr
->dip6_m
.s6_addr32
[0] ||
1899 pr
->dip6_m
.s6_addr32
[1] ||
1900 pr
->dip6_m
.s6_addr32
[2] ||
1901 pr
->dip6_m
.s6_addr32
[3]) &&
1902 !rtl930x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1906 if (ether_addr_to_u64(pr
->smac
) && !rtl930x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1909 if (ether_addr_to_u64(pr
->dmac
) && !rtl930x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1912 /* TODO: Check more */
1914 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1916 if (i
>= PIE_BLOCK_SIZE
)
1919 return i
+ PIE_BLOCK_SIZE
* block
;
1922 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1924 int idx
, block
, j
, t
;
1926 int max_block
= priv
->n_pie_blocks
/ 2;
1928 if (pr
->is_egress
) {
1929 min_block
= max_block
;
1930 max_block
= priv
->n_pie_blocks
;
1932 pr_debug("In %s\n", __func__
);
1934 mutex_lock(&priv
->pie_mutex
);
1936 for (block
= min_block
; block
< max_block
; block
++) {
1937 for (j
= 0; j
< 2; j
++) {
1938 t
= (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block
)) >> (j
* 4)) & 0xf;
1939 pr_debug("Testing block %d, template %d, template id %d\n", block
, j
, t
);
1940 pr_debug("%s: %08x\n",
1941 __func__
, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block
)));
1942 idx
= rtl930x_pie_verify_template(priv
, pr
, t
, block
);
1950 if (block
>= priv
->n_pie_blocks
) {
1951 mutex_unlock(&priv
->pie_mutex
);
1955 pr_debug("Using block: %d, index %d, template-id %d\n", block
, idx
, j
);
1956 set_bit(idx
, priv
->pie_use_bm
);
1959 pr
->tid
= j
; /* Mapped to template number */
1963 rtl930x_pie_lookup_enable(priv
, idx
);
1964 rtl930x_pie_rule_write(priv
, idx
, pr
);
1966 mutex_unlock(&priv
->pie_mutex
);
1970 /* Delete a range of Packet Inspection Engine rules */
1971 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
1973 u32 v
= (index_from
<< 1)| (index_to
<< 12 ) | BIT(0);
1975 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
1976 mutex_lock(&priv
->reg_mutex
);
1978 /* Write from-to and execute bit into control register */
1979 sw_w32(v
, RTL930X_PIE_CLR_CTRL
);
1981 /* Wait until command has completed */
1983 } while (sw_r32(RTL930X_PIE_CLR_CTRL
) & BIT(0));
1985 mutex_unlock(&priv
->reg_mutex
);
1989 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1993 rtl930x_pie_rule_del(priv
, idx
, idx
);
1994 clear_bit(idx
, priv
->pie_use_bm
);
1997 static void rtl930x_pie_init(struct rtl838x_switch_priv
*priv
)
1999 u32 template_selectors
;
2001 mutex_init(&priv
->pie_mutex
);
2003 pr_info("%s\n", __func__
);
2004 /* Enable ACL lookup on all ports, including CPU_PORT */
2005 for (int i
= 0; i
<= priv
->cpu_port
; i
++)
2006 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i
));
2008 /* Include IPG in metering */
2009 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL
);
2011 /* Delete all present rules, block size is 128 on all SoC families */
2012 rtl930x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* 128 - 1);
2014 /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */
2015 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL
);
2017 /* Enable predefined templates 0, 1 for first quarter of all blocks */
2018 template_selectors
= 0 | (1 << 4);
2019 for (int i
= 0; i
< priv
->n_pie_blocks
/ 4; i
++)
2020 sw_w32(template_selectors
, RTL930X_PIE_BLK_TMPLTE_CTRL(i
));
2022 /* Enable predefined templates 2, 3 for second quarter of all blocks */
2023 template_selectors
= 2 | (3 << 4);
2024 for (int i
= priv
->n_pie_blocks
/ 4; i
< priv
->n_pie_blocks
/ 2; i
++)
2025 sw_w32(template_selectors
, RTL930X_PIE_BLK_TMPLTE_CTRL(i
));
2027 /* Enable predefined templates 0, 1 for third half of all blocks */
2028 template_selectors
= 0 | (1 << 4);
2029 for (int i
= priv
->n_pie_blocks
/ 2; i
< priv
->n_pie_blocks
* 3 / 4; i
++)
2030 sw_w32(template_selectors
, RTL930X_PIE_BLK_TMPLTE_CTRL(i
));
2032 /* Enable predefined templates 2, 3 for fourth quater of all blocks */
2033 template_selectors
= 2 | (3 << 4);
2034 for (int i
= priv
->n_pie_blocks
* 3 / 4; i
< priv
->n_pie_blocks
; i
++)
2035 sw_w32(template_selectors
, RTL930X_PIE_BLK_TMPLTE_CTRL(i
));
2039 /* Sets up an egress interface for L3 actions
2040 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2041 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2043 * idx is the index in the HW interface table: idx < 0x80
2045 static void rtl930x_set_l3_egress_intf(int idx
, struct rtl838x_l3_intf
*intf
)
2048 /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */
2049 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 4);
2051 /* The table has 2 registers */
2052 u
= (intf
->vid
& 0xfff) << 9;
2053 u
|= (intf
->smac_idx
& 0x3f) << 3;
2054 u
|= (intf
->ip4_mtu_id
& 0x7);
2056 v
= (intf
->ip6_mtu_id
& 0x7) << 28;
2057 v
|= (intf
->ttl_scope
& 0xff) << 20;
2058 v
|= (intf
->hl_scope
& 0xff) << 12;
2059 v
|= (intf
->ip4_icmp_redirect
& 0x7) << 9;
2060 v
|= (intf
->ip6_icmp_redirect
& 0x7)<< 6;
2061 v
|= (intf
->ip4_pbr_icmp_redirect
& 0x7) << 3;
2062 v
|= (intf
->ip6_pbr_icmp_redirect
& 0x7);
2064 sw_w32(u
, rtl_table_data(r
, 0));
2065 sw_w32(v
, rtl_table_data(r
, 1));
2067 pr_info("%s writing to index %d: %08x %08x\n", __func__
, idx
, u
, v
);
2068 rtl_table_write(r
, idx
& 0x7f);
2069 rtl_table_release(r
);
2072 /* Reads a MAC entry for L3 termination as entry point for routing
2073 * from the hardware table
2074 * idx is the index into the L3_ROUTER_MAC table
2076 static void rtl930x_get_l3_router_mac(u32 idx
, struct rtl93xx_rt_mac
*m
)
2079 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2080 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 0);
2082 rtl_table_read(r
, idx
);
2083 /* The table has a size of 7 registers, 64 entries */
2084 v
= sw_r32(rtl_table_data(r
, 0));
2085 w
= sw_r32(rtl_table_data(r
, 3));
2086 m
->valid
= !!(v
& BIT(20));
2090 m
->p_type
= !!(v
& BIT(19));
2091 m
->p_id
= (v
>> 13) & 0x3f; /* trunk id of port */
2093 m
->vid_mask
= w
& 0xfff;
2094 m
->action
= sw_r32(rtl_table_data(r
, 6)) & 0x7;
2095 m
->mac_mask
= ((((u64
)sw_r32(rtl_table_data(r
, 5))) << 32) & 0xffffffffffffULL
) |
2096 (sw_r32(rtl_table_data(r
, 4)));
2097 m
->mac
= ((((u64
)sw_r32(rtl_table_data(r
, 1))) << 32) & 0xffffffffffffULL
) |
2098 (sw_r32(rtl_table_data(r
, 2)));
2099 /* Bits L3_INTF and BMSK_L3_INTF are 0 */
2102 rtl_table_release(r
);
2105 /* Writes a MAC entry for L3 termination as entry point for routing
2106 * into the hardware table
2107 * idx is the index into the L3_ROUTER_MAC table
2109 static void rtl930x_set_l3_router_mac(u32 idx
, struct rtl93xx_rt_mac
*m
)
2112 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2113 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_1
, 0);
2115 /* The table has a size of 7 registers, 64 entries */
2116 v
= BIT(20); /* mac entry valid, port type is 0: individual */
2117 v
|= (m
->p_id
& 0x3f) << 13;
2118 v
|= (m
->vid
& 0xfff); /* Set the interface_id to the vlan id */
2121 w
|= (m
->p_id_mask
& 0x3f) << 13;
2123 sw_w32(v
, rtl_table_data(r
, 0));
2124 sw_w32(w
, rtl_table_data(r
, 3));
2126 /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */
2127 sw_w32((u32
)(m
->mac
), rtl_table_data(r
, 2));
2128 sw_w32(m
->mac
>> 32, rtl_table_data(r
, 1));
2130 /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */
2131 sw_w32((u32
)(m
->mac_mask
>> 32), rtl_table_data(r
, 4));
2132 sw_w32((u32
)m
->mac_mask
, rtl_table_data(r
, 5));
2134 sw_w32(m
->action
& 0x7, rtl_table_data(r
, 6));
2136 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__
, idx
,
2137 sw_r32(rtl_table_data(r
, 0)), sw_r32(rtl_table_data(r
, 1)), sw_r32(rtl_table_data(r
, 2)),
2138 sw_r32(rtl_table_data(r
, 3)), sw_r32(rtl_table_data(r
, 4)), sw_r32(rtl_table_data(r
, 5)),
2139 sw_r32(rtl_table_data(r
, 6))
2141 rtl_table_write(r
, idx
);
2142 rtl_table_release(r
);
2145 /* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2146 * from the SoC's L3_EGR_INTF_MAC table
2147 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2149 static u64
rtl930x_get_l3_egress_mac(u32 idx
)
2152 /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2153 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_2
, 2);
2155 rtl_table_read(r
, idx
);
2156 /* The table has a size of 2 registers */
2157 mac
= sw_r32(rtl_table_data(r
, 0));
2159 mac
|= sw_r32(rtl_table_data(r
, 1));
2160 rtl_table_release(r
);
2165 /* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2166 * in the SoC's L3_EGR_INTF_MAC table
2167 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2169 static void rtl930x_set_l3_egress_mac(u32 idx
, u64 mac
)
2171 /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2172 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_2
, 2);
2174 /* The table has a size of 2 registers */
2175 sw_w32(mac
>> 32, rtl_table_data(r
, 0));
2176 sw_w32(mac
, rtl_table_data(r
, 1));
2178 pr_debug("%s: setting index %d to %016llx\n", __func__
, idx
, mac
);
2179 rtl_table_write(r
, idx
);
2180 rtl_table_release(r
);
2183 /* Configure L3 routing settings of the device:
2185 * - Egress interface
2186 * - The router's MAC address on which routed packets are expected
2187 * - MAC addresses used as source macs of routed packets
2189 int rtl930x_l3_setup(struct rtl838x_switch_priv
*priv
)
2191 /* Setup MTU with id 0 for default interface */
2192 for (int i
= 0; i
< MAX_INTF_MTUS
; i
++)
2193 priv
->intf_mtu_count
[i
] = priv
->intf_mtus
[i
] = 0;
2195 priv
->intf_mtu_count
[0] = 0; /* Needs to stay forever */
2196 priv
->intf_mtus
[0] = DEFAULT_MTU
;
2197 sw_w32_mask(0xffff, DEFAULT_MTU
, RTL930X_L3_IP_MTU_CTRL(0));
2198 sw_w32_mask(0xffff, DEFAULT_MTU
, RTL930X_L3_IP6_MTU_CTRL(0));
2199 priv
->intf_mtus
[1] = DEFAULT_MTU
;
2200 sw_w32_mask(0xffff0000, DEFAULT_MTU
<< 16, RTL930X_L3_IP_MTU_CTRL(0));
2201 sw_w32_mask(0xffff0000, DEFAULT_MTU
<< 16, RTL930X_L3_IP6_MTU_CTRL(0));
2203 sw_w32_mask(0xffff, DEFAULT_MTU
, RTL930X_L3_IP_MTU_CTRL(1));
2204 sw_w32_mask(0xffff, DEFAULT_MTU
, RTL930X_L3_IP6_MTU_CTRL(1));
2205 sw_w32_mask(0xffff0000, DEFAULT_MTU
<< 16, RTL930X_L3_IP_MTU_CTRL(1));
2206 sw_w32_mask(0xffff0000, DEFAULT_MTU
<< 16, RTL930X_L3_IP6_MTU_CTRL(1));
2208 /* Clear all source port MACs */
2209 for (int i
= 0; i
< MAX_SMACS
; i
++)
2210 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS
+ i
, 0ULL);
2212 /* Configure the default L3 hash algorithm */
2213 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL
); /* Algorithm selection 0 = 0 */
2214 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL
); /* Algorithm selection 1 = 1 */
2216 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2217 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL
), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL
),
2218 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL
), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL
));
2219 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL
);
2220 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL
);
2221 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL
);
2222 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL
);
2224 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL
);
2225 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL
);
2226 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL
);
2227 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL
);
2229 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2230 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL
), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL
),
2231 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL
), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL
));
2233 /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */
2234 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL
);
2235 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL
));
2237 /* PORT_ISO_RESTRICT_ROUTE_CTRL? */
2239 /* Do not use prefix route 0 because of HW limitations */
2240 set_bit(0, priv
->route_use_bm
);
2245 static u32
rtl930x_packet_cntr_read(int counter
)
2249 /* Read LOG table (3) via register RTL9300_TBL_0 */
2250 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 3);
2252 pr_debug("In %s, id %d\n", __func__
, counter
);
2253 rtl_table_read(r
, counter
/ 2);
2255 pr_debug("Registers: %08x %08x\n",
2256 sw_r32(rtl_table_data(r
, 0)), sw_r32(rtl_table_data(r
, 1)));
2257 /* The table has a size of 2 registers */
2259 v
= sw_r32(rtl_table_data(r
, 0));
2261 v
= sw_r32(rtl_table_data(r
, 1));
2263 rtl_table_release(r
);
2268 static void rtl930x_packet_cntr_clear(int counter
)
2270 /* Access LOG table (3) via register RTL9300_TBL_0 */
2271 struct table_reg
*r
= rtl_table_get(RTL9300_TBL_0
, 3);
2273 pr_info("In %s, id %d\n", __func__
, counter
);
2274 /* The table has a size of 2 registers */
2276 sw_w32(0, rtl_table_data(r
, 0));
2278 sw_w32(0, rtl_table_data(r
, 1));
2280 rtl_table_write(r
, counter
/ 2);
2282 rtl_table_release(r
);
2285 void rtl930x_vlan_port_keep_tag_set(int port
, bool keep_outer
, bool keep_inner
)
2287 sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK
,
2288 keep_outer
? RTL930X_VLAN_PORT_TAG_STS_TAGGED
: RTL930X_VLAN_PORT_TAG_STS_UNTAG
) |
2289 FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK
,
2290 keep_inner
? RTL930X_VLAN_PORT_TAG_STS_TAGGED
: RTL930X_VLAN_PORT_TAG_STS_UNTAG
),
2291 RTL930X_VLAN_PORT_TAG_STS_CTRL(port
));
2294 void rtl930x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
2296 if (type
== PBVLAN_TYPE_INNER
)
2297 sw_w32_mask(0x3, mode
, RTL930X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
2299 sw_w32_mask(0x3 << 14, mode
<< 14 ,RTL930X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
2302 void rtl930x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
2304 if (type
== PBVLAN_TYPE_INNER
)
2305 sw_w32_mask(0xfff << 2, pvid
<< 2, RTL930X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
2307 sw_w32_mask(0xfff << 16, pvid
<< 16, RTL930X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
2310 static int rtl930x_set_ageing_time(unsigned long msec
)
2312 int t
= sw_r32(RTL930X_L2_AGE_CTRL
);
2316 pr_debug("L2 AGING time: %d sec\n", t
);
2318 t
= (msec
/ 100 + 6) / 7;
2319 t
= t
> 0x1FFFFF ? 0x1FFFFF : t
;
2320 sw_w32_mask(0x1FFFFF, t
, RTL930X_L2_AGE_CTRL
);
2321 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL
));
2326 static void rtl930x_set_igr_filter(int port
, enum igr_filter state
)
2328 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
2329 RTL930X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
2332 static void rtl930x_set_egr_filter(int port
, enum egr_filter state
)
2334 sw_w32_mask(0x1 << (port
% 0x1D), state
<< (port
% 0x1D),
2335 RTL930X_VLAN_PORT_EGR_FLTR
+ (((port
/ 29) << 2)));
2338 void rtl930x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
2343 /* TODO: for now we set algoidx to 0 */
2345 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SIP_BIT
) {
2347 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT
;
2349 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_DIP_BIT
) {
2351 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT
;
2353 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT
) {
2355 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT
;
2357 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT
) {
2359 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT
;
2363 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SMAC_BIT
)
2364 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT
;
2366 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_DMAC_BIT
)
2367 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT
;
2369 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SMAC_BIT
)
2370 newmask
|= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT
;
2371 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_DMAC_BIT
)
2372 newmask
|= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT
;
2375 sw_w32(newmask
<< l3shift
, RTL930X_TRK_HASH_CTRL
+ (algoidx
<< 2));
2378 static void rtl930x_led_init(struct rtl838x_switch_priv
*priv
)
2380 struct device_node
*node
;
2383 pr_info("%s called\n", __func__
);
2384 node
= of_find_compatible_node(NULL
, NULL
, "realtek,rtl9300-leds");
2386 pr_info("%s No compatible LED node found\n", __func__
);
2390 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
2391 int pos
= (i
<< 1) % 32;
2395 sw_w32_mask(0x3 << pos
, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i
));
2396 sw_w32_mask(0x3 << pos
, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i
));
2398 if (!priv
->ports
[i
].phy
)
2402 if (priv
->ports
[i
].is10G
)
2404 if (priv
->ports
[i
].phy_is_integrated
)
2406 sw_w32_mask(0x3 << pos
, v
<< pos
, RTL930X_LED_PORT_NUM_CTRL(i
));
2410 set
= priv
->ports
[i
].led_set
;
2411 sw_w32_mask(0, set
<< pos
, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i
));
2412 sw_w32_mask(0, set
<< pos
, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i
));
2415 for (int i
= 0; i
< 4; i
++) {
2416 const __be32
*led_set
;
2421 sprintf(set_name
, "led_set%d", i
);
2422 led_set
= of_get_property(node
, set_name
, &setlen
);
2423 if (!led_set
|| setlen
!= 16)
2425 v
= be32_to_cpup(led_set
) << 16 | be32_to_cpup(led_set
+ 1);
2426 sw_w32(v
, RTL930X_LED_SET0_0_CTRL
- 4 - i
* 8);
2427 v
= be32_to_cpup(led_set
+ 2) << 16 | be32_to_cpup(led_set
+ 3);
2428 sw_w32(v
, RTL930X_LED_SET0_0_CTRL
- i
* 8);
2431 /* Set LED mode to serial (0x1) */
2432 sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL
);
2434 /* Set port type masks */
2435 sw_w32(pm
, RTL930X_LED_PORT_COPR_MASK_CTRL
);
2436 sw_w32(pm
, RTL930X_LED_PORT_FIB_MASK_CTRL
);
2437 sw_w32(pm
, RTL930X_LED_PORT_COMBO_MASK_CTRL
);
2439 for (int i
= 0; i
< 24; i
++)
2440 pr_info("%s %08x: %08x\n",__func__
, 0xbb00cc00 + i
* 4, sw_r32(0xcc00 + i
* 4));
2443 const struct rtl838x_reg rtl930x_reg
= {
2444 .mask_port_reg_be
= rtl838x_mask_port_reg
,
2445 .set_port_reg_be
= rtl838x_set_port_reg
,
2446 .get_port_reg_be
= rtl838x_get_port_reg
,
2447 .mask_port_reg_le
= rtl838x_mask_port_reg
,
2448 .set_port_reg_le
= rtl838x_set_port_reg
,
2449 .get_port_reg_le
= rtl838x_get_port_reg
,
2450 .stat_port_rst
= RTL930X_STAT_PORT_RST
,
2451 .stat_rst
= RTL930X_STAT_RST
,
2452 .stat_port_std_mib
= RTL930X_STAT_PORT_MIB_CNTR
,
2453 .traffic_enable
= rtl930x_traffic_enable
,
2454 .traffic_disable
= rtl930x_traffic_disable
,
2455 .traffic_get
= rtl930x_traffic_get
,
2456 .traffic_set
= rtl930x_traffic_set
,
2457 .l2_ctrl_0
= RTL930X_L2_CTRL
,
2458 .l2_ctrl_1
= RTL930X_L2_AGE_CTRL
,
2459 .l2_port_aging_out
= RTL930X_L2_PORT_AGE_CTRL
,
2460 .set_ageing_time
= rtl930x_set_ageing_time
,
2461 .smi_poll_ctrl
= RTL930X_SMI_POLL_CTRL
, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */
2462 .l2_tbl_flush_ctrl
= RTL930X_L2_TBL_FLUSH_CTRL
,
2463 .exec_tbl0_cmd
= rtl930x_exec_tbl0_cmd
,
2464 .exec_tbl1_cmd
= rtl930x_exec_tbl1_cmd
,
2465 .tbl_access_data_0
= rtl930x_tbl_access_data_0
,
2466 .isr_glb_src
= RTL930X_ISR_GLB
,
2467 .isr_port_link_sts_chg
= RTL930X_ISR_PORT_LINK_STS_CHG
,
2468 .imr_port_link_sts_chg
= RTL930X_IMR_PORT_LINK_STS_CHG
,
2469 .imr_glb
= RTL930X_IMR_GLB
,
2470 .vlan_tables_read
= rtl930x_vlan_tables_read
,
2471 .vlan_set_tagged
= rtl930x_vlan_set_tagged
,
2472 .vlan_set_untagged
= rtl930x_vlan_set_untagged
,
2473 .vlan_profile_dump
= rtl930x_vlan_profile_dump
,
2474 .vlan_profile_setup
= rtl930x_vlan_profile_setup
,
2475 .vlan_fwd_on_inner
= rtl930x_vlan_fwd_on_inner
,
2476 .set_vlan_igr_filter
= rtl930x_set_igr_filter
,
2477 .set_vlan_egr_filter
= rtl930x_set_egr_filter
,
2478 .stp_get
= rtl930x_stp_get
,
2479 .stp_set
= rtl930x_stp_set
,
2480 .mac_force_mode_ctrl
= rtl930x_mac_force_mode_ctrl
,
2481 .mac_port_ctrl
= rtl930x_mac_port_ctrl
,
2482 .l2_port_new_salrn
= rtl930x_l2_port_new_salrn
,
2483 .l2_port_new_sa_fwd
= rtl930x_l2_port_new_sa_fwd
,
2484 .mir_ctrl
= RTL930X_MIR_CTRL
,
2485 .mir_dpm
= RTL930X_MIR_DPM_CTRL
,
2486 .mir_spm
= RTL930X_MIR_SPM_CTRL
,
2487 .mac_link_sts
= RTL930X_MAC_LINK_STS
,
2488 .mac_link_dup_sts
= RTL930X_MAC_LINK_DUP_STS
,
2489 .mac_link_spd_sts
= rtl930x_mac_link_spd_sts
,
2490 .mac_rx_pause_sts
= RTL930X_MAC_RX_PAUSE_STS
,
2491 .mac_tx_pause_sts
= RTL930X_MAC_TX_PAUSE_STS
,
2492 .read_l2_entry_using_hash
= rtl930x_read_l2_entry_using_hash
,
2493 .write_l2_entry_using_hash
= rtl930x_write_l2_entry_using_hash
,
2494 .read_cam
= rtl930x_read_cam
,
2495 .write_cam
= rtl930x_write_cam
,
2496 .vlan_port_keep_tag_set
= rtl930x_vlan_port_keep_tag_set
,
2497 .vlan_port_pvidmode_set
= rtl930x_vlan_port_pvidmode_set
,
2498 .vlan_port_pvid_set
= rtl930x_vlan_port_pvid_set
,
2499 .trk_mbr_ctr
= rtl930x_trk_mbr_ctr
,
2500 .rma_bpdu_fld_pmask
= RTL930X_RMA_BPDU_FLD_PMSK
,
2501 .init_eee
= rtl930x_init_eee
,
2502 .port_eee_set
= rtl930x_port_eee_set
,
2503 .eee_port_ability
= rtl930x_eee_port_ability
,
2504 .l2_hash_seed
= rtl930x_l2_hash_seed
,
2505 .l2_hash_key
= rtl930x_l2_hash_key
,
2506 .read_mcast_pmask
= rtl930x_read_mcast_pmask
,
2507 .write_mcast_pmask
= rtl930x_write_mcast_pmask
,
2508 .pie_init
= rtl930x_pie_init
,
2509 .pie_rule_write
= rtl930x_pie_rule_write
,
2510 .pie_rule_add
= rtl930x_pie_rule_add
,
2511 .pie_rule_rm
= rtl930x_pie_rule_rm
,
2512 .l2_learning_setup
= rtl930x_l2_learning_setup
,
2513 .packet_cntr_read
= rtl930x_packet_cntr_read
,
2514 .packet_cntr_clear
= rtl930x_packet_cntr_clear
,
2515 .route_read
= rtl930x_route_read
,
2516 .route_write
= rtl930x_route_write
,
2517 .host_route_write
= rtl930x_host_route_write
,
2518 .l3_setup
= rtl930x_l3_setup
,
2519 .set_l3_nexthop
= rtl930x_set_l3_nexthop
,
2520 .get_l3_nexthop
= rtl930x_get_l3_nexthop
,
2521 .get_l3_egress_mac
= rtl930x_get_l3_egress_mac
,
2522 .set_l3_egress_mac
= rtl930x_set_l3_egress_mac
,
2523 .find_l3_slot
= rtl930x_find_l3_slot
,
2524 .route_lookup_hw
= rtl930x_route_lookup_hw
,
2525 .get_l3_router_mac
= rtl930x_get_l3_router_mac
,
2526 .set_l3_router_mac
= rtl930x_set_l3_router_mac
,
2527 .set_l3_egress_intf
= rtl930x_set_l3_egress_intf
,
2528 .set_distribution_algorithm
= rtl930x_set_distribution_algorithm
,
2529 .led_init
= rtl930x_led_init
,