1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/net/ethernet/rtl838x_eth.c
3 * Copyright (C) 2020 B. Koblitz
6 #include <linux/dma-mapping.h>
7 #include <linux/etherdevice.h>
8 #include <linux/interrupt.h>
10 #include <linux/platform_device.h>
11 #include <linux/sched.h>
12 #include <linux/slab.h>
14 #include <linux/of_net.h>
15 #include <linux/of_mdio.h>
16 #include <linux/module.h>
17 #include <linux/phylink.h>
18 #include <linux/pkt_sched.h>
20 #include <net/switchdev.h>
21 #include <asm/cacheflush.h>
23 #include <asm/mach-rtl838x/mach-rtl83xx.h>
24 #include "rtl838x_eth.h"
26 extern struct rtl83xx_soc_info soc_info
;
28 /* Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
29 * The ring is assigned by switch based on packet/port priortity
30 * Maximum number of TX rings is 2, Ring 2 being the high priority
31 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
32 * for an RX ring, MAX_ENTRIES the maximum number of entries
33 * available in total for all queues.
35 #define MAX_RXRINGS 32
37 #define MAX_ENTRIES (300 * 8)
40 #define NOTIFY_EVENTS 10
41 #define NOTIFY_BLOCKS 10
44 #define TX_EN_93XX 0x20
45 #define RX_EN_93XX 0x10
46 #define RX_TRUNCATE_EN_93XX BIT(6)
47 #define RX_TRUNCATE_EN_83XX BIT(4)
48 #define TX_PAD_EN_838X BIT(5)
52 #define MAX_SMI_BUSSES 4
54 #define RING_BUFFER 1600
59 uint16_t size
; /* buffer size */
61 uint16_t len
; /* pkt len */
62 /* cpu_tag[0] is a reserved uint16_t on RTL83xx */
64 } __packed
__aligned(1);
73 } __packed
__aligned(1);
76 uint32_t rx_r
[MAX_RXRINGS
][MAX_RXLEN
];
77 uint32_t tx_r
[TXRINGS
][TXRINGLEN
];
78 struct p_hdr rx_header
[MAX_RXRINGS
][MAX_RXLEN
];
79 struct p_hdr tx_header
[TXRINGS
][TXRINGLEN
];
80 uint32_t c_rx
[MAX_RXRINGS
];
81 uint32_t c_tx
[TXRINGS
];
82 uint8_t tx_space
[TXRINGS
* TXRINGLEN
* RING_BUFFER
];
87 struct n_event events
[NOTIFY_EVENTS
];
91 struct notify_block blocks
[NOTIFY_BLOCKS
];
93 u32 ring
[NOTIFY_BLOCKS
];
97 static void rtl838x_create_tx_header(struct p_hdr
*h
, unsigned int dest_port
, int prio
)
99 /* cpu_tag[0] is reserved on the RTL83XX SoCs */
100 h
->cpu_tag
[1] = 0x0400; /* BIT 10: RTL8380_CPU_TAG */
101 h
->cpu_tag
[2] = 0x0200; /* Set only AS_DPM, to enable DPM settings below */
102 h
->cpu_tag
[3] = 0x0000;
103 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
104 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
106 /* Set internal priority (PRI) and enable (AS_PRI) */
108 h
->cpu_tag
[2] |= ((prio
& 0x7) | BIT(3)) << 12;
111 static void rtl839x_create_tx_header(struct p_hdr
*h
, unsigned int dest_port
, int prio
)
113 /* cpu_tag[0] is reserved on the RTL83XX SoCs */
114 h
->cpu_tag
[1] = 0x0100; /* RTL8390_CPU_TAG marker */
115 h
->cpu_tag
[2] = BIT(4); /* AS_DPM flag */
116 h
->cpu_tag
[3] = h
->cpu_tag
[4] = h
->cpu_tag
[5] = 0;
117 /* h->cpu_tag[1] |= BIT(1) | BIT(0); */ /* Bypass filter 1/2 */
118 if (dest_port
>= 32) {
120 h
->cpu_tag
[2] |= (BIT(dest_port
) >> 16) & 0xf;
121 h
->cpu_tag
[3] = BIT(dest_port
) & 0xffff;
123 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
124 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
127 /* Set internal priority (PRI) and enable (AS_PRI) */
129 h
->cpu_tag
[2] |= ((prio
& 0x7) | BIT(3)) << 8;
132 static void rtl930x_create_tx_header(struct p_hdr
*h
, unsigned int dest_port
, int prio
)
134 h
->cpu_tag
[0] = 0x8000; /* CPU tag marker */
135 h
->cpu_tag
[1] = h
->cpu_tag
[2] = 0;
139 h
->cpu_tag
[6] = BIT(dest_port
) >> 16;
140 h
->cpu_tag
[7] = BIT(dest_port
) & 0xffff;
142 /* Enable (AS_QID) and set priority queue (QID) */
144 h
->cpu_tag
[2] = (BIT(5) | (prio
& 0x1f)) << 8;
147 static void rtl931x_create_tx_header(struct p_hdr
*h
, unsigned int dest_port
, int prio
)
149 h
->cpu_tag
[0] = 0x8000; /* CPU tag marker */
150 h
->cpu_tag
[1] = h
->cpu_tag
[2] = 0;
152 h
->cpu_tag
[4] = h
->cpu_tag
[5] = h
->cpu_tag
[6] = h
->cpu_tag
[7] = 0;
153 if (dest_port
>= 32) {
155 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
156 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
158 h
->cpu_tag
[6] = BIT(dest_port
) >> 16;
159 h
->cpu_tag
[7] = BIT(dest_port
) & 0xffff;
162 /* Enable (AS_QID) and set priority queue (QID) */
164 h
->cpu_tag
[2] = (BIT(5) | (prio
& 0x1f)) << 8;
168 // static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
170 // h->cpu_tag[2] |= BIT(4); /* Enable VLAN forwarding offload */
171 // h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 // h->cpu_tag[3] |= (vlan & 0xff) << 8;
175 struct rtl838x_rx_q
{
177 struct rtl838x_eth_priv
*priv
;
178 struct napi_struct napi
;
181 struct rtl838x_eth_priv
{
182 struct net_device
*netdev
;
183 struct platform_device
*pdev
;
186 struct mii_bus
*mii_bus
;
187 struct rtl838x_rx_q rx_qs
[MAX_RXRINGS
];
188 struct phylink
*phylink
;
189 struct phylink_config phylink_config
;
192 const struct rtl838x_eth_reg
*r
;
197 u8 smi_bus
[MAX_PORTS
];
198 u8 smi_addr
[MAX_PORTS
];
199 u32 sds_id
[MAX_PORTS
];
200 bool smi_bus_isc45
[MAX_SMI_BUSSES
];
201 bool phy_is_internal
[MAX_PORTS
];
202 phy_interface_t interfaces
[MAX_PORTS
];
205 extern int rtl838x_phy_init(struct rtl838x_eth_priv
*priv
);
206 extern int rtl838x_read_sds_phy(int phy_addr
, int phy_reg
);
207 extern int rtl839x_read_sds_phy(int phy_addr
, int phy_reg
);
208 extern int rtl839x_write_sds_phy(int phy_addr
, int phy_reg
, u16 v
);
209 extern int rtl930x_read_sds_phy(int phy_addr
, int page
, int phy_reg
);
210 extern int rtl930x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
);
211 extern int rtl931x_read_sds_phy(int phy_addr
, int page
, int phy_reg
);
212 extern int rtl931x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
);
213 extern int rtl930x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
214 extern int rtl930x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
);
215 extern int rtl931x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
216 extern int rtl931x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
);
218 /* On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
219 * the rings. Writing x into these registers substracts x from its content.
220 * When the content reaches the ring size, the ASIC no longer adds
221 * packets to this receive queue.
223 void rtl838x_update_cntr(int r
, int released
)
225 /* This feature is not available on RTL838x SoCs */
228 void rtl839x_update_cntr(int r
, int released
)
230 /* This feature is not available on RTL839x SoCs */
233 void rtl930x_update_cntr(int r
, int released
)
235 int pos
= (r
% 3) * 10;
236 u32 reg
= RTL930X_DMA_IF_RX_RING_CNTR
+ ((r
/ 3) << 2);
239 v
= (v
>> pos
) & 0x3ff;
240 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released
, v
, pos
, reg
);
241 sw_w32_mask(0x3ff << pos
, released
<< pos
, reg
);
245 void rtl931x_update_cntr(int r
, int released
)
247 int pos
= (r
% 3) * 10;
248 u32 reg
= RTL931X_DMA_IF_RX_RING_CNTR
+ ((r
/ 3) << 2);
251 v
= (v
>> pos
) & 0x3ff;
252 sw_w32_mask(0x3ff << pos
, released
<< pos
, reg
);
265 bool rtl838x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
267 /* cpu_tag[0] is reserved. Fields are off-by-one */
268 t
->reason
= h
->cpu_tag
[4] & 0xf;
269 t
->queue
= (h
->cpu_tag
[1] & 0xe0) >> 5;
270 t
->port
= h
->cpu_tag
[1] & 0x1f;
271 t
->crc_error
= t
->reason
== 13;
273 pr_debug("Reason: %d\n", t
->reason
);
274 if (t
->reason
!= 6) /* NIC_RX_REASON_SPECIAL_TRAP */
279 return t
->l2_offloaded
;
282 bool rtl839x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
284 /* cpu_tag[0] is reserved. Fields are off-by-one */
285 t
->reason
= h
->cpu_tag
[5] & 0x1f;
286 t
->queue
= (h
->cpu_tag
[4] & 0xe000) >> 13;
287 t
->port
= h
->cpu_tag
[1] & 0x3f;
288 t
->crc_error
= h
->cpu_tag
[4] & BIT(6);
290 pr_debug("Reason: %d\n", t
->reason
);
291 if ((t
->reason
>= 7 && t
->reason
<= 13) || /* NIC_RX_REASON_RMA */
292 (t
->reason
>= 23 && t
->reason
<= 25)) /* NIC_RX_REASON_SPECIAL_TRAP */
297 return t
->l2_offloaded
;
300 bool rtl930x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
302 t
->reason
= h
->cpu_tag
[7] & 0x3f;
303 t
->queue
= (h
->cpu_tag
[2] >> 11) & 0x1f;
304 t
->port
= (h
->cpu_tag
[0] >> 8) & 0x1f;
305 t
->crc_error
= h
->cpu_tag
[1] & BIT(6);
307 pr_debug("Reason %d, port %d, queue %d\n", t
->reason
, t
->port
, t
->queue
);
308 if (t
->reason
>= 19 && t
->reason
<= 27)
313 return t
->l2_offloaded
;
316 bool rtl931x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
318 t
->reason
= h
->cpu_tag
[7] & 0x3f;
319 t
->queue
= (h
->cpu_tag
[2] >> 11) & 0x1f;
320 t
->port
= (h
->cpu_tag
[0] >> 8) & 0x3f;
321 t
->crc_error
= h
->cpu_tag
[1] & BIT(6);
324 pr_info("%s: Reason %d, port %d, queue %d\n", __func__
, t
->reason
, t
->port
, t
->queue
);
325 if (t
->reason
>= 19 && t
->reason
<= 27) /* NIC_RX_REASON_RMA */
330 return t
->l2_offloaded
;
333 /* Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv
*priv
, int status
)
338 for (int r
= 0; r
< priv
->rxrings
; r
++) {
339 struct ring_b
*ring
= priv
->membase
;
343 pr_debug("In %s working on r: %d\n", __func__
, r
);
344 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
346 if ((ring
->rx_r
[r
][ring
->c_rx
[r
]] & 0x1))
348 pr_debug("Got something: %d\n", ring
->c_rx
[r
]);
349 h
= &ring
->rx_header
[r
][ring
->c_rx
[r
]];
350 memset(h
, 0, sizeof(struct p_hdr
));
351 h
->buf
= (u8
*)KSEG1ADDR(ring
->rx_space
+
352 r
* priv
->rxringlen
* RING_BUFFER
+
353 ring
->c_rx
[r
] * RING_BUFFER
);
354 h
->size
= RING_BUFFER
;
355 /* make sure the header is visible to the ASIC */
358 ring
->rx_r
[r
][ring
->c_rx
[r
]] = KSEG1ADDR(h
) | 0x1 | (ring
->c_rx
[r
] == (priv
->rxringlen
- 1) ?
361 ring
->c_rx
[r
] = (ring
->c_rx
[r
] + 1) % priv
->rxringlen
;
362 } while (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
);
366 struct fdb_update_work
{
367 struct work_struct work
;
368 struct net_device
*ndev
;
369 u64 macs
[NOTIFY_EVENTS
+ 1];
372 void rtl838x_fdb_sync(struct work_struct
*work
)
374 const struct fdb_update_work
*uw
= container_of(work
, struct fdb_update_work
, work
);
376 for (int i
= 0; uw
->macs
[i
]; i
++) {
377 struct switchdev_notifier_fdb_info info
;
381 action
= (uw
->macs
[i
] & (1ULL << 63)) ?
382 SWITCHDEV_FDB_ADD_TO_BRIDGE
:
383 SWITCHDEV_FDB_DEL_TO_BRIDGE
;
384 u64_to_ether_addr(uw
->macs
[i
] & 0xffffffffffffULL
, addr
);
385 info
.addr
= &addr
[0];
388 pr_debug("FDB entry %d: %llx, action %d\n", i
, uw
->macs
[0], action
);
389 call_switchdev_notifiers(action
, uw
->ndev
, &info
.info
, NULL
);
394 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv
*priv
)
396 struct notify_b
*nb
= priv
->membase
+ sizeof(struct ring_b
);
397 u32 e
= priv
->lastEvent
;
399 while (!(nb
->ring
[e
] & 1)) {
400 struct fdb_update_work
*w
;
401 struct n_event
*event
;
405 w
= kzalloc(sizeof(*w
), GFP_ATOMIC
);
407 pr_err("Out of memory: %s", __func__
);
410 INIT_WORK(&w
->work
, rtl838x_fdb_sync
);
412 for (i
= 0; i
< NOTIFY_EVENTS
; i
++) {
413 event
= &nb
->blocks
[e
].events
[i
];
419 w
->ndev
= priv
->netdev
;
423 /* Hand the ring entry back to the switch */
424 nb
->ring
[e
] = nb
->ring
[e
] | 1;
425 e
= (e
+ 1) % NOTIFY_BLOCKS
;
428 schedule_work(&w
->work
);
433 static irqreturn_t
rtl83xx_net_irq(int irq
, void *dev_id
)
435 struct net_device
*dev
= dev_id
;
436 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
437 u32 status
= sw_r32(priv
->r
->dma_if_intr_sts
);
439 pr_debug("IRQ: %08x\n", status
);
441 /* Ignore TX interrupt */
442 if ((status
& 0xf0000)) {
444 sw_w32(0x000f0000, priv
->r
->dma_if_intr_sts
);
448 if (status
& 0x0ff00) {
449 /* ACK and disable RX interrupt for this ring */
450 sw_w32_mask(0xff00 & status
, 0, priv
->r
->dma_if_intr_msk
);
451 sw_w32(0x0000ff00 & status
, priv
->r
->dma_if_intr_sts
);
452 for (int i
= 0; i
< priv
->rxrings
; i
++) {
453 if (status
& BIT(i
+ 8)) {
454 pr_debug("Scheduling queue: %d\n", i
);
455 napi_schedule(&priv
->rx_qs
[i
].napi
);
460 /* RX buffer overrun */
461 if (status
& 0x000ff) {
462 pr_debug("RX buffer overrun: status %x, mask: %x\n",
463 status
, sw_r32(priv
->r
->dma_if_intr_msk
));
464 sw_w32(status
, priv
->r
->dma_if_intr_sts
);
465 rtl838x_rb_cleanup(priv
, status
& 0xff);
468 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00100000) {
469 sw_w32(0x00100000, priv
->r
->dma_if_intr_sts
);
470 rtl839x_l2_notification_handler(priv
);
473 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00200000) {
474 sw_w32(0x00200000, priv
->r
->dma_if_intr_sts
);
475 rtl839x_l2_notification_handler(priv
);
478 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00400000) {
479 sw_w32(0x00400000, priv
->r
->dma_if_intr_sts
);
480 rtl839x_l2_notification_handler(priv
);
486 static irqreturn_t
rtl93xx_net_irq(int irq
, void *dev_id
)
488 struct net_device
*dev
= dev_id
;
489 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
490 u32 status_rx_r
= sw_r32(priv
->r
->dma_if_intr_rx_runout_sts
);
491 u32 status_rx
= sw_r32(priv
->r
->dma_if_intr_rx_done_sts
);
492 u32 status_tx
= sw_r32(priv
->r
->dma_if_intr_tx_done_sts
);
494 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
495 __func__
, status_tx
, status_rx
, status_rx_r
);
497 /* Ignore TX interrupt */
500 pr_debug("TX done\n");
501 sw_w32(status_tx
, priv
->r
->dma_if_intr_tx_done_sts
);
506 pr_debug("RX IRQ\n");
507 /* ACK and disable RX interrupt for given rings */
508 sw_w32(status_rx
, priv
->r
->dma_if_intr_rx_done_sts
);
509 sw_w32_mask(status_rx
, 0, priv
->r
->dma_if_intr_rx_done_msk
);
510 for (int i
= 0; i
< priv
->rxrings
; i
++) {
511 if (status_rx
& BIT(i
)) {
512 pr_debug("Scheduling queue: %d\n", i
);
513 napi_schedule(&priv
->rx_qs
[i
].napi
);
518 /* RX buffer overrun */
520 pr_debug("RX buffer overrun: status %x, mask: %x\n",
521 status_rx_r
, sw_r32(priv
->r
->dma_if_intr_rx_runout_msk
));
522 sw_w32(status_rx_r
, priv
->r
->dma_if_intr_rx_runout_sts
);
523 rtl838x_rb_cleanup(priv
, status_rx_r
);
529 static const struct rtl838x_eth_reg rtl838x_reg
= {
530 .net_irq
= rtl83xx_net_irq
,
531 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
532 .dma_if_intr_sts
= RTL838X_DMA_IF_INTR_STS
,
533 .dma_if_intr_msk
= RTL838X_DMA_IF_INTR_MSK
,
534 .dma_if_ctrl
= RTL838X_DMA_IF_CTRL
,
535 .mac_force_mode_ctrl
= RTL838X_MAC_FORCE_MODE_CTRL
,
536 .dma_rx_base
= RTL838X_DMA_RX_BASE
,
537 .dma_tx_base
= RTL838X_DMA_TX_BASE
,
538 .dma_if_rx_ring_size
= rtl838x_dma_if_rx_ring_size
,
539 .dma_if_rx_ring_cntr
= rtl838x_dma_if_rx_ring_cntr
,
540 .dma_if_rx_cur
= RTL838X_DMA_IF_RX_CUR
,
541 .rst_glb_ctrl
= RTL838X_RST_GLB_CTRL_0
,
542 .get_mac_link_sts
= rtl838x_get_mac_link_sts
,
543 .get_mac_link_dup_sts
= rtl838x_get_mac_link_dup_sts
,
544 .get_mac_link_spd_sts
= rtl838x_get_mac_link_spd_sts
,
545 .get_mac_rx_pause_sts
= rtl838x_get_mac_rx_pause_sts
,
546 .get_mac_tx_pause_sts
= rtl838x_get_mac_tx_pause_sts
,
548 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
549 .update_cntr
= rtl838x_update_cntr
,
550 .create_tx_header
= rtl838x_create_tx_header
,
551 .decode_tag
= rtl838x_decode_tag
,
554 static const struct rtl838x_eth_reg rtl839x_reg
= {
555 .net_irq
= rtl83xx_net_irq
,
556 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
557 .dma_if_intr_sts
= RTL839X_DMA_IF_INTR_STS
,
558 .dma_if_intr_msk
= RTL839X_DMA_IF_INTR_MSK
,
559 .dma_if_ctrl
= RTL839X_DMA_IF_CTRL
,
560 .mac_force_mode_ctrl
= RTL839X_MAC_FORCE_MODE_CTRL
,
561 .dma_rx_base
= RTL839X_DMA_RX_BASE
,
562 .dma_tx_base
= RTL839X_DMA_TX_BASE
,
563 .dma_if_rx_ring_size
= rtl839x_dma_if_rx_ring_size
,
564 .dma_if_rx_ring_cntr
= rtl839x_dma_if_rx_ring_cntr
,
565 .dma_if_rx_cur
= RTL839X_DMA_IF_RX_CUR
,
566 .rst_glb_ctrl
= RTL839X_RST_GLB_CTRL
,
567 .get_mac_link_sts
= rtl839x_get_mac_link_sts
,
568 .get_mac_link_dup_sts
= rtl839x_get_mac_link_dup_sts
,
569 .get_mac_link_spd_sts
= rtl839x_get_mac_link_spd_sts
,
570 .get_mac_rx_pause_sts
= rtl839x_get_mac_rx_pause_sts
,
571 .get_mac_tx_pause_sts
= rtl839x_get_mac_tx_pause_sts
,
573 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
574 .update_cntr
= rtl839x_update_cntr
,
575 .create_tx_header
= rtl839x_create_tx_header
,
576 .decode_tag
= rtl839x_decode_tag
,
579 static const struct rtl838x_eth_reg rtl930x_reg
= {
580 .net_irq
= rtl93xx_net_irq
,
581 .mac_port_ctrl
= rtl930x_mac_port_ctrl
,
582 .dma_if_intr_rx_runout_sts
= RTL930X_DMA_IF_INTR_RX_RUNOUT_STS
,
583 .dma_if_intr_rx_done_sts
= RTL930X_DMA_IF_INTR_RX_DONE_STS
,
584 .dma_if_intr_tx_done_sts
= RTL930X_DMA_IF_INTR_TX_DONE_STS
,
585 .dma_if_intr_rx_runout_msk
= RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK
,
586 .dma_if_intr_rx_done_msk
= RTL930X_DMA_IF_INTR_RX_DONE_MSK
,
587 .dma_if_intr_tx_done_msk
= RTL930X_DMA_IF_INTR_TX_DONE_MSK
,
588 .l2_ntfy_if_intr_sts
= RTL930X_L2_NTFY_IF_INTR_STS
,
589 .l2_ntfy_if_intr_msk
= RTL930X_L2_NTFY_IF_INTR_MSK
,
590 .dma_if_ctrl
= RTL930X_DMA_IF_CTRL
,
591 .mac_force_mode_ctrl
= RTL930X_MAC_FORCE_MODE_CTRL
,
592 .dma_rx_base
= RTL930X_DMA_RX_BASE
,
593 .dma_tx_base
= RTL930X_DMA_TX_BASE
,
594 .dma_if_rx_ring_size
= rtl930x_dma_if_rx_ring_size
,
595 .dma_if_rx_ring_cntr
= rtl930x_dma_if_rx_ring_cntr
,
596 .dma_if_rx_cur
= RTL930X_DMA_IF_RX_CUR
,
597 .rst_glb_ctrl
= RTL930X_RST_GLB_CTRL_0
,
598 .get_mac_link_sts
= rtl930x_get_mac_link_sts
,
599 .get_mac_link_dup_sts
= rtl930x_get_mac_link_dup_sts
,
600 .get_mac_link_spd_sts
= rtl930x_get_mac_link_spd_sts
,
601 .get_mac_rx_pause_sts
= rtl930x_get_mac_rx_pause_sts
,
602 .get_mac_tx_pause_sts
= rtl930x_get_mac_tx_pause_sts
,
603 .mac
= RTL930X_MAC_L2_ADDR_CTRL
,
604 .l2_tbl_flush_ctrl
= RTL930X_L2_TBL_FLUSH_CTRL
,
605 .update_cntr
= rtl930x_update_cntr
,
606 .create_tx_header
= rtl930x_create_tx_header
,
607 .decode_tag
= rtl930x_decode_tag
,
610 static const struct rtl838x_eth_reg rtl931x_reg
= {
611 .net_irq
= rtl93xx_net_irq
,
612 .mac_port_ctrl
= rtl931x_mac_port_ctrl
,
613 .dma_if_intr_rx_runout_sts
= RTL931X_DMA_IF_INTR_RX_RUNOUT_STS
,
614 .dma_if_intr_rx_done_sts
= RTL931X_DMA_IF_INTR_RX_DONE_STS
,
615 .dma_if_intr_tx_done_sts
= RTL931X_DMA_IF_INTR_TX_DONE_STS
,
616 .dma_if_intr_rx_runout_msk
= RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK
,
617 .dma_if_intr_rx_done_msk
= RTL931X_DMA_IF_INTR_RX_DONE_MSK
,
618 .dma_if_intr_tx_done_msk
= RTL931X_DMA_IF_INTR_TX_DONE_MSK
,
619 .l2_ntfy_if_intr_sts
= RTL931X_L2_NTFY_IF_INTR_STS
,
620 .l2_ntfy_if_intr_msk
= RTL931X_L2_NTFY_IF_INTR_MSK
,
621 .dma_if_ctrl
= RTL931X_DMA_IF_CTRL
,
622 .mac_force_mode_ctrl
= RTL931X_MAC_FORCE_MODE_CTRL
,
623 .dma_rx_base
= RTL931X_DMA_RX_BASE
,
624 .dma_tx_base
= RTL931X_DMA_TX_BASE
,
625 .dma_if_rx_ring_size
= rtl931x_dma_if_rx_ring_size
,
626 .dma_if_rx_ring_cntr
= rtl931x_dma_if_rx_ring_cntr
,
627 .dma_if_rx_cur
= RTL931X_DMA_IF_RX_CUR
,
628 .rst_glb_ctrl
= RTL931X_RST_GLB_CTRL
,
629 .get_mac_link_sts
= rtl931x_get_mac_link_sts
,
630 .get_mac_link_dup_sts
= rtl931x_get_mac_link_dup_sts
,
631 .get_mac_link_spd_sts
= rtl931x_get_mac_link_spd_sts
,
632 .get_mac_rx_pause_sts
= rtl931x_get_mac_rx_pause_sts
,
633 .get_mac_tx_pause_sts
= rtl931x_get_mac_tx_pause_sts
,
634 .mac
= RTL931X_MAC_L2_ADDR_CTRL
,
635 .l2_tbl_flush_ctrl
= RTL931X_L2_TBL_FLUSH_CTRL
,
636 .update_cntr
= rtl931x_update_cntr
,
637 .create_tx_header
= rtl931x_create_tx_header
,
638 .decode_tag
= rtl931x_decode_tag
,
641 static void rtl838x_hw_reset(struct rtl838x_eth_priv
*priv
)
646 pr_info("RESETTING %x, CPU_PORT %d\n", priv
->family_id
, priv
->cpu_port
);
647 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
650 /* Disable and clear interrupts */
651 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
652 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_runout_msk
);
653 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_sts
);
654 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_done_msk
);
655 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_sts
);
656 sw_w32(0x00000000, priv
->r
->dma_if_intr_tx_done_msk
);
657 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_sts
);
659 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
660 sw_w32(0xffffffff, priv
->r
->dma_if_intr_sts
);
663 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
664 /* Preserve L2 notification and NBUF settings */
665 int_saved
= sw_r32(priv
->r
->dma_if_intr_msk
);
666 nbuf
= sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
668 /* Disable link change interrupt on RTL839x */
669 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG
);
670 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG
+ 4);
672 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
673 sw_w32(0xffffffff, priv
->r
->dma_if_intr_sts
);
676 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
677 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
682 sw_w32_mask(0, reset_mask
, priv
->r
->rst_glb_ctrl
);
684 do { /* Wait for reset of NIC and Queues done */
686 } while (sw_r32(priv
->r
->rst_glb_ctrl
) & reset_mask
);
689 /* Setup Head of Line */
690 if (priv
->family_id
== RTL8380_FAMILY_ID
)
691 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE
); /* Disabled on RTL8380 */
692 if (priv
->family_id
== RTL8390_FAMILY_ID
)
693 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR
);
694 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
695 for (int i
= 0; i
< priv
->rxrings
; i
++) {
696 int pos
= (i
% 3) * 10;
698 sw_w32_mask(0x3ff << pos
, 0, priv
->r
->dma_if_rx_ring_size(i
));
699 sw_w32_mask(0x3ff << pos
, priv
->rxringlen
,
700 priv
->r
->dma_if_rx_ring_cntr(i
));
704 /* Re-enable link change interrupt */
705 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
706 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG
);
707 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG
+ 4);
708 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG
);
709 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG
+ 4);
711 /* Restore notification settings: on RTL838x these bits are null */
712 sw_w32_mask(7 << 20, int_saved
& (7 << 20), priv
->r
->dma_if_intr_msk
);
713 sw_w32(nbuf
, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
717 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv
*priv
)
719 struct ring_b
*ring
= priv
->membase
;
721 for (int i
= 0; i
< priv
->rxrings
; i
++)
722 sw_w32(KSEG1ADDR(&ring
->rx_r
[i
]), priv
->r
->dma_rx_base
+ i
* 4);
724 for (int i
= 0; i
< TXRINGS
; i
++)
725 sw_w32(KSEG1ADDR(&ring
->tx_r
[i
]), priv
->r
->dma_tx_base
+ i
* 4);
728 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
730 /* Disable Head of Line features for all RX rings */
731 sw_w32(0xffffffff, priv
->r
->dma_if_rx_ring_size(0));
733 /* Truncate RX buffer to DEFAULT_MTU bytes, pad TX */
734 sw_w32((DEFAULT_MTU
<< 16) | RX_TRUNCATE_EN_83XX
| TX_PAD_EN_838X
, priv
->r
->dma_if_ctrl
);
736 /* Enable RX done, RX overflow and TX done interrupts */
737 sw_w32(0xfffff, priv
->r
->dma_if_intr_msk
);
739 /* Enable DMA, engine expects empty FCS field */
740 sw_w32_mask(0, RX_EN
| TX_EN
, priv
->r
->dma_if_ctrl
);
742 /* Restart TX/RX to CPU port */
743 sw_w32_mask(0x0, 0x3, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
744 /* Set Speed, duplex, flow control
745 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
746 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
749 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
751 /* Enable CRC checks on CPU-port */
752 sw_w32_mask(0, BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
755 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
757 /* Setup CPU-Port: RX Buffer */
758 sw_w32((DEFAULT_MTU
<< 5) | RX_TRUNCATE_EN_83XX
, priv
->r
->dma_if_ctrl
);
760 /* Enable Notify, RX done, RX overflow and TX done interrupts */
761 sw_w32(0x007fffff, priv
->r
->dma_if_intr_msk
); /* Notify IRQ! */
764 sw_w32_mask(0, RX_EN
| TX_EN
, priv
->r
->dma_if_ctrl
);
766 /* Restart TX/RX to CPU port, enable CRC checking */
767 sw_w32_mask(0x0, 0x3 | BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
769 /* CPU port joins Lookup Miss Flooding Portmask */
770 /* TODO: The code below should also work for the RTL838x */
771 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL
);
772 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
773 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL
);
775 /* Force CPU port link up */
776 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
779 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
781 /* Setup CPU-Port: RX Buffer truncated at DEFAULT_MTU Bytes */
782 sw_w32((DEFAULT_MTU
<< 16) | RX_TRUNCATE_EN_93XX
, priv
->r
->dma_if_ctrl
);
784 for (int i
= 0; i
< priv
->rxrings
; i
++) {
785 int pos
= (i
% 3) * 10;
788 sw_w32_mask(0x3ff << pos
, priv
->rxringlen
<< pos
, priv
->r
->dma_if_rx_ring_size(i
));
790 /* Some SoCs have issues with missing underflow protection */
791 v
= (sw_r32(priv
->r
->dma_if_rx_ring_cntr(i
)) >> pos
) & 0x3ff;
792 sw_w32_mask(0x3ff << pos
, v
, priv
->r
->dma_if_rx_ring_cntr(i
));
795 /* Enable Notify, RX done, RX overflow and TX done interrupts */
796 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_msk
);
797 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_msk
);
798 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_msk
);
801 sw_w32_mask(0, RX_EN_93XX
| TX_EN_93XX
, priv
->r
->dma_if_ctrl
);
803 /* Restart TX/RX to CPU port, enable CRC checking */
804 sw_w32_mask(0x0, 0x3 | BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
806 if (priv
->family_id
== RTL9300_FAMILY_ID
)
807 sw_w32_mask(0, BIT(priv
->cpu_port
), RTL930X_L2_UNKN_UC_FLD_PMSK
);
809 sw_w32_mask(0, BIT(priv
->cpu_port
), RTL931X_L2_UNKN_UC_FLD_PMSK
);
811 if (priv
->family_id
== RTL9300_FAMILY_ID
)
812 sw_w32(0x217, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
814 sw_w32(0x2a1d, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
817 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv
*priv
, struct ring_b
*ring
)
819 for (int i
= 0; i
< priv
->rxrings
; i
++) {
823 for (j
= 0; j
< priv
->rxringlen
; j
++) {
824 h
= &ring
->rx_header
[i
][j
];
825 memset(h
, 0, sizeof(struct p_hdr
));
826 h
->buf
= (u8
*)KSEG1ADDR(ring
->rx_space
+
827 i
* priv
->rxringlen
* RING_BUFFER
+
829 h
->size
= RING_BUFFER
;
830 /* All rings owned by switch, last one wraps */
831 ring
->rx_r
[i
][j
] = KSEG1ADDR(h
) | 1 | (j
== (priv
->rxringlen
- 1) ?
838 for (int i
= 0; i
< TXRINGS
; i
++) {
842 for (j
= 0; j
< TXRINGLEN
; j
++) {
843 h
= &ring
->tx_header
[i
][j
];
844 memset(h
, 0, sizeof(struct p_hdr
));
845 h
->buf
= (u8
*)KSEG1ADDR(ring
->tx_space
+
846 i
* TXRINGLEN
* RING_BUFFER
+
848 h
->size
= RING_BUFFER
;
849 ring
->tx_r
[i
][j
] = KSEG1ADDR(&ring
->tx_header
[i
][j
]);
851 /* Last header is wrapping around */
852 ring
->tx_r
[i
][j
- 1] |= WRAP
;
857 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv
*priv
)
859 struct notify_b
*b
= priv
->membase
+ sizeof(struct ring_b
);
861 for (int i
= 0; i
< NOTIFY_BLOCKS
; i
++)
862 b
->ring
[i
] = KSEG1ADDR(&b
->blocks
[i
]) | 1 | (i
== (NOTIFY_BLOCKS
- 1) ? WRAP
: 0);
864 sw_w32((u32
) b
->ring
, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
865 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL
);
867 /* Setup notification events */
868 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0
); /* RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN */
869 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL
); /* SUSPEND_NOTIFICATION_EN */
871 /* Enable Notification */
872 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL
);
876 static int rtl838x_eth_open(struct net_device
*ndev
)
879 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
880 struct ring_b
*ring
= priv
->membase
;
882 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
883 __func__
, priv
->rxrings
, priv
->rxringlen
, TXRINGS
, TXRINGLEN
);
885 spin_lock_irqsave(&priv
->lock
, flags
);
886 rtl838x_hw_reset(priv
);
887 rtl838x_setup_ring_buffer(priv
, ring
);
888 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
889 rtl839x_setup_notify_ring_buffer(priv
);
890 /* Make sure the ring structure is visible to the ASIC */
895 rtl838x_hw_ring_setup(priv
);
896 phylink_start(priv
->phylink
);
898 for (int i
= 0; i
< priv
->rxrings
; i
++)
899 napi_enable(&priv
->rx_qs
[i
].napi
);
901 switch (priv
->family_id
) {
902 case RTL8380_FAMILY_ID
:
903 rtl838x_hw_en_rxtx(priv
);
904 /* Trap IGMP/MLD traffic to CPU-Port */
905 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL
);
906 /* Flush learned FDB entries on link down of a port */
907 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0
);
910 case RTL8390_FAMILY_ID
:
911 rtl839x_hw_en_rxtx(priv
);
912 /* Trap MLD and IGMP messages to CPU_PORT */
913 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL
);
914 /* Flush learned FDB entries on link down of a port */
915 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0
);
918 case RTL9300_FAMILY_ID
:
919 rtl93xx_hw_en_rxtx(priv
);
920 /* Flush learned FDB entries on link down of a port */
921 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL
);
922 /* Trap MLD and IGMP messages to CPU_PORT */
923 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL
);
926 case RTL9310_FAMILY_ID
:
927 rtl93xx_hw_en_rxtx(priv
);
929 /* Trap MLD and IGMP messages to CPU_PORT */
930 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL
);
932 /* Disable External CPU access to switch, clear EXT_CPU_EN */
933 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2
);
935 /* Set PCIE_PWR_DOWN */
936 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL
);
940 netif_tx_start_all_queues(ndev
);
942 spin_unlock_irqrestore(&priv
->lock
, flags
);
947 static void rtl838x_hw_stop(struct rtl838x_eth_priv
*priv
)
949 u32 force_mac
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x6192C : 0x75;
950 u32 clear_irq
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x000fffff : 0x007fffff;
952 /* Disable RX/TX from/to CPU-port */
953 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
955 /* Disable traffic */
956 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
957 sw_w32_mask(RX_EN_93XX
| TX_EN_93XX
, 0, priv
->r
->dma_if_ctrl
);
959 sw_w32_mask(RX_EN
| TX_EN
, 0, priv
->r
->dma_if_ctrl
);
960 mdelay(200); /* Test, whether this is needed */
962 /* Block all ports */
963 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
964 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
965 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
966 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0
);
969 /* Flush L2 address cache */
970 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
971 for (int i
= 0; i
<= priv
->cpu_port
; i
++) {
972 sw_w32(1 << 26 | 1 << 23 | i
<< 5, priv
->r
->l2_tbl_flush_ctrl
);
973 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << 26));
975 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
976 for (int i
= 0; i
<= priv
->cpu_port
; i
++) {
977 sw_w32(1 << 28 | 1 << 25 | i
<< 5, priv
->r
->l2_tbl_flush_ctrl
);
978 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << 28));
981 /* TODO: L2 flush register is 64 bit on RTL931X and 930X */
983 /* CPU-Port: Link down */
984 if (priv
->family_id
== RTL8380_FAMILY_ID
|| priv
->family_id
== RTL8390_FAMILY_ID
)
985 sw_w32(force_mac
, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
986 else if (priv
->family_id
== RTL9300_FAMILY_ID
)
987 sw_w32_mask(0x3, 0, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
*4);
988 else if (priv
->family_id
== RTL9310_FAMILY_ID
)
989 sw_w32_mask(BIT(0) | BIT(9), 0, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
*4);
992 /* Disable all TX/RX interrupts */
993 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
994 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_runout_msk
);
995 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_sts
);
996 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_done_msk
);
997 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_sts
);
998 sw_w32(0x00000000, priv
->r
->dma_if_intr_tx_done_msk
);
999 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_sts
);
1001 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
1002 sw_w32(clear_irq
, priv
->r
->dma_if_intr_sts
);
1005 /* Disable TX/RX DMA */
1006 sw_w32(0x00000000, priv
->r
->dma_if_ctrl
);
1010 static int rtl838x_eth_stop(struct net_device
*ndev
)
1012 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1014 pr_info("in %s\n", __func__
);
1016 phylink_stop(priv
->phylink
);
1017 rtl838x_hw_stop(priv
);
1019 for (int i
= 0; i
< priv
->rxrings
; i
++)
1020 napi_disable(&priv
->rx_qs
[i
].napi
);
1022 netif_tx_stop_all_queues(ndev
);
1027 static void rtl838x_eth_set_multicast_list(struct net_device
*ndev
)
1029 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1030 * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF
1032 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1033 sw_w32(0x0, RTL838X_RMA_CTRL_0
);
1034 sw_w32(0x0, RTL838X_RMA_CTRL_1
);
1036 if (ndev
->flags
& IFF_ALLMULTI
)
1037 sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0
);
1038 if (ndev
->flags
& IFF_PROMISC
) {
1039 sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0
);
1040 sw_w32(0x7fff, RTL838X_RMA_CTRL_1
);
1044 static void rtl839x_eth_set_multicast_list(struct net_device
*ndev
)
1046 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1047 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1048 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
1049 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1051 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1052 sw_w32(0x0, RTL839X_RMA_CTRL_0
);
1053 sw_w32(0x0, RTL839X_RMA_CTRL_1
);
1054 sw_w32(0x0, RTL839X_RMA_CTRL_2
);
1055 sw_w32(0x0, RTL839X_RMA_CTRL_3
);
1057 if (ndev
->flags
& IFF_ALLMULTI
) {
1058 sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0
);
1059 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1
);
1060 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2
);
1062 if (ndev
->flags
& IFF_PROMISC
) {
1063 sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0
);
1064 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1
);
1065 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2
);
1066 sw_w32(0x3ff, RTL839X_RMA_CTRL_3
);
1070 static void rtl930x_eth_set_multicast_list(struct net_device
*ndev
)
1072 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1073 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1074 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
1075 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1077 if (ndev
->flags
& (IFF_ALLMULTI
| IFF_PROMISC
)) {
1078 sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0
);
1079 sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1
);
1080 sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2
);
1082 sw_w32(0x0, RTL930X_RMA_CTRL_0
);
1083 sw_w32(0x0, RTL930X_RMA_CTRL_1
);
1084 sw_w32(0x0, RTL930X_RMA_CTRL_2
);
1088 static void rtl931x_eth_set_multicast_list(struct net_device
*ndev
)
1090 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1091 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1092 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00.
1093 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1095 if (ndev
->flags
& (IFF_ALLMULTI
| IFF_PROMISC
)) {
1096 sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0
);
1097 sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1
);
1098 sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2
);
1100 sw_w32(0x0, RTL931X_RMA_CTRL_0
);
1101 sw_w32(0x0, RTL931X_RMA_CTRL_1
);
1102 sw_w32(0x0, RTL931X_RMA_CTRL_2
);
1106 static void rtl838x_eth_tx_timeout(struct net_device
*ndev
, unsigned int txqueue
)
1108 unsigned long flags
;
1109 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1111 pr_warn("%s\n", __func__
);
1112 spin_lock_irqsave(&priv
->lock
, flags
);
1113 rtl838x_hw_stop(priv
);
1114 rtl838x_hw_ring_setup(priv
);
1115 rtl838x_hw_en_rxtx(priv
);
1116 netif_trans_update(ndev
);
1117 netif_start_queue(ndev
);
1118 spin_unlock_irqrestore(&priv
->lock
, flags
);
1121 static int rtl838x_eth_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1124 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1125 struct ring_b
*ring
= priv
->membase
;
1127 unsigned long flags
;
1130 int q
= skb_get_queue_mapping(skb
) % TXRINGS
;
1132 if (q
) /* Check for high prio queue */
1133 pr_debug("SKB priority: %d\n", skb
->priority
);
1135 spin_lock_irqsave(&priv
->lock
, flags
);
1138 /* Check for DSA tagging at the end of the buffer */
1139 if (netdev_uses_dsa(dev
) &&
1140 skb
->data
[len
- 4] == 0x80 &&
1141 skb
->data
[len
- 3] < priv
->cpu_port
&&
1142 skb
->data
[len
- 2] == 0x10 &&
1143 skb
->data
[len
- 1] == 0x00) {
1144 /* Reuse tag space for CRC if possible */
1145 dest_port
= skb
->data
[len
- 3];
1146 skb
->data
[len
- 4] = skb
->data
[len
- 3] = skb
->data
[len
- 2] = skb
->data
[len
- 1] = 0x00;
1150 len
+= 4; /* Add space for CRC */
1152 if (skb_padto(skb
, len
)) {
1157 /* We can send this packet if CPU owns the descriptor */
1158 if (!(ring
->tx_r
[q
][ring
->c_tx
[q
]] & 0x1)) {
1160 /* Set descriptor for tx */
1161 h
= &ring
->tx_header
[q
][ring
->c_tx
[q
]];
1164 /* On RTL8380 SoCs, small packet lengths being sent need adjustments */
1165 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1166 if (len
< ETH_ZLEN
- 4)
1171 priv
->r
->create_tx_header(h
, dest_port
, skb
->priority
>> 1);
1173 /* Copy packet data to tx buffer */
1174 memcpy((void *)KSEG1ADDR(h
->buf
), skb
->data
, len
);
1175 /* Make sure packet data is visible to ASIC */
1178 /* Hand over to switch */
1179 ring
->tx_r
[q
][ring
->c_tx
[q
]] |= 1;
1181 /* Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs */
1182 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1183 for (int i
= 0; i
< 10; i
++) {
1184 u32 val
= sw_r32(priv
->r
->dma_if_ctrl
);
1185 if ((val
& 0xc) == 0xc)
1190 /* Tell switch to send data */
1191 if (priv
->family_id
== RTL9310_FAMILY_ID
|| priv
->family_id
== RTL9300_FAMILY_ID
) {
1192 /* Ring ID q == 0: Low priority, Ring ID = 1: High prio queue */
1194 sw_w32_mask(0, BIT(2), priv
->r
->dma_if_ctrl
);
1196 sw_w32_mask(0, BIT(3), priv
->r
->dma_if_ctrl
);
1198 sw_w32_mask(0, TX_DO
, priv
->r
->dma_if_ctrl
);
1201 dev
->stats
.tx_packets
++;
1202 dev
->stats
.tx_bytes
+= len
;
1204 ring
->c_tx
[q
] = (ring
->c_tx
[q
] + 1) % TXRINGLEN
;
1207 dev_warn(&priv
->pdev
->dev
, "Data is owned by switch\n");
1208 ret
= NETDEV_TX_BUSY
;
1212 spin_unlock_irqrestore(&priv
->lock
, flags
);
1217 /* Return queue number for TX. On the RTL83XX, these queues have equal priority
1218 * so we do round-robin
1220 u16
rtl83xx_pick_tx_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1221 struct net_device
*sb_dev
)
1226 return last
% TXRINGS
;
1229 /* Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1231 u16
rtl93xx_pick_tx_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1232 struct net_device
*sb_dev
)
1234 if (skb
->priority
>= TC_PRIO_CONTROL
)
1240 static int rtl838x_hw_receive(struct net_device
*dev
, int r
, int budget
)
1242 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1243 struct ring_b
*ring
= priv
->membase
;
1245 unsigned long flags
;
1248 bool dsa
= netdev_uses_dsa(dev
);
1250 pr_debug("---------------------------------------------------------- RX - %d\n", r
);
1251 spin_lock_irqsave(&priv
->lock
, flags
);
1252 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
1255 struct sk_buff
*skb
;
1262 if ((ring
->rx_r
[r
][ring
->c_rx
[r
]] & 0x1)) {
1263 if (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
) {
1264 netdev_warn(dev
, "Ring contention: r: %x, last %x, cur %x\n",
1265 r
, (uint32_t)last
, (u32
) &ring
->rx_r
[r
][ring
->c_rx
[r
]]);
1270 h
= &ring
->rx_header
[r
][ring
->c_rx
[r
]];
1271 data
= (u8
*)KSEG1ADDR(h
->buf
);
1277 len
-= 4; /* strip the CRC */
1278 /* Add 4 bytes for cpu_tag */
1282 skb
= netdev_alloc_skb(dev
, len
+ 4);
1283 skb_reserve(skb
, NET_IP_ALIGN
);
1286 /* BUG: Prevent bug on RTL838x SoCs */
1287 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1288 sw_w32(0xffffffff, priv
->r
->dma_if_rx_ring_size(0));
1289 for (int i
= 0; i
< priv
->rxrings
; i
++) {
1292 /* Update each ring cnt */
1293 val
= sw_r32(priv
->r
->dma_if_rx_ring_cntr(i
));
1294 sw_w32(val
, priv
->r
->dma_if_rx_ring_cntr(i
));
1298 skb_data
= skb_put(skb
, len
);
1299 /* Make sure data is visible */
1301 memcpy(skb
->data
, (u8
*)KSEG1ADDR(data
), len
);
1302 /* Overwrite CRC with cpu_tag */
1304 priv
->r
->decode_tag(h
, &tag
);
1305 skb
->data
[len
- 4] = 0x80;
1306 skb
->data
[len
- 3] = tag
.port
;
1307 skb
->data
[len
- 2] = 0x10;
1308 skb
->data
[len
- 1] = 0x00;
1309 if (tag
.l2_offloaded
)
1310 skb
->data
[len
- 3] |= 0x40;
1314 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1315 tag
.queue
, len
, tag
.reason
, tag
.port
);
1317 skb
->protocol
= eth_type_trans(skb
, dev
);
1318 if (dev
->features
& NETIF_F_RXCSUM
) {
1320 skb_checksum_none_assert(skb
);
1322 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1324 dev
->stats
.rx_packets
++;
1325 dev
->stats
.rx_bytes
+= len
;
1327 list_add_tail(&skb
->list
, &rx_list
);
1329 if (net_ratelimit())
1330 dev_warn(&dev
->dev
, "low on memory - packet dropped\n");
1331 dev
->stats
.rx_dropped
++;
1334 /* Reset header structure */
1335 memset(h
, 0, sizeof(struct p_hdr
));
1337 h
->size
= RING_BUFFER
;
1339 ring
->rx_r
[r
][ring
->c_rx
[r
]] = KSEG1ADDR(h
) | 0x1 | (ring
->c_rx
[r
] == (priv
->rxringlen
- 1) ?
1342 ring
->c_rx
[r
] = (ring
->c_rx
[r
] + 1) % priv
->rxringlen
;
1343 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
1344 } while (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
&& work_done
< budget
);
1346 netif_receive_skb_list(&rx_list
);
1348 /* Update counters */
1349 priv
->r
->update_cntr(r
, 0);
1351 spin_unlock_irqrestore(&priv
->lock
, flags
);
1356 static int rtl838x_poll_rx(struct napi_struct
*napi
, int budget
)
1358 struct rtl838x_rx_q
*rx_q
= container_of(napi
, struct rtl838x_rx_q
, napi
);
1359 struct rtl838x_eth_priv
*priv
= rx_q
->priv
;
1364 while (work_done
< budget
) {
1365 work
= rtl838x_hw_receive(priv
->netdev
, r
, budget
- work_done
);
1371 if (work_done
< budget
) {
1372 napi_complete_done(napi
, work_done
);
1374 /* Enable RX interrupt */
1375 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
1376 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_msk
);
1378 sw_w32_mask(0, 0xf00ff | BIT(r
+ 8), priv
->r
->dma_if_intr_msk
);
1385 static void rtl838x_validate(struct phylink_config
*config
,
1386 unsigned long *supported
,
1387 struct phylink_link_state
*state
)
1389 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1391 pr_debug("In %s\n", __func__
);
1393 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1394 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
1395 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1396 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
1397 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
1398 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
1399 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
1400 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
1401 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1402 pr_err("Unsupported interface: %d\n", state
->interface
);
1406 /* Allow all the expected bits */
1407 phylink_set(mask
, Autoneg
);
1408 phylink_set_port_modes(mask
);
1409 phylink_set(mask
, Pause
);
1410 phylink_set(mask
, Asym_Pause
);
1412 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1413 * including Half duplex
1415 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1416 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
1417 phylink_set(mask
, 1000baseT_Full
);
1418 phylink_set(mask
, 1000baseT_Half
);
1421 phylink_set(mask
, 10baseT_Half
);
1422 phylink_set(mask
, 10baseT_Full
);
1423 phylink_set(mask
, 100baseT_Half
);
1424 phylink_set(mask
, 100baseT_Full
);
1426 bitmap_and(supported
, supported
, mask
,
1427 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1428 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1429 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1433 static void rtl838x_mac_config(struct phylink_config
*config
,
1435 const struct phylink_link_state
*state
)
1437 /* This is only being called for the master device,
1438 * i.e. the CPU-Port. We don't need to do anything.
1441 pr_info("In %s, mode %x\n", __func__
, mode
);
1444 static void rtl838x_mac_an_restart(struct phylink_config
*config
)
1446 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1447 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1449 /* This works only on RTL838x chips */
1450 if (priv
->family_id
!= RTL8380_FAMILY_ID
)
1453 pr_debug("In %s\n", __func__
);
1454 /* Restart by disabling and re-enabling link */
1455 sw_w32(0x6192D, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
1457 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
1460 static void rtl838x_mac_pcs_get_state(struct phylink_config
*config
,
1461 struct phylink_link_state
*state
)
1464 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1465 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1466 int port
= priv
->cpu_port
;
1468 pr_info("In %s\n", __func__
);
1470 state
->link
= priv
->r
->get_mac_link_sts(port
) ? 1 : 0;
1471 state
->duplex
= priv
->r
->get_mac_link_dup_sts(port
) ? 1 : 0;
1473 pr_info("%s link status is %d\n", __func__
, state
->link
);
1474 speed
= priv
->r
->get_mac_link_spd_sts(port
);
1477 state
->speed
= SPEED_10
;
1480 state
->speed
= SPEED_100
;
1483 state
->speed
= SPEED_1000
;
1486 state
->speed
= SPEED_2500
;
1489 state
->speed
= SPEED_5000
;
1492 state
->speed
= SPEED_10000
;
1495 state
->speed
= SPEED_UNKNOWN
;
1499 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
1500 if (priv
->r
->get_mac_rx_pause_sts(port
))
1501 state
->pause
|= MLO_PAUSE_RX
;
1502 if (priv
->r
->get_mac_tx_pause_sts(port
))
1503 state
->pause
|= MLO_PAUSE_TX
;
1506 static void rtl838x_mac_link_down(struct phylink_config
*config
,
1508 phy_interface_t interface
)
1510 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1511 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1513 pr_debug("In %s\n", __func__
);
1514 /* Stop TX/RX to port */
1515 sw_w32_mask(0x03, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1518 static void rtl838x_mac_link_up(struct phylink_config
*config
,
1519 struct phy_device
*phy
, unsigned int mode
,
1520 phy_interface_t interface
, int speed
, int duplex
,
1521 bool tx_pause
, bool rx_pause
)
1523 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1524 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1526 pr_debug("In %s\n", __func__
);
1527 /* Restart TX/RX to port */
1528 sw_w32_mask(0, 0x03, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1531 static void rtl838x_set_mac_hw(struct net_device
*dev
, u8
*mac
)
1533 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1534 unsigned long flags
;
1536 spin_lock_irqsave(&priv
->lock
, flags
);
1537 pr_debug("In %s\n", __func__
);
1538 sw_w32((mac
[0] << 8) | mac
[1], priv
->r
->mac
);
1539 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5], priv
->r
->mac
+ 4);
1541 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1542 /* 2 more registers, ALE/MAC block */
1543 sw_w32((mac
[0] << 8) | mac
[1], RTL838X_MAC_ALE
);
1544 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
1545 (RTL838X_MAC_ALE
+ 4));
1547 sw_w32((mac
[0] << 8) | mac
[1], RTL838X_MAC2
);
1548 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
1551 spin_unlock_irqrestore(&priv
->lock
, flags
);
1554 static int rtl838x_set_mac_address(struct net_device
*dev
, void *p
)
1556 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1557 const struct sockaddr
*addr
= p
;
1558 u8
*mac
= (u8
*) (addr
->sa_data
);
1560 if (!is_valid_ether_addr(addr
->sa_data
))
1561 return -EADDRNOTAVAIL
;
1563 dev_addr_set(dev
, addr
->sa_data
);
1564 rtl838x_set_mac_hw(dev
, mac
);
1566 pr_info("Using MAC %08x%08x\n", sw_r32(priv
->r
->mac
), sw_r32(priv
->r
->mac
+ 4));
1571 static int rtl8390_init_mac(struct rtl838x_eth_priv
*priv
)
1573 /* We will need to set-up EEE and the egress-rate limitation */
1577 static int rtl8380_init_mac(struct rtl838x_eth_priv
*priv
)
1579 if (priv
->family_id
== 0x8390)
1580 return rtl8390_init_mac(priv
);
1582 /* At present we do not know how to set up EEE on any other SoC than RTL8380 */
1583 if (priv
->family_id
!= 0x8380)
1586 pr_info("%s\n", __func__
);
1587 /* fix timer for EEE */
1588 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
1589 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
1591 /* Init VLAN. TODO: Understand what is being done, here */
1592 if (priv
->id
== 0x8382) {
1593 for (int i
= 0; i
<= 28; i
++)
1594 sw_w32(0, 0xd57c + i
* 0x80);
1596 if (priv
->id
== 0x8380) {
1597 for (int i
= 8; i
<= 28; i
++)
1598 sw_w32(0, 0xd57c + i
* 0x80);
1604 static int rtl838x_get_link_ksettings(struct net_device
*ndev
,
1605 struct ethtool_link_ksettings
*cmd
)
1607 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1609 pr_debug("%s called\n", __func__
);
1611 return phylink_ethtool_ksettings_get(priv
->phylink
, cmd
);
1614 static int rtl838x_set_link_ksettings(struct net_device
*ndev
,
1615 const struct ethtool_link_ksettings
*cmd
)
1617 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1619 pr_debug("%s called\n", __func__
);
1621 return phylink_ethtool_ksettings_set(priv
->phylink
, cmd
);
1624 static int rtl838x_mdio_read_paged(struct mii_bus
*bus
, int mii_id
, u16 page
, int regnum
)
1628 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1630 if (mii_id
>= 24 && mii_id
<= 27 && priv
->id
== 0x8380)
1631 return rtl838x_read_sds_phy(mii_id
, regnum
);
1633 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1634 err
= rtl838x_read_mmd_phy(mii_id
,
1635 mdiobus_c45_devad(regnum
),
1637 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id
,
1638 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1641 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id
, regnum
, val
, err
);
1642 err
= rtl838x_read_phy(mii_id
, page
, regnum
, &val
);
1650 static int rtl838x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1652 return rtl838x_mdio_read_paged(bus
, mii_id
, 0, regnum
);
1655 static int rtl839x_mdio_read_paged(struct mii_bus
*bus
, int mii_id
, u16 page
, int regnum
)
1659 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1661 if (mii_id
>= 48 && mii_id
<= 49 && priv
->id
== 0x8393)
1662 return rtl839x_read_sds_phy(mii_id
, regnum
);
1664 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1665 err
= rtl839x_read_mmd_phy(mii_id
,
1666 mdiobus_c45_devad(regnum
),
1668 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id
,
1669 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1672 err
= rtl839x_read_phy(mii_id
, page
, regnum
, &val
);
1673 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id
, regnum
, val
, err
);
1682 static int rtl839x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1684 return rtl839x_mdio_read_paged(bus
, mii_id
, 0, regnum
);
1687 static int rtl930x_mdio_read_paged(struct mii_bus
*bus
, int mii_id
, u16 page
, int regnum
)
1691 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1693 if (priv
->phy_is_internal
[mii_id
])
1694 return rtl930x_read_sds_phy(priv
->sds_id
[mii_id
], page
, regnum
);
1696 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1697 err
= rtl930x_read_mmd_phy(mii_id
,
1698 mdiobus_c45_devad(regnum
),
1700 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id
,
1701 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1704 err
= rtl930x_read_phy(mii_id
, page
, regnum
, &val
);
1705 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id
, regnum
, val
, err
);
1714 static int rtl930x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1716 return rtl930x_mdio_read_paged(bus
, mii_id
, 0, regnum
);
1719 static int rtl931x_mdio_read_paged(struct mii_bus
*bus
, int mii_id
, u16 page
, int regnum
)
1723 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1725 pr_debug("%s: In here, port %d\n", __func__
, mii_id
);
1726 if (priv
->phy_is_internal
[mii_id
]) {
1727 v
= rtl931x_read_sds_phy(priv
->sds_id
[mii_id
], page
, regnum
);
1735 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1736 err
= rtl931x_read_mmd_phy(mii_id
,
1737 mdiobus_c45_devad(regnum
),
1739 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id
,
1740 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1743 err
= rtl931x_read_phy(mii_id
, page
, regnum
, &val
);
1744 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id
, regnum
, val
, err
);
1754 static int rtl931x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1756 return rtl931x_mdio_read_paged(bus
, mii_id
, 0, regnum
);
1759 static int rtl838x_mdio_write_paged(struct mii_bus
*bus
, int mii_id
, u16 page
,
1760 int regnum
, u16 value
)
1763 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1766 if (mii_id
>= 24 && mii_id
<= 27 && priv
->id
== 0x8380) {
1769 sw_w32(value
, RTL838X_SDS4_FIB_REG0
+ offset
+ (regnum
<< 2));
1773 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1774 err
= rtl838x_write_mmd_phy(mii_id
, mdiobus_c45_devad(regnum
),
1776 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id
,
1777 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1782 err
= rtl838x_write_phy(mii_id
, page
, regnum
, value
);
1783 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id
, regnum
, value
, err
);
1788 static int rtl838x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1789 int regnum
, u16 value
)
1791 return rtl838x_mdio_write_paged(bus
, mii_id
, 0, regnum
, value
);
1794 static int rtl839x_mdio_write_paged(struct mii_bus
*bus
, int mii_id
, u16 page
,
1795 int regnum
, u16 value
)
1797 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1800 if (mii_id
>= 48 && mii_id
<= 49 && priv
->id
== 0x8393)
1801 return rtl839x_write_sds_phy(mii_id
, regnum
, value
);
1803 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1804 err
= rtl839x_write_mmd_phy(mii_id
, mdiobus_c45_devad(regnum
),
1806 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id
,
1807 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1813 err
= rtl839x_write_phy(mii_id
, page
, regnum
, value
);
1814 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id
, regnum
, value
, err
);
1819 static int rtl839x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1820 int regnum
, u16 value
)
1822 return rtl839x_mdio_write_paged(bus
, mii_id
, 0, regnum
, value
);
1825 static int rtl930x_mdio_write_paged(struct mii_bus
*bus
, int mii_id
, u16 page
,
1826 int regnum
, u16 value
)
1828 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1831 if (priv
->phy_is_internal
[mii_id
])
1832 return rtl930x_write_sds_phy(priv
->sds_id
[mii_id
], page
, regnum
, value
);
1834 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
))
1835 return rtl930x_write_mmd_phy(mii_id
, mdiobus_c45_devad(regnum
),
1838 err
= rtl930x_write_phy(mii_id
, page
, regnum
, value
);
1839 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id
, regnum
, value
, err
);
1844 static int rtl930x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1845 int regnum
, u16 value
)
1847 return rtl930x_mdio_write_paged(bus
, mii_id
, 0, regnum
, value
);
1850 static int rtl931x_mdio_write_paged(struct mii_bus
*bus
, int mii_id
, u16 page
,
1851 int regnum
, u16 value
)
1853 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1856 if (priv
->phy_is_internal
[mii_id
])
1857 return rtl931x_write_sds_phy(priv
->sds_id
[mii_id
], page
, regnum
, value
);
1859 if (regnum
& (MII_ADDR_C45
| MII_ADDR_C22_MMD
)) {
1860 err
= rtl931x_write_mmd_phy(mii_id
, mdiobus_c45_devad(regnum
),
1862 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id
,
1863 mdiobus_c45_devad(regnum
), mdiobus_c45_regad(regnum
),
1869 err
= rtl931x_write_phy(mii_id
, page
, regnum
, value
);
1870 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id
, regnum
, value
, err
);
1875 static int rtl931x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1876 int regnum
, u16 value
)
1878 return rtl931x_mdio_write_paged(bus
, mii_id
, 0, regnum
, value
);
1881 static int rtl838x_mdio_reset(struct mii_bus
*bus
)
1883 pr_debug("%s called\n", __func__
);
1884 /* Disable MAC polling the PHY so that we can start configuration */
1885 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL
);
1887 /* Enable PHY control via SoC */
1888 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL
);
1890 /* Probably should reset all PHYs here... */
1894 static int rtl839x_mdio_reset(struct mii_bus
*bus
)
1898 pr_debug("%s called\n", __func__
);
1899 /* BUG: The following does not work, but should! */
1900 /* Disable MAC polling the PHY so that we can start configuration */
1901 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL
);
1902 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
1903 /* Disable PHY polling via SoC */
1904 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL
);
1906 /* Probably should reset all PHYs here... */
1910 u8 mac_type_bit
[RTL930X_CPU_PORT
] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1911 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1913 static int rtl930x_mdio_reset(struct mii_bus
*bus
)
1915 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1919 u32 private_poll_mask
= 0;
1921 bool uses_usxgmii
= false; /* For the Aquantia PHYs */
1922 bool uses_hisgmii
= false; /* For the RTL8221/8226 */
1924 /* Mapping of port to phy-addresses on an SMI bus */
1925 poll_sel
[0] = poll_sel
[1] = 0;
1926 for (int i
= 0; i
< RTL930X_CPU_PORT
; i
++) {
1929 if (priv
->smi_bus
[i
] > 3)
1932 sw_w32_mask(0x1f << pos
, priv
->smi_addr
[i
] << pos
,
1933 RTL930X_SMI_PORT0_5_ADDR
+ (i
/ 6) * 4);
1936 poll_sel
[i
/ 16] |= priv
->smi_bus
[i
] << pos
;
1937 poll_ctrl
|= BIT(20 + priv
->smi_bus
[i
]);
1940 /* Configure which SMI bus is behind which port number */
1941 sw_w32(poll_sel
[0], RTL930X_SMI_PORT0_15_POLLING_SEL
);
1942 sw_w32(poll_sel
[1], RTL930X_SMI_PORT16_27_POLLING_SEL
);
1944 /* Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+) */
1945 sw_w32_mask(poll_ctrl
, 0, RTL930X_SMI_GLB_CTRL
);
1947 /* Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus */
1948 for (int i
= 0; i
< 4; i
++)
1949 if (priv
->smi_bus_isc45
[i
])
1950 c45_mask
|= BIT(i
+ 16);
1952 pr_info("c45_mask: %08x\n", c45_mask
);
1953 sw_w32_mask(0, c45_mask
, RTL930X_SMI_GLB_CTRL
);
1955 /* Set the MAC type of each port according to the PHY-interface */
1956 /* Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0 */
1958 for (int i
= 0; i
< RTL930X_CPU_PORT
; i
++) {
1959 switch (priv
->interfaces
[i
]) {
1960 case PHY_INTERFACE_MODE_10GBASER
:
1961 break; /* Serdes: Value = 0 */
1962 case PHY_INTERFACE_MODE_HSGMII
:
1963 private_poll_mask
|= BIT(i
);
1965 case PHY_INTERFACE_MODE_USXGMII
:
1966 v
|= BIT(mac_type_bit
[i
]);
1967 uses_usxgmii
= true;
1969 case PHY_INTERFACE_MODE_QSGMII
:
1970 private_poll_mask
|= BIT(i
);
1971 v
|= 3 << mac_type_bit
[i
];
1977 sw_w32(v
, RTL930X_SMI_MAC_TYPE_CTRL
);
1979 /* Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones) */
1980 sw_w32(private_poll_mask
, RTL930X_SMI_PRVTE_POLLING_CTRL
);
1982 /* The following magic values are found in the port configuration, they seem to
1983 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1984 * the XGS1250 and the RTL8226 of the XGS1210
1987 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG
);
1988 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG
);
1989 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG
);
1992 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG
);
1993 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG
);
1994 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG
);
1997 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__
,
1998 sw_r32(RTL930X_SMI_GLB_CTRL
));
1999 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__
,
2000 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL
));
2001 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__
,
2002 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL
));
2003 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__
,
2004 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL
));
2005 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__
,
2006 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG
));
2007 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__
,
2008 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG
));
2009 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__
,
2010 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG
));
2011 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__
,
2012 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL
));
2017 static int rtl931x_mdio_reset(struct mii_bus
*bus
)
2019 struct rtl838x_eth_priv
*priv
= bus
->priv
;
2025 pr_info("%s called\n", __func__
);
2026 /* Disable port polling for configuration purposes */
2027 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
);
2028 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
2031 mdc_on
[0] = mdc_on
[1] = mdc_on
[2] = mdc_on
[3] = false;
2032 /* Mapping of port to phy-addresses on an SMI bus */
2033 poll_sel
[0] = poll_sel
[1] = poll_sel
[2] = poll_sel
[3] = 0;
2034 for (int i
= 0; i
< 56; i
++) {
2038 sw_w32_mask(0x1f << pos
, priv
->smi_addr
[i
] << pos
, RTL931X_SMI_PORT_ADDR
+ (i
/ 6) * 4);
2040 poll_sel
[i
/ 16] |= priv
->smi_bus
[i
] << pos
;
2041 poll_ctrl
|= BIT(20 + priv
->smi_bus
[i
]);
2042 mdc_on
[priv
->smi_bus
[i
]] = true;
2045 /* Configure which SMI bus is behind which port number */
2046 for (int i
= 0; i
< 4; i
++) {
2047 pr_info("poll sel %d, %08x\n", i
, poll_sel
[i
]);
2048 sw_w32(poll_sel
[i
], RTL931X_SMI_PORT_POLLING_SEL
+ (i
* 4));
2051 /* Configure which SMI busses */
2052 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__
, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2
));
2053 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask
, sw_r32(RTL931X_SMI_GLB_CTRL0
));
2054 for (int i
= 0; i
< 4; i
++) {
2055 /* bus is polled in c45 */
2056 if (priv
->smi_bus_isc45
[i
])
2057 c45_mask
|= 0x2 << (i
* 2); /* Std. C45, non-standard is 0x3 */
2058 /* Enable bus access via MDC */
2060 sw_w32_mask(0, BIT(9 + i
), RTL931X_MAC_L2_GLOBAL_CTRL2
);
2063 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__
, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2
));
2064 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask
, sw_r32(RTL931X_SMI_GLB_CTRL0
));
2066 /* We have a 10G PHY enable polling
2067 * sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
2068 * sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
2069 * sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
2071 sw_w32_mask(0xff, c45_mask
, RTL931X_SMI_GLB_CTRL1
);
2076 static int rtl931x_chip_init(struct rtl838x_eth_priv
*priv
)
2078 pr_info("In %s\n", __func__
);
2080 /* Initialize Encapsulation memory and wait until finished */
2081 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT
);
2082 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT
) & 1);
2083 pr_info("%s: init ENCAP done\n", __func__
);
2085 /* Initialize Managemen Information Base memory and wait until finished */
2086 sw_w32(0x1, RTL931X_MEM_MIB_INIT
);
2087 do { } while (sw_r32(RTL931X_MEM_MIB_INIT
) & 1);
2088 pr_info("%s: init MIB done\n", __func__
);
2090 /* Initialize ACL (PIE) memory and wait until finished */
2091 sw_w32(0x1, RTL931X_MEM_ACL_INIT
);
2092 do { } while (sw_r32(RTL931X_MEM_ACL_INIT
) & 1);
2093 pr_info("%s: init ACL done\n", __func__
);
2095 /* Initialize ALE memory and wait until finished */
2096 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0
);
2097 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0
));
2098 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1
);
2099 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2
);
2100 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2
) & 0x7ff);
2101 pr_info("%s: init ALE done\n", __func__
);
2103 /* Enable ESD auto recovery */
2104 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD
);
2106 /* Init SPI, is this for thermal control or what? */
2107 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0
);
2112 static int rtl838x_mdio_init(struct rtl838x_eth_priv
*priv
)
2114 struct device_node
*mii_np
, *dn
;
2118 pr_debug("%s called\n", __func__
);
2119 mii_np
= of_get_child_by_name(priv
->pdev
->dev
.of_node
, "mdio-bus");
2122 dev_err(&priv
->pdev
->dev
, "no %s child node found", "mdio-bus");
2126 if (!of_device_is_available(mii_np
)) {
2131 priv
->mii_bus
= devm_mdiobus_alloc(&priv
->pdev
->dev
);
2132 if (!priv
->mii_bus
) {
2137 switch(priv
->family_id
) {
2138 case RTL8380_FAMILY_ID
:
2139 priv
->mii_bus
->name
= "rtl838x-eth-mdio";
2140 priv
->mii_bus
->read
= rtl838x_mdio_read
;
2141 priv
->mii_bus
->read_paged
= rtl838x_mdio_read_paged
;
2142 priv
->mii_bus
->write
= rtl838x_mdio_write
;
2143 priv
->mii_bus
->write_paged
= rtl838x_mdio_write_paged
;
2144 priv
->mii_bus
->reset
= rtl838x_mdio_reset
;
2146 case RTL8390_FAMILY_ID
:
2147 priv
->mii_bus
->name
= "rtl839x-eth-mdio";
2148 priv
->mii_bus
->read
= rtl839x_mdio_read
;
2149 priv
->mii_bus
->read_paged
= rtl839x_mdio_read_paged
;
2150 priv
->mii_bus
->write
= rtl839x_mdio_write
;
2151 priv
->mii_bus
->write_paged
= rtl839x_mdio_write_paged
;
2152 priv
->mii_bus
->reset
= rtl839x_mdio_reset
;
2154 case RTL9300_FAMILY_ID
:
2155 priv
->mii_bus
->name
= "rtl930x-eth-mdio";
2156 priv
->mii_bus
->read
= rtl930x_mdio_read
;
2157 priv
->mii_bus
->read_paged
= rtl930x_mdio_read_paged
;
2158 priv
->mii_bus
->write
= rtl930x_mdio_write
;
2159 priv
->mii_bus
->write_paged
= rtl930x_mdio_write_paged
;
2160 priv
->mii_bus
->reset
= rtl930x_mdio_reset
;
2161 priv
->mii_bus
->probe_capabilities
= MDIOBUS_C22_C45
;
2163 case RTL9310_FAMILY_ID
:
2164 priv
->mii_bus
->name
= "rtl931x-eth-mdio";
2165 priv
->mii_bus
->read
= rtl931x_mdio_read
;
2166 priv
->mii_bus
->read_paged
= rtl931x_mdio_read_paged
;
2167 priv
->mii_bus
->write
= rtl931x_mdio_write
;
2168 priv
->mii_bus
->write_paged
= rtl931x_mdio_write_paged
;
2169 priv
->mii_bus
->reset
= rtl931x_mdio_reset
;
2170 priv
->mii_bus
->probe_capabilities
= MDIOBUS_C22_C45
;
2173 priv
->mii_bus
->access_capabilities
= MDIOBUS_ACCESS_C22_MMD
;
2174 priv
->mii_bus
->priv
= priv
;
2175 priv
->mii_bus
->parent
= &priv
->pdev
->dev
;
2177 for_each_node_by_name(dn
, "ethernet-phy") {
2180 if (of_property_read_u32(dn
, "reg", &pn
))
2183 if (of_property_read_u32_array(dn
, "rtl9300,smi-address", &smi_addr
[0], 2)) {
2188 if (of_property_read_u32(dn
, "sds", &priv
->sds_id
[pn
]))
2189 priv
->sds_id
[pn
] = -1;
2191 pr_info("set sds port %d to %d\n", pn
, priv
->sds_id
[pn
]);
2194 if (pn
< MAX_PORTS
) {
2195 priv
->smi_bus
[pn
] = smi_addr
[0];
2196 priv
->smi_addr
[pn
] = smi_addr
[1];
2198 pr_err("%s: illegal port number %d\n", __func__
, pn
);
2201 if (of_device_is_compatible(dn
, "ethernet-phy-ieee802.3-c45"))
2202 priv
->smi_bus_isc45
[smi_addr
[0]] = true;
2204 if (of_property_read_bool(dn
, "phy-is-integrated")) {
2205 priv
->phy_is_internal
[pn
] = true;
2209 dn
= of_find_compatible_node(NULL
, NULL
, "realtek,rtl83xx-switch");
2211 dev_err(&priv
->pdev
->dev
, "No RTL switch node in DTS\n");
2215 for_each_node_by_name(dn
, "port") {
2216 if (of_property_read_u32(dn
, "reg", &pn
))
2218 pr_debug("%s Looking at port %d\n", __func__
, pn
);
2219 if (pn
> priv
->cpu_port
)
2221 if (of_get_phy_mode(dn
, &priv
->interfaces
[pn
]))
2222 priv
->interfaces
[pn
] = PHY_INTERFACE_MODE_NA
;
2223 pr_debug("%s phy mode of port %d is %s\n", __func__
, pn
, phy_modes(priv
->interfaces
[pn
]));
2226 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%pOFn", mii_np
);
2227 ret
= of_mdiobus_register(priv
->mii_bus
, mii_np
);
2230 of_node_put(mii_np
);
2235 static int rtl838x_mdio_remove(struct rtl838x_eth_priv
*priv
)
2237 pr_debug("%s called\n", __func__
);
2241 mdiobus_unregister(priv
->mii_bus
);
2242 mdiobus_free(priv
->mii_bus
);
2247 static netdev_features_t
rtl838x_fix_features(struct net_device
*dev
,
2248 netdev_features_t features
)
2253 static int rtl83xx_set_features(struct net_device
*dev
, netdev_features_t features
)
2255 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
2257 if ((features
^ dev
->features
) & NETIF_F_RXCSUM
) {
2258 if (!(features
& NETIF_F_RXCSUM
))
2259 sw_w32_mask(BIT(3), 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
2261 sw_w32_mask(0, BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
2267 static int rtl93xx_set_features(struct net_device
*dev
, netdev_features_t features
)
2269 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
2271 if ((features
^ dev
->features
) & NETIF_F_RXCSUM
) {
2272 if (!(features
& NETIF_F_RXCSUM
))
2273 sw_w32_mask(BIT(4), 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
2275 sw_w32_mask(0, BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
2281 static const struct net_device_ops rtl838x_eth_netdev_ops
= {
2282 .ndo_open
= rtl838x_eth_open
,
2283 .ndo_stop
= rtl838x_eth_stop
,
2284 .ndo_start_xmit
= rtl838x_eth_tx
,
2285 .ndo_select_queue
= rtl83xx_pick_tx_queue
,
2286 .ndo_set_mac_address
= rtl838x_set_mac_address
,
2287 .ndo_validate_addr
= eth_validate_addr
,
2288 .ndo_set_rx_mode
= rtl838x_eth_set_multicast_list
,
2289 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
2290 .ndo_set_features
= rtl83xx_set_features
,
2291 .ndo_fix_features
= rtl838x_fix_features
,
2292 .ndo_setup_tc
= rtl83xx_setup_tc
,
2295 static const struct net_device_ops rtl839x_eth_netdev_ops
= {
2296 .ndo_open
= rtl838x_eth_open
,
2297 .ndo_stop
= rtl838x_eth_stop
,
2298 .ndo_start_xmit
= rtl838x_eth_tx
,
2299 .ndo_select_queue
= rtl83xx_pick_tx_queue
,
2300 .ndo_set_mac_address
= rtl838x_set_mac_address
,
2301 .ndo_validate_addr
= eth_validate_addr
,
2302 .ndo_set_rx_mode
= rtl839x_eth_set_multicast_list
,
2303 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
2304 .ndo_set_features
= rtl83xx_set_features
,
2305 .ndo_fix_features
= rtl838x_fix_features
,
2306 .ndo_setup_tc
= rtl83xx_setup_tc
,
2309 static const struct net_device_ops rtl930x_eth_netdev_ops
= {
2310 .ndo_open
= rtl838x_eth_open
,
2311 .ndo_stop
= rtl838x_eth_stop
,
2312 .ndo_start_xmit
= rtl838x_eth_tx
,
2313 .ndo_select_queue
= rtl93xx_pick_tx_queue
,
2314 .ndo_set_mac_address
= rtl838x_set_mac_address
,
2315 .ndo_validate_addr
= eth_validate_addr
,
2316 .ndo_set_rx_mode
= rtl930x_eth_set_multicast_list
,
2317 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
2318 .ndo_set_features
= rtl93xx_set_features
,
2319 .ndo_fix_features
= rtl838x_fix_features
,
2320 .ndo_setup_tc
= rtl83xx_setup_tc
,
2323 static const struct net_device_ops rtl931x_eth_netdev_ops
= {
2324 .ndo_open
= rtl838x_eth_open
,
2325 .ndo_stop
= rtl838x_eth_stop
,
2326 .ndo_start_xmit
= rtl838x_eth_tx
,
2327 .ndo_select_queue
= rtl93xx_pick_tx_queue
,
2328 .ndo_set_mac_address
= rtl838x_set_mac_address
,
2329 .ndo_validate_addr
= eth_validate_addr
,
2330 .ndo_set_rx_mode
= rtl931x_eth_set_multicast_list
,
2331 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
2332 .ndo_set_features
= rtl93xx_set_features
,
2333 .ndo_fix_features
= rtl838x_fix_features
,
2336 static const struct phylink_mac_ops rtl838x_phylink_ops
= {
2337 .validate
= rtl838x_validate
,
2338 .mac_pcs_get_state
= rtl838x_mac_pcs_get_state
,
2339 .mac_an_restart
= rtl838x_mac_an_restart
,
2340 .mac_config
= rtl838x_mac_config
,
2341 .mac_link_down
= rtl838x_mac_link_down
,
2342 .mac_link_up
= rtl838x_mac_link_up
,
2345 static const struct ethtool_ops rtl838x_ethtool_ops
= {
2346 .get_link_ksettings
= rtl838x_get_link_ksettings
,
2347 .set_link_ksettings
= rtl838x_set_link_ksettings
,
2350 static int __init
rtl838x_eth_probe(struct platform_device
*pdev
)
2352 struct net_device
*dev
;
2353 struct device_node
*dn
= pdev
->dev
.of_node
;
2354 struct rtl838x_eth_priv
*priv
;
2355 struct resource
*res
, *mem
;
2356 phy_interface_t phy_mode
;
2357 struct phylink
*phylink
;
2358 u8 mac_addr
[ETH_ALEN
];
2359 int err
= 0, rxrings
, rxringlen
;
2360 struct ring_b
*ring
;
2362 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2363 (u32
)pdev
, (u32
)(&(pdev
->dev
)));
2366 dev_err(&pdev
->dev
, "No DT found\n");
2370 rxrings
= (soc_info
.family
== RTL8380_FAMILY_ID
2371 || soc_info
.family
== RTL8390_FAMILY_ID
) ? 8 : 32;
2372 rxrings
= rxrings
> MAX_RXRINGS
? MAX_RXRINGS
: rxrings
;
2373 rxringlen
= MAX_ENTRIES
/ rxrings
;
2374 rxringlen
= rxringlen
> MAX_RXLEN
? MAX_RXLEN
: rxringlen
;
2376 dev
= alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv
), TXRINGS
, rxrings
);
2381 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2382 priv
= netdev_priv(dev
);
2384 /* obtain buffer memory space */
2385 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2387 mem
= devm_request_mem_region(&pdev
->dev
, res
->start
,
2388 resource_size(res
), res
->name
);
2390 dev_err(&pdev
->dev
, "cannot request memory space\n");
2395 dev
->mem_start
= mem
->start
;
2396 dev
->mem_end
= mem
->end
;
2398 dev_err(&pdev
->dev
, "cannot request IO resource\n");
2403 /* Allocate buffer memory */
2404 priv
->membase
= dmam_alloc_coherent(&pdev
->dev
, rxrings
* rxringlen
* RING_BUFFER
+
2405 sizeof(struct ring_b
) + sizeof(struct notify_b
),
2406 (void *)&dev
->mem_start
, GFP_KERNEL
);
2407 if (!priv
->membase
) {
2408 dev_err(&pdev
->dev
, "cannot allocate DMA buffer\n");
2413 /* Allocate ring-buffer space at the end of the allocated memory */
2414 ring
= priv
->membase
;
2415 ring
->rx_space
= priv
->membase
+ sizeof(struct ring_b
) + sizeof(struct notify_b
);
2417 spin_lock_init(&priv
->lock
);
2419 dev
->ethtool_ops
= &rtl838x_ethtool_ops
;
2420 dev
->min_mtu
= ETH_ZLEN
;
2421 dev
->max_mtu
= DEFAULT_MTU
;
2422 dev
->features
= NETIF_F_RXCSUM
| NETIF_F_HW_CSUM
;
2423 dev
->hw_features
= NETIF_F_RXCSUM
;
2425 priv
->id
= soc_info
.id
;
2426 priv
->family_id
= soc_info
.family
;
2428 pr_info("Found SoC ID: %4x: %s, family %x\n",
2429 priv
->id
, soc_info
.name
, priv
->family_id
);
2431 pr_err("Unknown chip id (%04x)\n", priv
->id
);
2435 switch (priv
->family_id
) {
2436 case RTL8380_FAMILY_ID
:
2437 priv
->cpu_port
= RTL838X_CPU_PORT
;
2438 priv
->r
= &rtl838x_reg
;
2439 dev
->netdev_ops
= &rtl838x_eth_netdev_ops
;
2441 case RTL8390_FAMILY_ID
:
2442 priv
->cpu_port
= RTL839X_CPU_PORT
;
2443 priv
->r
= &rtl839x_reg
;
2444 dev
->netdev_ops
= &rtl839x_eth_netdev_ops
;
2446 case RTL9300_FAMILY_ID
:
2447 priv
->cpu_port
= RTL930X_CPU_PORT
;
2448 priv
->r
= &rtl930x_reg
;
2449 dev
->netdev_ops
= &rtl930x_eth_netdev_ops
;
2451 case RTL9310_FAMILY_ID
:
2452 priv
->cpu_port
= RTL931X_CPU_PORT
;
2453 priv
->r
= &rtl931x_reg
;
2454 dev
->netdev_ops
= &rtl931x_eth_netdev_ops
;
2455 rtl931x_chip_init(priv
);
2458 pr_err("Unknown SoC family\n");
2461 priv
->rxringlen
= rxringlen
;
2462 priv
->rxrings
= rxrings
;
2464 /* Obtain device IRQ number */
2465 dev
->irq
= platform_get_irq(pdev
, 0);
2467 dev_err(&pdev
->dev
, "cannot obtain network-device IRQ\n");
2471 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, priv
->r
->net_irq
,
2472 IRQF_SHARED
, dev
->name
, dev
);
2474 dev_err(&pdev
->dev
, "%s: could not acquire interrupt: %d\n",
2479 rtl8380_init_mac(priv
);
2481 /* Try to get mac address in the following order:
2482 * 1) from device tree data
2483 * 2) from internal registers set by bootloader
2485 of_get_mac_address(pdev
->dev
.of_node
, mac_addr
);
2486 if (is_valid_ether_addr(mac_addr
)) {
2487 rtl838x_set_mac_hw(dev
, mac_addr
);
2489 mac_addr
[0] = (sw_r32(priv
->r
->mac
) >> 8) & 0xff;
2490 mac_addr
[1] = sw_r32(priv
->r
->mac
) & 0xff;
2491 mac_addr
[2] = (sw_r32(priv
->r
->mac
+ 4) >> 24) & 0xff;
2492 mac_addr
[3] = (sw_r32(priv
->r
->mac
+ 4) >> 16) & 0xff;
2493 mac_addr
[4] = (sw_r32(priv
->r
->mac
+ 4) >> 8) & 0xff;
2494 mac_addr
[5] = sw_r32(priv
->r
->mac
+ 4) & 0xff;
2496 dev_addr_set(dev
, mac_addr
);
2497 /* if the address is invalid, use a random value */
2498 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2499 struct sockaddr sa
= { AF_UNSPEC
};
2501 netdev_warn(dev
, "Invalid MAC address, using random\n");
2502 eth_hw_addr_random(dev
);
2503 memcpy(sa
.sa_data
, dev
->dev_addr
, ETH_ALEN
);
2504 if (rtl838x_set_mac_address(dev
, &sa
))
2505 netdev_warn(dev
, "Failed to set MAC address.\n");
2507 pr_info("Using MAC %08x%08x\n", sw_r32(priv
->r
->mac
),
2508 sw_r32(priv
->r
->mac
+ 4));
2509 strcpy(dev
->name
, "eth%d");
2513 err
= rtl838x_mdio_init(priv
);
2517 err
= register_netdev(dev
);
2521 for (int i
= 0; i
< priv
->rxrings
; i
++) {
2522 priv
->rx_qs
[i
].id
= i
;
2523 priv
->rx_qs
[i
].priv
= priv
;
2524 netif_napi_add(dev
, &priv
->rx_qs
[i
].napi
, rtl838x_poll_rx
, 64);
2527 platform_set_drvdata(pdev
, dev
);
2529 phy_mode
= PHY_INTERFACE_MODE_NA
;
2530 err
= of_get_phy_mode(dn
, &phy_mode
);
2532 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
2536 priv
->phylink_config
.dev
= &dev
->dev
;
2537 priv
->phylink_config
.type
= PHYLINK_NETDEV
;
2539 phylink
= phylink_create(&priv
->phylink_config
, pdev
->dev
.fwnode
,
2540 phy_mode
, &rtl838x_phylink_ops
);
2542 if (IS_ERR(phylink
)) {
2543 err
= PTR_ERR(phylink
);
2546 priv
->phylink
= phylink
;
2551 pr_err("Error setting up netdev, freeing it again.\n");
2557 static int rtl838x_eth_remove(struct platform_device
*pdev
)
2559 struct net_device
*dev
= platform_get_drvdata(pdev
);
2560 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
2563 pr_info("Removing platform driver for rtl838x-eth\n");
2564 rtl838x_mdio_remove(priv
);
2565 rtl838x_hw_stop(priv
);
2567 netif_tx_stop_all_queues(dev
);
2569 for (int i
= 0; i
< priv
->rxrings
; i
++)
2570 netif_napi_del(&priv
->rx_qs
[i
].napi
);
2572 unregister_netdev(dev
);
2579 static const struct of_device_id rtl838x_eth_of_ids
[] = {
2580 { .compatible
= "realtek,rtl838x-eth"},
2583 MODULE_DEVICE_TABLE(of
, rtl838x_eth_of_ids
);
2585 static struct platform_driver rtl838x_eth_driver
= {
2586 .probe
= rtl838x_eth_probe
,
2587 .remove
= rtl838x_eth_remove
,
2589 .name
= "rtl838x-eth",
2591 .of_match_table
= rtl838x_eth_of_ids
,
2595 module_platform_driver(rtl838x_eth_driver
);
2597 MODULE_AUTHOR("B. Koblitz");
2598 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2599 MODULE_LICENSE("GPL");