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realtek: rtl839x: support rtl8214fc on rtl8393
[openwrt/staging/stintel.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
16 #include <linux/mdio.h>
17
18 #include <asm/mach-rtl838x/mach-rtl83xx.h>
19 #include "rtl83xx-phy.h"
20
21 extern struct rtl83xx_soc_info soc_info;
22 extern struct mutex smi_lock;
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /* Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_CHIP_ID 0x6276
50
51 #define RTL821X_MEDIA_PAGE_AUTO 0
52 #define RTL821X_MEDIA_PAGE_COPPER 1
53 #define RTL821X_MEDIA_PAGE_FIBRE 3
54 #define RTL821X_MEDIA_PAGE_INTERNAL 8
55
56 #define RTL9300_PHY_ID_MASK 0xf0ffffff
57
58 /* RTL930X SerDes supports the following modes:
59 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
60 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
61 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
62 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
63 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
64 */
65 #define RTL930X_SDS_MODE_SGMII 0x02
66 #define RTL930X_SDS_MODE_1000BASEX 0x04
67 #define RTL930X_SDS_MODE_USXGMII 0x0d
68 #define RTL930X_SDS_MODE_XGMII 0x10
69 #define RTL930X_SDS_MODE_HSGMII 0x12
70 #define RTL930X_SDS_MODE_2500BASEX 0x16
71 #define RTL930X_SDS_MODE_10GBASER 0x1a
72 #define RTL930X_SDS_OFF 0x1f
73 #define RTL930X_SDS_MASK 0x1f
74
75 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
76 * bus to detect e.g. link and media changes. For operations on the PHYs such as
77 * patching or other configuration changes such as EEE, polling needs to be disabled
78 * since otherwise these operations may fails or lead to unpredictable results.
79 */
80 DEFINE_MUTEX(poll_lock);
81
82 static const struct firmware rtl838x_8380_fw;
83 static const struct firmware rtl838x_8214fc_fw;
84 static const struct firmware rtl838x_8218b_fw;
85
86 static u64 disable_polling(int port)
87 {
88 u64 saved_state;
89
90 mutex_lock(&poll_lock);
91
92 switch (soc_info.family) {
93 case RTL8380_FAMILY_ID:
94 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
95 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
96 break;
97 case RTL8390_FAMILY_ID:
98 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
99 saved_state <<= 32;
100 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
101 sw_w32_mask(BIT(port % 32), 0,
102 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
103 break;
104 case RTL9300_FAMILY_ID:
105 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
106 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
107 break;
108 case RTL9310_FAMILY_ID:
109 pr_warn("%s not implemented for RTL931X\n", __func__);
110 break;
111 }
112
113 mutex_unlock(&poll_lock);
114
115 return saved_state;
116 }
117
118 static int resume_polling(u64 saved_state)
119 {
120 mutex_lock(&poll_lock);
121
122 switch (soc_info.family) {
123 case RTL8380_FAMILY_ID:
124 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
125 break;
126 case RTL8390_FAMILY_ID:
127 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
128 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
129 break;
130 case RTL9300_FAMILY_ID:
131 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
132 break;
133 case RTL9310_FAMILY_ID:
134 pr_warn("%s not implemented for RTL931X\n", __func__);
135 break;
136 }
137
138 mutex_unlock(&poll_lock);
139
140 return 0;
141 }
142
143 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
144 {
145 phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
146 }
147
148 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
149 {
150 /* fiber ports */
151 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
152 phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
153
154 /* copper ports */
155 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
156 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
157 }
158
159 static void rtl8380_phy_reset(struct phy_device *phydev)
160 {
161 phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
162 }
163
164 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
165 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
166 0x02A4, 0x02A4, 0x0198, 0x0198 };
167 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
168
169 /* Reset the SerDes by powering it off and set a new operation mode
170 * of the SerDes.
171 */
172 void rtl9300_sds_rst(int sds_num, u32 mode)
173 {
174 pr_info("%s %d\n", __func__, mode);
175 if (sds_num < 0 || sds_num > 11) {
176 pr_err("Wrong SerDes number: %d\n", sds_num);
177 return;
178 }
179
180 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num],
181 RTL930X_SDS_OFF << rtl9300_sds_lsb[sds_num],
182 rtl9300_sds_regs[sds_num]);
183 mdelay(10);
184
185 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
186 rtl9300_sds_regs[sds_num]);
187 mdelay(10);
188
189 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
190 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
191 }
192
193 void rtl9300_sds_set(int sds_num, u32 mode)
194 {
195 pr_info("%s %d\n", __func__, mode);
196 if (sds_num < 0 || sds_num > 11) {
197 pr_err("Wrong SerDes number: %d\n", sds_num);
198 return;
199 }
200
201 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
202 rtl9300_sds_regs[sds_num]);
203 mdelay(10);
204
205 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
206 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
207 }
208
209 u32 rtl9300_sds_mode_get(int sds_num)
210 {
211 u32 v;
212
213 if (sds_num < 0 || sds_num > 11) {
214 pr_err("Wrong SerDes number: %d\n", sds_num);
215 return 0;
216 }
217
218 v = sw_r32(rtl9300_sds_regs[sds_num]);
219 v >>= rtl9300_sds_lsb[sds_num];
220
221 return v & RTL930X_SDS_MASK;
222 }
223
224 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
225 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
226 */
227 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
228 {
229 int offset = 0;
230 int reg;
231 u32 val;
232
233 /* not sure about this one, but without it we get a "ghost" internal SERDES on addr 63 which causes breakage
234 * [ 3.076655] rtl8393_serdes_probe: id: 63
235 * [ 3.081135] Realtek RTL8393 SERDES rtl838x slave mii-0:3f: Detected internal RTL8390 SERDES
236 */
237 if (phy_addr > RTL839X_CPU_PORT)
238 return -EIO;
239
240 if (phy_addr == 49)
241 offset = 0x100;
242
243 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
244 * which would otherwise read as 0.
245 */
246 if (soc_info.id == 0x8393) {
247 if (phy_reg == MII_PHYSID1)
248 return 0x1c;
249 if (phy_reg == MII_PHYSID2)
250 return 0x8393;
251 }
252
253 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
254 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
255 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
256 * one 32 bit register.
257 */
258 reg = (phy_reg << 1) & 0xfc;
259 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
260
261 if (phy_reg & 1)
262 val = (val >> 16) & 0xffff;
263 else
264 val &= 0xffff;
265
266 return val;
267 }
268
269 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
270 * register which simulates commands to an internal MDIO bus.
271 */
272 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
273 {
274 int i;
275 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
276
277 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
278
279 for (i = 0; i < 100; i++) {
280 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
281 break;
282 mdelay(1);
283 }
284
285 if (i >= 100)
286 return -EIO;
287
288 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
289 }
290
291 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
292 {
293 int i;
294 u32 cmd;
295
296 sw_w32(v, RTL930X_SDS_INDACS_DATA);
297 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
298
299 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
300
301 for (i = 0; i < 100; i++) {
302 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
303 break;
304 mdelay(1);
305 }
306
307
308 if (i >= 100) {
309 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
310 return -EIO;
311 }
312
313 return 0;
314 }
315
316 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
317 {
318 int i;
319 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
320
321 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
322 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
323
324 for (i = 0; i < 100; i++) {
325 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
326 break;
327 mdelay(1);
328 }
329
330 if (i >= 100)
331 return -EIO;
332
333 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
334
335 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
336 }
337
338 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
339 {
340 int i;
341 u32 cmd;
342
343 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
344 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
345
346 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
347
348 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
349 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
350
351 for (i = 0; i < 100; i++) {
352 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
353 break;
354 mdelay(1);
355 }
356
357 if (i >= 100)
358 return -EIO;
359
360 return 0;
361 }
362
363 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
364 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
365 * in a standard page 0 of a PHY
366 */
367 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
368 {
369 int offset = 0;
370 u32 val;
371
372 if (phy_addr == 26)
373 offset = 0x100;
374 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
375
376 return val;
377 }
378
379 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
380 {
381 int offset = 0;
382 int reg;
383 u32 val;
384
385 if (phy_addr == 49)
386 offset = 0x100;
387
388 reg = (phy_reg << 1) & 0xfc;
389 val = v;
390 if (phy_reg & 1) {
391 val = val << 16;
392 sw_w32_mask(0xffff0000, val,
393 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
394 } else {
395 sw_w32_mask(0xffff, val,
396 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
397 }
398
399 return 0;
400 }
401
402 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
403 * ports of the RTL838x SoCs
404 */
405 static int rtl8380_read_status(struct phy_device *phydev)
406 {
407 int err;
408
409 err = genphy_read_status(phydev);
410
411 if (phydev->link) {
412 phydev->speed = SPEED_1000;
413 phydev->duplex = DUPLEX_FULL;
414 }
415
416 return err;
417 }
418
419 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
420 * ports of the RTL8393 SoC
421 */
422 static int rtl8393_read_status(struct phy_device *phydev)
423 {
424 int offset = 0;
425 int err;
426 int phy_addr = phydev->mdio.addr;
427 u32 v;
428
429 err = genphy_read_status(phydev);
430 if (phy_addr == 49)
431 offset = 0x100;
432
433 if (phydev->link) {
434 phydev->speed = SPEED_100;
435 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
436 * PHY registers
437 */
438 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
439 if (!(v & (1 << 13)) && (v & (1 << 6)))
440 phydev->speed = SPEED_1000;
441 phydev->duplex = DUPLEX_FULL;
442 }
443
444 return err;
445 }
446
447 static int rtl8226_read_page(struct phy_device *phydev)
448 {
449 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
450 }
451
452 static int rtl8226_write_page(struct phy_device *phydev, int page)
453 {
454 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
455 }
456
457 static int rtl8226_read_status(struct phy_device *phydev)
458 {
459 int ret = 0;
460 u32 val;
461
462 /* TODO: ret = genphy_read_status(phydev);
463 * if (ret < 0) {
464 * pr_info("%s: genphy_read_status failed\n", __func__);
465 * return ret;
466 * }
467 */
468
469 /* Link status must be read twice */
470 for (int i = 0; i < 2; i++)
471 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
472
473 phydev->link = val & BIT(2) ? 1 : 0;
474 if (!phydev->link)
475 goto out;
476
477 /* Read duplex status */
478 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
479 if (val < 0)
480 goto out;
481 phydev->duplex = !!(val & BIT(3));
482
483 /* Read speed */
484 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
485 switch (val & 0x0630) {
486 case 0x0000:
487 phydev->speed = SPEED_10;
488 break;
489 case 0x0010:
490 phydev->speed = SPEED_100;
491 break;
492 case 0x0020:
493 phydev->speed = SPEED_1000;
494 break;
495 case 0x0200:
496 phydev->speed = SPEED_10000;
497 break;
498 case 0x0210:
499 phydev->speed = SPEED_2500;
500 break;
501 case 0x0220:
502 phydev->speed = SPEED_5000;
503 break;
504 default:
505 break;
506 }
507
508 out:
509 return ret;
510 }
511
512 static int rtl8226_advertise_aneg(struct phy_device *phydev)
513 {
514 int ret = 0;
515 u32 v;
516
517 pr_info("In %s\n", __func__);
518
519 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
520 if (v < 0)
521 goto out;
522
523 v |= ADVERTISE_10HALF;
524 v |= ADVERTISE_10FULL;
525 v |= ADVERTISE_100HALF;
526 v |= ADVERTISE_100FULL;
527
528 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
529
530 /* Allow 1GBit */
531 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
532 if (v < 0)
533 goto out;
534 v |= ADVERTISE_1000FULL;
535
536 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
537 if (ret < 0)
538 goto out;
539
540 /* Allow 2.5G */
541 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
542 if (v < 0)
543 goto out;
544
545 v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
546 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
547
548 out:
549 return ret;
550 }
551
552 static int rtl8226_config_aneg(struct phy_device *phydev)
553 {
554 int ret = 0;
555 u32 v;
556
557 pr_debug("In %s\n", __func__);
558 if (phydev->autoneg == AUTONEG_ENABLE) {
559 ret = rtl8226_advertise_aneg(phydev);
560 if (ret)
561 goto out;
562 /* AutoNegotiationEnable */
563 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
564 if (v < 0)
565 goto out;
566
567 v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
568 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
569 if (ret < 0)
570 goto out;
571
572 /* RestartAutoNegotiation */
573 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
574 if (v < 0)
575 goto out;
576 v |= MDIO_AN_CTRL1_RESTART;
577
578 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
579 }
580
581 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
582
583 out:
584 return ret;
585 }
586
587 static int rtl8226_get_eee(struct phy_device *phydev,
588 struct ethtool_eee *e)
589 {
590 u32 val;
591 int addr = phydev->mdio.addr;
592
593 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
594
595 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
596 if (e->eee_enabled) {
597 e->eee_enabled = !!(val & MDIO_EEE_100TX);
598 if (!e->eee_enabled) {
599 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
600 e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
601 }
602 }
603 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
604
605 return 0;
606 }
607
608 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
609 {
610 int port = phydev->mdio.addr;
611 u64 poll_state;
612 bool an_enabled;
613 u32 val;
614
615 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
616
617 poll_state = disable_polling(port);
618
619 /* Remember aneg state */
620 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
621 an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
622
623 /* Setup 100/1000MBit */
624 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
625 if (e->eee_enabled)
626 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
627 else
628 val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
629 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
630
631 /* Setup 2.5GBit */
632 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
633 if (e->eee_enabled)
634 val |= MDIO_EEE_2_5GT;
635 else
636 val &= MDIO_EEE_2_5GT;
637 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
638
639 /* RestartAutoNegotiation */
640 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
641 val |= MDIO_AN_CTRL1_RESTART;
642 phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
643
644 resume_polling(poll_state);
645
646 return 0;
647 }
648
649 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
650 const struct firmware *fw,
651 const char *name)
652 {
653 struct device *dev = &phydev->mdio.dev;
654 int err;
655 struct fw_header *h;
656 uint32_t checksum, my_checksum;
657
658 err = request_firmware(&fw, name, dev);
659 if (err < 0)
660 goto out;
661
662 if (fw->size < sizeof(struct fw_header)) {
663 pr_err("Firmware size too small.\n");
664 err = -EINVAL;
665 goto out;
666 }
667
668 h = (struct fw_header *) fw->data;
669 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
670
671 if (h->magic != 0x83808380) {
672 pr_err("Wrong firmware file: MAGIC mismatch.\n");
673 goto out;
674 }
675
676 checksum = h->checksum;
677 h->checksum = 0;
678 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
679 if (checksum != my_checksum) {
680 pr_err("Firmware checksum mismatch.\n");
681 err = -EINVAL;
682 goto out;
683 }
684 h->checksum = checksum;
685
686 return h;
687 out:
688 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
689 return NULL;
690 }
691
692 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
693 {
694 int mac = phydev->mdio.addr;
695
696 /* select main page 0 */
697 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
698 /* write to 0x8 to register 0x1d on main page 0 */
699 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
700 /* select page 0x266 */
701 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
702 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
703 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
704 /* return to main page 0 */
705 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
706 /* write to 0x0 to register 0x1d on main page 0 */
707 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
708 mdelay(1);
709 }
710
711 static int rtl8390_configure_generic(struct phy_device *phydev)
712 {
713 int mac = phydev->mdio.addr;
714 u32 val, phy_id;
715
716 val = phy_read(phydev, 2);
717 phy_id = val << 16;
718 val = phy_read(phydev, 3);
719 phy_id |= val;
720 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
721
722 /* Read internal PHY ID */
723 phy_write_paged(phydev, 31, 27, 0x0002);
724 val = phy_read_paged(phydev, 31, 28);
725
726 /* Internal RTL8218B, version 2 */
727 phydev_info(phydev, "Detected unknown %x\n", val);
728
729 return 0;
730 }
731
732 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
733 {
734 u32 val, phy_id;
735 int mac = phydev->mdio.addr;
736 struct fw_header *h;
737 u32 *rtl838x_6275B_intPhy_perport;
738 u32 *rtl8218b_6276B_hwEsd_perport;
739
740 val = phy_read(phydev, 2);
741 phy_id = val << 16;
742 val = phy_read(phydev, 3);
743 phy_id |= val;
744 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
745
746 /* Read internal PHY ID */
747 phy_write_paged(phydev, 31, 27, 0x0002);
748 val = phy_read_paged(phydev, 31, 28);
749 if (val != 0x6275) {
750 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
751 return -1;
752 }
753
754 /* Internal RTL8218B, version 2 */
755 phydev_info(phydev, "Detected internal RTL8218B\n");
756
757 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
758 if (!h)
759 return -1;
760
761 if (h->phy != 0x83800000) {
762 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
763 return -1;
764 }
765
766 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
767 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
768
769 // Currently not used
770 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
771 // int ipd_flag = 1;
772 // }
773
774 val = phy_read(phydev, MII_BMCR);
775 if (val & BMCR_PDOWN)
776 rtl8380_int_phy_on_off(phydev, true);
777 else
778 rtl8380_phy_reset(phydev);
779 msleep(100);
780
781 /* Ready PHY for patch */
782 for (int p = 0; p < 8; p++) {
783 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
784 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
785 }
786 msleep(500);
787 for (int p = 0; p < 8; p++) {
788 int i;
789
790 for (i = 0; i < 100 ; i++) {
791 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
792 if (val & 0x40)
793 break;
794 }
795 if (i >= 100) {
796 phydev_err(phydev,
797 "ERROR: Port %d not ready for patch.\n",
798 mac + p);
799 return -1;
800 }
801 }
802 for (int p = 0; p < 8; p++) {
803 int i;
804
805 i = 0;
806 while (rtl838x_6275B_intPhy_perport[i * 2]) {
807 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
808 rtl838x_6275B_intPhy_perport[i * 2],
809 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
810 i++;
811 }
812 i = 0;
813 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
814 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
815 rtl8218b_6276B_hwEsd_perport[i * 2],
816 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
817 i++;
818 }
819 }
820
821 return 0;
822 }
823
824 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
825 {
826 u32 val, ipd, phy_id;
827 int mac = phydev->mdio.addr;
828 struct fw_header *h;
829 u32 *rtl8380_rtl8218b_perchip;
830 u32 *rtl8218B_6276B_rtl8380_perport;
831 u32 *rtl8380_rtl8218b_perport;
832
833 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
834 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
835 return -1;
836 }
837 val = phy_read(phydev, 2);
838 phy_id = val << 16;
839 val = phy_read(phydev, 3);
840 phy_id |= val;
841 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
842
843 /* Read internal PHY ID */
844 phy_write_paged(phydev, 31, 27, 0x0002);
845 val = phy_read_paged(phydev, 31, 28);
846 if (val != RTL821X_CHIP_ID) {
847 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
848 return -1;
849 }
850 phydev_info(phydev, "Detected external RTL8218B\n");
851
852 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
853 if (!h)
854 return -1;
855
856 if (h->phy != 0x8218b000) {
857 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
858 return -1;
859 }
860
861 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
862 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
863 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
864
865 val = phy_read(phydev, MII_BMCR);
866 if (val & BMCR_PDOWN)
867 rtl8380_int_phy_on_off(phydev, true);
868 else
869 rtl8380_phy_reset(phydev);
870
871 msleep(100);
872
873 /* Get Chip revision */
874 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
875 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
876 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
877
878 phydev_info(phydev, "Detected chip revision %04x\n", val);
879
880 for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
881 rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
882 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
883 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
884 rtl8380_rtl8218b_perchip[i * 3 + 2]);
885 }
886
887 /* Enable PHY */
888 for (int i = 0; i < 8; i++) {
889 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
890 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
891 }
892 mdelay(100);
893
894 /* Request patch */
895 for (int i = 0; i < 8; i++) {
896 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
897 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
898 }
899
900 mdelay(300);
901
902 /* Verify patch readiness */
903 for (int i = 0; i < 8; i++) {
904 int l;
905
906 for (l = 0; l < 100; l++) {
907 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
908 if (val & 0x40)
909 break;
910 }
911 if (l >= 100) {
912 phydev_err(phydev, "Could not patch PHY\n");
913 return -1;
914 }
915 }
916
917 /* Use Broadcast ID method for patching */
918 rtl821x_phy_setup_package_broadcast(phydev, true);
919
920 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
921 phy_write_paged(phydev, 0x26e, 17, 0xb);
922 phy_write_paged(phydev, 0x26e, 16, 0x2);
923 mdelay(1);
924 ipd = phy_read_paged(phydev, 0x26e, 19);
925 phy_write_paged(phydev, 0, 30, 0);
926 ipd = (ipd >> 4) & 0xf; /* unused ? */
927
928 for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
929 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
930 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
931 }
932
933 /* Disable broadcast ID */
934 rtl821x_phy_setup_package_broadcast(phydev, false);
935
936 return 0;
937 }
938
939 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
940 {
941 int addr = phydev->mdio.addr;
942
943 /* Both the RTL8214FC and the external RTL8218B have the same
944 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
945 * at PHY IDs 0-7, while the RTL8214FC must be attached via
946 * the pair of SGMII/1000Base-X with higher PHY-IDs
947 */
948 if (soc_info.family == RTL8380_FAMILY_ID)
949 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
950 else
951 return phydev->phy_id == PHY_ID_RTL8218B_E;
952 }
953
954 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
955 {
956 int mac = phydev->mdio.addr;
957
958 static int reg[] = {16, 19, 20, 21};
959 u32 val;
960
961 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
962 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
963 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
964
965 if (val & BMCR_PDOWN)
966 return false;
967
968 return true;
969 }
970
971 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
972 {
973 char *state = on ? "on" : "off";
974
975 if (port == PORT_FIBRE) {
976 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
977 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
978 } else {
979 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
980 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
981 }
982
983 if (on) {
984 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
985 } else {
986 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
987 }
988
989 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
990 }
991
992 static int rtl8214fc_suspend(struct phy_device *phydev)
993 {
994 rtl8214fc_power_set(phydev, PORT_MII, false);
995 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
996
997 return 0;
998 }
999
1000 static int rtl8214fc_resume(struct phy_device *phydev)
1001 {
1002 if (rtl8214fc_media_is_fibre(phydev)) {
1003 rtl8214fc_power_set(phydev, PORT_MII, false);
1004 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1005 } else {
1006 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1007 rtl8214fc_power_set(phydev, PORT_MII, true);
1008 }
1009
1010 return 0;
1011 }
1012
1013 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
1014 {
1015 int mac = phydev->mdio.addr;
1016
1017 static int reg[] = {16, 19, 20, 21};
1018 int val;
1019
1020 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1021 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1022 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1023
1024 val |= BIT(10);
1025 if (set_fibre) {
1026 val &= ~BMCR_PDOWN;
1027 } else {
1028 val |= BMCR_PDOWN;
1029 }
1030
1031 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1032 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1033 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1034
1035 if (!phydev->suspended) {
1036 if (set_fibre) {
1037 rtl8214fc_power_set(phydev, PORT_MII, false);
1038 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1039 } else {
1040 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1041 rtl8214fc_power_set(phydev, PORT_MII, true);
1042 }
1043 }
1044 }
1045
1046 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1047 {
1048 bool is_fibre = (port == PORT_FIBRE ? true : false);
1049 int addr = phydev->mdio.addr;
1050
1051 pr_debug("%s port %d to %d\n", __func__, addr, port);
1052
1053 rtl8214fc_media_set(phydev, is_fibre);
1054
1055 return 0;
1056 }
1057
1058 static int rtl8214fc_get_port(struct phy_device *phydev)
1059 {
1060 int addr = phydev->mdio.addr;
1061
1062 pr_debug("%s: port %d\n", __func__, addr);
1063 if (rtl8214fc_media_is_fibre(phydev))
1064 return PORT_FIBRE;
1065
1066 return PORT_MII;
1067 }
1068
1069 /* Enable EEE on the RTL8218B PHYs
1070 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1071 * but the only way that works since the kernel first enables EEE in the MAC
1072 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1073 */
1074 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1075 {
1076 u32 val;
1077 bool an_enabled;
1078
1079 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1080 /* Set GPHY page to copper */
1081 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1082
1083 val = phy_read(phydev, MII_BMCR);
1084 an_enabled = val & BMCR_ANENABLE;
1085
1086 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1087 val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
1088 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1089
1090 /* 500M EEE ability */
1091 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1092 if (enable)
1093 val |= BIT(7);
1094 else
1095 val &= ~BIT(7);
1096 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1097
1098 /* Restart AN if enabled */
1099 if (an_enabled) {
1100 val = phy_read(phydev, MII_BMCR);
1101 val |= BMCR_ANRESTART;
1102 phy_write(phydev, MII_BMCR, val);
1103 }
1104
1105 /* GPHY page back to auto */
1106 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1107 }
1108
1109 static int rtl8218b_get_eee(struct phy_device *phydev,
1110 struct ethtool_eee *e)
1111 {
1112 u32 val;
1113 int addr = phydev->mdio.addr;
1114
1115 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1116
1117 /* Set GPHY page to copper */
1118 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1119
1120 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1121 if (e->eee_enabled) {
1122 /* Verify vs MAC-based EEE */
1123 e->eee_enabled = !!(val & BIT(7));
1124 if (!e->eee_enabled) {
1125 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1126 e->eee_enabled = !!(val & BIT(4));
1127 }
1128 }
1129 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1130
1131 /* GPHY page to auto */
1132 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1133
1134 return 0;
1135 }
1136
1137 static int rtl8218d_get_eee(struct phy_device *phydev,
1138 struct ethtool_eee *e)
1139 {
1140 u32 val;
1141 int addr = phydev->mdio.addr;
1142
1143 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1144
1145 /* Set GPHY page to copper */
1146 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1147
1148 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1149 if (e->eee_enabled)
1150 e->eee_enabled = !!(val & BIT(7));
1151 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1152
1153 /* GPHY page to auto */
1154 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1155
1156 return 0;
1157 }
1158
1159 static int rtl8214fc_set_eee(struct phy_device *phydev,
1160 struct ethtool_eee *e)
1161 {
1162 u32 poll_state;
1163 int port = phydev->mdio.addr;
1164 bool an_enabled;
1165 u32 val;
1166
1167 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1168
1169 if (rtl8214fc_media_is_fibre(phydev)) {
1170 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1171 return -ENOTSUPP;
1172 }
1173
1174 poll_state = disable_polling(port);
1175
1176 /* Set GPHY page to copper */
1177 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1178
1179 /* Get auto-negotiation status */
1180 val = phy_read(phydev, MII_BMCR);
1181 an_enabled = val & BMCR_ANENABLE;
1182
1183 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1184 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1185 val &= ~BIT(5); /* Use MAC-based EEE */
1186 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1187
1188 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1189 phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1190
1191 /* 500M EEE ability */
1192 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1193 if (e->eee_enabled)
1194 val |= BIT(7);
1195 else
1196 val &= ~BIT(7);
1197
1198 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1199
1200 /* Restart AN if enabled */
1201 if (an_enabled) {
1202 pr_info("%s: doing aneg\n", __func__);
1203 val = phy_read(phydev, MII_BMCR);
1204 val |= BMCR_ANRESTART;
1205 phy_write(phydev, MII_BMCR, val);
1206 }
1207
1208 /* GPHY page back to auto */
1209 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1210
1211 resume_polling(poll_state);
1212
1213 return 0;
1214 }
1215
1216 static int rtl8214fc_get_eee(struct phy_device *phydev,
1217 struct ethtool_eee *e)
1218 {
1219 int addr = phydev->mdio.addr;
1220
1221 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1222 if (rtl8214fc_media_is_fibre(phydev)) {
1223 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1224 return -ENOTSUPP;
1225 }
1226
1227 return rtl8218b_get_eee(phydev, e);
1228 }
1229
1230 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1231 {
1232 int port = phydev->mdio.addr;
1233 u64 poll_state;
1234 u32 val;
1235 bool an_enabled;
1236
1237 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1238
1239 poll_state = disable_polling(port);
1240
1241 /* Set GPHY page to copper */
1242 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1243 val = phy_read(phydev, MII_BMCR);
1244 an_enabled = val & BMCR_ANENABLE;
1245
1246 if (e->eee_enabled) {
1247 /* 100/1000M EEE Capability */
1248 phy_write(phydev, 13, 0x0007);
1249 phy_write(phydev, 14, 0x003C);
1250 phy_write(phydev, 13, 0x4007);
1251 phy_write(phydev, 14, 0x0006);
1252
1253 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1254 val |= BIT(4);
1255 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1256 } else {
1257 /* 100/1000M EEE Capability */
1258 phy_write(phydev, 13, 0x0007);
1259 phy_write(phydev, 14, 0x003C);
1260 phy_write(phydev, 13, 0x0007);
1261 phy_write(phydev, 14, 0x0000);
1262
1263 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1264 val &= ~BIT(4);
1265 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1266 }
1267
1268 /* Restart AN if enabled */
1269 if (an_enabled) {
1270 val = phy_read(phydev, MII_BMCR);
1271 val |= BMCR_ANRESTART;
1272 phy_write(phydev, MII_BMCR, val);
1273 }
1274
1275 /* GPHY page back to auto */
1276 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1277
1278 pr_info("%s done\n", __func__);
1279 resume_polling(poll_state);
1280
1281 return 0;
1282 }
1283
1284 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1285 {
1286 int addr = phydev->mdio.addr;
1287 u64 poll_state;
1288
1289 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1290
1291 poll_state = disable_polling(addr);
1292
1293 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1294
1295 resume_polling(poll_state);
1296
1297 return 0;
1298 }
1299
1300 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1301 {
1302 return phydev->phy_id == PHY_ID_RTL8214C;
1303 }
1304
1305 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1306 {
1307 u32 phy_id, val;
1308 int mac = phydev->mdio.addr;
1309
1310 val = phy_read(phydev, 2);
1311 phy_id = val << 16;
1312 val = phy_read(phydev, 3);
1313 phy_id |= val;
1314 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1315
1316 phydev_info(phydev, "Detected external RTL8214C\n");
1317
1318 /* GPHY auto conf */
1319 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1320
1321 return 0;
1322 }
1323
1324 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1325 {
1326 int mac = phydev->mdio.addr;
1327 struct fw_header *h;
1328 u32 *rtl8380_rtl8214fc_perchip;
1329 u32 *rtl8380_rtl8214fc_perport;
1330 u32 phy_id;
1331 u32 val;
1332
1333 val = phy_read(phydev, 2);
1334 phy_id = val << 16;
1335 val = phy_read(phydev, 3);
1336 phy_id |= val;
1337 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1338
1339 /* Read internal PHY id */
1340 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1341 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1342 val = phy_read_paged(phydev, 0x1f, 0x1c);
1343 if (val != RTL821X_CHIP_ID) {
1344 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1345 return -1;
1346 }
1347 phydev_info(phydev, "Detected external RTL8214FC\n");
1348
1349 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1350 if (!h)
1351 return -1;
1352
1353 if (h->phy != 0x8214fc00) {
1354 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1355 return -1;
1356 }
1357
1358 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1359
1360 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1361
1362 /* detect phy version */
1363 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1364 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1365
1366 val = phy_read(phydev, 16);
1367 if (val & BMCR_PDOWN)
1368 rtl8380_rtl8214fc_on_off(phydev, true);
1369 else
1370 rtl8380_phy_reset(phydev);
1371
1372 msleep(100);
1373 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1374
1375 for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
1376 rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
1377 u32 page = 0;
1378
1379 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1380 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1381 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1382 val = phy_read_paged(phydev, 0x260, 13);
1383 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1384 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1385 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1386 } else {
1387 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1388 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1389 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1390 }
1391 }
1392
1393 /* Force copper medium */
1394 for (int i = 0; i < 4; i++) {
1395 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1396 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1397 }
1398
1399 /* Enable PHY */
1400 for (int i = 0; i < 4; i++) {
1401 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1402 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1403 }
1404 mdelay(100);
1405
1406 /* Disable Autosensing */
1407 for (int i = 0; i < 4; i++) {
1408 int l;
1409
1410 for (l = 0; l < 100; l++) {
1411 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1412 if ((val & 0x7) >= 3)
1413 break;
1414 }
1415 if (l >= 100) {
1416 phydev_err(phydev, "Could not disable autosensing\n");
1417 return -1;
1418 }
1419 }
1420
1421 /* Request patch */
1422 for (int i = 0; i < 4; i++) {
1423 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1424 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1425 }
1426 mdelay(300);
1427
1428 /* Verify patch readiness */
1429 for (int i = 0; i < 4; i++) {
1430 int l;
1431
1432 for (l = 0; l < 100; l++) {
1433 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1434 if (val & 0x40)
1435 break;
1436 }
1437 if (l >= 100) {
1438 phydev_err(phydev, "Could not patch PHY\n");
1439 return -1;
1440 }
1441 }
1442 /* Use Broadcast ID method for patching */
1443 rtl821x_phy_setup_package_broadcast(phydev, true);
1444
1445 for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
1446 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1447 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1448 }
1449
1450 /* Disable broadcast ID */
1451 rtl821x_phy_setup_package_broadcast(phydev, false);
1452
1453 /* Auto medium selection */
1454 for (int i = 0; i < 4; i++) {
1455 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1456 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1457 }
1458
1459 return 0;
1460 }
1461
1462 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1463 {
1464 int addr = phydev->mdio.addr;
1465
1466 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1467 }
1468
1469 static int rtl8380_configure_serdes(struct phy_device *phydev)
1470 {
1471 u32 v;
1472 u32 sds_conf_value;
1473 int i;
1474 struct fw_header *h;
1475 u32 *rtl8380_sds_take_reset;
1476 u32 *rtl8380_sds_common;
1477 u32 *rtl8380_sds01_qsgmii_6275b;
1478 u32 *rtl8380_sds23_qsgmii_6275b;
1479 u32 *rtl8380_sds4_fiber_6275b;
1480 u32 *rtl8380_sds5_fiber_6275b;
1481 u32 *rtl8380_sds_reset;
1482 u32 *rtl8380_sds_release_reset;
1483
1484 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1485
1486 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1487 if (!h)
1488 return -1;
1489
1490 if (h->magic != 0x83808380) {
1491 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1492 return -1;
1493 }
1494
1495 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1496
1497 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1498
1499 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1500
1501 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1502
1503 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1504
1505 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1506
1507 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1508
1509 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1510
1511 /* Back up serdes power off value */
1512 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1513 pr_info("SDS power down value: %x\n", sds_conf_value);
1514
1515 /* take serdes into reset */
1516 i = 0;
1517 while (rtl8380_sds_take_reset[2 * i]) {
1518 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1519 i++;
1520 udelay(1000);
1521 }
1522
1523 /* apply common serdes patch */
1524 i = 0;
1525 while (rtl8380_sds_common[2 * i]) {
1526 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1527 i++;
1528 udelay(1000);
1529 }
1530
1531 /* internal R/W enable */
1532 sw_w32(3, RTL838X_INT_RW_CTRL);
1533
1534 /* SerDes ports 4 and 5 are FIBRE ports */
1535 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1536
1537 /* SerDes module settings, SerDes 0-3 are QSGMII */
1538 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1539 /* SerDes 4 and 5 are 1000BX FIBRE */
1540 v |= 0x4 << 5 | 0x4;
1541 sw_w32(v, RTL838X_SDS_MODE_SEL);
1542
1543 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1544 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1545 i = 0;
1546 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1547 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1548 rtl8380_sds01_qsgmii_6275b[2 * i]);
1549 i++;
1550 }
1551
1552 i = 0;
1553 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1554 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1555 i++;
1556 }
1557
1558 i = 0;
1559 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1560 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1561 i++;
1562 }
1563
1564 i = 0;
1565 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1566 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1567 i++;
1568 }
1569
1570 i = 0;
1571 while (rtl8380_sds_reset[2 * i]) {
1572 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1573 i++;
1574 }
1575
1576 i = 0;
1577 while (rtl8380_sds_release_reset[2 * i]) {
1578 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1579 i++;
1580 }
1581
1582 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1583 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1584
1585 pr_info("Configuration of SERDES done\n");
1586
1587 return 0;
1588 }
1589
1590 static int rtl8390_configure_serdes(struct phy_device *phydev)
1591 {
1592 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1593
1594 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1595 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1596
1597 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1598 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1599 * and FRE16_EEE_QUIET_FIB1G
1600 */
1601 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1602
1603 return 0;
1604 }
1605
1606 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1607 {
1608 int l = end_bit - start_bit + 1;
1609 u32 data = v;
1610
1611 if (l < 32) {
1612 u32 mask = BIT(l) - 1;
1613
1614 data = rtl930x_read_sds_phy(sds, page, reg);
1615 data &= ~(mask << start_bit);
1616 data |= (v & mask) << start_bit;
1617 }
1618
1619 rtl930x_write_sds_phy(sds, page, reg, data);
1620 }
1621
1622 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1623 {
1624 int l = end_bit - start_bit + 1;
1625 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1626
1627 if (l >= 32)
1628 return v;
1629
1630 return (v >> start_bit) & (BIT(l) - 1);
1631 }
1632
1633 /* Read the link and speed status of the internal SerDes of the RTL9300
1634 */
1635 static int rtl9300_read_status(struct phy_device *phydev)
1636 {
1637 struct device *dev = &phydev->mdio.dev;
1638 int phy_addr = phydev->mdio.addr;
1639 struct device_node *dn;
1640 u32 sds_num = 0, status, latch_status, mode;
1641
1642 if (dev->of_node) {
1643 dn = dev->of_node;
1644
1645 if (of_property_read_u32(dn, "sds", &sds_num))
1646 sds_num = -1;
1647 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1648 } else {
1649 dev_err(dev, "No DT node.\n");
1650 return -EINVAL;
1651 }
1652
1653 if (sds_num < 0)
1654 return 0;
1655
1656 mode = rtl9300_sds_mode_get(sds_num);
1657 pr_info("%s got SDS mode %02x\n", __func__, mode);
1658 if (mode == RTL930X_SDS_OFF)
1659 mode = rtl9300_sds_field_r(sds_num, 0x1f, 9, 11, 7);
1660 if (mode == RTL930X_SDS_MODE_10GBASER) { /* 10GR mode */
1661 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1662 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1663 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1664 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1665 } else {
1666 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1667 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1668 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1669 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1670 }
1671
1672 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1673
1674 if (latch_status) {
1675 phydev->link = true;
1676 if (mode == RTL930X_SDS_MODE_10GBASER) {
1677 phydev->speed = SPEED_10000;
1678 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
1679 } else {
1680 phydev->speed = SPEED_1000;
1681 phydev->interface = PHY_INTERFACE_MODE_1000BASEX;
1682 }
1683
1684 phydev->duplex = DUPLEX_FULL;
1685 }
1686
1687 return 0;
1688 }
1689
1690 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1691 {
1692 int page = 0x2e; /* 10GR and USXGMII */
1693
1694 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1695 page = 0x24;
1696
1697 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1698 mdelay(5);
1699 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1700 }
1701
1702 /* Force PHY modes on 10GBit Serdes
1703 */
1704 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1705 {
1706 int lc_value;
1707 int sds_mode;
1708 bool lc_on;
1709 int lane_0 = (sds % 2) ? sds - 1 : sds;
1710 u32 v;
1711
1712 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1713 switch (phy_if) {
1714 case PHY_INTERFACE_MODE_SGMII:
1715 sds_mode = RTL930X_SDS_MODE_SGMII;
1716 lc_on = false;
1717 lc_value = 0x1;
1718 break;
1719
1720 case PHY_INTERFACE_MODE_HSGMII:
1721 sds_mode = RTL930X_SDS_MODE_HSGMII;
1722 lc_value = 0x3;
1723 /* Configure LC */
1724 break;
1725
1726 case PHY_INTERFACE_MODE_1000BASEX:
1727 sds_mode = RTL930X_SDS_MODE_1000BASEX;
1728 lc_on = false;
1729 break;
1730
1731 case PHY_INTERFACE_MODE_2500BASEX:
1732 sds_mode = RTL930X_SDS_MODE_2500BASEX;
1733 lc_value = 0x3;
1734 /* Configure LC */
1735 break;
1736
1737 case PHY_INTERFACE_MODE_10GBASER:
1738 sds_mode = RTL930X_SDS_MODE_10GBASER;
1739 lc_on = true;
1740 lc_value = 0x5;
1741 break;
1742
1743 case PHY_INTERFACE_MODE_NA:
1744 /* This will disable SerDes */
1745 sds_mode = RTL930X_SDS_OFF;
1746 break;
1747
1748 default:
1749 pr_err("%s: unknown serdes mode: %s\n",
1750 __func__, phy_modes(phy_if));
1751 return;
1752 }
1753
1754 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1755 /* Power down SerDes */
1756 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1757 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1758
1759 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1760 /* Force mode enable */
1761 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1762 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1763
1764 /* SerDes off */
1765 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, RTL930X_SDS_OFF);
1766
1767 if (phy_if == PHY_INTERFACE_MODE_NA)
1768 return;
1769
1770 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1771 /* Enable LC and ring */
1772 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1773
1774 if (sds == lane_0)
1775 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1776 else
1777 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1778
1779 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1780
1781 if (lc_on)
1782 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1783 else
1784 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1785
1786 /* Force analog LC & ring on */
1787 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1788
1789 v = lc_on ? 0x3 : 0x1;
1790
1791 if (sds == lane_0)
1792 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1793 else
1794 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1795
1796 /* Force SerDes mode */
1797 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1798 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1799
1800 /* Toggle LC or Ring */
1801 for (int i = 0; i < 20; i++) {
1802 u32 cr_0, cr_1, cr_2;
1803 u32 m_bit, l_bit;
1804
1805 mdelay(200);
1806
1807 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1808
1809 m_bit = (lane_0 == sds) ? (4) : (5);
1810 l_bit = (lane_0 == sds) ? (4) : (5);
1811
1812 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1813 mdelay(10);
1814 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1815 mdelay(10);
1816 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1817
1818 if (cr_0 && cr_1 && cr_2) {
1819 u32 t;
1820
1821 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1822 break;
1823
1824 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1825 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1826
1827 /* Reset FSM */
1828 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1829 mdelay(10);
1830 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1831 mdelay(10);
1832
1833 /* Need to read this twice */
1834 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1835 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1836
1837 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1838
1839 /* Reset FSM again */
1840 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1841 mdelay(10);
1842 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1843 mdelay(10);
1844
1845 if (v == 1)
1846 break;
1847 }
1848
1849 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1850 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1851
1852 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1853 mdelay(10);
1854 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1855 }
1856
1857 rtl930x_sds_rx_rst(sds, phy_if);
1858
1859 /* Re-enable power */
1860 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1861
1862 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1863 }
1864
1865 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1866 {
1867 /* parameters: rtl9303_80G_txParam_s2 */
1868 int impedance = 0x8;
1869 int pre_amp = 0x2;
1870 int main_amp = 0x9;
1871 int post_amp = 0x2;
1872 int pre_en = 0x1;
1873 int post_en = 0x1;
1874 int page;
1875
1876 switch(phy_if) {
1877 case PHY_INTERFACE_MODE_1000BASEX:
1878 pre_amp = 0x1;
1879 main_amp = 0x9;
1880 post_amp = 0x1;
1881 page = 0x25;
1882 break;
1883 case PHY_INTERFACE_MODE_HSGMII:
1884 case PHY_INTERFACE_MODE_2500BASEX:
1885 pre_amp = 0;
1886 post_amp = 0x8;
1887 pre_en = 0;
1888 page = 0x29;
1889 break;
1890 case PHY_INTERFACE_MODE_10GBASER:
1891 case PHY_INTERFACE_MODE_USXGMII:
1892 case PHY_INTERFACE_MODE_XGMII:
1893 pre_en = 0;
1894 pre_amp = 0;
1895 main_amp = 0x10;
1896 post_amp = 0;
1897 post_en = 0;
1898 page = 0x2f;
1899 break;
1900 default:
1901 pr_err("%s: unsupported PHY mode\n", __func__);
1902 return;
1903 }
1904
1905 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1906 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1907 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1908 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1909 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1910 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1911 }
1912
1913 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1914 * timeout is in ms
1915 */
1916 int rtl9300_sds_clock_wait(int timeout)
1917 {
1918 u32 v;
1919 unsigned long start = jiffies;
1920
1921 do {
1922 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1923 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1924 if (v == 3)
1925 return 0;
1926 } while (jiffies < start + (HZ / 1000) * timeout);
1927
1928 return 1;
1929 }
1930
1931 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1932 {
1933 u32 v10, v1;
1934
1935 v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
1936 v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
1937 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1938
1939 v10 &= ~(BIT(13) | BIT(14));
1940 v1 &= ~(BIT(8) | BIT(9));
1941
1942 v10 |= rx_normal ? 0 : BIT(13);
1943 v1 |= rx_normal ? 0 : BIT(9);
1944
1945 v10 |= tx_normal ? 0 : BIT(14);
1946 v1 |= tx_normal ? 0 : BIT(8);
1947
1948 rtl930x_write_sds_phy(sds, 6, 2, v10);
1949 rtl930x_write_sds_phy(sds, 0, 0, v1);
1950
1951 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1952 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1953 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1954 }
1955
1956 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1957 {
1958 if (manual) {
1959 switch(dcvs_id) {
1960 case 0:
1961 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1962 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1963 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1964 break;
1965 case 1:
1966 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1967 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1968 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1969 break;
1970 case 2:
1971 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1972 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1973 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1974 break;
1975 case 3:
1976 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1977 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1978 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1979 break;
1980 case 4:
1981 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1982 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1983 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1984 break;
1985 case 5:
1986 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1987 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1988 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1989 break;
1990 default:
1991 break;
1992 }
1993 } else {
1994 switch(dcvs_id) {
1995 case 0:
1996 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1997 break;
1998 case 1:
1999 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
2000 break;
2001 case 2:
2002 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
2003 break;
2004 case 3:
2005 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
2006 break;
2007 case 4:
2008 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
2009 break;
2010 case 5:
2011 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
2012 break;
2013 default:
2014 break;
2015 }
2016 mdelay(1);
2017 }
2018 }
2019
2020 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
2021 {
2022 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
2023 bool dcvs_manual;
2024
2025 if (!(sds_num % 2))
2026 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2027 else
2028 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2029
2030 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2031 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2032
2033 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2034 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2035
2036 switch(dcvs_id) {
2037 case 0:
2038 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2039 mdelay(1);
2040
2041 /* ##DCVS0 Read Out */
2042 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2043 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2044 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2045 break;
2046
2047 case 1:
2048 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2049 mdelay(1);
2050
2051 /* ##DCVS0 Read Out */
2052 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2053 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2054 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2055 break;
2056
2057 case 2:
2058 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2059 mdelay(1);
2060
2061 /* ##DCVS0 Read Out */
2062 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2063 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2064 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2065 break;
2066 case 3:
2067 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2068 mdelay(1);
2069
2070 /* ##DCVS0 Read Out */
2071 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2072 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2073 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2074 break;
2075
2076 case 4:
2077 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2078 mdelay(1);
2079
2080 /* ##DCVS0 Read Out */
2081 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2082 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2083 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2084 break;
2085
2086 case 5:
2087 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2088 mdelay(1);
2089
2090 /* ##DCVS0 Read Out */
2091 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2092 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2093 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2094 break;
2095
2096 default:
2097 break;
2098 }
2099
2100 if (dcvs_sign_out)
2101 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2102 else
2103 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2104
2105 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2106 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2107
2108 dcvs_list[0] = dcvs_sign_out;
2109 dcvs_list[1] = dcvs_coef_bin;
2110 }
2111
2112 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2113 {
2114 if (manual) {
2115 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2116 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2117 } else {
2118 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2119 mdelay(100);
2120 }
2121 }
2122
2123 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2124 {
2125 if (manual) {
2126 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2127 } else {
2128 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2129 mdelay(1);
2130 }
2131 }
2132
2133 #define GRAY_BITS 5
2134 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2135 {
2136 int i, j, m;
2137 u32 g[GRAY_BITS];
2138 u32 c[GRAY_BITS];
2139 u32 leq_binary = 0;
2140
2141 for(i = 0; i < GRAY_BITS; i++)
2142 g[i] = (gray_code & BIT(i)) >> i;
2143
2144 m = GRAY_BITS - 1;
2145
2146 c[m] = g[m];
2147
2148 for(i = 0; i < m; i++) {
2149 c[i] = g[i];
2150 for(j = i + 1; j < GRAY_BITS; j++)
2151 c[i] = c[i] ^ g[j];
2152 }
2153
2154 for(i = 0; i < GRAY_BITS; i++)
2155 leq_binary += c[i] << i;
2156
2157 return leq_binary;
2158 }
2159
2160 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2161 {
2162 u32 leq_gray, leq_bin;
2163 bool leq_manual;
2164
2165 if (!(sds_num % 2))
2166 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2167 else
2168 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2169
2170 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2171 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2172
2173 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2174 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2175 mdelay(1);
2176
2177 /* ##LEQ Read Out */
2178 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2179 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2180 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2181
2182 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2183 pr_info("LEQ manual: %u", leq_manual);
2184
2185 return leq_bin;
2186 }
2187
2188 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2189 {
2190 if (manual) {
2191 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2192 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2193 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2194 } else {
2195 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2196 mdelay(10);
2197 }
2198 }
2199
2200 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2201 {
2202 u32 vth_manual;
2203
2204 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2205 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2206 if (!(sds_num % 2))
2207 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2208 else
2209 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2210
2211 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2212 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2213 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2214 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2215 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2216 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2217
2218 mdelay(1);
2219
2220 /* ##VthP & VthN Read Out */
2221 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2222 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2223
2224 pr_info("vth_set_bin = %d", vth_list[0]);
2225 pr_info("vth_set_bin = %d", vth_list[1]);
2226
2227 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2228 pr_info("Vth Maunal = %d", vth_manual);
2229 }
2230
2231 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2232 {
2233 if (manual) {
2234 switch(tap_id) {
2235 case 0:
2236 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2237 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2238 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2239 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2240 break;
2241 case 1:
2242 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2243 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2244 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2245 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2246 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2247 break;
2248 case 2:
2249 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2250 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2251 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2252 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2253 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2254 break;
2255 case 3:
2256 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2257 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2258 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2259 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2260 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2261 break;
2262 case 4:
2263 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2264 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2265 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2266 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2267 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2268 break;
2269 default:
2270 break;
2271 }
2272 } else {
2273 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2274 mdelay(10);
2275 }
2276 }
2277
2278 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2279 {
2280 u32 tap0_sign_out;
2281 u32 tap0_coef_bin;
2282 u32 tap_sign_out_even;
2283 u32 tap_coef_bin_even;
2284 u32 tap_sign_out_odd;
2285 u32 tap_coef_bin_odd;
2286 bool tap_manual;
2287
2288 if (!(sds_num % 2))
2289 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2290 else
2291 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2292
2293 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2294 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2295 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2296 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2297
2298 if (!tap_id) {
2299 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2300 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2301 /* ##Tap1 Even Read Out */
2302 mdelay(1);
2303 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2304 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2305
2306 if (tap0_sign_out == 1)
2307 pr_info("Tap0 Sign : -");
2308 else
2309 pr_info("Tap0 Sign : +");
2310
2311 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2312
2313 tap_list[0] = tap0_sign_out;
2314 tap_list[1] = tap0_coef_bin;
2315
2316 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2317 pr_info("tap0 manual = %u",tap_manual);
2318 } else {
2319 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2320 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2321 mdelay(1);
2322 /* ##Tap1 Even Read Out */
2323 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2324 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2325
2326 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2327 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2328 /* ##Tap1 Odd Read Out */
2329 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2330 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2331
2332 if (tap_sign_out_even == 1)
2333 pr_info("Tap %u even sign: -", tap_id);
2334 else
2335 pr_info("Tap %u even sign: +", tap_id);
2336
2337 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2338
2339 if (tap_sign_out_odd == 1)
2340 pr_info("Tap %u odd sign: -", tap_id);
2341 else
2342 pr_info("Tap %u odd sign: +", tap_id);
2343
2344 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2345
2346 tap_list[0] = tap_sign_out_even;
2347 tap_list[1] = tap_coef_bin_even;
2348 tap_list[2] = tap_sign_out_odd;
2349 tap_list[3] = tap_coef_bin_odd;
2350
2351 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2352 pr_info("tap %u manual = %d",tap_id, tap_manual);
2353 }
2354 }
2355
2356 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2357 {
2358 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2359 int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2360 int vth_min = 0x0;
2361
2362 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2363 rtl930x_write_sds_phy(sds, 6, 0, 0);
2364
2365 /* FGCAL */
2366 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2368 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2369
2370 /* DCVS */
2371 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2372 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2373 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2374 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2375 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2376 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2377 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2378 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2379 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2380 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2381 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2382 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2383
2384 /* LEQ (Long Term Equivalent signal level) */
2385 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2386
2387 /* DFE (Decision Fed Equalizer) */
2388 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2389 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2390 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2391 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2392 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2393 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2394 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2395 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2396 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2397
2398 /* Vth */
2399 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2400 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2401 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2402
2403 pr_info("end_1.1.1 --\n");
2404
2405 pr_info("start_1.1.2 Load DFE init. value\n");
2406
2407 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2408
2409 pr_info("end_1.1.2\n");
2410
2411 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2412
2413 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2414 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2415 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2416 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2417 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2418 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2419
2420 pr_info("end_1.1.3 --\n");
2421
2422 pr_info("start_1.1.4 offset cali setting\n");
2423
2424 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2425
2426 pr_info("end_1.1.4\n");
2427
2428 pr_info("start_1.1.5 LEQ and DFE setting\n");
2429
2430 /* TODO: make this work for DAC cables of different lengths */
2431 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2432 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2433 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2434 else
2435 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2436
2437 /* No serdes, check for Aquantia PHYs */
2438 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2439
2440 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2441 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2442 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2443 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2444 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2445
2446 pr_info("end_1.1.5\n");
2447 }
2448
2449 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2450 {
2451 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2452
2453 /* Gray config endis to 1 */
2454 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2455
2456 /* ForegroundOffsetCal_Manual(auto mode) */
2457 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2458
2459 pr_info("end_1.2.1");
2460 }
2461
2462 void rtl9300_do_rx_calibration_2_2(int sds_num)
2463 {
2464 /* Force Rx-Run = 0 */
2465 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2466
2467 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2468 }
2469
2470 void rtl9300_do_rx_calibration_2_3(int sds_num)
2471 {
2472 u32 fgcal_binary, fgcal_gray;
2473 u32 offset_range;
2474
2475 pr_info("start_1.2.3 Foreground Calibration\n");
2476
2477 while(1) {
2478 if (!(sds_num % 2))
2479 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2480 else
2481 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2482
2483 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2484 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2485 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2486 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2487 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2488 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2489 /* ##FGCAL read gray */
2490 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2491 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2492 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2493 /* ##FGCAL read binary */
2494 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2495
2496 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2497 __func__, fgcal_gray, fgcal_binary);
2498
2499 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2500
2501 if (fgcal_binary > 60 || fgcal_binary < 3) {
2502 if (offset_range == 3) {
2503 pr_info("%s: Foreground Calibration result marginal!", __func__);
2504 break;
2505 } else {
2506 offset_range++;
2507 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2508 rtl9300_do_rx_calibration_2_2(sds_num);
2509 }
2510 } else {
2511 break;
2512 }
2513 }
2514 pr_info("%s: end_1.2.3\n", __func__);
2515 }
2516
2517 void rtl9300_do_rx_calibration_2(int sds)
2518 {
2519 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2520 rtl9300_do_rx_calibration_2_1(sds);
2521 rtl9300_do_rx_calibration_2_2(sds);
2522 rtl9300_do_rx_calibration_2_3(sds);
2523 }
2524
2525 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2526 {
2527 pr_info("start_1.3.1");
2528
2529 /* ##1.3.1 */
2530 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2531 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2532
2533 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2534 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2535
2536 pr_info("end_1.3.1");
2537 }
2538
2539 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2540 {
2541 u32 sum10 = 0, avg10, int10;
2542 int dac_long_cable_offset;
2543 bool eq_hold_enabled;
2544 int i;
2545
2546 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2547 /* rtl9300_rxCaliConf_serdes_myParam */
2548 dac_long_cable_offset = 3;
2549 eq_hold_enabled = true;
2550 } else {
2551 /* rtl9300_rxCaliConf_phy_myParam */
2552 dac_long_cable_offset = 0;
2553 eq_hold_enabled = false;
2554 }
2555
2556 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2557 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2558
2559 pr_info("start_1.3.2");
2560
2561 for(i = 0; i < 10; i++) {
2562 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2563 mdelay(10);
2564 }
2565
2566 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2567 int10 = sum10 / 10;
2568
2569 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2570
2571 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2572 if (dac_long_cable_offset) {
2573 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2574 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2575 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2576 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2577 } else {
2578 if (sum10 >= 5) {
2579 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2580 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2581 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2582 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2583 } else {
2584 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2585 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2586 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2587 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2588 }
2589 }
2590 }
2591
2592 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2593
2594 pr_info("end_1.3.2");
2595 }
2596
2597 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2598 {
2599 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2600
2601 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2602 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2603 }
2604
2605 void rtl9300_do_rx_calibration_4_1(int sds_num)
2606 {
2607 u32 vth_list[2] = {0, 0};
2608 u32 tap0_list[4] = {0, 0, 0, 0};
2609
2610 pr_info("start_1.4.1");
2611
2612 /* ##1.4.1 */
2613 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2614 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2615 mdelay(200);
2616
2617 pr_info("end_1.4.1");
2618 }
2619
2620 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2621 {
2622 u32 vth_list[2];
2623 u32 tap_list[4];
2624
2625 pr_info("start_1.4.2");
2626
2627 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2628 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2629
2630 mdelay(100);
2631
2632 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2633 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2634
2635 pr_info("end_1.4.2");
2636 }
2637
2638 void rtl9300_do_rx_calibration_4(u32 sds_num)
2639 {
2640 rtl9300_do_rx_calibration_4_1(sds_num);
2641 rtl9300_do_rx_calibration_4_2(sds_num);
2642 }
2643
2644 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2645 {
2646 u32 tap1_list[4] = {0};
2647 u32 tap2_list[4] = {0};
2648 u32 tap3_list[4] = {0};
2649 u32 tap4_list[4] = {0};
2650
2651 pr_info("start_1.5.2");
2652
2653 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2654 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2655 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2656 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2657
2658 mdelay(30);
2659
2660 pr_info("end_1.5.2");
2661 }
2662
2663 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2664 {
2665 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */
2666 rtl9300_do_rx_calibration_5_2(sds_num);
2667 }
2668
2669
2670 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2671 {
2672 u32 tap1_list[4] = {0};
2673 u32 tap2_list[4] = {0};
2674 u32 tap3_list[4] = {0};
2675 u32 tap4_list[4] = {0};
2676
2677 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2678 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2679 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2680 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2681
2682 mdelay(10);
2683 }
2684
2685 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2686 {
2687 u32 latch_sts;
2688
2689 rtl9300_do_rx_calibration_1(sds, phy_mode);
2690 rtl9300_do_rx_calibration_2(sds);
2691 rtl9300_do_rx_calibration_4(sds);
2692 rtl9300_do_rx_calibration_5(sds, phy_mode);
2693 mdelay(20);
2694
2695 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2696 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == RTL930X_SDS_MODE_10GBASER) {
2697 pr_info("%s: SDS enabled\n", __func__);
2698 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2699 mdelay(1);
2700 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2701 if (latch_sts) {
2702 rtl9300_do_rx_calibration_dfe_disable(sds);
2703 rtl9300_do_rx_calibration_4(sds);
2704 rtl9300_do_rx_calibration_5(sds, phy_mode);
2705 }
2706 }
2707 }
2708
2709 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2710 {
2711 switch (phy_mode) {
2712 case PHY_INTERFACE_MODE_XGMII:
2713 break;
2714
2715 case PHY_INTERFACE_MODE_10GBASER:
2716 /* Read twice to clear */
2717 rtl930x_read_sds_phy(sds_num, 5, 1);
2718 rtl930x_read_sds_phy(sds_num, 5, 1);
2719 break;
2720
2721 case PHY_INTERFACE_MODE_1000BASEX:
2722 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2723 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2724 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2725 break;
2726
2727 default:
2728 pr_info("%s unsupported phy mode\n", __func__);
2729 return -1;
2730 }
2731
2732 return 0;
2733 }
2734
2735 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2736 {
2737 u32 v = 0;
2738
2739 switch (phy_mode) {
2740 case PHY_INTERFACE_MODE_XGMII:
2741 break;
2742
2743 case PHY_INTERFACE_MODE_1000BASEX:
2744 case PHY_INTERFACE_MODE_10GBASER:
2745 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2746 return v & 0xff;
2747
2748 default:
2749 pr_info("%s unsupported PHY-mode\n", __func__);
2750 }
2751
2752 return v;
2753 }
2754
2755 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2756 {
2757 u32 errors1, errors2;
2758
2759 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2760 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2761
2762 /* Count errors during 1ms */
2763 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2764 mdelay(1);
2765 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2766
2767 switch (phy_mode) {
2768 case PHY_INTERFACE_MODE_1000BASEX:
2769 case PHY_INTERFACE_MODE_XGMII:
2770 if ((errors2 - errors1 > 100) ||
2771 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2772 pr_info("%s XSGMII error rate too high\n", __func__);
2773 return 1;
2774 }
2775 break;
2776 case PHY_INTERFACE_MODE_10GBASER:
2777 if (errors2 > 0) {
2778 pr_info("%s 10GBASER error rate too high\n", __func__);
2779 return 1;
2780 }
2781 break;
2782 default:
2783 return 1;
2784 }
2785
2786 return 0;
2787 }
2788
2789 void rtl9300_phy_enable_10g_1g(int sds_num)
2790 {
2791 u32 v;
2792
2793 /* Enable 1GBit PHY */
2794 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
2795 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2796 v &= ~BMCR_PDOWN;
2797 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
2798 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2799
2800 /* Enable 10GBit PHY */
2801 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
2802 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2803 v &= ~BMCR_PDOWN;
2804 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
2805 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2806
2807 /* dal_longan_construct_mac_default_10gmedia_fiber */
2808 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2809 pr_info("%s set medium: %08x\n", __func__, v);
2810 v |= BIT(1);
2811 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2812 pr_info("%s set medium after: %08x\n", __func__, v);
2813 }
2814
2815 static int rtl9300_sds_10g_idle(int sds_num);
2816 static void rtl9300_serdes_patch(int sds_num);
2817
2818 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2819 int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode)
2820 {
2821 int calib_tries = 0;
2822
2823 /* Turn Off Serdes */
2824 rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
2825
2826 /* Apply serdes patches */
2827 rtl9300_serdes_patch(sds_num);
2828
2829 /* Maybe use dal_longan_sds_init */
2830
2831 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2832 rtl9300_phy_enable_10g_1g(sds_num);
2833
2834 /* Disable MAC */
2835 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
2836 mdelay(20);
2837
2838 /* ----> dal_longan_sds_mode_set */
2839 pr_info("%s: Configuring RTL9300 SERDES %d\n", __func__, sds_num);
2840
2841 /* Configure link to MAC */
2842 rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
2843
2844 /* Re-Enable MAC */
2845 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
2846
2847 /* Enable SDS in desired mode */
2848 rtl9300_force_sds_mode(sds_num, phy_mode);
2849
2850 /* Enable Fiber RX */
2851 rtl9300_sds_field_w(sds_num, 0x20, 2, 12, 12, 0);
2852
2853 /* Calibrate SerDes receiver in loopback mode */
2854 rtl9300_sds_10g_idle(sds_num);
2855 do {
2856 rtl9300_do_rx_calibration(sds_num, phy_mode);
2857 calib_tries++;
2858 mdelay(50);
2859 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2860 if (calib_tries >= 3)
2861 pr_warn("%s: SerDes RX calibration failed\n", __func__);
2862
2863 /* Leave loopback mode */
2864 rtl9300_sds_tx_config(sds_num, phy_mode);
2865
2866 return 0;
2867 }
2868
2869 static int rtl9300_sds_10g_idle(int sds_num)
2870 {
2871 bool busy;
2872 int i = 0;
2873
2874 do {
2875 if (sds_num % 2) {
2876 rtl9300_sds_field_w(sds_num - 1, 0x1f, 0x2, 15, 0, 53);
2877 busy = !!rtl9300_sds_field_r(sds_num - 1, 0x1f, 0x14, 1, 1);
2878 } else {
2879 rtl9300_sds_field_w(sds_num, 0x1f, 0x2, 15, 0, 53);
2880 busy = !!rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 0, 0);
2881 }
2882 i++;
2883 } while (busy && i < 100);
2884
2885 if (i < 100)
2886 return 0;
2887
2888 pr_warn("%s WARNING: Waiting for RX idle timed out, SDS %d\n", __func__, sds_num);
2889 return -EIO;
2890 }
2891
2892 typedef struct {
2893 u8 page;
2894 u8 reg;
2895 u16 data;
2896 } sds_config;
2897
2898 sds_config rtl9300_a_sds_10gr_lane0[] =
2899 {
2900 /* 1G */
2901 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2902 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2903 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2904 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2905 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2906 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2907 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2908 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2909 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2910 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2911 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2912 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2913 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2914 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2915 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2916 {0x2F, 0x1D, 0x66E1},
2917 /* 3.125G */
2918 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2919 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2920 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2921 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2922 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2923 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2924 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2925 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2926 /* 10G */
2927 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2928 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2929 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2930 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2931 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2932 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2933 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2934 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2935 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2936 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2937 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2938 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2939 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2940 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2941 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2942 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2943 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2944 };
2945
2946 sds_config rtl9300_a_sds_10gr_lane1[] =
2947 {
2948 /* 1G */
2949 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2950 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2951 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2952 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2953 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2954 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2955 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2956 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2957 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2958 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2959 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2960 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2961 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2962 {0x2D, 0x14, 0x1808},
2963 /* 3.125G */
2964 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2965 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2966 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2967 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2968 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2969 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2970 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2971 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2972 /* 10G */
2973 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2974 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2975 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2976 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2977 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2978 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2979 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2980 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2981 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2982 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2983 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2984 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2985 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2986 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2987 };
2988
2989 static void rtl9300_serdes_patch(int sds_num)
2990 {
2991 if (sds_num % 2) {
2992 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2993 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2994 rtl9300_a_sds_10gr_lane1[i].reg,
2995 rtl9300_a_sds_10gr_lane1[i].data);
2996 }
2997 } else {
2998 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
2999 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3000 rtl9300_a_sds_10gr_lane0[i].reg,
3001 rtl9300_a_sds_10gr_lane0[i].data);
3002 }
3003 }
3004 }
3005
3006 int rtl9300_sds_cmu_band_get(int sds)
3007 {
3008 u32 page;
3009 u32 en;
3010 u32 cmu_band;
3011
3012 /* page = rtl9300_sds_cmu_page_get(sds); */
3013 page = 0x25; /* 10GR and 1000BX */
3014 sds = (sds % 2) ? (sds - 1) : (sds);
3015
3016 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
3017 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
3018
3019 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
3020 if(!en) { /* Auto mode */
3021 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
3022
3023 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
3024 } else {
3025 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
3026 }
3027
3028 return cmu_band;
3029 }
3030
3031 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3032 {
3033 int l = end_bit - start_bit + 1;
3034 u32 data = v;
3035
3036 if (l < 32) {
3037 u32 mask = BIT(l) - 1;
3038
3039 data = rtl930x_read_sds_phy(sds, page, reg);
3040 data &= ~(mask << start_bit);
3041 data |= (v & mask) << start_bit;
3042 }
3043
3044 rtl931x_write_sds_phy(sds, page, reg, data);
3045 }
3046
3047 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3048 {
3049 int l = end_bit - start_bit + 1;
3050 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3051
3052 if (l >= 32)
3053 return v;
3054
3055 return (v >> start_bit) & (BIT(l) - 1);
3056 }
3057
3058 static void rtl931x_sds_rst(u32 sds)
3059 {
3060 u32 o, v, o_mode;
3061 int shift = ((sds & 0x3) << 3);
3062
3063 /* TODO: We need to lock this! */
3064
3065 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3066 v = o | BIT(sds);
3067 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3068
3069 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3070 v = BIT(7) | 0x1F;
3071 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3072 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3073
3074 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3075 }
3076
3077 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3078 {
3079
3080 switch (mode) {
3081 case PHY_INTERFACE_MODE_NA:
3082 break;
3083 case PHY_INTERFACE_MODE_XGMII:
3084 u32 xsg_sdsid_0, xsg_sdsid_1;
3085
3086 if (sds < 2)
3087 xsg_sdsid_0 = sds;
3088 else
3089 xsg_sdsid_0 = (sds - 1) * 2;
3090 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3091
3092 for (int i = 0; i < 4; ++i) {
3093 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3094 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3095 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3096 }
3097
3098 for (int i = 0; i < 4; ++i) {
3099 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3100 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3101 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3102 }
3103
3104 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3105 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3106 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3107 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3108 break;
3109 default:
3110 break;
3111 }
3112
3113 return;
3114 }
3115
3116 static u32 rtl931x_get_analog_sds(u32 sds)
3117 {
3118 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3119
3120 if (sds < 14)
3121 return sds_map[sds];
3122
3123 return sds;
3124 }
3125
3126 void rtl931x_sds_fiber_disable(u32 sds)
3127 {
3128 u32 v = 0x3F;
3129 u32 asds = rtl931x_get_analog_sds(sds);
3130
3131 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3132 }
3133
3134 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3135 {
3136 u32 val, asds = rtl931x_get_analog_sds(sds);
3137
3138 /* clear symbol error count before changing mode */
3139 rtl931x_symerr_clear(sds, mode);
3140
3141 val = 0x9F;
3142 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3143
3144 switch (mode) {
3145 case PHY_INTERFACE_MODE_SGMII:
3146 val = 0x5;
3147 break;
3148
3149 case PHY_INTERFACE_MODE_1000BASEX:
3150 /* serdes mode FIBER1G */
3151 val = 0x9;
3152 break;
3153
3154 case PHY_INTERFACE_MODE_10GBASER:
3155 case PHY_INTERFACE_MODE_10GKR:
3156 val = 0x35;
3157 break;
3158 /* case MII_10GR1000BX_AUTO:
3159 val = 0x39;
3160 break; */
3161
3162
3163 case PHY_INTERFACE_MODE_USXGMII:
3164 val = 0x1B;
3165 break;
3166 default:
3167 val = 0x25;
3168 }
3169
3170 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3171 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3172
3173 return;
3174 }
3175
3176 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3177 {
3178 switch (mode) {
3179 case PHY_INTERFACE_MODE_SGMII:
3180 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3181 return 0x24;
3182 case PHY_INTERFACE_MODE_HSGMII:
3183 case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */
3184 return 0x28;
3185 /* case MII_HISGMII_5G: */
3186 /* return 0x2a; */
3187 case PHY_INTERFACE_MODE_QSGMII:
3188 return 0x2a; /* Code also has 0x34 */
3189 case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */
3190 return 0x2c;
3191 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3192 case PHY_INTERFACE_MODE_10GKR:
3193 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */
3194 return 0x2e;
3195 default:
3196 return -1;
3197 }
3198
3199 return -1;
3200 }
3201
3202 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3203 {
3204 int cmu_type = 0; /* Clock Management Unit */
3205 u32 cmu_page = 0;
3206 u32 frc_cmu_spd;
3207 u32 evenSds;
3208 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3209
3210 switch (mode) {
3211 case PHY_INTERFACE_MODE_NA:
3212 case PHY_INTERFACE_MODE_10GKR:
3213 case PHY_INTERFACE_MODE_XGMII:
3214 case PHY_INTERFACE_MODE_10GBASER:
3215 case PHY_INTERFACE_MODE_USXGMII:
3216 return;
3217
3218 /* case MII_10GR1000BX_AUTO:
3219 if (chiptype)
3220 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3221 return; */
3222
3223 case PHY_INTERFACE_MODE_QSGMII:
3224 cmu_type = 1;
3225 frc_cmu_spd = 0;
3226 break;
3227
3228 case PHY_INTERFACE_MODE_HSGMII:
3229 cmu_type = 1;
3230 frc_cmu_spd = 1;
3231 break;
3232
3233 case PHY_INTERFACE_MODE_1000BASEX:
3234 cmu_type = 1;
3235 frc_cmu_spd = 0;
3236 break;
3237
3238 /* case MII_1000BX100BX_AUTO:
3239 cmu_type = 1;
3240 frc_cmu_spd = 0;
3241 break; */
3242
3243 case PHY_INTERFACE_MODE_SGMII:
3244 cmu_type = 1;
3245 frc_cmu_spd = 0;
3246 break;
3247
3248 case PHY_INTERFACE_MODE_2500BASEX:
3249 cmu_type = 1;
3250 frc_cmu_spd = 1;
3251 break;
3252
3253 default:
3254 pr_info("SerDes %d mode is invalid\n", asds);
3255 return;
3256 }
3257
3258 if (cmu_type == 1)
3259 cmu_page = rtl931x_sds_cmu_page_get(mode);
3260
3261 lane = asds % 2;
3262
3263 if (!lane) {
3264 frc_lc_mode_bitnum = 4;
3265 frc_lc_mode_val_bitnum = 5;
3266 } else {
3267 frc_lc_mode_bitnum = 6;
3268 frc_lc_mode_val_bitnum = 7;
3269 }
3270
3271 evenSds = asds - lane;
3272
3273 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3274 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3275
3276 if (cmu_type == 1) {
3277 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3278 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3279 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3280 if (chiptype) {
3281 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3282 }
3283
3284 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3285 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3286 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3287 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3288 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3289 }
3290
3291 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3292 return;
3293 }
3294
3295 static void rtl931x_sds_rx_rst(u32 sds)
3296 {
3297 u32 asds = rtl931x_get_analog_sds(sds);
3298
3299 if (sds < 2)
3300 return;
3301
3302 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3303 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3304 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3305 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3306
3307 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3308 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3309 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3310 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3311
3312 mdelay(50);
3313 }
3314
3315 // Currently not used
3316 // static void rtl931x_sds_disable(u32 sds)
3317 // {
3318 // u32 v = 0x1f;
3319
3320 // v |= BIT(7);
3321 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3322 // }
3323
3324 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3325 {
3326 u32 val;
3327
3328 switch (mode) {
3329 case PHY_INTERFACE_MODE_QSGMII:
3330 val = 0x6;
3331 break;
3332 case PHY_INTERFACE_MODE_XGMII:
3333 val = 0x10; /* serdes mode XSGMII */
3334 break;
3335 case PHY_INTERFACE_MODE_USXGMII:
3336 case PHY_INTERFACE_MODE_2500BASEX:
3337 val = 0xD;
3338 break;
3339 case PHY_INTERFACE_MODE_HSGMII:
3340 val = 0x12;
3341 break;
3342 case PHY_INTERFACE_MODE_SGMII:
3343 val = 0x2;
3344 break;
3345 default:
3346 return;
3347 }
3348
3349 val |= (1 << 7);
3350
3351 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3352 }
3353
3354 static sds_config sds_config_10p3125g_type1[] = {
3355 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3356 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3357 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3358 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3359 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3360 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3361 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3362 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3363 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3364 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3365 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3366 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3367 { 0x2F, 0x13, 0x0000 }
3368 };
3369
3370 static sds_config sds_config_10p3125g_cmu_type1[] = {
3371 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3372 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3373 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3374 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3375 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3376 };
3377
3378 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3379 {
3380 u32 board_sds_tx_type1[] = {
3381 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3382 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3383 };
3384 u32 board_sds_tx[] = {
3385 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3386 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3387 };
3388 u32 board_sds_tx2[] = {
3389 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3390 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3391 };
3392 u32 asds, dSds, ori, model_info, val;
3393 int chiptype = 0;
3394
3395 asds = rtl931x_get_analog_sds(sds);
3396
3397 if (sds > 13)
3398 return;
3399
3400 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3401 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3402
3403 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3404 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3405 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3406 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3407 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3408 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3409 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3410 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3411 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3412 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3413 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3414 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3415
3416 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3417 if ((model_info >> 4) & 0x1) {
3418 pr_info("detected chiptype 1\n");
3419 chiptype = 1;
3420 } else {
3421 pr_info("detected chiptype 0\n");
3422 }
3423
3424 if (sds < 2)
3425 dSds = sds;
3426 else
3427 dSds = (sds - 1) * 2;
3428
3429 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3430 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3431
3432 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3433 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3434 val = ori | (1 << sds);
3435 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3436
3437 switch (mode) {
3438 case PHY_INTERFACE_MODE_NA:
3439 break;
3440
3441 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3442
3443 if (chiptype) {
3444 u32 xsg_sdsid_1;
3445 xsg_sdsid_1 = dSds + 1;
3446 /* fifo inv clk */
3447 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3448 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3449
3450 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3451 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3452
3453 }
3454
3455 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3456 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3457 break;
3458
3459 case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3460 u32 op_code = 0x6003;
3461 u32 evenSds;
3462
3463 if (chiptype) {
3464 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3465
3466 for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3467 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3468 }
3469
3470 evenSds = asds - (asds % 2);
3471
3472 for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3473 rtl931x_write_sds_phy(evenSds,
3474 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3475 }
3476
3477 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3478 } else {
3479
3480 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3481 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3482
3483 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3484 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3485 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3486 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3487 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3488
3489 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3490 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3491
3492 rtl931x_sds_rx_rst(sds);
3493
3494 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3495 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3496 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3497 }
3498 break;
3499
3500 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
3501 /* configure 10GR fiber mode=1 */
3502 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3503
3504 /* init fiber_1g */
3505 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3506
3507 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3508 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3509 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3510
3511 /* init auto */
3512 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3513 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3514 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3515 break;
3516
3517 case PHY_INTERFACE_MODE_HSGMII:
3518 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3519 break;
3520
3521 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */
3522 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3523
3524 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3525 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3526 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3527 break;
3528
3529 case PHY_INTERFACE_MODE_SGMII:
3530 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3531 break;
3532
3533 case PHY_INTERFACE_MODE_2500BASEX:
3534 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3535 break;
3536
3537 case PHY_INTERFACE_MODE_QSGMII:
3538 default:
3539 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3540 __func__, phy_modes(mode), sds);
3541 return;
3542 }
3543
3544 rtl931x_cmu_type_set(asds, mode, chiptype);
3545
3546 if (sds >= 2 && sds <= 13) {
3547 if (chiptype)
3548 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3549 else {
3550 val = 0xa0000;
3551 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3552 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3553 if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3554 {
3555 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3556 } else {
3557 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3558 }
3559 val = 0;
3560 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3561 }
3562 }
3563
3564 val = ori & ~BIT(sds);
3565 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3566 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3567
3568 if (mode == PHY_INTERFACE_MODE_XGMII ||
3569 mode == PHY_INTERFACE_MODE_QSGMII ||
3570 mode == PHY_INTERFACE_MODE_HSGMII ||
3571 mode == PHY_INTERFACE_MODE_SGMII ||
3572 mode == PHY_INTERFACE_MODE_USXGMII) {
3573 if (mode == PHY_INTERFACE_MODE_XGMII)
3574 rtl931x_sds_mii_mode_set(sds, mode);
3575 else
3576 rtl931x_sds_fiber_mode_set(sds, mode);
3577 }
3578 }
3579
3580 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3581 {
3582 u32 asds;
3583 int page = rtl931x_sds_cmu_page_get(mode);
3584
3585 sds -= (sds % 2);
3586 sds = sds & ~1;
3587 asds = rtl931x_get_analog_sds(sds);
3588 page += 1;
3589
3590 if (enable) {
3591 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3592 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3593 } else {
3594 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3595 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3596 }
3597
3598 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3599
3600 rtl931x_sds_rst(sds);
3601
3602 return 0;
3603 }
3604
3605 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3606 {
3607 int page = rtl931x_sds_cmu_page_get(mode);
3608 u32 asds, band;
3609
3610 sds -= (sds % 2);
3611 asds = rtl931x_get_analog_sds(sds);
3612 page += 1;
3613 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3614
3615 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3616 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3617 pr_info("%s band is: %d\n", __func__, band);
3618
3619 return band;
3620 }
3621
3622
3623 int rtl931x_link_sts_get(u32 sds)
3624 {
3625 u32 sts, sts1, latch_sts, latch_sts1;
3626 if (0){
3627 u32 xsg_sdsid_0, xsg_sdsid_1;
3628
3629 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3630 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3631
3632 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3633 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3634 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3635 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3636 } else {
3637 u32 asds, dsds;
3638
3639 asds = rtl931x_get_analog_sds(sds);
3640 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3641 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3642
3643 dsds = sds < 2 ? sds : (sds - 1) * 2;
3644 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3645 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3646 }
3647
3648 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3649 sds, sts, sts1, latch_sts, latch_sts1);
3650
3651 return sts1;
3652 }
3653
3654 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3655 {
3656 struct phy_device *phydev = upstream;
3657
3658 rtl8214fc_media_set(phydev, true);
3659
3660 return 0;
3661 }
3662
3663 static void rtl8214fc_sfp_remove(void *upstream)
3664 {
3665 struct phy_device *phydev = upstream;
3666
3667 rtl8214fc_media_set(phydev, false);
3668 }
3669
3670 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3671 .attach = phy_sfp_attach,
3672 .detach = phy_sfp_detach,
3673 .module_insert = rtl8214fc_sfp_insert,
3674 .module_remove = rtl8214fc_sfp_remove,
3675 };
3676
3677 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3678 {
3679 struct device *dev = &phydev->mdio.dev;
3680 int addr = phydev->mdio.addr;
3681 int ret = 0;
3682
3683 /* All base addresses of the PHYs start at multiples of 8 */
3684 devm_phy_package_join(dev, phydev, addr & (~7),
3685 sizeof(struct rtl83xx_shared_private));
3686
3687 if (!(addr % 8)) {
3688 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3689 shared->name = "RTL8214FC";
3690 if (soc_info.id != 0x8393) {
3691 /* Configuration must be done while patching still possible */
3692 ret = rtl8380_configure_rtl8214fc(phydev);
3693 if (ret)
3694 return ret;
3695 }
3696 }
3697
3698 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3699 }
3700
3701 static int rtl8214c_phy_probe(struct phy_device *phydev)
3702 {
3703 struct device *dev = &phydev->mdio.dev;
3704 int addr = phydev->mdio.addr;
3705
3706 /* All base addresses of the PHYs start at multiples of 8 */
3707 devm_phy_package_join(dev, phydev, addr & (~7),
3708 sizeof(struct rtl83xx_shared_private));
3709
3710 if (!(addr % 8)) {
3711 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3712 shared->name = "RTL8214C";
3713 /* Configuration must be done whil patching still possible */
3714 return rtl8380_configure_rtl8214c(phydev);
3715 }
3716
3717 return 0;
3718 }
3719
3720 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3721 {
3722 struct device *dev = &phydev->mdio.dev;
3723 int addr = phydev->mdio.addr;
3724
3725 /* All base addresses of the PHYs start at multiples of 8 */
3726 devm_phy_package_join(dev, phydev, addr & (~7),
3727 sizeof(struct rtl83xx_shared_private));
3728
3729 if (!(addr % 8)) {
3730 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3731 shared->name = "RTL8218B (external)";
3732 if (soc_info.family == RTL8380_FAMILY_ID) {
3733 /* Configuration must be done while patching still possible */
3734 return rtl8380_configure_ext_rtl8218b(phydev);
3735 }
3736 }
3737
3738 return 0;
3739 }
3740
3741 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3742 {
3743 struct device *dev = &phydev->mdio.dev;
3744 int addr = phydev->mdio.addr;
3745
3746 if (soc_info.family != RTL8380_FAMILY_ID)
3747 return -ENODEV;
3748 if (addr >= 24)
3749 return -ENODEV;
3750
3751 pr_debug("%s: id: %d\n", __func__, addr);
3752 /* All base addresses of the PHYs start at multiples of 8 */
3753 devm_phy_package_join(dev, phydev, addr & (~7),
3754 sizeof(struct rtl83xx_shared_private));
3755
3756 if (!(addr % 8)) {
3757 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3758 shared->name = "RTL8218B (internal)";
3759 /* Configuration must be done while patching still possible */
3760 return rtl8380_configure_int_rtl8218b(phydev);
3761 }
3762
3763 return 0;
3764 }
3765
3766 static int rtl8218d_phy_probe(struct phy_device *phydev)
3767 {
3768 struct device *dev = &phydev->mdio.dev;
3769 int addr = phydev->mdio.addr;
3770
3771 pr_debug("%s: id: %d\n", __func__, addr);
3772 /* All base addresses of the PHYs start at multiples of 8 */
3773 devm_phy_package_join(dev, phydev, addr & (~7),
3774 sizeof(struct rtl83xx_shared_private));
3775
3776 /* All base addresses of the PHYs start at multiples of 8 */
3777 if (!(addr % 8)) {
3778 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3779 shared->name = "RTL8218D";
3780 /* Configuration must be done while patching still possible */
3781 /* TODO: return configure_rtl8218d(phydev); */
3782 }
3783
3784 return 0;
3785 }
3786
3787 static int rtl838x_serdes_probe(struct phy_device *phydev)
3788 {
3789 int addr = phydev->mdio.addr;
3790
3791 if (soc_info.family != RTL8380_FAMILY_ID)
3792 return -ENODEV;
3793 if (addr < 24)
3794 return -ENODEV;
3795
3796 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3797 if (soc_info.id == 0x8380) {
3798 if (addr == 24)
3799 return rtl8380_configure_serdes(phydev);
3800 return 0;
3801 }
3802
3803 return -ENODEV;
3804 }
3805
3806 static int rtl8393_serdes_probe(struct phy_device *phydev)
3807 {
3808 int addr = phydev->mdio.addr;
3809
3810 pr_info("%s: id: %d\n", __func__, addr);
3811 if (soc_info.family != RTL8390_FAMILY_ID)
3812 return -ENODEV;
3813
3814 if (addr < 24)
3815 return -ENODEV;
3816
3817 return rtl8390_configure_serdes(phydev);
3818 }
3819
3820 static int rtl8390_serdes_probe(struct phy_device *phydev)
3821 {
3822 int addr = phydev->mdio.addr;
3823
3824 if (soc_info.family != RTL8390_FAMILY_ID)
3825 return -ENODEV;
3826
3827 if (addr < 24)
3828 return -ENODEV;
3829
3830 return rtl8390_configure_generic(phydev);
3831 }
3832
3833 static int rtl9300_serdes_probe(struct phy_device *phydev)
3834 {
3835 if (soc_info.family != RTL9300_FAMILY_ID)
3836 return -ENODEV;
3837
3838 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3839
3840 return 0;
3841 }
3842
3843 static struct phy_driver rtl83xx_phy_driver[] = {
3844 {
3845 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3846 .name = "Realtek RTL8214C",
3847 .features = PHY_GBIT_FEATURES,
3848 .flags = PHY_HAS_REALTEK_PAGES,
3849 .match_phy_device = rtl8214c_match_phy_device,
3850 .probe = rtl8214c_phy_probe,
3851 .suspend = genphy_suspend,
3852 .resume = genphy_resume,
3853 .set_loopback = genphy_loopback,
3854 },
3855 {
3856 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3857 .name = "Realtek RTL8214FC",
3858 .features = PHY_GBIT_FIBRE_FEATURES,
3859 .flags = PHY_HAS_REALTEK_PAGES,
3860 .match_phy_device = rtl8214fc_match_phy_device,
3861 .probe = rtl8214fc_phy_probe,
3862 .suspend = rtl8214fc_suspend,
3863 .resume = rtl8214fc_resume,
3864 .set_loopback = genphy_loopback,
3865 .set_port = rtl8214fc_set_port,
3866 .get_port = rtl8214fc_get_port,
3867 .set_eee = rtl8214fc_set_eee,
3868 .get_eee = rtl8214fc_get_eee,
3869 },
3870 {
3871 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3872 .name = "Realtek RTL8218B (external)",
3873 .features = PHY_GBIT_FEATURES,
3874 .flags = PHY_HAS_REALTEK_PAGES,
3875 .match_phy_device = rtl8218b_ext_match_phy_device,
3876 .probe = rtl8218b_ext_phy_probe,
3877 .suspend = genphy_suspend,
3878 .resume = genphy_resume,
3879 .set_loopback = genphy_loopback,
3880 .set_eee = rtl8218b_set_eee,
3881 .get_eee = rtl8218b_get_eee,
3882 },
3883 {
3884 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3885 .name = "REALTEK RTL8218D",
3886 .features = PHY_GBIT_FEATURES,
3887 .flags = PHY_HAS_REALTEK_PAGES,
3888 .probe = rtl8218d_phy_probe,
3889 .suspend = genphy_suspend,
3890 .resume = genphy_resume,
3891 .set_loopback = genphy_loopback,
3892 .set_eee = rtl8218d_set_eee,
3893 .get_eee = rtl8218d_get_eee,
3894 },
3895 {
3896 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3897 .name = "REALTEK RTL8221B",
3898 .features = PHY_GBIT_FEATURES,
3899 .flags = PHY_HAS_REALTEK_PAGES,
3900 .suspend = genphy_suspend,
3901 .resume = genphy_resume,
3902 .set_loopback = genphy_loopback,
3903 .read_page = rtl8226_read_page,
3904 .write_page = rtl8226_write_page,
3905 .read_status = rtl8226_read_status,
3906 .config_aneg = rtl8226_config_aneg,
3907 .set_eee = rtl8226_set_eee,
3908 .get_eee = rtl8226_get_eee,
3909 },
3910 {
3911 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3912 .name = "REALTEK RTL8226",
3913 .features = PHY_GBIT_FEATURES,
3914 .flags = PHY_HAS_REALTEK_PAGES,
3915 .suspend = genphy_suspend,
3916 .resume = genphy_resume,
3917 .set_loopback = genphy_loopback,
3918 .read_page = rtl8226_read_page,
3919 .write_page = rtl8226_write_page,
3920 .read_status = rtl8226_read_status,
3921 .config_aneg = rtl8226_config_aneg,
3922 .set_eee = rtl8226_set_eee,
3923 .get_eee = rtl8226_get_eee,
3924 },
3925 {
3926 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3927 .name = "Realtek RTL8218B (internal)",
3928 .features = PHY_GBIT_FEATURES,
3929 .flags = PHY_HAS_REALTEK_PAGES,
3930 .probe = rtl8218b_int_phy_probe,
3931 .suspend = genphy_suspend,
3932 .resume = genphy_resume,
3933 .set_loopback = genphy_loopback,
3934 .set_eee = rtl8218b_set_eee,
3935 .get_eee = rtl8218b_get_eee,
3936 },
3937 {
3938 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3939 .name = "Realtek RTL8380 SERDES",
3940 .features = PHY_GBIT_FIBRE_FEATURES,
3941 .flags = PHY_HAS_REALTEK_PAGES,
3942 .probe = rtl838x_serdes_probe,
3943 .suspend = genphy_suspend,
3944 .resume = genphy_resume,
3945 .set_loopback = genphy_loopback,
3946 .read_status = rtl8380_read_status,
3947 },
3948 {
3949 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3950 .name = "Realtek RTL8393 SERDES",
3951 .features = PHY_GBIT_FIBRE_FEATURES,
3952 .flags = PHY_HAS_REALTEK_PAGES,
3953 .probe = rtl8393_serdes_probe,
3954 .suspend = genphy_suspend,
3955 .resume = genphy_resume,
3956 .set_loopback = genphy_loopback,
3957 .read_status = rtl8393_read_status,
3958 },
3959 {
3960 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3961 .name = "Realtek RTL8390 Generic",
3962 .features = PHY_GBIT_FIBRE_FEATURES,
3963 .flags = PHY_HAS_REALTEK_PAGES,
3964 .probe = rtl8390_serdes_probe,
3965 .suspend = genphy_suspend,
3966 .resume = genphy_resume,
3967 .set_loopback = genphy_loopback,
3968 },
3969 {
3970 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3971 .name = "REALTEK RTL9300 SERDES",
3972 .features = PHY_GBIT_FIBRE_FEATURES,
3973 .flags = PHY_HAS_REALTEK_PAGES,
3974 .probe = rtl9300_serdes_probe,
3975 .suspend = genphy_suspend,
3976 .resume = genphy_resume,
3977 .set_loopback = genphy_loopback,
3978 .read_status = rtl9300_read_status,
3979 },
3980 };
3981
3982 module_phy_driver(rtl83xx_phy_driver);
3983
3984 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
3985 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
3986 { }
3987 };
3988
3989 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
3990
3991 MODULE_AUTHOR("B. Koblitz");
3992 MODULE_DESCRIPTION("RTL83xx PHY driver");
3993 MODULE_LICENSE("GPL");
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