1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
4 * Copyright (C) 2020 B. Koblitz
7 #include <linux/module.h>
8 #include <linux/delay.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
17 #include <asm/mach-rtl838x/mach-rtl83xx.h>
18 #include "rtl83xx-phy.h"
20 extern struct rtl83xx_soc_info soc_info
;
21 extern struct mutex smi_lock
;
26 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
27 #define RTL8XXX_PAGE_SELECT 0x1f
29 #define RTL8XXX_PAGE_MAIN 0x0000
30 #define RTL821X_PAGE_PORT 0x0266
31 #define RTL821X_PAGE_POWER 0x0a40
32 #define RTL821X_PAGE_GPHY 0x0a42
33 #define RTL821X_PAGE_MAC 0x0a43
34 #define RTL821X_PAGE_STATE 0x0b80
35 #define RTL821X_PAGE_PATCH 0x0b82
37 /* Using the special page 0xfff with the MDIO controller found in
38 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
39 * the cache and paging engine of the MDIO controller.
41 #define RTL83XX_PAGE_RAW 0x0fff
43 /* internal RTL821X PHY uses register 0x1d to select media page */
44 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
45 /* external RTL821X PHY uses register 0x1e to select media page */
46 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48 #define RTL821X_MEDIA_PAGE_AUTO 0
49 #define RTL821X_MEDIA_PAGE_COPPER 1
50 #define RTL821X_MEDIA_PAGE_FIBRE 3
51 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
56 * bus to detect e.g. link and media changes. For operations on the PHYs such as
57 * patching or other configuration changes such as EEE, polling needs to be disabled
58 * since otherwise these operations may fails or lead to unpredictable results.
60 DEFINE_MUTEX(poll_lock
);
62 static const struct firmware rtl838x_8380_fw
;
63 static const struct firmware rtl838x_8214fc_fw
;
64 static const struct firmware rtl838x_8218b_fw
;
66 static u64
disable_polling(int port
)
70 mutex_lock(&poll_lock
);
72 switch (soc_info
.family
) {
73 case RTL8380_FAMILY_ID
:
74 saved_state
= sw_r32(RTL838X_SMI_POLL_CTRL
);
75 sw_w32_mask(BIT(port
), 0, RTL838X_SMI_POLL_CTRL
);
77 case RTL8390_FAMILY_ID
:
78 saved_state
= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
80 saved_state
|= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL
);
81 sw_w32_mask(BIT(port
% 32), 0,
82 RTL839X_SMI_PORT_POLLING_CTRL
+ ((port
>> 5) << 2));
84 case RTL9300_FAMILY_ID
:
85 saved_state
= sw_r32(RTL930X_SMI_POLL_CTRL
);
86 sw_w32_mask(BIT(port
), 0, RTL930X_SMI_POLL_CTRL
);
88 case RTL9310_FAMILY_ID
:
89 pr_warn("%s not implemented for RTL931X\n", __func__
);
93 mutex_unlock(&poll_lock
);
98 static int resume_polling(u64 saved_state
)
100 mutex_lock(&poll_lock
);
102 switch (soc_info
.family
) {
103 case RTL8380_FAMILY_ID
:
104 sw_w32(saved_state
, RTL838X_SMI_POLL_CTRL
);
106 case RTL8390_FAMILY_ID
:
107 sw_w32(saved_state
>> 32, RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
108 sw_w32(saved_state
, RTL839X_SMI_PORT_POLLING_CTRL
);
110 case RTL9300_FAMILY_ID
:
111 sw_w32(saved_state
, RTL930X_SMI_POLL_CTRL
);
113 case RTL9310_FAMILY_ID
:
114 pr_warn("%s not implemented for RTL931X\n", __func__
);
118 mutex_unlock(&poll_lock
);
123 static void rtl8380_int_phy_on_off(struct phy_device
*phydev
, bool on
)
125 phy_modify(phydev
, 0, BMCR_PDOWN
, on
? 0 : BMCR_PDOWN
);
128 static void rtl8380_rtl8214fc_on_off(struct phy_device
*phydev
, bool on
)
131 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_FIBRE
);
132 phy_modify(phydev
, 0x10, BMCR_PDOWN
, on
? 0 : BMCR_PDOWN
);
135 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
136 phy_modify_paged(phydev
, RTL821X_PAGE_POWER
, 0x10, BMCR_PDOWN
, on
? 0 : BMCR_PDOWN
);
139 static void rtl8380_phy_reset(struct phy_device
*phydev
)
141 phy_modify(phydev
, 0, BMCR_RESET
, BMCR_RESET
);
144 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
145 u16 rtl9300_sds_regs
[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
146 0x02A4, 0x02A4, 0x0198, 0x0198 };
147 u8 rtl9300_sds_lsb
[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
149 /* Reset the SerDes by powering it off and set a new operations mode
150 * of the SerDes. 0x1f is off. Other modes are
151 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
152 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
153 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
154 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
155 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
157 void rtl9300_sds_rst(int sds_num
, u32 mode
)
159 pr_info("%s %d\n", __func__
, mode
);
160 if (sds_num
< 0 || sds_num
> 11) {
161 pr_err("Wrong SerDes number: %d\n", sds_num
);
165 sw_w32_mask(0x1f << rtl9300_sds_lsb
[sds_num
], 0x1f << rtl9300_sds_lsb
[sds_num
],
166 rtl9300_sds_regs
[sds_num
]);
169 sw_w32_mask(0x1f << rtl9300_sds_lsb
[sds_num
], mode
<< rtl9300_sds_lsb
[sds_num
],
170 rtl9300_sds_regs
[sds_num
]);
173 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__
,
174 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
177 void rtl9300_sds_set(int sds_num
, u32 mode
)
179 pr_info("%s %d\n", __func__
, mode
);
180 if (sds_num
< 0 || sds_num
> 11) {
181 pr_err("Wrong SerDes number: %d\n", sds_num
);
185 sw_w32_mask(0x1f << rtl9300_sds_lsb
[sds_num
], mode
<< rtl9300_sds_lsb
[sds_num
],
186 rtl9300_sds_regs
[sds_num
]);
189 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__
,
190 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
193 u32
rtl9300_sds_mode_get(int sds_num
)
197 if (sds_num
< 0 || sds_num
> 11) {
198 pr_err("Wrong SerDes number: %d\n", sds_num
);
202 v
= sw_r32(rtl9300_sds_regs
[sds_num
]);
203 v
>>= rtl9300_sds_lsb
[sds_num
];
208 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
209 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
211 int rtl839x_read_sds_phy(int phy_addr
, int phy_reg
)
220 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
221 * which would otherwise read as 0.
223 if (soc_info
.id
== 0x8393) {
224 if (phy_reg
== MII_PHYSID1
)
226 if (phy_reg
== MII_PHYSID2
)
230 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
231 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
232 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
233 * one 32 bit register.
235 reg
= (phy_reg
<< 1) & 0xfc;
236 val
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
239 val
= (val
>> 16) & 0xffff;
246 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
247 * register which simulates commands to an internal MDIO bus.
249 int rtl930x_read_sds_phy(int phy_addr
, int page
, int phy_reg
)
252 u32 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 1;
254 sw_w32(cmd
, RTL930X_SDS_INDACS_CMD
);
256 for (i
= 0; i
< 100; i
++) {
257 if (!(sw_r32(RTL930X_SDS_INDACS_CMD
) & 0x1))
265 return sw_r32(RTL930X_SDS_INDACS_DATA
) & 0xffff;
268 int rtl930x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
)
273 sw_w32(v
, RTL930X_SDS_INDACS_DATA
);
274 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 0x3;
276 for (i
= 0; i
< 100; i
++) {
277 if (!(sw_r32(RTL930X_SDS_INDACS_CMD
) & 0x1))
284 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__
);
291 int rtl931x_read_sds_phy(int phy_addr
, int page
, int phy_reg
)
294 u32 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13 | 1;
296 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__
, phy_addr
, phy_reg
);
297 sw_w32(cmd
, RTL931X_SERDES_INDRT_ACCESS_CTRL
);
299 for (i
= 0; i
< 100; i
++) {
300 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL
) & 0x1))
308 pr_debug("%s: returning %04x\n", __func__
, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL
) & 0xffff);
310 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL
) & 0xffff;
313 int rtl931x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
)
318 cmd
= phy_addr
<< 2 | page
<< 7 | phy_reg
<< 13;
319 sw_w32(cmd
, RTL931X_SERDES_INDRT_ACCESS_CTRL
);
321 sw_w32(v
, RTL931X_SERDES_INDRT_DATA_CTRL
);
323 cmd
= sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL
) | 0x3;
324 sw_w32(cmd
, RTL931X_SERDES_INDRT_ACCESS_CTRL
);
326 for (i
= 0; i
< 100; i
++) {
327 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL
) & 0x1))
338 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
339 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
340 * in a standard page 0 of a PHY
342 int rtl838x_read_sds_phy(int phy_addr
, int phy_reg
)
349 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
354 int rtl839x_write_sds_phy(int phy_addr
, int phy_reg
, u16 v
)
363 reg
= (phy_reg
<< 1) & 0xfc;
367 sw_w32_mask(0xffff0000, val
,
368 RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
370 sw_w32_mask(0xffff, val
,
371 RTL839X_SDS12_13_XSG0
+ offset
+ 0x80 + reg
);
377 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
378 * ports of the RTL838x SoCs
380 static int rtl8380_read_status(struct phy_device
*phydev
)
384 err
= genphy_read_status(phydev
);
387 phydev
->speed
= SPEED_1000
;
388 phydev
->duplex
= DUPLEX_FULL
;
394 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
395 * ports of the RTL8393 SoC
397 static int rtl8393_read_status(struct phy_device
*phydev
)
401 int phy_addr
= phydev
->mdio
.addr
;
404 err
= genphy_read_status(phydev
);
409 phydev
->speed
= SPEED_100
;
410 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
413 v
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80);
414 if (!(v
& (1 << 13)) && (v
& (1 << 6)))
415 phydev
->speed
= SPEED_1000
;
416 phydev
->duplex
= DUPLEX_FULL
;
422 static int rtl8226_read_page(struct phy_device
*phydev
)
424 return __phy_read(phydev
, RTL8XXX_PAGE_SELECT
);
427 static int rtl8226_write_page(struct phy_device
*phydev
, int page
)
429 return __phy_write(phydev
, RTL8XXX_PAGE_SELECT
, page
);
432 static int rtl8226_read_status(struct phy_device
*phydev
)
437 /* TODO: ret = genphy_read_status(phydev);
439 * pr_info("%s: genphy_read_status failed\n", __func__);
444 /* Link status must be read twice */
445 for (int i
= 0; i
< 2; i
++)
446 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA402);
448 phydev
->link
= val
& BIT(2) ? 1 : 0;
452 /* Read duplex status */
453 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA434);
456 phydev
->duplex
= !!(val
& BIT(3));
459 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA434);
460 switch (val
& 0x0630) {
462 phydev
->speed
= SPEED_10
;
465 phydev
->speed
= SPEED_100
;
468 phydev
->speed
= SPEED_1000
;
471 phydev
->speed
= SPEED_10000
;
474 phydev
->speed
= SPEED_2500
;
477 phydev
->speed
= SPEED_5000
;
487 static int rtl8226_advertise_aneg(struct phy_device
*phydev
)
492 pr_info("In %s\n", __func__
);
494 v
= phy_read_mmd(phydev
, MMD_AN
, 16);
498 v
|= ADVERTISE_10HALF
;
499 v
|= ADVERTISE_10FULL
;
500 v
|= ADVERTISE_100HALF
;
501 v
|= ADVERTISE_100FULL
;
503 ret
= phy_write_mmd(phydev
, MMD_AN
, 16, v
);
506 v
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA412);
509 v
|= ADVERTISE_1000FULL
;
511 ret
= phy_write_mmd(phydev
, MMD_VEND2
, 0xA412, v
);
516 v
= phy_read_mmd(phydev
, MMD_AN
, 32);
521 ret
= phy_write_mmd(phydev
, MMD_AN
, 32, v
);
527 static int rtl8226_config_aneg(struct phy_device
*phydev
)
532 pr_debug("In %s\n", __func__
);
533 if (phydev
->autoneg
== AUTONEG_ENABLE
) {
534 ret
= rtl8226_advertise_aneg(phydev
);
537 /* AutoNegotiationEnable */
538 v
= phy_read_mmd(phydev
, MMD_AN
, 0);
542 v
|= BIT(12); /* Enable AN */
543 ret
= phy_write_mmd(phydev
, MMD_AN
, 0, v
);
547 /* RestartAutoNegotiation */
548 v
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA400);
553 ret
= phy_write_mmd(phydev
, MMD_VEND2
, 0xA400, v
);
556 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
562 static int rtl8226_get_eee(struct phy_device
*phydev
,
563 struct ethtool_eee
*e
)
566 int addr
= phydev
->mdio
.addr
;
568 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
570 val
= phy_read_mmd(phydev
, MMD_AN
, 60);
571 if (e
->eee_enabled
) {
572 e
->eee_enabled
= !!(val
& BIT(1));
573 if (!e
->eee_enabled
) {
574 val
= phy_read_mmd(phydev
, MMD_AN
, 62);
575 e
->eee_enabled
= !!(val
& BIT(0));
578 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
583 static int rtl8226_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
585 int port
= phydev
->mdio
.addr
;
590 pr_info("In %s, port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
592 poll_state
= disable_polling(port
);
594 /* Remember aneg state */
595 val
= phy_read_mmd(phydev
, MMD_AN
, 0);
596 an_enabled
= !!(val
& BIT(12));
598 /* Setup 100/1000MBit */
599 val
= phy_read_mmd(phydev
, MMD_AN
, 60);
604 phy_write_mmd(phydev
, MMD_AN
, 60, val
);
607 val
= phy_read_mmd(phydev
, MMD_AN
, 62);
612 phy_write_mmd(phydev
, MMD_AN
, 62, val
);
614 /* RestartAutoNegotiation */
615 val
= phy_read_mmd(phydev
, MMD_VEND2
, 0xA400);
617 phy_write_mmd(phydev
, MMD_VEND2
, 0xA400, val
);
619 resume_polling(poll_state
);
624 static struct fw_header
*rtl838x_request_fw(struct phy_device
*phydev
,
625 const struct firmware
*fw
,
628 struct device
*dev
= &phydev
->mdio
.dev
;
631 uint32_t checksum
, my_checksum
;
633 err
= request_firmware(&fw
, name
, dev
);
637 if (fw
->size
< sizeof(struct fw_header
)) {
638 pr_err("Firmware size too small.\n");
643 h
= (struct fw_header
*) fw
->data
;
644 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw
->size
, h
->magic
);
646 if (h
->magic
!= 0x83808380) {
647 pr_err("Wrong firmware file: MAGIC mismatch.\n");
651 checksum
= h
->checksum
;
653 my_checksum
= ~crc32(0xFFFFFFFFU
, fw
->data
, fw
->size
);
654 if (checksum
!= my_checksum
) {
655 pr_err("Firmware checksum mismatch.\n");
659 h
->checksum
= checksum
;
663 dev_err(dev
, "Unable to load firmware %s (%d)\n", name
, err
);
667 static void rtl821x_phy_setup_package_broadcast(struct phy_device
*phydev
, bool enable
)
669 int mac
= phydev
->mdio
.addr
;
671 /* select main page 0 */
672 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
673 /* write to 0x8 to register 0x1d on main page 0 */
674 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
675 /* select page 0x266 */
676 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PORT
);
677 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
678 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 0x16, (enable
?0xff00:0x00) | mac
);
679 /* return to main page 0 */
680 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
681 /* write to 0x0 to register 0x1d on main page 0 */
682 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
686 static int rtl8390_configure_generic(struct phy_device
*phydev
)
688 int mac
= phydev
->mdio
.addr
;
691 val
= phy_read(phydev
, 2);
693 val
= phy_read(phydev
, 3);
695 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
697 /* Read internal PHY ID */
698 phy_write_paged(phydev
, 31, 27, 0x0002);
699 val
= phy_read_paged(phydev
, 31, 28);
701 /* Internal RTL8218B, version 2 */
702 phydev_info(phydev
, "Detected unknown %x\n", val
);
707 static int rtl8380_configure_int_rtl8218b(struct phy_device
*phydev
)
710 int mac
= phydev
->mdio
.addr
;
712 u32
*rtl838x_6275B_intPhy_perport
;
713 u32
*rtl8218b_6276B_hwEsd_perport
;
715 val
= phy_read(phydev
, 2);
717 val
= phy_read(phydev
, 3);
719 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
721 /* Read internal PHY ID */
722 phy_write_paged(phydev
, 31, 27, 0x0002);
723 val
= phy_read_paged(phydev
, 31, 28);
725 phydev_err(phydev
, "Expected internal RTL8218B, found PHY-ID %x\n", val
);
729 /* Internal RTL8218B, version 2 */
730 phydev_info(phydev
, "Detected internal RTL8218B\n");
732 h
= rtl838x_request_fw(phydev
, &rtl838x_8380_fw
, FIRMWARE_838X_8380_1
);
736 if (h
->phy
!= 0x83800000) {
737 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
741 rtl838x_6275B_intPhy_perport
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[8].start
;
742 rtl8218b_6276B_hwEsd_perport
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[9].start
;
744 // Currently not used
745 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
749 val
= phy_read(phydev
, MII_BMCR
);
750 if (val
& BMCR_PDOWN
)
751 rtl8380_int_phy_on_off(phydev
, true);
753 rtl8380_phy_reset(phydev
);
756 /* Ready PHY for patch */
757 for (int p
= 0; p
< 8; p
++) {
758 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PATCH
);
759 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
, 0x10, 0x0010);
762 for (int p
= 0; p
< 8; p
++) {
765 for (i
= 0; i
< 100 ; i
++) {
766 val
= phy_package_port_read_paged(phydev
, p
, RTL821X_PAGE_STATE
, 0x10);
772 "ERROR: Port %d not ready for patch.\n",
777 for (int p
= 0; p
< 8; p
++) {
781 while (rtl838x_6275B_intPhy_perport
[i
* 2]) {
782 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
,
783 rtl838x_6275B_intPhy_perport
[i
* 2],
784 rtl838x_6275B_intPhy_perport
[i
* 2 + 1]);
788 while (rtl8218b_6276B_hwEsd_perport
[i
* 2]) {
789 phy_package_port_write_paged(phydev
, p
, RTL83XX_PAGE_RAW
,
790 rtl8218b_6276B_hwEsd_perport
[i
* 2],
791 rtl8218b_6276B_hwEsd_perport
[i
* 2 + 1]);
799 static int rtl8380_configure_ext_rtl8218b(struct phy_device
*phydev
)
801 u32 val
, ipd
, phy_id
;
802 int mac
= phydev
->mdio
.addr
;
804 u32
*rtl8380_rtl8218b_perchip
;
805 u32
*rtl8218B_6276B_rtl8380_perport
;
806 u32
*rtl8380_rtl8218b_perport
;
808 if (soc_info
.family
== RTL8380_FAMILY_ID
&& mac
!= 0 && mac
!= 16) {
809 phydev_err(phydev
, "External RTL8218B must have PHY-IDs 0 or 16!\n");
812 val
= phy_read(phydev
, 2);
814 val
= phy_read(phydev
, 3);
816 pr_info("Phy on MAC %d: %x\n", mac
, phy_id
);
818 /* Read internal PHY ID */
819 phy_write_paged(phydev
, 31, 27, 0x0002);
820 val
= phy_read_paged(phydev
, 31, 28);
822 phydev_err(phydev
, "Expected external RTL8218B, found PHY-ID %x\n", val
);
825 phydev_info(phydev
, "Detected external RTL8218B\n");
827 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8218b_1
);
831 if (h
->phy
!= 0x8218b000) {
832 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
836 rtl8380_rtl8218b_perchip
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[0].start
;
837 rtl8218B_6276B_rtl8380_perport
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[1].start
;
838 rtl8380_rtl8218b_perport
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[2].start
;
840 val
= phy_read(phydev
, MII_BMCR
);
841 if (val
& BMCR_PDOWN
)
842 rtl8380_int_phy_on_off(phydev
, true);
844 rtl8380_phy_reset(phydev
);
848 /* Get Chip revision */
849 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
850 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 0x1b, 0x4);
851 val
= phy_read_paged(phydev
, RTL83XX_PAGE_RAW
, 0x1c);
853 phydev_info(phydev
, "Detected chip revision %04x\n", val
);
855 for (int i
= 0; rtl8380_rtl8218b_perchip
[i
* 3] &&
856 rtl8380_rtl8218b_perchip
[i
* 3 + 1]; i
++) {
857 phy_package_port_write_paged(phydev
, rtl8380_rtl8218b_perchip
[i
* 3],
858 RTL83XX_PAGE_RAW
, rtl8380_rtl8218b_perchip
[i
* 3 + 1],
859 rtl8380_rtl8218b_perchip
[i
* 3 + 2]);
863 for (int i
= 0; i
< 8; i
++) {
864 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
865 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x00, 0x1140);
870 for (int i
= 0; i
< 8; i
++) {
871 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PATCH
);
872 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x10, 0x0010);
877 /* Verify patch readiness */
878 for (int i
= 0; i
< 8; i
++) {
881 for (l
= 0; l
< 100; l
++) {
882 val
= phy_package_port_read_paged(phydev
, i
, RTL821X_PAGE_STATE
, 0x10);
887 phydev_err(phydev
, "Could not patch PHY\n");
892 /* Use Broadcast ID method for patching */
893 rtl821x_phy_setup_package_broadcast(phydev
, true);
895 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 30, 8);
896 phy_write_paged(phydev
, 0x26e, 17, 0xb);
897 phy_write_paged(phydev
, 0x26e, 16, 0x2);
899 ipd
= phy_read_paged(phydev
, 0x26e, 19);
900 phy_write_paged(phydev
, 0, 30, 0);
901 ipd
= (ipd
>> 4) & 0xf; /* unused ? */
903 for (int i
= 0; rtl8218B_6276B_rtl8380_perport
[i
* 2]; i
++) {
904 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, rtl8218B_6276B_rtl8380_perport
[i
* 2],
905 rtl8218B_6276B_rtl8380_perport
[i
* 2 + 1]);
908 /* Disable broadcast ID */
909 rtl821x_phy_setup_package_broadcast(phydev
, false);
914 static int rtl8218b_ext_match_phy_device(struct phy_device
*phydev
)
916 int addr
= phydev
->mdio
.addr
;
918 /* Both the RTL8214FC and the external RTL8218B have the same
919 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
920 * at PHY IDs 0-7, while the RTL8214FC must be attached via
921 * the pair of SGMII/1000Base-X with higher PHY-IDs
923 if (soc_info
.family
== RTL8380_FAMILY_ID
)
924 return phydev
->phy_id
== PHY_ID_RTL8218B_E
&& addr
< 8;
926 return phydev
->phy_id
== PHY_ID_RTL8218B_E
;
929 static bool rtl8214fc_media_is_fibre(struct phy_device
*phydev
)
931 int mac
= phydev
->mdio
.addr
;
933 static int reg
[] = {16, 19, 20, 21};
936 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
937 val
= phy_package_read_paged(phydev
, RTL821X_PAGE_PORT
, reg
[mac
% 4]);
938 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
940 if (val
& BMCR_PDOWN
)
946 static void rtl8214fc_power_set(struct phy_device
*phydev
, int port
, bool on
)
948 char *state
= on
? "on" : "off";
950 if (port
== PORT_FIBRE
) {
951 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__
, state
, phydev
->mdio
.addr
);
952 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_FIBRE
);
954 pr_info("%s: Powering %s COPPER (port %d)\n", __func__
, state
, phydev
->mdio
.addr
);
955 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
959 phy_modify_paged(phydev
, RTL821X_PAGE_POWER
, 0x10, BMCR_PDOWN
, 0);
961 phy_modify_paged(phydev
, RTL821X_PAGE_POWER
, 0x10, 0, BMCR_PDOWN
);
964 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
967 static int rtl8214fc_suspend(struct phy_device
*phydev
)
969 rtl8214fc_power_set(phydev
, PORT_MII
, false);
970 rtl8214fc_power_set(phydev
, PORT_FIBRE
, false);
975 static int rtl8214fc_resume(struct phy_device
*phydev
)
977 if (rtl8214fc_media_is_fibre(phydev
)) {
978 rtl8214fc_power_set(phydev
, PORT_MII
, false);
979 rtl8214fc_power_set(phydev
, PORT_FIBRE
, true);
981 rtl8214fc_power_set(phydev
, PORT_FIBRE
, false);
982 rtl8214fc_power_set(phydev
, PORT_MII
, true);
988 static void rtl8214fc_media_set(struct phy_device
*phydev
, bool set_fibre
)
990 int mac
= phydev
->mdio
.addr
;
992 static int reg
[] = {16, 19, 20, 21};
995 pr_info("%s: port %d, set_fibre: %d\n", __func__
, mac
, set_fibre
);
996 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
997 val
= phy_package_read_paged(phydev
, RTL821X_PAGE_PORT
, reg
[mac
% 4]);
1006 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_INTERNAL
);
1007 phy_package_write_paged(phydev
, RTL821X_PAGE_PORT
, reg
[mac
% 4], val
);
1008 phy_package_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1010 if (!phydev
->suspended
) {
1012 rtl8214fc_power_set(phydev
, PORT_MII
, false);
1013 rtl8214fc_power_set(phydev
, PORT_FIBRE
, true);
1015 rtl8214fc_power_set(phydev
, PORT_FIBRE
, false);
1016 rtl8214fc_power_set(phydev
, PORT_MII
, true);
1021 static int rtl8214fc_set_port(struct phy_device
*phydev
, int port
)
1023 bool is_fibre
= (port
== PORT_FIBRE
? true : false);
1024 int addr
= phydev
->mdio
.addr
;
1026 pr_debug("%s port %d to %d\n", __func__
, addr
, port
);
1028 rtl8214fc_media_set(phydev
, is_fibre
);
1033 static int rtl8214fc_get_port(struct phy_device
*phydev
)
1035 int addr
= phydev
->mdio
.addr
;
1037 pr_debug("%s: port %d\n", __func__
, addr
);
1038 if (rtl8214fc_media_is_fibre(phydev
))
1044 /* Enable EEE on the RTL8218B PHYs
1045 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1046 * but the only way that works since the kernel first enables EEE in the MAC
1047 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1049 void rtl8218d_eee_set(struct phy_device
*phydev
, bool enable
)
1054 pr_debug("In %s %d, enable %d\n", __func__
, phydev
->mdio
.addr
, enable
);
1055 /* Set GPHY page to copper */
1056 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1058 val
= phy_read(phydev
, MII_BMCR
);
1059 an_enabled
= val
& BMCR_ANENABLE
;
1061 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1062 val
= phy_read_mmd(phydev
, 7, 60);
1063 val
|= BIT(2) | BIT(1);
1064 phy_write_mmd(phydev
, 7, 60, enable
? 0x6 : 0);
1066 /* 500M EEE ability */
1067 val
= phy_read_paged(phydev
, RTL821X_PAGE_GPHY
, 20);
1072 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, 20, val
);
1074 /* Restart AN if enabled */
1076 val
= phy_read(phydev
, MII_BMCR
);
1077 val
|= BMCR_ANRESTART
;
1078 phy_write(phydev
, MII_BMCR
, val
);
1081 /* GPHY page back to auto */
1082 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1085 static int rtl8218b_get_eee(struct phy_device
*phydev
,
1086 struct ethtool_eee
*e
)
1089 int addr
= phydev
->mdio
.addr
;
1091 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
1093 /* Set GPHY page to copper */
1094 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1096 val
= phy_read_paged(phydev
, 7, 60);
1097 if (e
->eee_enabled
) {
1098 /* Verify vs MAC-based EEE */
1099 e
->eee_enabled
= !!(val
& BIT(7));
1100 if (!e
->eee_enabled
) {
1101 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1102 e
->eee_enabled
= !!(val
& BIT(4));
1105 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
1107 /* GPHY page to auto */
1108 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1113 static int rtl8218d_get_eee(struct phy_device
*phydev
,
1114 struct ethtool_eee
*e
)
1117 int addr
= phydev
->mdio
.addr
;
1119 pr_debug("In %s, port %d, was enabled: %d\n", __func__
, addr
, e
->eee_enabled
);
1121 /* Set GPHY page to copper */
1122 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1124 val
= phy_read_paged(phydev
, 7, 60);
1126 e
->eee_enabled
= !!(val
& BIT(7));
1127 pr_debug("%s: enabled: %d\n", __func__
, e
->eee_enabled
);
1129 /* GPHY page to auto */
1130 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1135 static int rtl8214fc_set_eee(struct phy_device
*phydev
,
1136 struct ethtool_eee
*e
)
1139 int port
= phydev
->mdio
.addr
;
1143 pr_debug("In %s port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
1145 if (rtl8214fc_media_is_fibre(phydev
)) {
1146 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", port
);
1150 poll_state
= disable_polling(port
);
1152 /* Set GPHY page to copper */
1153 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1155 /* Get auto-negotiation status */
1156 val
= phy_read(phydev
, MII_BMCR
);
1157 an_enabled
= val
& BMCR_ANENABLE
;
1159 pr_info("%s: aneg: %d\n", __func__
, an_enabled
);
1160 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1161 val
&= ~BIT(5); /* Use MAC-based EEE */
1162 phy_write_paged(phydev
, RTL821X_PAGE_MAC
, 25, val
);
1164 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1165 phy_write_paged(phydev
, 7, 60, e
->eee_enabled
? 0x6 : 0);
1167 /* 500M EEE ability */
1168 val
= phy_read_paged(phydev
, RTL821X_PAGE_GPHY
, 20);
1174 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, 20, val
);
1176 /* Restart AN if enabled */
1178 pr_info("%s: doing aneg\n", __func__
);
1179 val
= phy_read(phydev
, MII_BMCR
);
1180 val
|= BMCR_ANRESTART
;
1181 phy_write(phydev
, MII_BMCR
, val
);
1184 /* GPHY page back to auto */
1185 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1187 resume_polling(poll_state
);
1192 static int rtl8214fc_get_eee(struct phy_device
*phydev
,
1193 struct ethtool_eee
*e
)
1195 int addr
= phydev
->mdio
.addr
;
1197 pr_debug("In %s port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
1198 if (rtl8214fc_media_is_fibre(phydev
)) {
1199 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", addr
);
1203 return rtl8218b_get_eee(phydev
, e
);
1206 static int rtl8218b_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
1208 int port
= phydev
->mdio
.addr
;
1213 pr_info("In %s, port %d, enabled %d\n", __func__
, port
, e
->eee_enabled
);
1215 poll_state
= disable_polling(port
);
1217 /* Set GPHY page to copper */
1218 phy_write(phydev
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1219 val
= phy_read(phydev
, MII_BMCR
);
1220 an_enabled
= val
& BMCR_ANENABLE
;
1222 if (e
->eee_enabled
) {
1223 /* 100/1000M EEE Capability */
1224 phy_write(phydev
, 13, 0x0007);
1225 phy_write(phydev
, 14, 0x003C);
1226 phy_write(phydev
, 13, 0x4007);
1227 phy_write(phydev
, 14, 0x0006);
1229 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1231 phy_write_paged(phydev
, RTL821X_PAGE_MAC
, 25, val
);
1233 /* 100/1000M EEE Capability */
1234 phy_write(phydev
, 13, 0x0007);
1235 phy_write(phydev
, 14, 0x003C);
1236 phy_write(phydev
, 13, 0x0007);
1237 phy_write(phydev
, 14, 0x0000);
1239 val
= phy_read_paged(phydev
, RTL821X_PAGE_MAC
, 25);
1241 phy_write_paged(phydev
, RTL821X_PAGE_MAC
, 25, val
);
1244 /* Restart AN if enabled */
1246 val
= phy_read(phydev
, MII_BMCR
);
1247 val
|= BMCR_ANRESTART
;
1248 phy_write(phydev
, MII_BMCR
, val
);
1251 /* GPHY page back to auto */
1252 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1254 pr_info("%s done\n", __func__
);
1255 resume_polling(poll_state
);
1260 static int rtl8218d_set_eee(struct phy_device
*phydev
, struct ethtool_eee
*e
)
1262 int addr
= phydev
->mdio
.addr
;
1265 pr_info("In %s, port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
1267 poll_state
= disable_polling(addr
);
1269 rtl8218d_eee_set(phydev
, (bool) e
->eee_enabled
);
1271 resume_polling(poll_state
);
1276 static int rtl8214c_match_phy_device(struct phy_device
*phydev
)
1278 return phydev
->phy_id
== PHY_ID_RTL8214C
;
1281 static int rtl8380_configure_rtl8214c(struct phy_device
*phydev
)
1284 int mac
= phydev
->mdio
.addr
;
1286 val
= phy_read(phydev
, 2);
1288 val
= phy_read(phydev
, 3);
1290 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
1292 phydev_info(phydev
, "Detected external RTL8214C\n");
1294 /* GPHY auto conf */
1295 phy_write_paged(phydev
, RTL821X_PAGE_GPHY
, RTL821XINT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1300 static int rtl8380_configure_rtl8214fc(struct phy_device
*phydev
)
1302 int mac
= phydev
->mdio
.addr
;
1303 struct fw_header
*h
;
1304 u32
*rtl8380_rtl8214fc_perchip
;
1305 u32
*rtl8380_rtl8214fc_perport
;
1309 val
= phy_read(phydev
, 2);
1311 val
= phy_read(phydev
, 3);
1313 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
1315 /* Read internal PHY id */
1316 phy_write_paged(phydev
, 0, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1317 phy_write_paged(phydev
, 0x1f, 0x1b, 0x0002);
1318 val
= phy_read_paged(phydev
, 0x1f, 0x1c);
1319 if (val
!= 0x6276) {
1320 phydev_err(phydev
, "Expected external RTL8214FC, found PHY-ID %x\n", val
);
1323 phydev_info(phydev
, "Detected external RTL8214FC\n");
1325 h
= rtl838x_request_fw(phydev
, &rtl838x_8214fc_fw
, FIRMWARE_838X_8214FC_1
);
1329 if (h
->phy
!= 0x8214fc00) {
1330 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
1334 rtl8380_rtl8214fc_perchip
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[0].start
;
1336 rtl8380_rtl8214fc_perport
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[1].start
;
1338 /* detect phy version */
1339 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, 27, 0x0004);
1340 val
= phy_read_paged(phydev
, RTL83XX_PAGE_RAW
, 28);
1342 val
= phy_read(phydev
, 16);
1343 if (val
& BMCR_PDOWN
)
1344 rtl8380_rtl8214fc_on_off(phydev
, true);
1346 rtl8380_phy_reset(phydev
);
1349 phy_write_paged(phydev
, 0, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1351 for (int i
= 0; rtl8380_rtl8214fc_perchip
[i
* 3] &&
1352 rtl8380_rtl8214fc_perchip
[i
* 3 + 1]; i
++) {
1355 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x1f)
1356 page
= rtl8380_rtl8214fc_perchip
[i
* 3 + 2];
1357 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x13 && page
== 0x260) {
1358 val
= phy_read_paged(phydev
, 0x260, 13);
1359 val
= (val
& 0x1f00) | (rtl8380_rtl8214fc_perchip
[i
* 3 + 2] & 0xe0ff);
1360 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
,
1361 rtl8380_rtl8214fc_perchip
[i
* 3 + 1], val
);
1363 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
,
1364 rtl8380_rtl8214fc_perchip
[i
* 3 + 1],
1365 rtl8380_rtl8214fc_perchip
[i
* 3 + 2]);
1369 /* Force copper medium */
1370 for (int i
= 0; i
< 4; i
++) {
1371 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
1372 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_COPPER
);
1376 for (int i
= 0; i
< 4; i
++) {
1377 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
1378 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x00, 0x1140);
1382 /* Disable Autosensing */
1383 for (int i
= 0; i
< 4; i
++) {
1386 for (l
= 0; l
< 100; l
++) {
1387 val
= phy_package_port_read_paged(phydev
, i
, RTL821X_PAGE_GPHY
, 0x10);
1388 if ((val
& 0x7) >= 3)
1392 phydev_err(phydev
, "Could not disable autosensing\n");
1398 for (int i
= 0; i
< 4; i
++) {
1399 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL821X_PAGE_PATCH
);
1400 phy_package_port_write_paged(phydev
, i
, RTL83XX_PAGE_RAW
, 0x10, 0x0010);
1404 /* Verify patch readiness */
1405 for (int i
= 0; i
< 4; i
++) {
1408 for (l
= 0; l
< 100; l
++) {
1409 val
= phy_package_port_read_paged(phydev
, i
, RTL821X_PAGE_STATE
, 0x10);
1414 phydev_err(phydev
, "Could not patch PHY\n");
1418 /* Use Broadcast ID method for patching */
1419 rtl821x_phy_setup_package_broadcast(phydev
, true);
1421 for (int i
= 0; rtl8380_rtl8214fc_perport
[i
* 2]; i
++) {
1422 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, rtl8380_rtl8214fc_perport
[i
* 2],
1423 rtl8380_rtl8214fc_perport
[i
* 2 + 1]);
1426 /* Disable broadcast ID */
1427 rtl821x_phy_setup_package_broadcast(phydev
, false);
1429 /* Auto medium selection */
1430 for (int i
= 0; i
< 4; i
++) {
1431 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL8XXX_PAGE_SELECT
, RTL8XXX_PAGE_MAIN
);
1432 phy_write_paged(phydev
, RTL83XX_PAGE_RAW
, RTL821XEXT_MEDIA_PAGE_SELECT
, RTL821X_MEDIA_PAGE_AUTO
);
1438 static int rtl8214fc_match_phy_device(struct phy_device
*phydev
)
1440 int addr
= phydev
->mdio
.addr
;
1442 return phydev
->phy_id
== PHY_ID_RTL8214FC
&& addr
>= 24;
1445 static int rtl8380_configure_serdes(struct phy_device
*phydev
)
1450 struct fw_header
*h
;
1451 u32
*rtl8380_sds_take_reset
;
1452 u32
*rtl8380_sds_common
;
1453 u32
*rtl8380_sds01_qsgmii_6275b
;
1454 u32
*rtl8380_sds23_qsgmii_6275b
;
1455 u32
*rtl8380_sds4_fiber_6275b
;
1456 u32
*rtl8380_sds5_fiber_6275b
;
1457 u32
*rtl8380_sds_reset
;
1458 u32
*rtl8380_sds_release_reset
;
1460 phydev_info(phydev
, "Detected internal RTL8380 SERDES\n");
1462 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8380_1
);
1466 if (h
->magic
!= 0x83808380) {
1467 phydev_err(phydev
, "Wrong firmware file: magic number mismatch.\n");
1471 rtl8380_sds_take_reset
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[0].start
;
1473 rtl8380_sds_common
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[1].start
;
1475 rtl8380_sds01_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[2].start
;
1477 rtl8380_sds23_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[3].start
;
1479 rtl8380_sds4_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[4].start
;
1481 rtl8380_sds5_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[5].start
;
1483 rtl8380_sds_reset
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[6].start
;
1485 rtl8380_sds_release_reset
= (void *)h
+ sizeof(struct fw_header
) + h
->parts
[7].start
;
1487 /* Back up serdes power off value */
1488 sds_conf_value
= sw_r32(RTL838X_SDS_CFG_REG
);
1489 pr_info("SDS power down value: %x\n", sds_conf_value
);
1491 /* take serdes into reset */
1493 while (rtl8380_sds_take_reset
[2 * i
]) {
1494 sw_w32(rtl8380_sds_take_reset
[2 * i
+ 1], rtl8380_sds_take_reset
[2 * i
]);
1499 /* apply common serdes patch */
1501 while (rtl8380_sds_common
[2 * i
]) {
1502 sw_w32(rtl8380_sds_common
[2 * i
+ 1], rtl8380_sds_common
[2 * i
]);
1507 /* internal R/W enable */
1508 sw_w32(3, RTL838X_INT_RW_CTRL
);
1510 /* SerDes ports 4 and 5 are FIBRE ports */
1511 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL
);
1513 /* SerDes module settings, SerDes 0-3 are QSGMII */
1514 v
= 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1515 /* SerDes 4 and 5 are 1000BX FIBRE */
1516 v
|= 0x4 << 5 | 0x4;
1517 sw_w32(v
, RTL838X_SDS_MODE_SEL
);
1519 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL
));
1520 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL
);
1522 while (rtl8380_sds01_qsgmii_6275b
[2 * i
]) {
1523 sw_w32(rtl8380_sds01_qsgmii_6275b
[2 * i
+ 1],
1524 rtl8380_sds01_qsgmii_6275b
[2 * i
]);
1529 while (rtl8380_sds23_qsgmii_6275b
[2 * i
]) {
1530 sw_w32(rtl8380_sds23_qsgmii_6275b
[2 * i
+ 1], rtl8380_sds23_qsgmii_6275b
[2 * i
]);
1535 while (rtl8380_sds4_fiber_6275b
[2 * i
]) {
1536 sw_w32(rtl8380_sds4_fiber_6275b
[2 * i
+ 1], rtl8380_sds4_fiber_6275b
[2 * i
]);
1541 while (rtl8380_sds5_fiber_6275b
[2 * i
]) {
1542 sw_w32(rtl8380_sds5_fiber_6275b
[2 * i
+ 1], rtl8380_sds5_fiber_6275b
[2 * i
]);
1547 while (rtl8380_sds_reset
[2 * i
]) {
1548 sw_w32(rtl8380_sds_reset
[2 * i
+ 1], rtl8380_sds_reset
[2 * i
]);
1553 while (rtl8380_sds_release_reset
[2 * i
]) {
1554 sw_w32(rtl8380_sds_release_reset
[2 * i
+ 1], rtl8380_sds_release_reset
[2 * i
]);
1558 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG
));
1559 sw_w32(sds_conf_value
, RTL838X_SDS_CFG_REG
);
1561 pr_info("Configuration of SERDES done\n");
1566 static int rtl8390_configure_serdes(struct phy_device
*phydev
)
1568 phydev_info(phydev
, "Detected internal RTL8390 SERDES\n");
1570 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1571 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0
+ 0x0a);
1573 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1574 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1575 * and FRE16_EEE_QUIET_FIB1G
1577 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0
+ 0xe0);
1582 void rtl9300_sds_field_w(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
, u32 v
)
1584 int l
= end_bit
- start_bit
+ 1;
1588 u32 mask
= BIT(l
) - 1;
1590 data
= rtl930x_read_sds_phy(sds
, page
, reg
);
1591 data
&= ~(mask
<< start_bit
);
1592 data
|= (v
& mask
) << start_bit
;
1595 rtl930x_write_sds_phy(sds
, page
, reg
, data
);
1598 u32
rtl9300_sds_field_r(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
)
1600 int l
= end_bit
- start_bit
+ 1;
1601 u32 v
= rtl930x_read_sds_phy(sds
, page
, reg
);
1606 return (v
>> start_bit
) & (BIT(l
) - 1);
1609 /* Read the link and speed status of the internal SerDes of the RTL9300
1611 static int rtl9300_read_status(struct phy_device
*phydev
)
1613 struct device
*dev
= &phydev
->mdio
.dev
;
1614 int phy_addr
= phydev
->mdio
.addr
;
1615 struct device_node
*dn
;
1616 u32 sds_num
= 0, status
, latch_status
, mode
;
1621 if (of_property_read_u32(dn
, "sds", &sds_num
))
1623 pr_info("%s: Port %d, SerDes is %d\n", __func__
, phy_addr
, sds_num
);
1625 dev_err(dev
, "No DT node.\n");
1632 mode
= rtl9300_sds_mode_get(sds_num
);
1633 pr_info("%s got SDS mode %02x\n", __func__
, mode
);
1634 if (mode
== 0x1a) { /* 10GR mode */
1635 status
= rtl9300_sds_field_r(sds_num
, 0x5, 0, 12, 12);
1636 latch_status
= rtl9300_sds_field_r(sds_num
, 0x4, 1, 2, 2);
1637 status
|= rtl9300_sds_field_r(sds_num
, 0x5, 0, 12, 12);
1638 latch_status
|= rtl9300_sds_field_r(sds_num
, 0x4, 1, 2, 2);
1640 status
= rtl9300_sds_field_r(sds_num
, 0x1, 29, 8, 0);
1641 latch_status
= rtl9300_sds_field_r(sds_num
, 0x1, 30, 8, 0);
1642 status
|= rtl9300_sds_field_r(sds_num
, 0x1, 29, 8, 0);
1643 latch_status
|= rtl9300_sds_field_r(sds_num
, 0x1, 30, 8, 0);
1646 pr_info("%s link status: status: %d, latch %d\n", __func__
, status
, latch_status
);
1649 phydev
->link
= true;
1651 phydev
->speed
= SPEED_10000
;
1653 phydev
->speed
= SPEED_1000
;
1655 phydev
->duplex
= DUPLEX_FULL
;
1661 void rtl930x_sds_rx_rst(int sds_num
, phy_interface_t phy_if
)
1663 int page
= 0x2e; /* 10GR and USXGMII */
1665 if (phy_if
== PHY_INTERFACE_MODE_1000BASEX
)
1668 rtl9300_sds_field_w(sds_num
, page
, 0x15, 4, 4, 0x1);
1670 rtl9300_sds_field_w(sds_num
, page
, 0x15, 4, 4, 0x0);
1673 /* Force PHY modes on 10GBit Serdes
1675 void rtl9300_force_sds_mode(int sds
, phy_interface_t phy_if
)
1680 int lane_0
= (sds
% 2) ? sds
- 1 : sds
;
1683 pr_info("%s: SDS: %d, mode %d\n", __func__
, sds
, phy_if
);
1685 case PHY_INTERFACE_MODE_SGMII
:
1691 case PHY_INTERFACE_MODE_HSGMII
:
1697 case PHY_INTERFACE_MODE_1000BASEX
:
1702 case PHY_INTERFACE_MODE_2500BASEX
:
1708 case PHY_INTERFACE_MODE_10GBASER
:
1714 case PHY_INTERFACE_MODE_NA
:
1715 /* This will disable SerDes */
1720 pr_err("%s: unknown serdes mode: %s\n",
1721 __func__
, phy_modes(phy_if
));
1725 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__
, sds
, sds_mode
);
1726 /* Power down SerDes */
1727 rtl9300_sds_field_w(sds
, 0x20, 0, 7, 6, 0x3);
1728 if (sds
== 5) pr_info("%s after %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x20, 0));
1730 if (sds
== 5) pr_info("%s a %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x1f, 9));
1731 /* Force mode enable */
1732 rtl9300_sds_field_w(sds
, 0x1f, 9, 6, 6, 0x1);
1733 if (sds
== 5) pr_info("%s b %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x1f, 9));
1736 rtl9300_sds_field_w(sds
, 0x1f, 9, 11, 7, 0x1f);
1738 if (phy_if
== PHY_INTERFACE_MODE_NA
)
1741 if (sds
== 5) pr_info("%s c %x\n", __func__
, rtl930x_read_sds_phy(sds
, 0x20, 18));
1742 /* Enable LC and ring */
1743 rtl9300_sds_field_w(lane_0
, 0x20, 18, 3, 0, 0xf);
1746 rtl9300_sds_field_w(lane_0
, 0x20, 18, 5, 4, 0x1);
1748 rtl9300_sds_field_w(lane_0
, 0x20, 18, 7, 6, 0x1);
1750 rtl9300_sds_field_w(sds
, 0x20, 0, 5, 4, 0x3);
1753 rtl9300_sds_field_w(lane_0
, 0x20, 18, 11, 8, lc_value
);
1755 rtl9300_sds_field_w(lane_0
, 0x20, 18, 15, 12, lc_value
);
1757 /* Force analog LC & ring on */
1758 rtl9300_sds_field_w(lane_0
, 0x21, 11, 3, 0, 0xf);
1760 v
= lc_on
? 0x3 : 0x1;
1763 rtl9300_sds_field_w(lane_0
, 0x20, 18, 5, 4, v
);
1765 rtl9300_sds_field_w(lane_0
, 0x20, 18, 7, 6, v
);
1767 /* Force SerDes mode */
1768 rtl9300_sds_field_w(sds
, 0x1f, 9, 6, 6, 1);
1769 rtl9300_sds_field_w(sds
, 0x1f, 9, 11, 7, sds_mode
);
1771 /* Toggle LC or Ring */
1772 for (int i
= 0; i
< 20; i
++) {
1773 u32 cr_0
, cr_1
, cr_2
;
1778 rtl930x_write_sds_phy(lane_0
, 0x1f, 2, 53);
1780 m_bit
= (lane_0
== sds
) ? (4) : (5);
1781 l_bit
= (lane_0
== sds
) ? (4) : (5);
1783 cr_0
= rtl9300_sds_field_r(lane_0
, 0x1f, 20, m_bit
, l_bit
);
1785 cr_1
= rtl9300_sds_field_r(lane_0
, 0x1f, 20, m_bit
, l_bit
);
1787 cr_2
= rtl9300_sds_field_r(lane_0
, 0x1f, 20, m_bit
, l_bit
);
1789 if (cr_0
&& cr_1
&& cr_2
) {
1792 if (phy_if
!= PHY_INTERFACE_MODE_10GBASER
)
1795 t
= rtl9300_sds_field_r(sds
, 0x6, 0x1, 2, 2);
1796 rtl9300_sds_field_w(sds
, 0x6, 0x1, 2, 2, 0x1);
1799 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x1);
1801 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x0);
1804 /* Need to read this twice */
1805 v
= rtl9300_sds_field_r(sds
, 0x5, 0, 12, 12);
1806 v
= rtl9300_sds_field_r(sds
, 0x5, 0, 12, 12);
1808 rtl9300_sds_field_w(sds
, 0x6, 0x1, 2, 2, t
);
1810 /* Reset FSM again */
1811 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x1);
1813 rtl9300_sds_field_w(sds
, 0x6, 0x2, 12, 12, 0x0);
1820 m_bit
= (phy_if
== PHY_INTERFACE_MODE_10GBASER
) ? 3 : 1;
1821 l_bit
= (phy_if
== PHY_INTERFACE_MODE_10GBASER
) ? 2 : 0;
1823 rtl9300_sds_field_w(lane_0
, 0x21, 11, m_bit
, l_bit
, 0x2);
1825 rtl9300_sds_field_w(lane_0
, 0x21, 11, m_bit
, l_bit
, 0x3);
1828 rtl930x_sds_rx_rst(sds
, phy_if
);
1830 /* Re-enable power */
1831 rtl9300_sds_field_w(sds
, 0x20, 0, 7, 6, 0);
1833 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__
, sds
, sds_mode
);
1836 void rtl9300_sds_tx_config(int sds
, phy_interface_t phy_if
)
1838 /* parameters: rtl9303_80G_txParam_s2 */
1839 int impedance
= 0x8;
1848 case PHY_INTERFACE_MODE_1000BASEX
:
1851 case PHY_INTERFACE_MODE_HSGMII
:
1852 case PHY_INTERFACE_MODE_2500BASEX
:
1855 case PHY_INTERFACE_MODE_10GBASER
:
1859 pr_err("%s: unsupported PHY mode\n", __func__
);
1863 rtl9300_sds_field_w(sds
, page
, 0x01, 15, 11, pre_amp
);
1864 rtl9300_sds_field_w(sds
, page
, 0x06, 4, 0, post_amp
);
1865 rtl9300_sds_field_w(sds
, page
, 0x07, 0, 0, pre_en
);
1866 rtl9300_sds_field_w(sds
, page
, 0x07, 3, 3, post_en
);
1867 rtl9300_sds_field_w(sds
, page
, 0x07, 8, 4, main_amp
);
1868 rtl9300_sds_field_w(sds
, page
, 0x18, 15, 12, impedance
);
1871 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1874 int rtl9300_sds_clock_wait(int timeout
)
1877 unsigned long start
= jiffies
;
1880 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1881 v
= rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1884 } while (jiffies
< start
+ (HZ
/ 1000) * timeout
);
1889 void rtl9300_serdes_mac_link_config(int sds
, bool tx_normal
, bool rx_normal
)
1893 v10
= rtl930x_read_sds_phy(sds
, 6, 2); /* 10GBit, page 6, reg 2 */
1894 v1
= rtl930x_read_sds_phy(sds
, 0, 0); /* 1GBit, page 0, reg 0 */
1895 pr_info("%s: registers before %08x %08x\n", __func__
, v10
, v1
);
1897 v10
&= ~(BIT(13) | BIT(14));
1898 v1
&= ~(BIT(8) | BIT(9));
1900 v10
|= rx_normal
? 0 : BIT(13);
1901 v1
|= rx_normal
? 0 : BIT(9);
1903 v10
|= tx_normal
? 0 : BIT(14);
1904 v1
|= tx_normal
? 0 : BIT(8);
1906 rtl930x_write_sds_phy(sds
, 6, 2, v10
);
1907 rtl930x_write_sds_phy(sds
, 0, 0, v1
);
1909 v10
= rtl930x_read_sds_phy(sds
, 6, 2);
1910 v1
= rtl930x_read_sds_phy(sds
, 0, 0);
1911 pr_info("%s: registers after %08x %08x\n", __func__
, v10
, v1
);
1914 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num
, u32 dcvs_id
, bool manual
, u32 dvcs_list
[])
1919 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 14, 14, 0x1);
1920 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 5, 5, dvcs_list
[0]);
1921 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 4, 0, dvcs_list
[1]);
1924 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 13, 13, 0x1);
1925 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 15, 15, dvcs_list
[0]);
1926 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 14, 11, dvcs_list
[1]);
1929 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 12, 12, 0x1);
1930 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 10, 10, dvcs_list
[0]);
1931 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 9, 6, dvcs_list
[1]);
1934 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 11, 11, 0x1);
1935 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 5, 5, dvcs_list
[0]);
1936 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1d, 4, 1, dvcs_list
[1]);
1939 rtl9300_sds_field_w(sds_num
, 0x2e, 0x01, 15, 15, 0x1);
1940 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 10, 10, dvcs_list
[0]);
1941 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 9, 6, dvcs_list
[1]);
1944 rtl9300_sds_field_w(sds_num
, 0x2e, 0x02, 11, 11, 0x1);
1945 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 4, 4, dvcs_list
[0]);
1946 rtl9300_sds_field_w(sds_num
, 0x2e, 0x11, 3, 0, dvcs_list
[1]);
1954 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 14, 14, 0x0);
1957 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 13, 13, 0x0);
1960 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 12, 12, 0x0);
1963 rtl9300_sds_field_w(sds_num
, 0x2e, 0x1e, 11, 11, 0x0);
1966 rtl9300_sds_field_w(sds_num
, 0x2e, 0x01, 15, 15, 0x0);
1969 rtl9300_sds_field_w(sds_num
, 0x2e, 0x02, 11, 11, 0x0);
1978 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num
, u32 dcvs_id
, u32 dcvs_list
[])
1980 u32 dcvs_sign_out
= 0, dcvs_coef_bin
= 0;
1984 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
1986 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
1988 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
1989 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
1991 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
1992 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
1996 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x22);
1999 /* ##DCVS0 Read Out */
2000 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2001 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2002 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 14, 14);
2006 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x23);
2009 /* ##DCVS0 Read Out */
2010 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2011 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2012 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 13, 13);
2016 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x24);
2019 /* ##DCVS0 Read Out */
2020 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2021 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2022 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 12, 12);
2025 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x25);
2028 /* ##DCVS0 Read Out */
2029 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2030 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2031 dcvs_manual
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x1e, 11, 11);
2035 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x2c);
2038 /* ##DCVS0 Read Out */
2039 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2040 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2041 dcvs_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x01, 15, 15);
2045 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0x2d);
2048 /* ##DCVS0 Read Out */
2049 dcvs_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 4);
2050 dcvs_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 3, 0);
2051 dcvs_manual
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x02, 11, 11);
2059 pr_info("%s DCVS %u Sign: -", __func__
, dcvs_id
);
2061 pr_info("%s DCVS %u Sign: +", __func__
, dcvs_id
);
2063 pr_info("DCVS %u even coefficient = %u", dcvs_id
, dcvs_coef_bin
);
2064 pr_info("DCVS %u manual = %u", dcvs_id
, dcvs_manual
);
2066 dcvs_list
[0] = dcvs_sign_out
;
2067 dcvs_list
[1] = dcvs_coef_bin
;
2070 void rtl9300_sds_rxcal_leq_manual(u32 sds_num
, bool manual
, u32 leq_gray
)
2073 rtl9300_sds_field_w(sds_num
, 0x2e, 0x18, 15, 15, 0x1);
2074 rtl9300_sds_field_w(sds_num
, 0x2e, 0x16, 14, 10, leq_gray
);
2076 rtl9300_sds_field_w(sds_num
, 0x2e, 0x18, 15, 15, 0x0);
2081 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num
, bool manual
, u32 offset
)
2084 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 6, 2, offset
);
2086 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 6, 2, offset
);
2092 u32
rtl9300_sds_rxcal_gray_to_binary(u32 gray_code
)
2099 for(i
= 0; i
< GRAY_BITS
; i
++)
2100 g
[i
] = (gray_code
& BIT(i
)) >> i
;
2106 for(i
= 0; i
< m
; i
++) {
2108 for(j
= i
+ 1; j
< GRAY_BITS
; j
++)
2112 for(i
= 0; i
< GRAY_BITS
; i
++)
2113 leq_binary
+= c
[i
] << i
;
2118 u32
rtl9300_sds_rxcal_leq_read(int sds_num
)
2120 u32 leq_gray
, leq_bin
;
2124 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2126 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2128 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2129 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2131 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2132 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x10);
2135 /* ##LEQ Read Out */
2136 leq_gray
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 7, 3);
2137 leq_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x18, 15, 15);
2138 leq_bin
= rtl9300_sds_rxcal_gray_to_binary(leq_gray
);
2140 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray
, leq_bin
);
2141 pr_info("LEQ manual: %u", leq_manual
);
2146 void rtl9300_sds_rxcal_vth_manual(u32 sds_num
, bool manual
, u32 vth_list
[])
2149 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, 13, 13, 0x1);
2150 rtl9300_sds_field_w(sds_num
, 0x2e, 0x13, 5, 3, vth_list
[0]);
2151 rtl9300_sds_field_w(sds_num
, 0x2e, 0x13, 2, 0, vth_list
[1]);
2153 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, 13, 13, 0x0);
2158 void rtl9300_sds_rxcal_vth_get(u32 sds_num
, u32 vth_list
[])
2162 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2163 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2165 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2167 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2169 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2170 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2171 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2172 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2173 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2174 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0xc);
2178 /* ##VthP & VthN Read Out */
2179 vth_list
[0] = rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2180 vth_list
[1] = rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2182 pr_info("vth_set_bin = %d", vth_list
[0]);
2183 pr_info("vth_set_bin = %d", vth_list
[1]);
2185 vth_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x0f, 13, 13);
2186 pr_info("Vth Maunal = %d", vth_manual
);
2189 void rtl9300_sds_rxcal_tap_manual(u32 sds_num
, int tap_id
, bool manual
, u32 tap_list
[])
2194 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2195 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2196 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 5, 5, tap_list
[0]);
2197 rtl9300_sds_field_w(sds_num
, 0x2f, 0x03, 4, 0, tap_list
[1]);
2200 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2201 rtl9300_sds_field_w(sds_num
, 0x21, 0x07, 6, 6, tap_list
[0]);
2202 rtl9300_sds_field_w(sds_num
, 0x2e, 0x09, 11, 6, tap_list
[1]);
2203 rtl9300_sds_field_w(sds_num
, 0x21, 0x07, 5, 5, tap_list
[2]);
2204 rtl9300_sds_field_w(sds_num
, 0x2f, 0x12, 5, 0, tap_list
[3]);
2207 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2208 rtl9300_sds_field_w(sds_num
, 0x2e, 0x09, 5, 5, tap_list
[0]);
2209 rtl9300_sds_field_w(sds_num
, 0x2e, 0x09, 4, 0, tap_list
[1]);
2210 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 11, 11, tap_list
[2]);
2211 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 10, 6, tap_list
[3]);
2214 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2215 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 5, 5, tap_list
[0]);
2216 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0a, 4, 0, tap_list
[1]);
2217 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 5, 5, tap_list
[2]);
2218 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 4, 0, tap_list
[3]);
2221 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x1);
2222 rtl9300_sds_field_w(sds_num
, 0x2f, 0x01, 5, 5, tap_list
[0]);
2223 rtl9300_sds_field_w(sds_num
, 0x2f, 0x01, 4, 0, tap_list
[1]);
2224 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 11, 11, tap_list
[2]);
2225 rtl9300_sds_field_w(sds_num
, 0x2e, 0x06, 10, 6, tap_list
[3]);
2231 rtl9300_sds_field_w(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7, 0x0);
2236 void rtl9300_sds_rxcal_tap_get(u32 sds_num
, u32 tap_id
, u32 tap_list
[])
2240 u32 tap_sign_out_even
;
2241 u32 tap_coef_bin_even
;
2242 u32 tap_sign_out_odd
;
2243 u32 tap_coef_bin_odd
;
2247 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2249 rtl930x_write_sds_phy(sds_num
- 1, 0x1f, 0x2, 0x31);
2251 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2252 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2253 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2254 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2257 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2258 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0);
2259 /* ##Tap1 Even Read Out */
2261 tap0_sign_out
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 5);
2262 tap0_coef_bin
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 0);
2264 if (tap0_sign_out
== 1)
2265 pr_info("Tap0 Sign : -");
2267 pr_info("Tap0 Sign : +");
2269 pr_info("tap0_coef_bin = %d", tap0_coef_bin
);
2271 tap_list
[0] = tap0_sign_out
;
2272 tap_list
[1] = tap0_coef_bin
;
2274 tap_manual
= !!rtl9300_sds_field_r(sds_num
, 0x2e, 0x0f, 7, 7);
2275 pr_info("tap0 manual = %u",tap_manual
);
2277 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2278 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, tap_id
);
2280 /* ##Tap1 Even Read Out */
2281 tap_sign_out_even
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 5);
2282 tap_coef_bin_even
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 0);
2284 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2285 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, (tap_id
+ 5));
2286 /* ##Tap1 Odd Read Out */
2287 tap_sign_out_odd
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 5);
2288 tap_coef_bin_odd
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 4, 0);
2290 if (tap_sign_out_even
== 1)
2291 pr_info("Tap %u even sign: -", tap_id
);
2293 pr_info("Tap %u even sign: +", tap_id
);
2295 pr_info("Tap %u even coefficient = %u", tap_id
, tap_coef_bin_even
);
2297 if (tap_sign_out_odd
== 1)
2298 pr_info("Tap %u odd sign: -", tap_id
);
2300 pr_info("Tap %u odd sign: +", tap_id
);
2302 pr_info("Tap %u odd coefficient = %u", tap_id
,tap_coef_bin_odd
);
2304 tap_list
[0] = tap_sign_out_even
;
2305 tap_list
[1] = tap_coef_bin_even
;
2306 tap_list
[2] = tap_sign_out_odd
;
2307 tap_list
[3] = tap_coef_bin_odd
;
2309 tap_manual
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x0f, tap_id
+ 7, tap_id
+ 7);
2310 pr_info("tap %u manual = %d",tap_id
, tap_manual
);
2314 void rtl9300_do_rx_calibration_1(int sds
, phy_interface_t phy_mode
)
2316 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2317 int tap0_init_val
= 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2320 pr_info("start_1.1.1 initial value for sds %d\n", sds
);
2321 rtl930x_write_sds_phy(sds
, 6, 0, 0);
2324 rtl9300_sds_field_w(sds
, 0x2e, 0x01, 14, 14, 0x00);
2325 rtl9300_sds_field_w(sds
, 0x2e, 0x1c, 10, 5, 0x20);
2326 rtl9300_sds_field_w(sds
, 0x2f, 0x02, 0, 0, 0x01);
2329 rtl9300_sds_field_w(sds
, 0x2e, 0x1e, 14, 11, 0x00);
2330 rtl9300_sds_field_w(sds
, 0x2e, 0x01, 15, 15, 0x00);
2331 rtl9300_sds_field_w(sds
, 0x2e, 0x02, 11, 11, 0x00);
2332 rtl9300_sds_field_w(sds
, 0x2e, 0x1c, 4, 0, 0x00);
2333 rtl9300_sds_field_w(sds
, 0x2e, 0x1d, 15, 11, 0x00);
2334 rtl9300_sds_field_w(sds
, 0x2e, 0x1d, 10, 6, 0x00);
2335 rtl9300_sds_field_w(sds
, 0x2e, 0x1d, 5, 1, 0x00);
2336 rtl9300_sds_field_w(sds
, 0x2e, 0x02, 10, 6, 0x00);
2337 rtl9300_sds_field_w(sds
, 0x2e, 0x11, 4, 0, 0x00);
2338 rtl9300_sds_field_w(sds
, 0x2f, 0x00, 3, 0, 0x0f);
2339 rtl9300_sds_field_w(sds
, 0x2e, 0x04, 6, 6, 0x01);
2340 rtl9300_sds_field_w(sds
, 0x2e, 0x04, 7, 7, 0x01);
2342 /* LEQ (Long Term Equivalent signal level) */
2343 rtl9300_sds_field_w(sds
, 0x2e, 0x16, 14, 8, 0x00);
2345 /* DFE (Decision Fed Equalizer) */
2346 rtl9300_sds_field_w(sds
, 0x2f, 0x03, 5, 0, tap0_init_val
);
2347 rtl9300_sds_field_w(sds
, 0x2e, 0x09, 11, 6, 0x00);
2348 rtl9300_sds_field_w(sds
, 0x2e, 0x09, 5, 0, 0x00);
2349 rtl9300_sds_field_w(sds
, 0x2e, 0x0a, 5, 0, 0x00);
2350 rtl9300_sds_field_w(sds
, 0x2f, 0x01, 5, 0, 0x00);
2351 rtl9300_sds_field_w(sds
, 0x2f, 0x12, 5, 0, 0x00);
2352 rtl9300_sds_field_w(sds
, 0x2e, 0x0a, 11, 6, 0x00);
2353 rtl9300_sds_field_w(sds
, 0x2e, 0x06, 5, 0, 0x00);
2354 rtl9300_sds_field_w(sds
, 0x2f, 0x01, 5, 0, 0x00);
2357 rtl9300_sds_field_w(sds
, 0x2e, 0x13, 5, 3, 0x07);
2358 rtl9300_sds_field_w(sds
, 0x2e, 0x13, 2, 0, 0x07);
2359 rtl9300_sds_field_w(sds
, 0x2f, 0x0b, 5, 3, vth_min
);
2361 pr_info("end_1.1.1 --\n");
2363 pr_info("start_1.1.2 Load DFE init. value\n");
2365 rtl9300_sds_field_w(sds
, 0x2e, 0x0f, 13, 7, 0x7f);
2367 pr_info("end_1.1.2\n");
2369 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2371 rtl9300_sds_field_w(sds
, 0x2e, 0x17, 7, 7, 0x00);
2372 rtl9300_sds_field_w(sds
, 0x2e, 0x17, 6, 2, 0x00);
2373 rtl9300_sds_field_w(sds
, 0x2e, 0x0c, 8, 8, 0x00);
2374 rtl9300_sds_field_w(sds
, 0x2e, 0x0b, 4, 4, 0x01);
2375 rtl9300_sds_field_w(sds
, 0x2e, 0x12, 14, 14, 0x00);
2376 rtl9300_sds_field_w(sds
, 0x2f, 0x02, 15, 15, 0x00);
2378 pr_info("end_1.1.3 --\n");
2380 pr_info("start_1.1.4 offset cali setting\n");
2382 rtl9300_sds_field_w(sds
, 0x2e, 0x0f, 15, 14, 0x03);
2384 pr_info("end_1.1.4\n");
2386 pr_info("start_1.1.5 LEQ and DFE setting\n");
2388 /* TODO: make this work for DAC cables of different lengths */
2389 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2390 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| PHY_INTERFACE_MODE_1000BASEX
)
2391 rtl9300_sds_field_w(sds
, 0x2e, 0x16, 3, 2, 0x02);
2393 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__
);
2395 /* No serdes, check for Aquantia PHYs */
2396 rtl9300_sds_field_w(sds
, 0x2e, 0x16, 3, 2, 0x02);
2398 rtl9300_sds_field_w(sds
, 0x2e, 0x0f, 6, 0, 0x5f);
2399 rtl9300_sds_field_w(sds
, 0x2f, 0x05, 7, 2, 0x1f);
2400 rtl9300_sds_field_w(sds
, 0x2e, 0x19, 9, 5, 0x1f);
2401 rtl9300_sds_field_w(sds
, 0x2f, 0x0b, 15, 9, 0x3c);
2402 rtl9300_sds_field_w(sds
, 0x2e, 0x0b, 1, 0, 0x03);
2404 pr_info("end_1.1.5\n");
2407 void rtl9300_do_rx_calibration_2_1(u32 sds_num
)
2409 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2411 /* Gray config endis to 1 */
2412 rtl9300_sds_field_w(sds_num
, 0x2f, 0x02, 2, 2, 0x01);
2414 /* ForegroundOffsetCal_Manual(auto mode) */
2415 rtl9300_sds_field_w(sds_num
, 0x2e, 0x01, 14, 14, 0x00);
2417 pr_info("end_1.2.1");
2420 void rtl9300_do_rx_calibration_2_2(int sds_num
)
2422 /* Force Rx-Run = 0 */
2423 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 8, 8, 0x0);
2425 rtl930x_sds_rx_rst(sds_num
, PHY_INTERFACE_MODE_10GBASER
);
2428 void rtl9300_do_rx_calibration_2_3(int sds_num
)
2430 u32 fgcal_binary
, fgcal_gray
;
2433 pr_info("start_1.2.3 Foreground Calibration\n");
2437 rtl930x_write_sds_phy(sds_num
, 0x1f, 0x2, 0x2f);
2439 rtl930x_write_sds_phy(sds_num
-1 , 0x1f, 0x2, 0x31);
2441 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2442 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 9, 9, 0x1);
2443 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2444 rtl9300_sds_field_w(sds_num
, 0x21, 0x06, 11, 6, 0x20);
2445 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2446 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0xf);
2447 /* ##FGCAL read gray */
2448 fgcal_gray
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 0);
2449 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2450 rtl9300_sds_field_w(sds_num
, 0x2f, 0x0c, 5, 0, 0xe);
2451 /* ##FGCAL read binary */
2452 fgcal_binary
= rtl9300_sds_field_r(sds_num
, 0x1f, 0x14, 5, 0);
2454 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2455 __func__
, fgcal_gray
, fgcal_binary
);
2457 offset_range
= rtl9300_sds_field_r(sds_num
, 0x2e, 0x15, 15, 14);
2459 if (fgcal_binary
> 60 || fgcal_binary
< 3) {
2460 if (offset_range
== 3) {
2461 pr_info("%s: Foreground Calibration result marginal!", __func__
);
2465 rtl9300_sds_field_w(sds_num
, 0x2e, 0x15, 15, 14, offset_range
);
2466 rtl9300_do_rx_calibration_2_2(sds_num
);
2472 pr_info("%s: end_1.2.3\n", __func__
);
2475 void rtl9300_do_rx_calibration_2(int sds
)
2477 rtl930x_sds_rx_rst(sds
, PHY_INTERFACE_MODE_10GBASER
);
2478 rtl9300_do_rx_calibration_2_1(sds
);
2479 rtl9300_do_rx_calibration_2_2(sds
);
2480 rtl9300_do_rx_calibration_2_3(sds
);
2483 void rtl9300_sds_rxcal_3_1(int sds_num
, phy_interface_t phy_mode
)
2485 pr_info("start_1.3.1");
2488 if (phy_mode
!= PHY_INTERFACE_MODE_10GBASER
&& phy_mode
!= PHY_INTERFACE_MODE_1000BASEX
)
2489 rtl9300_sds_field_w(sds_num
, 0x2e, 0xc, 8, 8, 0);
2491 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, 0x0);
2492 rtl9300_sds_rxcal_leq_manual(sds_num
, false, 0);
2494 pr_info("end_1.3.1");
2497 void rtl9300_sds_rxcal_3_2(int sds_num
, phy_interface_t phy_mode
)
2499 u32 sum10
= 0, avg10
, int10
;
2500 int dac_long_cable_offset
;
2501 bool eq_hold_enabled
;
2504 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| phy_mode
== PHY_INTERFACE_MODE_1000BASEX
) {
2505 /* rtl9300_rxCaliConf_serdes_myParam */
2506 dac_long_cable_offset
= 3;
2507 eq_hold_enabled
= true;
2509 /* rtl9300_rxCaliConf_phy_myParam */
2510 dac_long_cable_offset
= 0;
2511 eq_hold_enabled
= false;
2514 if (phy_mode
== PHY_INTERFACE_MODE_1000BASEX
)
2515 pr_warn("%s: LEQ only valid for 10GR!\n", __func__
);
2517 pr_info("start_1.3.2");
2519 for(i
= 0; i
< 10; i
++) {
2520 sum10
+= rtl9300_sds_rxcal_leq_read(sds_num
);
2524 avg10
= (sum10
/ 10) + (((sum10
% 10) >= 5) ? 1 : 0);
2527 pr_info("sum10:%u, avg10:%u, int10:%u", sum10
, avg10
, int10
);
2529 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| phy_mode
== PHY_INTERFACE_MODE_1000BASEX
) {
2530 if (dac_long_cable_offset
) {
2531 rtl9300_sds_rxcal_leq_offset_manual(sds_num
, 1, dac_long_cable_offset
);
2532 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, eq_hold_enabled
);
2533 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
)
2534 rtl9300_sds_rxcal_leq_manual(sds_num
, true, avg10
);
2537 rtl9300_sds_rxcal_leq_offset_manual(sds_num
, 1, 3);
2538 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, 0x1);
2539 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
)
2540 rtl9300_sds_rxcal_leq_manual(sds_num
, true, avg10
);
2542 rtl9300_sds_rxcal_leq_offset_manual(sds_num
, 1, 0);
2543 rtl9300_sds_field_w(sds_num
, 0x2e, 0x17, 7, 7, 0x1);
2544 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
)
2545 rtl9300_sds_rxcal_leq_manual(sds_num
, true, avg10
);
2550 pr_info("Sds:%u LEQ = %u",sds_num
, rtl9300_sds_rxcal_leq_read(sds_num
));
2552 pr_info("end_1.3.2");
2555 void rtl9300_do_rx_calibration_3(int sds_num
, phy_interface_t phy_mode
)
2557 rtl9300_sds_rxcal_3_1(sds_num
, phy_mode
);
2559 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
|| phy_mode
== PHY_INTERFACE_MODE_1000BASEX
)
2560 rtl9300_sds_rxcal_3_2(sds_num
, phy_mode
);
2563 void rtl9300_do_rx_calibration_4_1(int sds_num
)
2565 u32 vth_list
[2] = {0, 0};
2566 u32 tap0_list
[4] = {0, 0, 0, 0};
2568 pr_info("start_1.4.1");
2571 rtl9300_sds_rxcal_vth_manual(sds_num
, false, vth_list
);
2572 rtl9300_sds_rxcal_tap_manual(sds_num
, 0, false, tap0_list
);
2575 pr_info("end_1.4.1");
2578 void rtl9300_do_rx_calibration_4_2(u32 sds_num
)
2583 pr_info("start_1.4.2");
2585 rtl9300_sds_rxcal_vth_get(sds_num
, vth_list
);
2586 rtl9300_sds_rxcal_vth_manual(sds_num
, true, vth_list
);
2590 rtl9300_sds_rxcal_tap_get(sds_num
, 0, tap_list
);
2591 rtl9300_sds_rxcal_tap_manual(sds_num
, 0, true, tap_list
);
2593 pr_info("end_1.4.2");
2596 void rtl9300_do_rx_calibration_4(u32 sds_num
)
2598 rtl9300_do_rx_calibration_4_1(sds_num
);
2599 rtl9300_do_rx_calibration_4_2(sds_num
);
2602 void rtl9300_do_rx_calibration_5_2(u32 sds_num
)
2604 u32 tap1_list
[4] = {0};
2605 u32 tap2_list
[4] = {0};
2606 u32 tap3_list
[4] = {0};
2607 u32 tap4_list
[4] = {0};
2609 pr_info("start_1.5.2");
2611 rtl9300_sds_rxcal_tap_manual(sds_num
, 1, false, tap1_list
);
2612 rtl9300_sds_rxcal_tap_manual(sds_num
, 2, false, tap2_list
);
2613 rtl9300_sds_rxcal_tap_manual(sds_num
, 3, false, tap3_list
);
2614 rtl9300_sds_rxcal_tap_manual(sds_num
, 4, false, tap4_list
);
2618 pr_info("end_1.5.2");
2621 void rtl9300_do_rx_calibration_5(u32 sds_num
, phy_interface_t phy_mode
)
2623 if (phy_mode
== PHY_INTERFACE_MODE_10GBASER
) /* dfeTap1_4Enable true */
2624 rtl9300_do_rx_calibration_5_2(sds_num
);
2628 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num
)
2630 u32 tap1_list
[4] = {0};
2631 u32 tap2_list
[4] = {0};
2632 u32 tap3_list
[4] = {0};
2633 u32 tap4_list
[4] = {0};
2635 rtl9300_sds_rxcal_tap_manual(sds_num
, 1, true, tap1_list
);
2636 rtl9300_sds_rxcal_tap_manual(sds_num
, 2, true, tap2_list
);
2637 rtl9300_sds_rxcal_tap_manual(sds_num
, 3, true, tap3_list
);
2638 rtl9300_sds_rxcal_tap_manual(sds_num
, 4, true, tap4_list
);
2643 void rtl9300_do_rx_calibration(int sds
, phy_interface_t phy_mode
)
2647 rtl9300_do_rx_calibration_1(sds
, phy_mode
);
2648 rtl9300_do_rx_calibration_2(sds
);
2649 rtl9300_do_rx_calibration_4(sds
);
2650 rtl9300_do_rx_calibration_5(sds
, phy_mode
);
2653 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2654 if (rtl9300_sds_field_r(sds
, 0x1f, 9, 11, 7) == 0x1a) {
2655 pr_info("%s: SDS enabled\n", __func__
);
2656 latch_sts
= rtl9300_sds_field_r(sds
, 0x4, 1, 2, 2);
2658 latch_sts
= rtl9300_sds_field_r(sds
, 0x4, 1, 2, 2);
2660 rtl9300_do_rx_calibration_dfe_disable(sds
);
2661 rtl9300_do_rx_calibration_4(sds
);
2662 rtl9300_do_rx_calibration_5(sds
, phy_mode
);
2667 int rtl9300_sds_sym_err_reset(int sds_num
, phy_interface_t phy_mode
)
2670 case PHY_INTERFACE_MODE_XGMII
:
2673 case PHY_INTERFACE_MODE_10GBASER
:
2674 /* Read twice to clear */
2675 rtl930x_read_sds_phy(sds_num
, 5, 1);
2676 rtl930x_read_sds_phy(sds_num
, 5, 1);
2679 case PHY_INTERFACE_MODE_1000BASEX
:
2680 rtl9300_sds_field_w(sds_num
, 0x1, 24, 2, 0, 0);
2681 rtl9300_sds_field_w(sds_num
, 0x1, 3, 15, 8, 0);
2682 rtl9300_sds_field_w(sds_num
, 0x1, 2, 15, 0, 0);
2686 pr_info("%s unsupported phy mode\n", __func__
);
2693 u32
rtl9300_sds_sym_err_get(int sds_num
, phy_interface_t phy_mode
)
2698 case PHY_INTERFACE_MODE_XGMII
:
2701 case PHY_INTERFACE_MODE_10GBASER
:
2702 v
= rtl930x_read_sds_phy(sds_num
, 5, 1);
2706 pr_info("%s unsupported PHY-mode\n", __func__
);
2712 int rtl9300_sds_check_calibration(int sds_num
, phy_interface_t phy_mode
)
2714 u32 errors1
, errors2
;
2716 rtl9300_sds_sym_err_reset(sds_num
, phy_mode
);
2717 rtl9300_sds_sym_err_reset(sds_num
, phy_mode
);
2719 /* Count errors during 1ms */
2720 errors1
= rtl9300_sds_sym_err_get(sds_num
, phy_mode
);
2722 errors2
= rtl9300_sds_sym_err_get(sds_num
, phy_mode
);
2725 case PHY_INTERFACE_MODE_XGMII
:
2727 if ((errors2
- errors1
> 100) ||
2728 (errors1
>= 0xffff00) || (errors2
>= 0xffff00)) {
2729 pr_info("%s XSGMII error rate too high\n", __func__
);
2733 case PHY_INTERFACE_MODE_10GBASER
:
2735 pr_info("%s 10GBASER error rate too high\n", __func__
);
2746 void rtl9300_phy_enable_10g_1g(int sds_num
)
2750 /* Enable 1GBit PHY */
2751 v
= rtl930x_read_sds_phy(sds_num
, PHY_PAGE_2
, MII_BMCR
);
2752 pr_info("%s 1gbit phy: %08x\n", __func__
, v
);
2754 rtl930x_write_sds_phy(sds_num
, PHY_PAGE_2
, MII_BMCR
, v
);
2755 pr_info("%s 1gbit phy enabled: %08x\n", __func__
, v
);
2757 /* Enable 10GBit PHY */
2758 v
= rtl930x_read_sds_phy(sds_num
, PHY_PAGE_4
, MII_BMCR
);
2759 pr_info("%s 10gbit phy: %08x\n", __func__
, v
);
2761 rtl930x_write_sds_phy(sds_num
, PHY_PAGE_4
, MII_BMCR
, v
);
2762 pr_info("%s 10gbit phy after: %08x\n", __func__
, v
);
2764 /* dal_longan_construct_mac_default_10gmedia_fiber */
2765 v
= rtl930x_read_sds_phy(sds_num
, 0x1f, 11);
2766 pr_info("%s set medium: %08x\n", __func__
, v
);
2768 rtl930x_write_sds_phy(sds_num
, 0x1f, 11, v
);
2769 pr_info("%s set medium after: %08x\n", __func__
, v
);
2772 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2773 /* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */
2774 int rtl9300_serdes_setup(int sds_num
, phy_interface_t phy_mode
)
2777 int calib_tries
= 0;
2780 case PHY_INTERFACE_MODE_HSGMII
:
2783 case PHY_INTERFACE_MODE_1000BASEX
:
2786 case PHY_INTERFACE_MODE_XGMII
:
2789 case PHY_INTERFACE_MODE_10GBASER
:
2792 case PHY_INTERFACE_MODE_USXGMII
:
2796 pr_err("%s: unknown serdes mode: %s\n", __func__
, phy_modes(phy_mode
));
2800 /* Maybe use dal_longan_sds_init */
2802 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2803 rtl9300_phy_enable_10g_1g(sds_num
);
2805 /* Set Serdes Mode */
2806 rtl9300_sds_set(sds_num
, 0x1a); /* 0x1b: RTK_MII_10GR1000BX_AUTO */
2808 /* Do RX calibration */
2810 rtl9300_do_rx_calibration(sds_num
, phy_mode
);
2813 } while (rtl9300_sds_check_calibration(sds_num
, phy_mode
) && calib_tries
< 3);
2825 sds_config rtl9300_a_sds_10gr_lane0
[] =
2828 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2829 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2830 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2831 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2832 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2833 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2834 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2835 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2836 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2837 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2838 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2839 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2840 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2841 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2842 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2843 {0x2F, 0x1D, 0x66E1},
2845 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2846 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2847 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2848 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2849 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2850 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2851 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2852 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2854 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2855 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2856 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2857 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2858 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2859 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2860 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2861 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2862 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2863 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2864 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2865 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2866 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2867 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2868 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2869 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2870 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2873 sds_config rtl9300_a_sds_10gr_lane1
[] =
2876 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2877 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2878 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2879 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2880 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2881 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2882 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2883 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2884 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2885 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2886 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2887 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2888 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2889 {0x2D, 0x14, 0x1808},
2891 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2892 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2893 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2894 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2895 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2896 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2897 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2898 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2900 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2901 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2902 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2903 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2904 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2905 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2906 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2907 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2908 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2909 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2910 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2911 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2912 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2913 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2916 int rtl9300_sds_cmu_band_get(int sds
)
2922 /* page = rtl9300_sds_cmu_page_get(sds); */
2923 page
= 0x25; /* 10GR and 1000BX */
2924 sds
= (sds
% 2) ? (sds
- 1) : (sds
);
2926 rtl9300_sds_field_w(sds
, page
, 0x1c, 15, 15, 1);
2927 rtl9300_sds_field_w(sds
+ 1, page
, 0x1c, 15, 15, 1);
2929 en
= rtl9300_sds_field_r(sds
, page
, 27, 1, 1);
2930 if(!en
) { /* Auto mode */
2931 rtl930x_write_sds_phy(sds
, 0x1f, 0x02, 31);
2933 cmu_band
= rtl9300_sds_field_r(sds
, 0x1f, 0x15, 5, 1);
2935 cmu_band
= rtl9300_sds_field_r(sds
, page
, 30, 4, 0);
2941 int rtl9300_configure_serdes(struct phy_device
*phydev
)
2943 int phy_mode
= PHY_INTERFACE_MODE_10GBASER
;
2944 struct device
*dev
= &phydev
->mdio
.dev
;
2945 int calib_tries
= 0;
2950 struct device_node
*dn
= dev
->of_node
;
2951 int phy_addr
= phydev
->mdio
.addr
;
2953 if (of_property_read_u32(dn
, "sds", &sds_num
))
2955 pr_info("%s: Port %d, SerDes is %d\n", __func__
, phy_addr
, sds_num
);
2957 dev_err(dev
, "No DT node.\n");
2964 if (phy_mode
!= PHY_INTERFACE_MODE_10GBASER
) /* TODO: for now we only patch 10GR SerDes */
2968 case PHY_INTERFACE_MODE_HSGMII
:
2971 case PHY_INTERFACE_MODE_1000BASEX
:
2974 case PHY_INTERFACE_MODE_XGMII
:
2977 case PHY_INTERFACE_MODE_10GBASER
:
2980 case PHY_INTERFACE_MODE_USXGMII
:
2984 pr_err("%s: unknown serdes mode: %s\n", __func__
, phy_modes(phy_mode
));
2988 pr_info("%s CMU BAND is %d\n", __func__
, rtl9300_sds_cmu_band_get(sds_num
));
2990 /* Turn Off Serdes */
2991 rtl9300_sds_rst(sds_num
, 0x1f);
2993 pr_info("%s PATCHING SerDes %d\n", __func__
, sds_num
);
2995 for (int i
= 0; i
< sizeof(rtl9300_a_sds_10gr_lane1
) / sizeof(sds_config
); ++i
) {
2996 rtl930x_write_sds_phy(sds_num
, rtl9300_a_sds_10gr_lane1
[i
].page
,
2997 rtl9300_a_sds_10gr_lane1
[i
].reg
,
2998 rtl9300_a_sds_10gr_lane1
[i
].data
);
3001 for (int i
= 0; i
< sizeof(rtl9300_a_sds_10gr_lane0
) / sizeof(sds_config
); ++i
) {
3002 rtl930x_write_sds_phy(sds_num
, rtl9300_a_sds_10gr_lane0
[i
].page
,
3003 rtl9300_a_sds_10gr_lane0
[i
].reg
,
3004 rtl9300_a_sds_10gr_lane0
[i
].data
);
3008 rtl9300_phy_enable_10g_1g(sds_num
);
3011 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL
);
3014 /* ----> dal_longan_sds_mode_set */
3015 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__
, sds_num
, sds_mode
);
3017 /* Configure link to MAC */
3018 rtl9300_serdes_mac_link_config(sds_num
, true, true); /* MAC Construct */
3021 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL
);
3024 rtl9300_force_sds_mode(sds_num
, PHY_INTERFACE_MODE_NA
);
3027 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL
);
3029 rtl9300_force_sds_mode(sds_num
, phy_mode
);
3031 /* Do RX calibration */
3033 rtl9300_do_rx_calibration(sds_num
, phy_mode
);
3036 } while (rtl9300_sds_check_calibration(sds_num
, phy_mode
) && calib_tries
< 3);
3038 if (calib_tries
>= 3)
3039 pr_err("%s CALIBTRATION FAILED\n", __func__
);
3041 rtl9300_sds_tx_config(sds_num
, phy_mode
);
3043 /* The clock needs only to be configured on the FPGA implementation */
3048 void rtl9310_sds_field_w(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
, u32 v
)
3050 int l
= end_bit
- start_bit
+ 1;
3054 u32 mask
= BIT(l
) - 1;
3056 data
= rtl930x_read_sds_phy(sds
, page
, reg
);
3057 data
&= ~(mask
<< start_bit
);
3058 data
|= (v
& mask
) << start_bit
;
3061 rtl931x_write_sds_phy(sds
, page
, reg
, data
);
3064 u32
rtl9310_sds_field_r(int sds
, u32 page
, u32 reg
, int end_bit
, int start_bit
)
3066 int l
= end_bit
- start_bit
+ 1;
3067 u32 v
= rtl931x_read_sds_phy(sds
, page
, reg
);
3072 return (v
>> start_bit
) & (BIT(l
) - 1);
3075 static void rtl931x_sds_rst(u32 sds
)
3078 int shift
= ((sds
& 0x3) << 3);
3080 /* TODO: We need to lock this! */
3082 o
= sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3084 sw_w32(v
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3086 o_mode
= sw_r32(RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3088 sw_w32_mask(0xff << shift
, v
<< shift
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3089 sw_w32(o_mode
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3091 sw_w32(o
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3094 static void rtl931x_symerr_clear(u32 sds
, phy_interface_t mode
)
3098 case PHY_INTERFACE_MODE_NA
:
3100 case PHY_INTERFACE_MODE_XGMII
:
3101 u32 xsg_sdsid_0
, xsg_sdsid_1
;
3106 xsg_sdsid_0
= (sds
- 1) * 2;
3107 xsg_sdsid_1
= xsg_sdsid_0
+ 1;
3109 for (int i
= 0; i
< 4; ++i
) {
3110 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 24, 2, 0, i
);
3111 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 3, 15, 8, 0x0);
3112 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 2, 15, 0, 0x0);
3115 for (int i
= 0; i
< 4; ++i
) {
3116 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 24, 2, 0, i
);
3117 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 3, 15, 8, 0x0);
3118 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 2, 15, 0, 0x0);
3121 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 0, 15, 0, 0x0);
3122 rtl9310_sds_field_w(xsg_sdsid_0
, 0x1, 1, 15, 8, 0x0);
3123 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 0, 15, 0, 0x0);
3124 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 1, 15, 8, 0x0);
3133 static u32
rtl931x_get_analog_sds(u32 sds
)
3135 u32 sds_map
[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3138 return sds_map
[sds
];
3143 void rtl931x_sds_fiber_disable(u32 sds
)
3146 u32 asds
= rtl931x_get_analog_sds(sds
);
3148 rtl9310_sds_field_w(asds
, 0x1F, 0x9, 11, 6, v
);
3151 static void rtl931x_sds_fiber_mode_set(u32 sds
, phy_interface_t mode
)
3153 u32 val
, asds
= rtl931x_get_analog_sds(sds
);
3155 /* clear symbol error count before changing mode */
3156 rtl931x_symerr_clear(sds
, mode
);
3159 sw_w32(val
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3162 case PHY_INTERFACE_MODE_SGMII
:
3166 case PHY_INTERFACE_MODE_1000BASEX
:
3167 /* serdes mode FIBER1G */
3171 case PHY_INTERFACE_MODE_10GBASER
:
3172 case PHY_INTERFACE_MODE_10GKR
:
3175 /* case MII_10GR1000BX_AUTO:
3180 case PHY_INTERFACE_MODE_USXGMII
:
3187 pr_info("%s writing analog SerDes Mode value %02x\n", __func__
, val
);
3188 rtl9310_sds_field_w(asds
, 0x1F, 0x9, 11, 6, val
);
3193 static int rtl931x_sds_cmu_page_get(phy_interface_t mode
)
3196 case PHY_INTERFACE_MODE_SGMII
:
3197 case PHY_INTERFACE_MODE_1000BASEX
: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3199 case PHY_INTERFACE_MODE_HSGMII
:
3200 case PHY_INTERFACE_MODE_2500BASEX
: /* MII_2500Base_X: */
3202 /* case MII_HISGMII_5G: */
3204 case PHY_INTERFACE_MODE_QSGMII
:
3205 return 0x2a; /* Code also has 0x34 */
3206 case PHY_INTERFACE_MODE_XAUI
: /* MII_RXAUI_LITE: */
3208 case PHY_INTERFACE_MODE_XGMII
: /* MII_XSGMII */
3209 case PHY_INTERFACE_MODE_10GKR
:
3210 case PHY_INTERFACE_MODE_10GBASER
: /* MII_10GR */
3219 static void rtl931x_cmu_type_set(u32 asds
, phy_interface_t mode
, int chiptype
)
3221 int cmu_type
= 0; /* Clock Management Unit */
3225 u32 lane
, frc_lc_mode_bitnum
, frc_lc_mode_val_bitnum
;
3228 case PHY_INTERFACE_MODE_NA
:
3229 case PHY_INTERFACE_MODE_10GKR
:
3230 case PHY_INTERFACE_MODE_XGMII
:
3231 case PHY_INTERFACE_MODE_10GBASER
:
3232 case PHY_INTERFACE_MODE_USXGMII
:
3235 /* case MII_10GR1000BX_AUTO:
3237 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3240 case PHY_INTERFACE_MODE_QSGMII
:
3245 case PHY_INTERFACE_MODE_HSGMII
:
3250 case PHY_INTERFACE_MODE_1000BASEX
:
3255 /* case MII_1000BX100BX_AUTO:
3260 case PHY_INTERFACE_MODE_SGMII
:
3265 case PHY_INTERFACE_MODE_2500BASEX
:
3271 pr_info("SerDes %d mode is invalid\n", asds
);
3276 cmu_page
= rtl931x_sds_cmu_page_get(mode
);
3281 frc_lc_mode_bitnum
= 4;
3282 frc_lc_mode_val_bitnum
= 5;
3284 frc_lc_mode_bitnum
= 6;
3285 frc_lc_mode_val_bitnum
= 7;
3288 evenSds
= asds
- lane
;
3290 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3291 __func__
, cmu_type
, cmu_page
, frc_cmu_spd
, lane
, asds
);
3293 if (cmu_type
== 1) {
3294 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3295 rtl9310_sds_field_w(asds
, cmu_page
, 0x7, 15, 15, 0);
3296 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3298 rtl9310_sds_field_w(asds
, cmu_page
, 0xd, 14, 14, 0);
3301 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, 3, 2, 0x3);
3302 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, frc_lc_mode_bitnum
, frc_lc_mode_bitnum
, 1);
3303 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, frc_lc_mode_val_bitnum
, frc_lc_mode_val_bitnum
, 0);
3304 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, 12, 12, 1);
3305 rtl9310_sds_field_w(evenSds
, 0x20, 0x12, 15, 13, frc_cmu_spd
);
3308 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3312 static void rtl931x_sds_rx_rst(u32 sds
)
3314 u32 asds
= rtl931x_get_analog_sds(sds
);
3319 rtl931x_write_sds_phy(asds
, 0x2e, 0x12, 0x2740);
3320 rtl931x_write_sds_phy(asds
, 0x2f, 0x0, 0x0);
3321 rtl931x_write_sds_phy(asds
, 0x2f, 0x2, 0x2010);
3322 rtl931x_write_sds_phy(asds
, 0x20, 0x0, 0xc10);
3324 rtl931x_write_sds_phy(asds
, 0x2e, 0x12, 0x27c0);
3325 rtl931x_write_sds_phy(asds
, 0x2f, 0x0, 0xc000);
3326 rtl931x_write_sds_phy(asds
, 0x2f, 0x2, 0x6010);
3327 rtl931x_write_sds_phy(asds
, 0x20, 0x0, 0xc30);
3332 // Currently not used
3333 // static void rtl931x_sds_disable(u32 sds)
3338 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3341 static void rtl931x_sds_mii_mode_set(u32 sds
, phy_interface_t mode
)
3346 case PHY_INTERFACE_MODE_QSGMII
:
3349 case PHY_INTERFACE_MODE_XGMII
:
3350 val
= 0x10; /* serdes mode XSGMII */
3352 case PHY_INTERFACE_MODE_USXGMII
:
3353 case PHY_INTERFACE_MODE_2500BASEX
:
3356 case PHY_INTERFACE_MODE_HSGMII
:
3359 case PHY_INTERFACE_MODE_SGMII
:
3368 sw_w32(val
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3371 static sds_config sds_config_10p3125g_type1
[] = {
3372 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3373 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3374 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3375 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3376 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3377 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3378 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3379 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3380 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3381 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3382 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3383 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3384 { 0x2F, 0x13, 0x0000 }
3387 static sds_config sds_config_10p3125g_cmu_type1
[] = {
3388 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3389 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3390 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3391 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3392 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3395 void rtl931x_sds_init(u32 sds
, phy_interface_t mode
)
3397 u32 board_sds_tx_type1
[] = {
3398 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3399 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3401 u32 board_sds_tx
[] = {
3402 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3403 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3405 u32 board_sds_tx2
[] = {
3406 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3407 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3409 u32 asds
, dSds
, ori
, model_info
, val
;
3412 asds
= rtl931x_get_analog_sds(sds
);
3417 pr_info("%s: set sds %d to mode %d\n", __func__
, sds
, mode
);
3418 val
= rtl9310_sds_field_r(asds
, 0x1F, 0x9, 11, 6);
3420 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__
,
3421 rtl931x_read_sds_phy(asds
, 0x1f, 0x9), val
, asds
);
3422 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__
,
3423 rtl931x_read_sds_phy(asds
, 0x24, 0x9), asds
);
3424 pr_info("%s: CMU mode %08X stored even SDS %d", __func__
,
3425 rtl931x_read_sds_phy(asds
& ~1, 0x20, 0x12), asds
& ~1);
3426 pr_info("%s: serdes_mode_ctrl %08X", __func__
, RTL931X_SERDES_MODE_CTRL
+ 4 * (sds
>> 2));
3427 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x24, 0x7));
3428 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x26, 0x7));
3429 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__
, rtl931x_read_sds_phy(asds
, 0x28, 0x7));
3430 pr_info("%s XSG page 0x0 0xe %08x\n", __func__
, rtl931x_read_sds_phy(dSds
, 0x0, 0xe));
3431 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__
, rtl931x_read_sds_phy(dSds
+ 1, 0x0, 0xe));
3433 model_info
= sw_r32(RTL93XX_MODEL_NAME_INFO
);
3434 if ((model_info
>> 4) & 0x1) {
3435 pr_info("detected chiptype 1\n");
3438 pr_info("detected chiptype 0\n");
3444 dSds
= (sds
- 1) * 2;
3446 pr_info("%s: 2.5gbit %08X dsds %d", __func__
,
3447 rtl931x_read_sds_phy(dSds
, 0x1, 0x14), dSds
);
3449 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__
, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
));
3450 ori
= sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3451 val
= ori
| (1 << sds
);
3452 sw_w32(val
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3455 case PHY_INTERFACE_MODE_NA
:
3458 case PHY_INTERFACE_MODE_XGMII
: /* MII_XSGMII */
3462 xsg_sdsid_1
= dSds
+ 1;
3464 rtl9310_sds_field_w(dSds
, 0x1, 0x1, 7, 4, 0xf);
3465 rtl9310_sds_field_w(dSds
, 0x1, 0x1, 3, 0, 0xf);
3467 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 0x1, 7, 4, 0xf);
3468 rtl9310_sds_field_w(xsg_sdsid_1
, 0x1, 0x1, 3, 0, 0xf);
3472 rtl9310_sds_field_w(dSds
, 0x0, 0xE, 12, 12, 1);
3473 rtl9310_sds_field_w(dSds
+ 1, 0x0, 0xE, 12, 12, 1);
3476 case PHY_INTERFACE_MODE_USXGMII
: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3477 u32 op_code
= 0x6003;
3481 rtl9310_sds_field_w(asds
, 0x6, 0x2, 12, 12, 1);
3483 for (int i
= 0; i
< sizeof(sds_config_10p3125g_type1
) / sizeof(sds_config
); ++i
) {
3484 rtl931x_write_sds_phy(asds
, sds_config_10p3125g_type1
[i
].page
- 0x4, sds_config_10p3125g_type1
[i
].reg
, sds_config_10p3125g_type1
[i
].data
);
3487 evenSds
= asds
- (asds
% 2);
3489 for (int i
= 0; i
< sizeof(sds_config_10p3125g_cmu_type1
) / sizeof(sds_config
); ++i
) {
3490 rtl931x_write_sds_phy(evenSds
,
3491 sds_config_10p3125g_cmu_type1
[i
].page
- 0x4, sds_config_10p3125g_cmu_type1
[i
].reg
, sds_config_10p3125g_cmu_type1
[i
].data
);
3494 rtl9310_sds_field_w(asds
, 0x6, 0x2, 12, 12, 0);
3497 rtl9310_sds_field_w(asds
, 0x2e, 0xd, 6, 0, 0x0);
3498 rtl9310_sds_field_w(asds
, 0x2e, 0xd, 7, 7, 0x1);
3500 rtl9310_sds_field_w(asds
, 0x2e, 0x1c, 5, 0, 0x1E);
3501 rtl9310_sds_field_w(asds
, 0x2e, 0x1d, 11, 0, 0x00);
3502 rtl9310_sds_field_w(asds
, 0x2e, 0x1f, 11, 0, 0x00);
3503 rtl9310_sds_field_w(asds
, 0x2f, 0x0, 11, 0, 0x00);
3504 rtl9310_sds_field_w(asds
, 0x2f, 0x1, 11, 0, 0x00);
3506 rtl9310_sds_field_w(asds
, 0x2e, 0xf, 12, 6, 0x7F);
3507 rtl931x_write_sds_phy(asds
, 0x2f, 0x12, 0xaaa);
3509 rtl931x_sds_rx_rst(sds
);
3511 rtl931x_write_sds_phy(asds
, 0x7, 0x10, op_code
);
3512 rtl931x_write_sds_phy(asds
, 0x6, 0x1d, 0x0480);
3513 rtl931x_write_sds_phy(asds
, 0x6, 0xe, 0x0400);
3517 case PHY_INTERFACE_MODE_10GBASER
: /* MII_10GR / MII_10GR1000BX_AUTO: */
3518 /* configure 10GR fiber mode=1 */
3519 rtl9310_sds_field_w(asds
, 0x1f, 0xb, 1, 1, 1);
3522 rtl9310_sds_field_w(dSds
, 0x3, 0x13, 15, 14, 0);
3524 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 12, 12, 1);
3525 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 6, 6, 1);
3526 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 13, 13, 0);
3529 rtl9310_sds_field_w(asds
, 0x1f, 13, 15, 0, 0x109e);
3530 rtl9310_sds_field_w(asds
, 0x1f, 0x6, 14, 10, 0x8);
3531 rtl9310_sds_field_w(asds
, 0x1f, 0x7, 10, 4, 0x7f);
3534 case PHY_INTERFACE_MODE_HSGMII
:
3535 rtl9310_sds_field_w(dSds
, 0x1, 0x14, 8, 8, 1);
3538 case PHY_INTERFACE_MODE_1000BASEX
: /* MII_1000BX_FIBER */
3539 rtl9310_sds_field_w(dSds
, 0x3, 0x13, 15, 14, 0);
3541 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 12, 12, 1);
3542 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 6, 6, 1);
3543 rtl9310_sds_field_w(dSds
, 0x2, 0x0, 13, 13, 0);
3546 case PHY_INTERFACE_MODE_SGMII
:
3547 rtl9310_sds_field_w(asds
, 0x24, 0x9, 15, 15, 0);
3550 case PHY_INTERFACE_MODE_2500BASEX
:
3551 rtl9310_sds_field_w(dSds
, 0x1, 0x14, 8, 8, 1);
3554 case PHY_INTERFACE_MODE_QSGMII
:
3556 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3557 __func__
, phy_modes(mode
), sds
);
3561 rtl931x_cmu_type_set(asds
, mode
, chiptype
);
3563 if (sds
>= 2 && sds
<= 13) {
3565 rtl931x_write_sds_phy(asds
, 0x2E, 0x1, board_sds_tx_type1
[sds
- 2]);
3568 sw_w32(val
, RTL931X_CHIP_INFO_ADDR
);
3569 val
= sw_r32(RTL931X_CHIP_INFO_ADDR
);
3570 if (val
& BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3572 rtl931x_write_sds_phy(asds
, 0x2E, 0x1, board_sds_tx2
[sds
- 2]);
3574 rtl931x_write_sds_phy(asds
, 0x2E, 0x1, board_sds_tx
[sds
- 2]);
3577 sw_w32(val
, RTL931X_CHIP_INFO_ADDR
);
3581 val
= ori
& ~BIT(sds
);
3582 sw_w32(val
, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
);
3583 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__
, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR
));
3585 if (mode
== PHY_INTERFACE_MODE_XGMII
||
3586 mode
== PHY_INTERFACE_MODE_QSGMII
||
3587 mode
== PHY_INTERFACE_MODE_HSGMII
||
3588 mode
== PHY_INTERFACE_MODE_SGMII
||
3589 mode
== PHY_INTERFACE_MODE_USXGMII
) {
3590 if (mode
== PHY_INTERFACE_MODE_XGMII
)
3591 rtl931x_sds_mii_mode_set(sds
, mode
);
3593 rtl931x_sds_fiber_mode_set(sds
, mode
);
3597 int rtl931x_sds_cmu_band_set(int sds
, bool enable
, u32 band
, phy_interface_t mode
)
3600 int page
= rtl931x_sds_cmu_page_get(mode
);
3604 asds
= rtl931x_get_analog_sds(sds
);
3608 rtl9310_sds_field_w(asds
, page
, 0x7, 13, 13, 0);
3609 rtl9310_sds_field_w(asds
, page
, 0x7, 11, 11, 0);
3611 rtl9310_sds_field_w(asds
, page
, 0x7, 13, 13, 0);
3612 rtl9310_sds_field_w(asds
, page
, 0x7, 11, 11, 0);
3615 rtl9310_sds_field_w(asds
, page
, 0x7, 4, 0, band
);
3617 rtl931x_sds_rst(sds
);
3622 int rtl931x_sds_cmu_band_get(int sds
, phy_interface_t mode
)
3624 int page
= rtl931x_sds_cmu_page_get(mode
);
3628 asds
= rtl931x_get_analog_sds(sds
);
3630 rtl931x_write_sds_phy(asds
, 0x1f, 0x02, 73);
3632 rtl9310_sds_field_w(asds
, page
, 0x5, 15, 15, 1);
3633 band
= rtl9310_sds_field_r(asds
, 0x1f, 0x15, 8, 3);
3634 pr_info("%s band is: %d\n", __func__
, band
);
3640 int rtl931x_link_sts_get(u32 sds
)
3642 u32 sts
, sts1
, latch_sts
, latch_sts1
;
3644 u32 xsg_sdsid_0
, xsg_sdsid_1
;
3646 xsg_sdsid_0
= sds
< 2 ? sds
: (sds
- 1) * 2;
3647 xsg_sdsid_1
= xsg_sdsid_0
+ 1;
3649 sts
= rtl9310_sds_field_r(xsg_sdsid_0
, 0x1, 29, 8, 0);
3650 sts1
= rtl9310_sds_field_r(xsg_sdsid_1
, 0x1, 29, 8, 0);
3651 latch_sts
= rtl9310_sds_field_r(xsg_sdsid_0
, 0x1, 30, 8, 0);
3652 latch_sts1
= rtl9310_sds_field_r(xsg_sdsid_1
, 0x1, 30, 8, 0);
3656 asds
= rtl931x_get_analog_sds(sds
);
3657 sts
= rtl9310_sds_field_r(asds
, 0x5, 0, 12, 12);
3658 latch_sts
= rtl9310_sds_field_r(asds
, 0x4, 1, 2, 2);
3660 dsds
= sds
< 2 ? sds
: (sds
- 1) * 2;
3661 latch_sts1
= rtl9310_sds_field_r(dsds
, 0x2, 1, 2, 2);
3662 sts1
= rtl9310_sds_field_r(dsds
, 0x2, 1, 2, 2);
3665 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__
,
3666 sds
, sts
, sts1
, latch_sts
, latch_sts1
);
3671 static int rtl8214fc_sfp_insert(void *upstream
, const struct sfp_eeprom_id
*id
)
3673 struct phy_device
*phydev
= upstream
;
3675 rtl8214fc_media_set(phydev
, true);
3680 static void rtl8214fc_sfp_remove(void *upstream
)
3682 struct phy_device
*phydev
= upstream
;
3684 rtl8214fc_media_set(phydev
, false);
3687 static const struct sfp_upstream_ops rtl8214fc_sfp_ops
= {
3688 .attach
= phy_sfp_attach
,
3689 .detach
= phy_sfp_detach
,
3690 .module_insert
= rtl8214fc_sfp_insert
,
3691 .module_remove
= rtl8214fc_sfp_remove
,
3694 static int rtl8214fc_phy_probe(struct phy_device
*phydev
)
3696 struct device
*dev
= &phydev
->mdio
.dev
;
3697 int addr
= phydev
->mdio
.addr
;
3700 /* 839x has internal SerDes */
3701 if (soc_info
.id
== 0x8393)
3704 /* All base addresses of the PHYs start at multiples of 8 */
3705 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3706 sizeof(struct rtl83xx_shared_private
));
3709 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3710 shared
->name
= "RTL8214FC";
3711 /* Configuration must be done while patching still possible */
3712 ret
= rtl8380_configure_rtl8214fc(phydev
);
3717 return phy_sfp_probe(phydev
, &rtl8214fc_sfp_ops
);
3720 static int rtl8214c_phy_probe(struct phy_device
*phydev
)
3722 struct device
*dev
= &phydev
->mdio
.dev
;
3723 int addr
= phydev
->mdio
.addr
;
3725 /* All base addresses of the PHYs start at multiples of 8 */
3726 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3727 sizeof(struct rtl83xx_shared_private
));
3730 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3731 shared
->name
= "RTL8214C";
3732 /* Configuration must be done whil patching still possible */
3733 return rtl8380_configure_rtl8214c(phydev
);
3739 static int rtl8218b_ext_phy_probe(struct phy_device
*phydev
)
3741 struct device
*dev
= &phydev
->mdio
.dev
;
3742 int addr
= phydev
->mdio
.addr
;
3744 /* All base addresses of the PHYs start at multiples of 8 */
3745 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3746 sizeof(struct rtl83xx_shared_private
));
3749 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3750 shared
->name
= "RTL8218B (external)";
3751 if (soc_info
.family
== RTL8380_FAMILY_ID
) {
3752 /* Configuration must be done while patching still possible */
3753 return rtl8380_configure_ext_rtl8218b(phydev
);
3760 static int rtl8218b_int_phy_probe(struct phy_device
*phydev
)
3762 struct device
*dev
= &phydev
->mdio
.dev
;
3763 int addr
= phydev
->mdio
.addr
;
3765 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
3770 pr_debug("%s: id: %d\n", __func__
, addr
);
3771 /* All base addresses of the PHYs start at multiples of 8 */
3772 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3773 sizeof(struct rtl83xx_shared_private
));
3776 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3777 shared
->name
= "RTL8218B (internal)";
3778 /* Configuration must be done while patching still possible */
3779 return rtl8380_configure_int_rtl8218b(phydev
);
3785 static int rtl8218d_phy_probe(struct phy_device
*phydev
)
3787 struct device
*dev
= &phydev
->mdio
.dev
;
3788 int addr
= phydev
->mdio
.addr
;
3790 pr_debug("%s: id: %d\n", __func__
, addr
);
3791 /* All base addresses of the PHYs start at multiples of 8 */
3792 devm_phy_package_join(dev
, phydev
, addr
& (~7),
3793 sizeof(struct rtl83xx_shared_private
));
3795 /* All base addresses of the PHYs start at multiples of 8 */
3797 struct rtl83xx_shared_private
*shared
= phydev
->shared
->priv
;
3798 shared
->name
= "RTL8218D";
3799 /* Configuration must be done while patching still possible */
3800 /* TODO: return configure_rtl8218d(phydev); */
3806 static int rtl838x_serdes_probe(struct phy_device
*phydev
)
3808 int addr
= phydev
->mdio
.addr
;
3810 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
3815 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3816 if (soc_info
.id
== 0x8380) {
3818 return rtl8380_configure_serdes(phydev
);
3825 static int rtl8393_serdes_probe(struct phy_device
*phydev
)
3827 int addr
= phydev
->mdio
.addr
;
3829 pr_info("%s: id: %d\n", __func__
, addr
);
3830 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
3836 return rtl8390_configure_serdes(phydev
);
3839 static int rtl8390_serdes_probe(struct phy_device
*phydev
)
3841 int addr
= phydev
->mdio
.addr
;
3843 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
3849 return rtl8390_configure_generic(phydev
);
3852 static int rtl9300_serdes_probe(struct phy_device
*phydev
)
3854 if (soc_info
.family
!= RTL9300_FAMILY_ID
)
3857 phydev_info(phydev
, "Detected internal RTL9300 Serdes\n");
3859 return rtl9300_configure_serdes(phydev
);
3862 static struct phy_driver rtl83xx_phy_driver
[] = {
3864 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C
),
3865 .name
= "Realtek RTL8214C",
3866 .features
= PHY_GBIT_FEATURES
,
3867 .flags
= PHY_HAS_REALTEK_PAGES
,
3868 .match_phy_device
= rtl8214c_match_phy_device
,
3869 .probe
= rtl8214c_phy_probe
,
3870 .suspend
= genphy_suspend
,
3871 .resume
= genphy_resume
,
3872 .set_loopback
= genphy_loopback
,
3875 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
),
3876 .name
= "Realtek RTL8214FC",
3877 .features
= PHY_GBIT_FIBRE_FEATURES
,
3878 .flags
= PHY_HAS_REALTEK_PAGES
,
3879 .match_phy_device
= rtl8214fc_match_phy_device
,
3880 .probe
= rtl8214fc_phy_probe
,
3881 .suspend
= rtl8214fc_suspend
,
3882 .resume
= rtl8214fc_resume
,
3883 .set_loopback
= genphy_loopback
,
3884 .set_port
= rtl8214fc_set_port
,
3885 .get_port
= rtl8214fc_get_port
,
3886 .set_eee
= rtl8214fc_set_eee
,
3887 .get_eee
= rtl8214fc_get_eee
,
3890 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E
),
3891 .name
= "Realtek RTL8218B (external)",
3892 .features
= PHY_GBIT_FEATURES
,
3893 .flags
= PHY_HAS_REALTEK_PAGES
,
3894 .match_phy_device
= rtl8218b_ext_match_phy_device
,
3895 .probe
= rtl8218b_ext_phy_probe
,
3896 .suspend
= genphy_suspend
,
3897 .resume
= genphy_resume
,
3898 .set_loopback
= genphy_loopback
,
3899 .set_eee
= rtl8218b_set_eee
,
3900 .get_eee
= rtl8218b_get_eee
,
3903 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D
),
3904 .name
= "REALTEK RTL8218D",
3905 .features
= PHY_GBIT_FEATURES
,
3906 .flags
= PHY_HAS_REALTEK_PAGES
,
3907 .probe
= rtl8218d_phy_probe
,
3908 .suspend
= genphy_suspend
,
3909 .resume
= genphy_resume
,
3910 .set_loopback
= genphy_loopback
,
3911 .set_eee
= rtl8218d_set_eee
,
3912 .get_eee
= rtl8218d_get_eee
,
3915 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B
),
3916 .name
= "REALTEK RTL8221B",
3917 .features
= PHY_GBIT_FEATURES
,
3918 .flags
= PHY_HAS_REALTEK_PAGES
,
3919 .suspend
= genphy_suspend
,
3920 .resume
= genphy_resume
,
3921 .set_loopback
= genphy_loopback
,
3922 .read_page
= rtl8226_read_page
,
3923 .write_page
= rtl8226_write_page
,
3924 .read_status
= rtl8226_read_status
,
3925 .config_aneg
= rtl8226_config_aneg
,
3926 .set_eee
= rtl8226_set_eee
,
3927 .get_eee
= rtl8226_get_eee
,
3930 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226
),
3931 .name
= "REALTEK RTL8226",
3932 .features
= PHY_GBIT_FEATURES
,
3933 .flags
= PHY_HAS_REALTEK_PAGES
,
3934 .suspend
= genphy_suspend
,
3935 .resume
= genphy_resume
,
3936 .set_loopback
= genphy_loopback
,
3937 .read_page
= rtl8226_read_page
,
3938 .write_page
= rtl8226_write_page
,
3939 .read_status
= rtl8226_read_status
,
3940 .config_aneg
= rtl8226_config_aneg
,
3941 .set_eee
= rtl8226_set_eee
,
3942 .get_eee
= rtl8226_get_eee
,
3945 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
3946 .name
= "Realtek RTL8218B (internal)",
3947 .features
= PHY_GBIT_FEATURES
,
3948 .flags
= PHY_HAS_REALTEK_PAGES
,
3949 .probe
= rtl8218b_int_phy_probe
,
3950 .suspend
= genphy_suspend
,
3951 .resume
= genphy_resume
,
3952 .set_loopback
= genphy_loopback
,
3953 .set_eee
= rtl8218b_set_eee
,
3954 .get_eee
= rtl8218b_get_eee
,
3957 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
3958 .name
= "Realtek RTL8380 SERDES",
3959 .features
= PHY_GBIT_FIBRE_FEATURES
,
3960 .flags
= PHY_HAS_REALTEK_PAGES
,
3961 .probe
= rtl838x_serdes_probe
,
3962 .suspend
= genphy_suspend
,
3963 .resume
= genphy_resume
,
3964 .set_loopback
= genphy_loopback
,
3965 .read_status
= rtl8380_read_status
,
3968 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I
),
3969 .name
= "Realtek RTL8393 SERDES",
3970 .features
= PHY_GBIT_FIBRE_FEATURES
,
3971 .flags
= PHY_HAS_REALTEK_PAGES
,
3972 .probe
= rtl8393_serdes_probe
,
3973 .suspend
= genphy_suspend
,
3974 .resume
= genphy_resume
,
3975 .set_loopback
= genphy_loopback
,
3976 .read_status
= rtl8393_read_status
,
3979 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC
),
3980 .name
= "Realtek RTL8390 Generic",
3981 .features
= PHY_GBIT_FIBRE_FEATURES
,
3982 .flags
= PHY_HAS_REALTEK_PAGES
,
3983 .probe
= rtl8390_serdes_probe
,
3984 .suspend
= genphy_suspend
,
3985 .resume
= genphy_resume
,
3986 .set_loopback
= genphy_loopback
,
3989 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I
),
3990 .name
= "REALTEK RTL9300 SERDES",
3991 .features
= PHY_GBIT_FIBRE_FEATURES
,
3992 .flags
= PHY_HAS_REALTEK_PAGES
,
3993 .probe
= rtl9300_serdes_probe
,
3994 .suspend
= genphy_suspend
,
3995 .resume
= genphy_resume
,
3996 .set_loopback
= genphy_loopback
,
3997 .read_status
= rtl9300_read_status
,
4001 module_phy_driver(rtl83xx_phy_driver
);
4003 static struct mdio_device_id __maybe_unused rtl83xx_tbl
[] = {
4004 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
) },
4008 MODULE_DEVICE_TABLE(mdio
, rtl83xx_tbl
);
4010 MODULE_AUTHOR("B. Koblitz");
4011 MODULE_DESCRIPTION("RTL83xx PHY driver");
4012 MODULE_LICENSE("GPL");