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realtek: Whitespace and codestyle cleanup
[openwrt/staging/dedeckeh.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15
16 #include <asm/mach-rtl838x/mach-rtl83xx.h>
17 #include "rtl83xx-phy.h"
18
19 extern struct rtl83xx_soc_info soc_info;
20 extern struct mutex smi_lock;
21
22 #define PHY_CTRL_REG 0
23 #define PHY_POWER_BIT 11
24
25 #define PHY_PAGE_2 2
26 #define PHY_PAGE_4 4
27
28 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
29 #define RTL8XXX_PAGE_SELECT 0x1f
30
31 #define RTL8XXX_PAGE_MAIN 0x0000
32 #define RTL821X_PAGE_PORT 0x0266
33 #define RTL821X_PAGE_POWER 0x0a40
34 #define RTL821X_PAGE_GPHY 0x0a42
35 #define RTL821X_PAGE_MAC 0x0a43
36 #define RTL821X_PAGE_STATE 0x0b80
37 #define RTL821X_PAGE_PATCH 0x0b82
38
39 /* Using the special page 0xfff with the MDIO controller found in
40 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
41 * the cache and paging engine of the MDIO controller.
42 */
43 #define RTL83XX_PAGE_RAW 0x0fff
44
45 /* internal RTL821X PHY uses register 0x1d to select media page */
46 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
47 /* external RTL821X PHY uses register 0x1e to select media page */
48 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
49
50 #define RTL821X_MEDIA_PAGE_AUTO 0
51 #define RTL821X_MEDIA_PAGE_COPPER 1
52 #define RTL821X_MEDIA_PAGE_FIBRE 3
53 #define RTL821X_MEDIA_PAGE_INTERNAL 8
54
55 #define RTL9300_PHY_ID_MASK 0xf0ffffff
56
57 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
58 * bus to detect e.g. link and media changes. For operations on the PHYs such as
59 * patching or other configuration changes such as EEE, polling needs to be disabled
60 * since otherwise these operations may fails or lead to unpredictable results.
61 */
62 DEFINE_MUTEX(poll_lock);
63
64 static const struct firmware rtl838x_8380_fw;
65 static const struct firmware rtl838x_8214fc_fw;
66 static const struct firmware rtl838x_8218b_fw;
67
68 static u64 disable_polling(int port)
69 {
70 u64 saved_state;
71
72 mutex_lock(&poll_lock);
73
74 switch (soc_info.family) {
75 case RTL8380_FAMILY_ID:
76 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
77 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
78 break;
79 case RTL8390_FAMILY_ID:
80 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
81 saved_state <<= 32;
82 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
83 sw_w32_mask(BIT(port % 32), 0,
84 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
85 break;
86 case RTL9300_FAMILY_ID:
87 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
88 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
89 break;
90 case RTL9310_FAMILY_ID:
91 pr_warn("%s not implemented for RTL931X\n", __func__);
92 break;
93 }
94
95 mutex_unlock(&poll_lock);
96
97 return saved_state;
98 }
99
100 static int resume_polling(u64 saved_state)
101 {
102 mutex_lock(&poll_lock);
103
104 switch (soc_info.family) {
105 case RTL8380_FAMILY_ID:
106 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
107 break;
108 case RTL8390_FAMILY_ID:
109 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
110 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
111 break;
112 case RTL9300_FAMILY_ID:
113 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
114 break;
115 case RTL9310_FAMILY_ID:
116 pr_warn("%s not implemented for RTL931X\n", __func__);
117 break;
118 }
119
120 mutex_unlock(&poll_lock);
121
122 return 0;
123 }
124
125 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
126 {
127 phy_modify(phydev, 0, BIT(11), on?0:BIT(11));
128 }
129
130 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
131 {
132 /* fiber ports */
133 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
134 phy_modify(phydev, 0x10, BIT(11), on?0:BIT(11));
135
136 /* copper ports */
137 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
138 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11));
139 }
140
141 static void rtl8380_phy_reset(struct phy_device *phydev)
142 {
143 phy_modify(phydev, 0, BIT(15), BIT(15));
144 }
145
146 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
147 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
148 0x02A4, 0x02A4, 0x0198, 0x0198 };
149 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
150
151 /* Reset the SerDes by powering it off and set a new operations mode
152 * of the SerDes. 0x1f is off. Other modes are
153 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
154 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
155 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
156 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
157 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
158 */
159 void rtl9300_sds_rst(int sds_num, u32 mode)
160 {
161 pr_info("%s %d\n", __func__, mode);
162 if (sds_num < 0 || sds_num > 11) {
163 pr_err("Wrong SerDes number: %d\n", sds_num);
164 return;
165 }
166
167 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
168 rtl9300_sds_regs[sds_num]);
169 mdelay(10);
170
171 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
172 rtl9300_sds_regs[sds_num]);
173 mdelay(10);
174
175 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
176 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
177 }
178
179 void rtl9300_sds_set(int sds_num, u32 mode)
180 {
181 pr_info("%s %d\n", __func__, mode);
182 if (sds_num < 0 || sds_num > 11) {
183 pr_err("Wrong SerDes number: %d\n", sds_num);
184 return;
185 }
186
187 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
188 rtl9300_sds_regs[sds_num]);
189 mdelay(10);
190
191 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
192 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
193 }
194
195 u32 rtl9300_sds_mode_get(int sds_num)
196 {
197 u32 v;
198
199 if (sds_num < 0 || sds_num > 11) {
200 pr_err("Wrong SerDes number: %d\n", sds_num);
201 return 0;
202 }
203
204 v = sw_r32(rtl9300_sds_regs[sds_num]);
205 v >>= rtl9300_sds_lsb[sds_num];
206
207 return v & 0x1f;
208 }
209
210 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
211 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
212 */
213 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
214 {
215 int offset = 0;
216 int reg;
217 u32 val;
218
219 if (phy_addr == 49)
220 offset = 0x100;
221
222 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
223 * which would otherwise read as 0.
224 */
225 if (soc_info.id == 0x8393) {
226 if (phy_reg == 2)
227 return 0x1c;
228 if (phy_reg == 3)
229 return 0x8393;
230 }
231
232 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
233 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
234 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
235 * one 32 bit register.
236 */
237 reg = (phy_reg << 1) & 0xfc;
238 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
239
240 if (phy_reg & 1)
241 val = (val >> 16) & 0xffff;
242 else
243 val &= 0xffff;
244
245 return val;
246 }
247
248 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
249 * register which simulates commands to an internal MDIO bus.
250 */
251 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
252 {
253 int i;
254 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
255
256 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
257
258 for (i = 0; i < 100; i++) {
259 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
260 break;
261 mdelay(1);
262 }
263
264 if (i >= 100)
265 return -EIO;
266
267 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
268 }
269
270 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
271 {
272 int i;
273 u32 cmd;
274
275 sw_w32(v, RTL930X_SDS_INDACS_DATA);
276 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
277
278 for (i = 0; i < 100; i++) {
279 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
280 break;
281 mdelay(1);
282 }
283
284
285 if (i >= 100) {
286 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
287 return -EIO;
288 }
289
290 return 0;
291 }
292
293 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
294 {
295 int i;
296 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
297
298 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
299 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
300
301 for (i = 0; i < 100; i++) {
302 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
303 break;
304 mdelay(1);
305 }
306
307 if (i >= 100)
308 return -EIO;
309
310 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
311
312 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
313 }
314
315 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
316 {
317 int i;
318 u32 cmd;
319
320 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
321 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
322
323 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
324
325 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
326 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
327
328 for (i = 0; i < 100; i++) {
329 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
330 break;
331 mdelay(1);
332 }
333
334 if (i >= 100)
335 return -EIO;
336
337 return 0;
338 }
339
340 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
341 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
342 * in a standard page 0 of a PHY
343 */
344 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
345 {
346 int offset = 0;
347 u32 val;
348
349 if (phy_addr == 26)
350 offset = 0x100;
351 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
352
353 return val;
354 }
355
356 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
357 {
358 int offset = 0;
359 int reg;
360 u32 val;
361
362 if (phy_addr == 49)
363 offset = 0x100;
364
365 reg = (phy_reg << 1) & 0xfc;
366 val = v;
367 if (phy_reg & 1) {
368 val = val << 16;
369 sw_w32_mask(0xffff0000, val,
370 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
371 } else {
372 sw_w32_mask(0xffff, val,
373 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
374 }
375
376 return 0;
377 }
378
379 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
380 * ports of the RTL838x SoCs
381 */
382 static int rtl8380_read_status(struct phy_device *phydev)
383 {
384 int err;
385
386 err = genphy_read_status(phydev);
387
388 if (phydev->link) {
389 phydev->speed = SPEED_1000;
390 phydev->duplex = DUPLEX_FULL;
391 }
392
393 return err;
394 }
395
396 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
397 * ports of the RTL8393 SoC
398 */
399 static int rtl8393_read_status(struct phy_device *phydev)
400 {
401 int offset = 0;
402 int err;
403 int phy_addr = phydev->mdio.addr;
404 u32 v;
405
406 err = genphy_read_status(phydev);
407 if (phy_addr == 49)
408 offset = 0x100;
409
410 if (phydev->link) {
411 phydev->speed = SPEED_100;
412 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
413 * PHY registers
414 */
415 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
416 if (!(v & (1 << 13)) && (v & (1 << 6)))
417 phydev->speed = SPEED_1000;
418 phydev->duplex = DUPLEX_FULL;
419 }
420
421 return err;
422 }
423
424 static int rtl8226_read_page(struct phy_device *phydev)
425 {
426 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
427 }
428
429 static int rtl8226_write_page(struct phy_device *phydev, int page)
430 {
431 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
432 }
433
434 static int rtl8226_read_status(struct phy_device *phydev)
435 {
436 int ret = 0, i;
437 u32 val;
438
439 // TODO: ret = genphy_read_status(phydev);
440 // if (ret < 0) {
441 // pr_info("%s: genphy_read_status failed\n", __func__);
442 // return ret;
443 // }
444
445 // Link status must be read twice
446 for (i = 0; i < 2; i++)
447 val = phy_read_mmd(phydev, MMD_VEND2, 0xA402);
448
449 phydev->link = val & BIT(2) ? 1 : 0;
450 if (!phydev->link)
451 goto out;
452
453 // Read duplex status
454 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
455 if (val < 0)
456 goto out;
457 phydev->duplex = !!(val & BIT(3));
458
459 // Read speed
460 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
461 switch (val & 0x0630) {
462 case 0x0000:
463 phydev->speed = SPEED_10;
464 break;
465 case 0x0010:
466 phydev->speed = SPEED_100;
467 break;
468 case 0x0020:
469 phydev->speed = SPEED_1000;
470 break;
471 case 0x0200:
472 phydev->speed = SPEED_10000;
473 break;
474 case 0x0210:
475 phydev->speed = SPEED_2500;
476 break;
477 case 0x0220:
478 phydev->speed = SPEED_5000;
479 break;
480 default:
481 break;
482 }
483
484 out:
485 return ret;
486 }
487
488 static int rtl8226_advertise_aneg(struct phy_device *phydev)
489 {
490 int ret = 0;
491 u32 v;
492
493 pr_info("In %s\n", __func__);
494
495 v = phy_read_mmd(phydev, MMD_AN, 16);
496 if (v < 0)
497 goto out;
498
499 v |= BIT(5); // HD 10M
500 v |= BIT(6); // FD 10M
501 v |= BIT(7); // HD 100M
502 v |= BIT(8); // FD 100M
503
504 ret = phy_write_mmd(phydev, MMD_AN, 16, v);
505
506 // Allow 1GBit
507 v = phy_read_mmd(phydev, MMD_VEND2, 0xA412);
508 if (v < 0)
509 goto out;
510 v |= BIT(9); // FD 1000M
511
512 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v);
513 if (ret < 0)
514 goto out;
515
516 // Allow 2.5G
517 v = phy_read_mmd(phydev, MMD_AN, 32);
518 if (v < 0)
519 goto out;
520
521 v |= BIT(7);
522 ret = phy_write_mmd(phydev, MMD_AN, 32, v);
523
524 out:
525 return ret;
526 }
527
528 static int rtl8226_config_aneg(struct phy_device *phydev)
529 {
530 int ret = 0;
531 u32 v;
532
533 pr_debug("In %s\n", __func__);
534 if (phydev->autoneg == AUTONEG_ENABLE) {
535 ret = rtl8226_advertise_aneg(phydev);
536 if (ret)
537 goto out;
538 // AutoNegotiationEnable
539 v = phy_read_mmd(phydev, MMD_AN, 0);
540 if (v < 0)
541 goto out;
542
543 v |= BIT(12); // Enable AN
544 ret = phy_write_mmd(phydev, MMD_AN, 0, v);
545 if (ret < 0)
546 goto out;
547
548 // RestartAutoNegotiation
549 v = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
550 if (v < 0)
551 goto out;
552 v |= BIT(9);
553
554 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v);
555 }
556
557 // TODO: ret = __genphy_config_aneg(phydev, ret);
558
559 out:
560 return ret;
561 }
562
563 static int rtl8226_get_eee(struct phy_device *phydev,
564 struct ethtool_eee *e)
565 {
566 u32 val;
567 int addr = phydev->mdio.addr;
568
569 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
570
571 val = phy_read_mmd(phydev, MMD_AN, 60);
572 if (e->eee_enabled) {
573 e->eee_enabled = !!(val & BIT(1));
574 if (!e->eee_enabled) {
575 val = phy_read_mmd(phydev, MMD_AN, 62);
576 e->eee_enabled = !!(val & BIT(0));
577 }
578 }
579 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
580
581 return 0;
582 }
583
584 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
585 {
586 int port = phydev->mdio.addr;
587 u64 poll_state;
588 bool an_enabled;
589 u32 val;
590
591 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
592
593 poll_state = disable_polling(port);
594
595 // Remember aneg state
596 val = phy_read_mmd(phydev, MMD_AN, 0);
597 an_enabled = !!(val & BIT(12));
598
599 // Setup 100/1000MBit
600 val = phy_read_mmd(phydev, MMD_AN, 60);
601 if (e->eee_enabled)
602 val |= 0x6;
603 else
604 val &= 0x6;
605 phy_write_mmd(phydev, MMD_AN, 60, val);
606
607 // Setup 2.5GBit
608 val = phy_read_mmd(phydev, MMD_AN, 62);
609 if (e->eee_enabled)
610 val |= 0x1;
611 else
612 val &= 0x1;
613 phy_write_mmd(phydev, MMD_AN, 62, val);
614
615 // RestartAutoNegotiation
616 val = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
617 val |= BIT(9);
618 phy_write_mmd(phydev, MMD_VEND2, 0xA400, val);
619
620 resume_polling(poll_state);
621
622 return 0;
623 }
624
625 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
626 const struct firmware *fw,
627 const char *name)
628 {
629 struct device *dev = &phydev->mdio.dev;
630 int err;
631 struct fw_header *h;
632 uint32_t checksum, my_checksum;
633
634 err = request_firmware(&fw, name, dev);
635 if (err < 0)
636 goto out;
637
638 if (fw->size < sizeof(struct fw_header)) {
639 pr_err("Firmware size too small.\n");
640 err = -EINVAL;
641 goto out;
642 }
643
644 h = (struct fw_header *) fw->data;
645 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
646
647 if (h->magic != 0x83808380) {
648 pr_err("Wrong firmware file: MAGIC mismatch.\n");
649 goto out;
650 }
651
652 checksum = h->checksum;
653 h->checksum = 0;
654 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
655 if (checksum != my_checksum) {
656 pr_err("Firmware checksum mismatch.\n");
657 err = -EINVAL;
658 goto out;
659 }
660 h->checksum = checksum;
661
662 return h;
663 out:
664 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
665 return NULL;
666 }
667
668 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
669 {
670 int mac = phydev->mdio.addr;
671
672 /* select main page 0 */
673 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
674 /* write to 0x8 to register 0x1d on main page 0 */
675 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
676 /* select page 0x266 */
677 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
678 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
679 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
680 /* return to main page 0 */
681 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
682 /* write to 0x0 to register 0x1d on main page 0 */
683 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
684 mdelay(1);
685 }
686
687 static int rtl8390_configure_generic(struct phy_device *phydev)
688 {
689 int mac = phydev->mdio.addr;
690 u32 val, phy_id;
691
692 val = phy_read(phydev, 2);
693 phy_id = val << 16;
694 val = phy_read(phydev, 3);
695 phy_id |= val;
696 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
697
698 /* Read internal PHY ID */
699 phy_write_paged(phydev, 31, 27, 0x0002);
700 val = phy_read_paged(phydev, 31, 28);
701
702 /* Internal RTL8218B, version 2 */
703 phydev_info(phydev, "Detected unknown %x\n", val);
704
705 return 0;
706 }
707
708 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
709 {
710 u32 val, phy_id;
711 int i, p, ipd_flag;
712 int mac = phydev->mdio.addr;
713 struct fw_header *h;
714 u32 *rtl838x_6275B_intPhy_perport;
715 u32 *rtl8218b_6276B_hwEsd_perport;
716
717 val = phy_read(phydev, 2);
718 phy_id = val << 16;
719 val = phy_read(phydev, 3);
720 phy_id |= val;
721 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
722
723 /* Read internal PHY ID */
724 phy_write_paged(phydev, 31, 27, 0x0002);
725 val = phy_read_paged(phydev, 31, 28);
726 if (val != 0x6275) {
727 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
728 return -1;
729 }
730
731 /* Internal RTL8218B, version 2 */
732 phydev_info(phydev, "Detected internal RTL8218B\n");
733
734 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
735 if (!h)
736 return -1;
737
738 if (h->phy != 0x83800000) {
739 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
740 return -1;
741 }
742
743 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
744 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
745
746 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
747 ipd_flag = 1;
748
749 val = phy_read(phydev, 0);
750 if (val & BIT(11))
751 rtl8380_int_phy_on_off(phydev, true);
752 else
753 rtl8380_phy_reset(phydev);
754 msleep(100);
755
756 /* Ready PHY for patch */
757 for (p = 0; p < 8; p++) {
758 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
759 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
760 }
761 msleep(500);
762 for (p = 0; p < 8; p++) {
763 for (i = 0; i < 100 ; i++) {
764 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
765 if (val & 0x40)
766 break;
767 }
768 if (i >= 100) {
769 phydev_err(phydev,
770 "ERROR: Port %d not ready for patch.\n",
771 mac + p);
772 return -1;
773 }
774 }
775 for (p = 0; p < 8; p++) {
776 i = 0;
777 while (rtl838x_6275B_intPhy_perport[i * 2]) {
778 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
779 rtl838x_6275B_intPhy_perport[i * 2],
780 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
781 i++;
782 }
783 i = 0;
784 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
785 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
786 rtl8218b_6276B_hwEsd_perport[i * 2],
787 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
788 i++;
789 }
790 }
791
792 return 0;
793 }
794
795 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
796 {
797 u32 val, ipd, phy_id;
798 int i, l;
799 int mac = phydev->mdio.addr;
800 struct fw_header *h;
801 u32 *rtl8380_rtl8218b_perchip;
802 u32 *rtl8218B_6276B_rtl8380_perport;
803 u32 *rtl8380_rtl8218b_perport;
804
805 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
806 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
807 return -1;
808 }
809 val = phy_read(phydev, 2);
810 phy_id = val << 16;
811 val = phy_read(phydev, 3);
812 phy_id |= val;
813 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
814
815 /* Read internal PHY ID */
816 phy_write_paged(phydev, 31, 27, 0x0002);
817 val = phy_read_paged(phydev, 31, 28);
818 if (val != 0x6276) {
819 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
820 return -1;
821 }
822 phydev_info(phydev, "Detected external RTL8218B\n");
823
824 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
825 if (!h)
826 return -1;
827
828 if (h->phy != 0x8218b000) {
829 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
830 return -1;
831 }
832
833 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
834 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
835 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
836
837 val = phy_read(phydev, 0);
838 if (val & (1 << 11))
839 rtl8380_int_phy_on_off(phydev, true);
840 else
841 rtl8380_phy_reset(phydev);
842
843 msleep(100);
844
845 /* Get Chip revision */
846 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
847 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
848 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
849
850 phydev_info(phydev, "Detected chip revision %04x\n", val);
851
852 i = 0;
853 while (rtl8380_rtl8218b_perchip[i * 3] &&
854 rtl8380_rtl8218b_perchip[i * 3 + 1]) {
855 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
856 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
857 rtl8380_rtl8218b_perchip[i * 3 + 2]);
858 i++;
859 }
860
861 /* Enable PHY */
862 for (i = 0; i < 8; i++) {
863 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
864 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
865 }
866 mdelay(100);
867
868 /* Request patch */
869 for (i = 0; i < 8; i++) {
870 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
871 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
872 }
873
874 mdelay(300);
875
876 /* Verify patch readiness */
877 for (i = 0; i < 8; i++) {
878 for (l = 0; l < 100; l++) {
879 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
880 if (val & 0x40)
881 break;
882 }
883 if (l >= 100) {
884 phydev_err(phydev, "Could not patch PHY\n");
885 return -1;
886 }
887 }
888
889 /* Use Broadcast ID method for patching */
890 rtl821x_phy_setup_package_broadcast(phydev, true);
891
892 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
893 phy_write_paged(phydev, 0x26e, 17, 0xb);
894 phy_write_paged(phydev, 0x26e, 16, 0x2);
895 mdelay(1);
896 ipd = phy_read_paged(phydev, 0x26e, 19);
897 phy_write_paged(phydev, 0, 30, 0);
898 ipd = (ipd >> 4) & 0xf; /* unused ? */
899
900 i = 0;
901 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
902 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
903 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
904 i++;
905 }
906
907 /* Disable broadcast ID */
908 rtl821x_phy_setup_package_broadcast(phydev, false);
909
910 return 0;
911 }
912
913 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
914 {
915 int addr = phydev->mdio.addr;
916
917 /* Both the RTL8214FC and the external RTL8218B have the same
918 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
919 * at PHY IDs 0-7, while the RTL8214FC must be attached via
920 * the pair of SGMII/1000Base-X with higher PHY-IDs
921 */
922 if (soc_info.family == RTL8380_FAMILY_ID)
923 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
924 else
925 return phydev->phy_id == PHY_ID_RTL8218B_E;
926 }
927
928 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
929 {
930 int mac = phydev->mdio.addr;
931
932 static int reg[] = {16, 19, 20, 21};
933 u32 val;
934
935 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
936 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
937 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
938
939 if (val & BIT(11))
940 return false;
941
942 return true;
943 }
944
945 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
946 {
947 char *state = on ? "on" : "off";
948
949 if (port == PORT_FIBRE) {
950 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
951 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
952 } else {
953 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
954 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
955 }
956
957 if (on) {
958 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), 0);
959 } else {
960 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BIT(11));
961 }
962
963 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
964 }
965
966 static int rtl8214fc_suspend(struct phy_device *phydev)
967 {
968 rtl8214fc_power_set(phydev, PORT_MII, false);
969 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
970
971 return 0;
972 }
973
974 static int rtl8214fc_resume(struct phy_device *phydev)
975 {
976 if (rtl8214fc_media_is_fibre(phydev)) {
977 rtl8214fc_power_set(phydev, PORT_MII, false);
978 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
979 } else {
980 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
981 rtl8214fc_power_set(phydev, PORT_MII, true);
982 }
983
984 return 0;
985 }
986
987 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
988 {
989 int mac = phydev->mdio.addr;
990
991 static int reg[] = {16, 19, 20, 21};
992 int val;
993
994 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
995 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
996 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
997
998 val |= BIT(10);
999 if (set_fibre) {
1000 val &= ~BIT(11);
1001 } else {
1002 val |= BIT(11);
1003 }
1004
1005 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1006 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1007 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1008
1009 if (!phydev->suspended) {
1010 if (set_fibre) {
1011 rtl8214fc_power_set(phydev, PORT_MII, false);
1012 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1013 } else {
1014 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1015 rtl8214fc_power_set(phydev, PORT_MII, true);
1016 }
1017 }
1018 }
1019
1020 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1021 {
1022 bool is_fibre = (port == PORT_FIBRE ? true : false);
1023 int addr = phydev->mdio.addr;
1024
1025 pr_debug("%s port %d to %d\n", __func__, addr, port);
1026
1027 rtl8214fc_media_set(phydev, is_fibre);
1028
1029 return 0;
1030 }
1031
1032 static int rtl8214fc_get_port(struct phy_device *phydev)
1033 {
1034 int addr = phydev->mdio.addr;
1035
1036 pr_debug("%s: port %d\n", __func__, addr);
1037 if (rtl8214fc_media_is_fibre(phydev))
1038 return PORT_FIBRE;
1039
1040 return PORT_MII;
1041 }
1042
1043 /* Enable EEE on the RTL8218B PHYs
1044 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1045 * but the only way that works since the kernel first enables EEE in the MAC
1046 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1047 */
1048 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1049 {
1050 u32 val;
1051 bool an_enabled;
1052
1053 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1054 /* Set GPHY page to copper */
1055 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1056
1057 val = phy_read(phydev, 0);
1058 an_enabled = val & BIT(12);
1059
1060 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1061 val = phy_read_mmd(phydev, 7, 60);
1062 val |= BIT(2) | BIT(1);
1063 phy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0);
1064
1065 /* 500M EEE ability */
1066 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1067 if (enable)
1068 val |= BIT(7);
1069 else
1070 val &= ~BIT(7);
1071 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1072
1073 /* Restart AN if enabled */
1074 if (an_enabled) {
1075 val = phy_read(phydev, 0);
1076 val |= BIT(9);
1077 phy_write(phydev, 0, val);
1078 }
1079
1080 /* GPHY page back to auto */
1081 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1082 }
1083
1084 static int rtl8218b_get_eee(struct phy_device *phydev,
1085 struct ethtool_eee *e)
1086 {
1087 u32 val;
1088 int addr = phydev->mdio.addr;
1089
1090 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1091
1092 /* Set GPHY page to copper */
1093 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1094
1095 val = phy_read_paged(phydev, 7, 60);
1096 if (e->eee_enabled) {
1097 // Verify vs MAC-based EEE
1098 e->eee_enabled = !!(val & BIT(7));
1099 if (!e->eee_enabled) {
1100 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1101 e->eee_enabled = !!(val & BIT(4));
1102 }
1103 }
1104 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1105
1106 /* GPHY page to auto */
1107 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1108
1109 return 0;
1110 }
1111
1112 static int rtl8218d_get_eee(struct phy_device *phydev,
1113 struct ethtool_eee *e)
1114 {
1115 u32 val;
1116 int addr = phydev->mdio.addr;
1117
1118 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1119
1120 /* Set GPHY page to copper */
1121 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1122
1123 val = phy_read_paged(phydev, 7, 60);
1124 if (e->eee_enabled)
1125 e->eee_enabled = !!(val & BIT(7));
1126 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1127
1128 /* GPHY page to auto */
1129 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1130
1131 return 0;
1132 }
1133
1134 static int rtl8214fc_set_eee(struct phy_device *phydev,
1135 struct ethtool_eee *e)
1136 {
1137 u32 poll_state;
1138 int port = phydev->mdio.addr;
1139 bool an_enabled;
1140 u32 val;
1141
1142 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1143
1144 if (rtl8214fc_media_is_fibre(phydev)) {
1145 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1146 return -ENOTSUPP;
1147 }
1148
1149 poll_state = disable_polling(port);
1150
1151 /* Set GPHY page to copper */
1152 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1153
1154 // Get auto-negotiation status
1155 val = phy_read(phydev, 0);
1156 an_enabled = val & BIT(12);
1157
1158 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1159 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1160 val &= ~BIT(5); // Use MAC-based EEE
1161 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1162
1163 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1164 phy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0);
1165
1166 /* 500M EEE ability */
1167 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1168 if (e->eee_enabled)
1169 val |= BIT(7);
1170 else
1171 val &= ~BIT(7);
1172
1173 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1174
1175 /* Restart AN if enabled */
1176 if (an_enabled) {
1177 pr_info("%s: doing aneg\n", __func__);
1178 val = phy_read(phydev, 0);
1179 val |= BIT(9);
1180 phy_write(phydev, 0, val);
1181 }
1182
1183 /* GPHY page back to auto */
1184 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1185
1186 resume_polling(poll_state);
1187
1188 return 0;
1189 }
1190
1191 static int rtl8214fc_get_eee(struct phy_device *phydev,
1192 struct ethtool_eee *e)
1193 {
1194 int addr = phydev->mdio.addr;
1195
1196 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1197 if (rtl8214fc_media_is_fibre(phydev)) {
1198 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1199 return -ENOTSUPP;
1200 }
1201
1202 return rtl8218b_get_eee(phydev, e);
1203 }
1204
1205 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1206 {
1207 int port = phydev->mdio.addr;
1208 u64 poll_state;
1209 u32 val;
1210 bool an_enabled;
1211
1212 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1213
1214 poll_state = disable_polling(port);
1215
1216 /* Set GPHY page to copper */
1217 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1218 val = phy_read(phydev, 0);
1219 an_enabled = val & BIT(12);
1220
1221 if (e->eee_enabled) {
1222 /* 100/1000M EEE Capability */
1223 phy_write(phydev, 13, 0x0007);
1224 phy_write(phydev, 14, 0x003C);
1225 phy_write(phydev, 13, 0x4007);
1226 phy_write(phydev, 14, 0x0006);
1227
1228 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1229 val |= BIT(4);
1230 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1231 } else {
1232 /* 100/1000M EEE Capability */
1233 phy_write(phydev, 13, 0x0007);
1234 phy_write(phydev, 14, 0x003C);
1235 phy_write(phydev, 13, 0x0007);
1236 phy_write(phydev, 14, 0x0000);
1237
1238 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1239 val &= ~BIT(4);
1240 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1241 }
1242
1243 /* Restart AN if enabled */
1244 if (an_enabled) {
1245 val = phy_read(phydev, 0);
1246 val |= BIT(9);
1247 phy_write(phydev, 0, val);
1248 }
1249
1250 /* GPHY page back to auto */
1251 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1252
1253 pr_info("%s done\n", __func__);
1254 resume_polling(poll_state);
1255
1256 return 0;
1257 }
1258
1259 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1260 {
1261 int addr = phydev->mdio.addr;
1262 u64 poll_state;
1263
1264 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1265
1266 poll_state = disable_polling(addr);
1267
1268 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1269
1270 resume_polling(poll_state);
1271
1272 return 0;
1273 }
1274
1275 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1276 {
1277 return phydev->phy_id == PHY_ID_RTL8214C;
1278 }
1279
1280 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1281 {
1282 u32 phy_id, val;
1283 int mac = phydev->mdio.addr;
1284
1285 val = phy_read(phydev, 2);
1286 phy_id = val << 16;
1287 val = phy_read(phydev, 3);
1288 phy_id |= val;
1289 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1290
1291 phydev_info(phydev, "Detected external RTL8214C\n");
1292
1293 /* GPHY auto conf */
1294 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1295
1296 return 0;
1297 }
1298
1299 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1300 {
1301 u32 phy_id, val, page = 0;
1302 int i, l;
1303 int mac = phydev->mdio.addr;
1304 struct fw_header *h;
1305 u32 *rtl8380_rtl8214fc_perchip;
1306 u32 *rtl8380_rtl8214fc_perport;
1307
1308 val = phy_read(phydev, 2);
1309 phy_id = val << 16;
1310 val = phy_read(phydev, 3);
1311 phy_id |= val;
1312 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1313
1314 /* Read internal PHY id */
1315 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1316 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1317 val = phy_read_paged(phydev, 0x1f, 0x1c);
1318 if (val != 0x6276) {
1319 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1320 return -1;
1321 }
1322 phydev_info(phydev, "Detected external RTL8214FC\n");
1323
1324 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1325 if (!h)
1326 return -1;
1327
1328 if (h->phy != 0x8214fc00) {
1329 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1330 return -1;
1331 }
1332
1333 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1334
1335 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1336
1337 /* detect phy version */
1338 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1339 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1340
1341 val = phy_read(phydev, 16);
1342 if (val & (1 << 11))
1343 rtl8380_rtl8214fc_on_off(phydev, true);
1344 else
1345 rtl8380_phy_reset(phydev);
1346
1347 msleep(100);
1348 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1349
1350 i = 0;
1351 while (rtl8380_rtl8214fc_perchip[i * 3] &&
1352 rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1353 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1354 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1355 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1356 val = phy_read_paged(phydev, 0x260, 13);
1357 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1358 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1359 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1360 } else {
1361 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1362 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1363 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1364 }
1365 i++;
1366 }
1367
1368 /* Force copper medium */
1369 for (i = 0; i < 4; i++) {
1370 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1371 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1372 }
1373
1374 /* Enable PHY */
1375 for (i = 0; i < 4; i++) {
1376 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1377 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1378 }
1379 mdelay(100);
1380
1381 /* Disable Autosensing */
1382 for (i = 0; i < 4; i++) {
1383 for (l = 0; l < 100; l++) {
1384 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1385 if ((val & 0x7) >= 3)
1386 break;
1387 }
1388 if (l >= 100) {
1389 phydev_err(phydev, "Could not disable autosensing\n");
1390 return -1;
1391 }
1392 }
1393
1394 /* Request patch */
1395 for (i = 0; i < 4; i++) {
1396 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1397 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1398 }
1399 mdelay(300);
1400
1401 /* Verify patch readiness */
1402 for (i = 0; i < 4; i++) {
1403 for (l = 0; l < 100; l++) {
1404 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1405 if (val & 0x40)
1406 break;
1407 }
1408 if (l >= 100) {
1409 phydev_err(phydev, "Could not patch PHY\n");
1410 return -1;
1411 }
1412 }
1413 /* Use Broadcast ID method for patching */
1414 rtl821x_phy_setup_package_broadcast(phydev, true);
1415
1416 i = 0;
1417 while (rtl8380_rtl8214fc_perport[i * 2]) {
1418 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1419 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1420 i++;
1421 }
1422
1423 /* Disable broadcast ID */
1424 rtl821x_phy_setup_package_broadcast(phydev, false);
1425
1426 /* Auto medium selection */
1427 for (i = 0; i < 4; i++) {
1428 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1429 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1430 }
1431
1432 return 0;
1433 }
1434
1435 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1436 {
1437 int addr = phydev->mdio.addr;
1438
1439 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1440 }
1441
1442 static int rtl8380_configure_serdes(struct phy_device *phydev)
1443 {
1444 u32 v;
1445 u32 sds_conf_value;
1446 int i;
1447 struct fw_header *h;
1448 u32 *rtl8380_sds_take_reset;
1449 u32 *rtl8380_sds_common;
1450 u32 *rtl8380_sds01_qsgmii_6275b;
1451 u32 *rtl8380_sds23_qsgmii_6275b;
1452 u32 *rtl8380_sds4_fiber_6275b;
1453 u32 *rtl8380_sds5_fiber_6275b;
1454 u32 *rtl8380_sds_reset;
1455 u32 *rtl8380_sds_release_reset;
1456
1457 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1458
1459 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1460 if (!h)
1461 return -1;
1462
1463 if (h->magic != 0x83808380) {
1464 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1465 return -1;
1466 }
1467
1468 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1469
1470 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1471
1472 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1473
1474 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1475
1476 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1477
1478 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1479
1480 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1481
1482 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1483
1484 /* Back up serdes power off value */
1485 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1486 pr_info("SDS power down value: %x\n", sds_conf_value);
1487
1488 /* take serdes into reset */
1489 i = 0;
1490 while (rtl8380_sds_take_reset[2 * i]) {
1491 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1492 i++;
1493 udelay(1000);
1494 }
1495
1496 /* apply common serdes patch */
1497 i = 0;
1498 while (rtl8380_sds_common[2 * i]) {
1499 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1500 i++;
1501 udelay(1000);
1502 }
1503
1504 /* internal R/W enable */
1505 sw_w32(3, RTL838X_INT_RW_CTRL);
1506
1507 /* SerDes ports 4 and 5 are FIBRE ports */
1508 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1509
1510 /* SerDes module settings, SerDes 0-3 are QSGMII */
1511 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1512 /* SerDes 4 and 5 are 1000BX FIBRE */
1513 v |= 0x4 << 5 | 0x4;
1514 sw_w32(v, RTL838X_SDS_MODE_SEL);
1515
1516 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1517 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1518 i = 0;
1519 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1520 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1521 rtl8380_sds01_qsgmii_6275b[2 * i]);
1522 i++;
1523 }
1524
1525 i = 0;
1526 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1527 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1528 i++;
1529 }
1530
1531 i = 0;
1532 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1533 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1534 i++;
1535 }
1536
1537 i = 0;
1538 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1539 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1540 i++;
1541 }
1542
1543 i = 0;
1544 while (rtl8380_sds_reset[2 * i]) {
1545 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1546 i++;
1547 }
1548
1549 i = 0;
1550 while (rtl8380_sds_release_reset[2 * i]) {
1551 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1552 i++;
1553 }
1554
1555 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1556 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1557
1558 pr_info("Configuration of SERDES done\n");
1559
1560 return 0;
1561 }
1562
1563 static int rtl8390_configure_serdes(struct phy_device *phydev)
1564 {
1565 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1566
1567 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1568 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1569
1570 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1571 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1572 * and FRE16_EEE_QUIET_FIB1G
1573 */
1574 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1575
1576 return 0;
1577 }
1578
1579 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1580 {
1581 int l = end_bit - start_bit + 1;
1582 u32 data = v;
1583
1584 if (l < 32) {
1585 u32 mask = BIT(l) - 1;
1586
1587 data = rtl930x_read_sds_phy(sds, page, reg);
1588 data &= ~(mask << start_bit);
1589 data |= (v & mask) << start_bit;
1590 }
1591
1592 rtl930x_write_sds_phy(sds, page, reg, data);
1593 }
1594
1595 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1596 {
1597 int l = end_bit - start_bit + 1;
1598 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1599
1600 if (l >= 32)
1601 return v;
1602
1603 return (v >> start_bit) & (BIT(l) - 1);
1604 }
1605
1606 /* Read the link and speed status of the internal SerDes of the RTL9300
1607 */
1608 static int rtl9300_read_status(struct phy_device *phydev)
1609 {
1610 struct device *dev = &phydev->mdio.dev;
1611 int phy_addr = phydev->mdio.addr;
1612 struct device_node *dn;
1613 u32 sds_num = 0, status, latch_status, mode;
1614
1615 if (dev->of_node) {
1616 dn = dev->of_node;
1617
1618 if (of_property_read_u32(dn, "sds", &sds_num))
1619 sds_num = -1;
1620 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1621 } else {
1622 dev_err(dev, "No DT node.\n");
1623 return -EINVAL;
1624 }
1625
1626 if (sds_num < 0)
1627 return 0;
1628
1629 mode = rtl9300_sds_mode_get(sds_num);
1630 pr_info("%s got SDS mode %02x\n", __func__, mode);
1631 if (mode == 0x1a) { // 10GR mode
1632 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1633 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1634 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1635 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1636 } else {
1637 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1638 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1639 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1640 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1641 }
1642
1643 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1644
1645 if (latch_status) {
1646 phydev->link = true;
1647 if (mode == 0x1a)
1648 phydev->speed = SPEED_10000;
1649 else
1650 phydev->speed = SPEED_1000;
1651
1652 phydev->duplex = DUPLEX_FULL;
1653 }
1654
1655 return 0;
1656 }
1657
1658 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1659 {
1660 int page = 0x2e; // 10GR and USXGMII
1661
1662 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1663 page = 0x24;
1664
1665 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1666 mdelay(5);
1667 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1668 }
1669
1670 /* Force PHY modes on 10GBit Serdes
1671 */
1672 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1673 {
1674 int sds_mode;
1675 bool lc_on;
1676 int i, lc_value;
1677 int lane_0 = (sds % 2) ? sds - 1 : sds;
1678 u32 v, cr_0, cr_1, cr_2;
1679 u32 m_bit, l_bit;
1680
1681 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1682 switch (phy_if) {
1683 case PHY_INTERFACE_MODE_SGMII:
1684 sds_mode = 0x2;
1685 lc_on = false;
1686 lc_value = 0x1;
1687 break;
1688
1689 case PHY_INTERFACE_MODE_HSGMII:
1690 sds_mode = 0x12;
1691 lc_value = 0x3;
1692 // Configure LC
1693 break;
1694
1695 case PHY_INTERFACE_MODE_1000BASEX:
1696 sds_mode = 0x04;
1697 lc_on = false;
1698 break;
1699
1700 case PHY_INTERFACE_MODE_2500BASEX:
1701 sds_mode = 0x16;
1702 lc_value = 0x3;
1703 // Configure LC
1704 break;
1705
1706 case PHY_INTERFACE_MODE_10GBASER:
1707 sds_mode = 0x1a;
1708 lc_on = true;
1709 lc_value = 0x5;
1710 break;
1711
1712 case PHY_INTERFACE_MODE_NA:
1713 // This will disable SerDes
1714 sds_mode = 0x1f;
1715 break;
1716
1717 default:
1718 pr_err("%s: unknown serdes mode: %s\n",
1719 __func__, phy_modes(phy_if));
1720 return;
1721 }
1722
1723 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1724 // Power down SerDes
1725 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1726 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1727
1728 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1729 // Force mode enable
1730 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1731 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1732
1733 /* SerDes off */
1734 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1735
1736 if (phy_if == PHY_INTERFACE_MODE_NA)
1737 return;
1738
1739 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1740 // Enable LC and ring
1741 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1742
1743 if (sds == lane_0)
1744 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1745 else
1746 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1747
1748 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1749
1750 if (lc_on)
1751 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1752 else
1753 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1754
1755 // Force analog LC & ring on
1756 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1757
1758 v = lc_on ? 0x3 : 0x1;
1759
1760 if (sds == lane_0)
1761 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1762 else
1763 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1764
1765 // Force SerDes mode
1766 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1767 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1768
1769 // Toggle LC or Ring
1770 for (i = 0; i < 20; i++) {
1771 mdelay(200);
1772
1773 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1774
1775 m_bit = (lane_0 == sds) ? (4) : (5);
1776 l_bit = (lane_0 == sds) ? (4) : (5);
1777
1778 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1779 mdelay(10);
1780 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1781 mdelay(10);
1782 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1783
1784 if (cr_0 && cr_1 && cr_2) {
1785 u32 t;
1786
1787 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1788 break;
1789
1790 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1791 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1792
1793 // Reset FSM
1794 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1795 mdelay(10);
1796 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1797 mdelay(10);
1798
1799 // Need to read this twice
1800 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1801 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1802
1803 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1804
1805 // Reset FSM again
1806 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1807 mdelay(10);
1808 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1809 mdelay(10);
1810
1811 if (v == 1)
1812 break;
1813 }
1814
1815 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1816 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1817
1818 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1819 mdelay(10);
1820 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1821 }
1822
1823 rtl930x_sds_rx_rst(sds, phy_if);
1824
1825 // Re-enable power
1826 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1827
1828 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1829 }
1830
1831 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1832 {
1833 // parameters: rtl9303_80G_txParam_s2
1834 int impedance = 0x8;
1835 int pre_amp = 0x2;
1836 int main_amp = 0x9;
1837 int post_amp = 0x2;
1838 int pre_en = 0x1;
1839 int post_en = 0x1;
1840 int page;
1841
1842 switch(phy_if) {
1843 case PHY_INTERFACE_MODE_1000BASEX:
1844 page = 0x25;
1845 break;
1846 case PHY_INTERFACE_MODE_HSGMII:
1847 case PHY_INTERFACE_MODE_2500BASEX:
1848 page = 0x29;
1849 break;
1850 case PHY_INTERFACE_MODE_10GBASER:
1851 page = 0x2f;
1852 break;
1853 default:
1854 pr_err("%s: unsupported PHY mode\n", __func__);
1855 return;
1856 }
1857
1858 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1859 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1860 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1861 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1862 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1863 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1864 }
1865
1866 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1867 * timeout is in ms
1868 */
1869 int rtl9300_sds_clock_wait(int timeout)
1870 {
1871 u32 v;
1872 unsigned long start = jiffies;
1873
1874 do {
1875 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1876 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1877 if (v == 3)
1878 return 0;
1879 } while (jiffies < start + (HZ / 1000) * timeout);
1880
1881 return 1;
1882 }
1883
1884 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1885 {
1886 u32 v10, v1;
1887
1888 v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2
1889 v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0
1890 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1891
1892 v10 &= ~(BIT(13) | BIT(14));
1893 v1 &= ~(BIT(8) | BIT(9));
1894
1895 v10 |= rx_normal ? 0 : BIT(13);
1896 v1 |= rx_normal ? 0 : BIT(9);
1897
1898 v10 |= tx_normal ? 0 : BIT(14);
1899 v1 |= tx_normal ? 0 : BIT(8);
1900
1901 rtl930x_write_sds_phy(sds, 6, 2, v10);
1902 rtl930x_write_sds_phy(sds, 0, 0, v1);
1903
1904 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1905 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1906 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1907 }
1908
1909 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1910 {
1911 if (manual) {
1912 switch(dcvs_id) {
1913 case 0:
1914 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1915 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1916 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1917 break;
1918 case 1:
1919 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1920 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1921 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1922 break;
1923 case 2:
1924 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1925 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1926 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1927 break;
1928 case 3:
1929 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1930 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1931 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1932 break;
1933 case 4:
1934 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1935 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1936 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1937 break;
1938 case 5:
1939 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1940 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1941 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1942 break;
1943 default:
1944 break;
1945 }
1946 } else {
1947 switch(dcvs_id) {
1948 case 0:
1949 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1950 break;
1951 case 1:
1952 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1953 break;
1954 case 2:
1955 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1956 break;
1957 case 3:
1958 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1959 break;
1960 case 4:
1961 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1962 break;
1963 case 5:
1964 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1965 break;
1966 default:
1967 break;
1968 }
1969 mdelay(1);
1970 }
1971 }
1972
1973 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1974 {
1975 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1976 bool dcvs_manual;
1977
1978 if (!(sds_num % 2))
1979 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
1980 else
1981 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
1982
1983 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
1984 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
1985
1986 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
1987 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
1988
1989 switch(dcvs_id) {
1990 case 0:
1991 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
1992 mdelay(1);
1993
1994 // ##DCVS0 Read Out
1995 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
1996 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
1997 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
1998 break;
1999
2000 case 1:
2001 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2002 mdelay(1);
2003
2004 // ##DCVS0 Read Out
2005 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2006 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2007 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2008 break;
2009
2010 case 2:
2011 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2012 mdelay(1);
2013
2014 // ##DCVS0 Read Out
2015 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2016 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2017 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2018 break;
2019 case 3:
2020 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2021 mdelay(1);
2022
2023 // ##DCVS0 Read Out
2024 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2025 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2026 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2027 break;
2028
2029 case 4:
2030 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2031 mdelay(1);
2032
2033 // ##DCVS0 Read Out
2034 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2035 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2036 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2037 break;
2038
2039 case 5:
2040 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2041 mdelay(1);
2042
2043 // ##DCVS0 Read Out
2044 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2045 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2046 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2047 break;
2048
2049 default:
2050 break;
2051 }
2052
2053 if (dcvs_sign_out)
2054 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2055 else
2056 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2057
2058 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2059 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2060
2061 dcvs_list[0] = dcvs_sign_out;
2062 dcvs_list[1] = dcvs_coef_bin;
2063 }
2064
2065 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2066 {
2067 if (manual) {
2068 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2069 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2070 } else {
2071 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2072 mdelay(100);
2073 }
2074 }
2075
2076 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2077 {
2078 if (manual) {
2079 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2080 } else {
2081 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2082 mdelay(1);
2083 }
2084 }
2085
2086 #define GRAY_BITS 5
2087 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2088 {
2089 int i, j, m;
2090 u32 g[GRAY_BITS];
2091 u32 c[GRAY_BITS];
2092 u32 leq_binary = 0;
2093
2094 for(i = 0; i < GRAY_BITS; i++)
2095 g[i] = (gray_code & BIT(i)) >> i;
2096
2097 m = GRAY_BITS - 1;
2098
2099 c[m] = g[m];
2100
2101 for(i = 0; i < m; i++) {
2102 c[i] = g[i];
2103 for(j = i + 1; j < GRAY_BITS; j++)
2104 c[i] = c[i] ^ g[j];
2105 }
2106
2107 for(i = 0; i < GRAY_BITS; i++)
2108 leq_binary += c[i] << i;
2109
2110 return leq_binary;
2111 }
2112
2113 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2114 {
2115 u32 leq_gray, leq_bin;
2116 bool leq_manual;
2117
2118 if (!(sds_num % 2))
2119 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2120 else
2121 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2122
2123 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2124 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2125
2126 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]
2127 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2128 mdelay(1);
2129
2130 // ##LEQ Read Out
2131 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2132 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2133 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2134
2135 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2136 pr_info("LEQ manual: %u", leq_manual);
2137
2138 return leq_bin;
2139 }
2140
2141 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2142 {
2143 if (manual) {
2144 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2145 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2146 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2147 } else {
2148 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2149 mdelay(10);
2150 }
2151 }
2152
2153 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2154 {
2155 u32 vth_manual;
2156
2157 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0
2158 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1
2159 if (!(sds_num % 2))
2160 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2161 else
2162 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2163
2164 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2165 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2166 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2167 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2168 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]
2169 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2170
2171 mdelay(1);
2172
2173 //##VthP & VthN Read Out
2174 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin
2175 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin
2176
2177 pr_info("vth_set_bin = %d", vth_list[0]);
2178 pr_info("vth_set_bin = %d", vth_list[1]);
2179
2180 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2181 pr_info("Vth Maunal = %d", vth_manual);
2182 }
2183
2184 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2185 {
2186 if (manual) {
2187 switch(tap_id) {
2188 case 0:
2189 //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value
2190 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2191 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2192 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2193 break;
2194 case 1:
2195 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2196 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2197 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2198 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2199 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2200 break;
2201 case 2:
2202 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2203 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2204 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2205 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2206 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2207 break;
2208 case 3:
2209 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2210 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2211 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2212 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2213 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2214 break;
2215 case 4:
2216 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2217 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2218 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2219 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2220 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2221 break;
2222 default:
2223 break;
2224 }
2225 } else {
2226 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2227 mdelay(10);
2228 }
2229 }
2230
2231 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2232 {
2233 u32 tap0_sign_out;
2234 u32 tap0_coef_bin;
2235 u32 tap_sign_out_even;
2236 u32 tap_coef_bin_even;
2237 u32 tap_sign_out_odd;
2238 u32 tap_coef_bin_odd;
2239 bool tap_manual;
2240
2241 if (!(sds_num % 2))
2242 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2243 else
2244 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2245
2246 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2247 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2248 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2249 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2250
2251 if (!tap_id) {
2252 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2253 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2254 //##Tap1 Even Read Out
2255 mdelay(1);
2256 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2257 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2258
2259 if (tap0_sign_out == 1)
2260 pr_info("Tap0 Sign : -");
2261 else
2262 pr_info("Tap0 Sign : +");
2263
2264 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2265
2266 tap_list[0] = tap0_sign_out;
2267 tap_list[1] = tap0_coef_bin;
2268
2269 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2270 pr_info("tap0 manual = %u",tap_manual);
2271 } else {
2272 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2273 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2274 mdelay(1);
2275 //##Tap1 Even Read Out
2276 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2277 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2278
2279 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]
2280 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2281 //##Tap1 Odd Read Out
2282 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2283 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2284
2285 if (tap_sign_out_even == 1)
2286 pr_info("Tap %u even sign: -", tap_id);
2287 else
2288 pr_info("Tap %u even sign: +", tap_id);
2289
2290 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2291
2292 if (tap_sign_out_odd == 1)
2293 pr_info("Tap %u odd sign: -", tap_id);
2294 else
2295 pr_info("Tap %u odd sign: +", tap_id);
2296
2297 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2298
2299 tap_list[0] = tap_sign_out_even;
2300 tap_list[1] = tap_coef_bin_even;
2301 tap_list[2] = tap_sign_out_odd;
2302 tap_list[3] = tap_coef_bin_odd;
2303
2304 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2305 pr_info("tap %u manual = %d",tap_id, tap_manual);
2306 }
2307 }
2308
2309 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2310 {
2311 // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam
2312 int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap
2313 int vth_min = 0x0;
2314
2315 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2316 rtl930x_write_sds_phy(sds, 6, 0, 0);
2317
2318 // FGCAL
2319 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2320 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2321 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2322
2323 // DCVS
2324 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2325 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2326 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2327 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2328 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2329 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2330 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2331 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2332 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2333 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2334 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2335 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2336
2337 // LEQ (Long Term Equivalent signal level)
2338 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2339
2340 // DFE (Decision Fed Equalizer)
2341 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2342 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2343 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2344 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2345 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2346 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2347 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2348 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2349 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2350
2351 // Vth
2352 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2353 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2354 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2355
2356 pr_info("end_1.1.1 --\n");
2357
2358 pr_info("start_1.1.2 Load DFE init. value\n");
2359
2360 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2361
2362 pr_info("end_1.1.2\n");
2363
2364 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2365
2366 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2368 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2369 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2370 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2371 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2372
2373 pr_info("end_1.1.3 --\n");
2374
2375 pr_info("start_1.1.4 offset cali setting\n");
2376
2377 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2378
2379 pr_info("end_1.1.4\n");
2380
2381 pr_info("start_1.1.5 LEQ and DFE setting\n");
2382
2383 // TODO: make this work for DAC cables of different lengths
2384 // For a 10GBit serdes wit Fibre, SDS 8 or 9
2385 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2386 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2387 else
2388 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2389
2390 // No serdes, check for Aquantia PHYs
2391 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2392
2393 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2394 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2395 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2396 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2397 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2398
2399 pr_info("end_1.1.5\n");
2400 }
2401
2402 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2403 {
2404 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2405
2406 // Gray config endis to 1
2407 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2408
2409 // ForegroundOffsetCal_Manual(auto mode)
2410 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2411
2412 pr_info("end_1.2.1");
2413 }
2414
2415 void rtl9300_do_rx_calibration_2_2(int sds_num)
2416 {
2417 //Force Rx-Run = 0
2418 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2419
2420 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2421 }
2422
2423 void rtl9300_do_rx_calibration_2_3(int sds_num)
2424 {
2425 u32 fgcal_binary, fgcal_gray;
2426 u32 offset_range;
2427
2428 pr_info("start_1.2.3 Foreground Calibration\n");
2429
2430 while(1) {
2431 if (!(sds_num % 2))
2432 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2433 else
2434 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2435
2436 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2437 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2438 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2439 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2440 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]
2441 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2442 // ##FGCAL read gray
2443 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2444 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]
2445 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2446 // ##FGCAL read binary
2447 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2448
2449 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2450 __func__, fgcal_gray, fgcal_binary);
2451
2452 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2453
2454 if (fgcal_binary > 60 || fgcal_binary < 3) {
2455 if (offset_range == 3) {
2456 pr_info("%s: Foreground Calibration result marginal!", __func__);
2457 break;
2458 } else {
2459 offset_range++;
2460 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2461 rtl9300_do_rx_calibration_2_2(sds_num);
2462 }
2463 } else {
2464 break;
2465 }
2466 }
2467 pr_info("%s: end_1.2.3\n", __func__);
2468 }
2469
2470 void rtl9300_do_rx_calibration_2(int sds)
2471 {
2472 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2473 rtl9300_do_rx_calibration_2_1(sds);
2474 rtl9300_do_rx_calibration_2_2(sds);
2475 rtl9300_do_rx_calibration_2_3(sds);
2476 }
2477
2478 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2479 {
2480 pr_info("start_1.3.1");
2481
2482 // ##1.3.1
2483 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2484 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2485
2486 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2487 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2488
2489 pr_info("end_1.3.1");
2490 }
2491
2492 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2493 {
2494 u32 sum10 = 0, avg10, int10;
2495 int dac_long_cable_offset;
2496 bool eq_hold_enabled;
2497 int i;
2498
2499 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2500 // rtl9300_rxCaliConf_serdes_myParam
2501 dac_long_cable_offset = 3;
2502 eq_hold_enabled = true;
2503 } else {
2504 // rtl9300_rxCaliConf_phy_myParam
2505 dac_long_cable_offset = 0;
2506 eq_hold_enabled = false;
2507 }
2508
2509 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2510 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2511
2512 pr_info("start_1.3.2");
2513
2514 for(i = 0; i < 10; i++) {
2515 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2516 mdelay(10);
2517 }
2518
2519 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2520 int10 = sum10 / 10;
2521
2522 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2523
2524 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2525 if (dac_long_cable_offset) {
2526 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2527 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2528 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2529 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2530 } else {
2531 if (sum10 >= 5) {
2532 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2533 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2534 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2535 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2536 } else {
2537 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2538 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2539 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2540 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2541 }
2542 }
2543 }
2544
2545 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2546
2547 pr_info("end_1.3.2");
2548 }
2549
2550 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2551 {
2552 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2553
2554 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2555 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2556 }
2557
2558 void rtl9300_do_rx_calibration_4_1(int sds_num)
2559 {
2560 u32 vth_list[2] = {0, 0};
2561 u32 tap0_list[4] = {0, 0, 0, 0};
2562
2563 pr_info("start_1.4.1");
2564
2565 // ##1.4.1
2566 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2567 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2568 mdelay(200);
2569
2570 pr_info("end_1.4.1");
2571 }
2572
2573 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2574 {
2575 u32 vth_list[2];
2576 u32 tap_list[4];
2577
2578 pr_info("start_1.4.2");
2579
2580 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2581 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2582
2583 mdelay(100);
2584
2585 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2586 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2587
2588 pr_info("end_1.4.2");
2589 }
2590
2591 void rtl9300_do_rx_calibration_4(u32 sds_num)
2592 {
2593 rtl9300_do_rx_calibration_4_1(sds_num);
2594 rtl9300_do_rx_calibration_4_2(sds_num);
2595 }
2596
2597 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2598 {
2599 u32 tap1_list[4] = {0};
2600 u32 tap2_list[4] = {0};
2601 u32 tap3_list[4] = {0};
2602 u32 tap4_list[4] = {0};
2603
2604 pr_info("start_1.5.2");
2605
2606 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2607 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2608 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2609 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2610
2611 mdelay(30);
2612
2613 pr_info("end_1.5.2");
2614 }
2615
2616 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2617 {
2618 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true
2619 rtl9300_do_rx_calibration_5_2(sds_num);
2620 }
2621
2622
2623 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2624 {
2625 u32 tap1_list[4] = {0};
2626 u32 tap2_list[4] = {0};
2627 u32 tap3_list[4] = {0};
2628 u32 tap4_list[4] = {0};
2629
2630 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2631 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2632 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2633 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2634
2635 mdelay(10);
2636 }
2637
2638 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2639 {
2640 u32 latch_sts;
2641
2642 rtl9300_do_rx_calibration_1(sds, phy_mode);
2643 rtl9300_do_rx_calibration_2(sds);
2644 rtl9300_do_rx_calibration_4(sds);
2645 rtl9300_do_rx_calibration_5(sds, phy_mode);
2646 mdelay(20);
2647
2648 // Do this only for 10GR mode, SDS active in mode 0x1a
2649 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2650 pr_info("%s: SDS enabled\n", __func__);
2651 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2652 mdelay(1);
2653 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2654 if (latch_sts) {
2655 rtl9300_do_rx_calibration_dfe_disable(sds);
2656 rtl9300_do_rx_calibration_4(sds);
2657 rtl9300_do_rx_calibration_5(sds, phy_mode);
2658 }
2659 }
2660 }
2661
2662 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2663 {
2664 switch (phy_mode) {
2665 case PHY_INTERFACE_MODE_XGMII:
2666 break;
2667
2668 case PHY_INTERFACE_MODE_10GBASER:
2669 // Read twice to clear
2670 rtl930x_read_sds_phy(sds_num, 5, 1);
2671 rtl930x_read_sds_phy(sds_num, 5, 1);
2672 break;
2673
2674 case PHY_INTERFACE_MODE_1000BASEX:
2675 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2676 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2677 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2678 break;
2679
2680 default:
2681 pr_info("%s unsupported phy mode\n", __func__);
2682 return -1;
2683 }
2684
2685 return 0;
2686 }
2687
2688 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2689 {
2690 u32 v = 0;
2691
2692 switch (phy_mode) {
2693 case PHY_INTERFACE_MODE_XGMII:
2694 break;
2695
2696 case PHY_INTERFACE_MODE_10GBASER:
2697 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2698 return v & 0xff;
2699
2700 default:
2701 pr_info("%s unsupported PHY-mode\n", __func__);
2702 }
2703
2704 return v;
2705 }
2706
2707 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2708 {
2709 u32 errors1, errors2;
2710
2711 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2712 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2713
2714 // Count errors during 1ms
2715 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2716 mdelay(1);
2717 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2718
2719 switch (phy_mode) {
2720 case PHY_INTERFACE_MODE_XGMII:
2721
2722 if ((errors2 - errors1 > 100) ||
2723 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2724 pr_info("%s XSGMII error rate too high\n", __func__);
2725 return 1;
2726 }
2727 break;
2728 case PHY_INTERFACE_MODE_10GBASER:
2729 if (errors2 > 0) {
2730 pr_info("%s 10GBASER error rate too high\n", __func__);
2731 return 1;
2732 }
2733 break;
2734 default:
2735 return 1;
2736 }
2737
2738 return 0;
2739 }
2740
2741 void rtl9300_phy_enable_10g_1g(int sds_num)
2742 {
2743 u32 v;
2744
2745 // Enable 1GBit PHY
2746 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);
2747 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2748 v &= ~BIT(PHY_POWER_BIT);
2749 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);
2750 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2751
2752 // Enable 10GBit PHY
2753 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);
2754 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2755 v &= ~BIT(PHY_POWER_BIT);
2756 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);
2757 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2758
2759 // dal_longan_construct_mac_default_10gmedia_fiber
2760 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2761 pr_info("%s set medium: %08x\n", __func__, v);
2762 v |= BIT(1);
2763 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2764 pr_info("%s set medium after: %08x\n", __func__, v);
2765 }
2766
2767 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2768 // phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a
2769 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2770 {
2771 int sds_mode;
2772 int calib_tries = 0;
2773
2774 switch (phy_mode) {
2775 case PHY_INTERFACE_MODE_HSGMII:
2776 sds_mode = 0x12;
2777 break;
2778 case PHY_INTERFACE_MODE_1000BASEX:
2779 sds_mode = 0x04;
2780 break;
2781 case PHY_INTERFACE_MODE_XGMII:
2782 sds_mode = 0x10;
2783 break;
2784 case PHY_INTERFACE_MODE_10GBASER:
2785 sds_mode = 0x1a;
2786 break;
2787 case PHY_INTERFACE_MODE_USXGMII:
2788 sds_mode = 0x0d;
2789 break;
2790 default:
2791 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2792 return -EINVAL;
2793 }
2794
2795 // Maybe use dal_longan_sds_init
2796
2797 // dal_longan_construct_serdesConfig_init // Serdes Construct
2798 rtl9300_phy_enable_10g_1g(sds_num);
2799
2800 // Set Serdes Mode
2801 rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO
2802
2803 // Do RX calibration
2804 do {
2805 rtl9300_do_rx_calibration(sds_num, phy_mode);
2806 calib_tries++;
2807 mdelay(50);
2808 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2809
2810
2811 return 0;
2812 }
2813
2814 typedef struct {
2815 u8 page;
2816 u8 reg;
2817 u16 data;
2818 } sds_config;
2819
2820 sds_config rtl9300_a_sds_10gr_lane0[] =
2821 {
2822 /* 1G */
2823 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2824 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2825 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2826 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2827 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2828 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2829 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2830 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2831 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2832 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2833 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2834 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2835 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2836 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2837 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2838 {0x2F, 0x1D, 0x66E1},
2839 /* 3.125G */
2840 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2841 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2842 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2843 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2844 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2845 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2846 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2847 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2848 /* 10G */
2849 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2850 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2851 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2852 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2853 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2854 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2855 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2856 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2857 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2858 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2859 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2860 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2861 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2862 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2863 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2864 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2865 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2866 };
2867
2868 sds_config rtl9300_a_sds_10gr_lane1[] =
2869 {
2870 /* 1G */
2871 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2872 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2873 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2874 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2875 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2876 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2877 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2878 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2879 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2880 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2881 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2882 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2883 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2884 {0x2D, 0x14, 0x1808},
2885 /* 3.125G */
2886 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2887 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2888 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2889 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2890 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2891 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2892 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2893 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2894 /* 10G */
2895 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2896 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2897 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2898 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2899 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2900 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2901 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2902 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2903 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2904 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2905 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2906 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2907 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2908 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2909 };
2910
2911 int rtl9300_sds_cmu_band_get(int sds)
2912 {
2913 u32 page;
2914 u32 en;
2915 u32 cmu_band;
2916
2917 // page = rtl9300_sds_cmu_page_get(sds);
2918 page = 0x25; // 10GR and 1000BX
2919 sds = (sds % 2) ? (sds - 1) : (sds);
2920
2921 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2922 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2923
2924 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2925 if(!en) { // Auto mode
2926 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2927
2928 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2929 } else {
2930 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2931 }
2932
2933 return cmu_band;
2934 }
2935
2936 int rtl9300_configure_serdes(struct phy_device *phydev)
2937 {
2938 struct device *dev = &phydev->mdio.dev;
2939 int phy_addr = phydev->mdio.addr;
2940 struct device_node *dn;
2941 u32 sds_num = 0;
2942 int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i;
2943
2944 if (dev->of_node) {
2945 dn = dev->of_node;
2946
2947 if (of_property_read_u32(dn, "sds", &sds_num))
2948 sds_num = -1;
2949 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2950 } else {
2951 dev_err(dev, "No DT node.\n");
2952 return -EINVAL;
2953 }
2954
2955 if (sds_num < 0)
2956 return 0;
2957
2958 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes
2959 return 0;
2960
2961 switch (phy_mode) {
2962 case PHY_INTERFACE_MODE_HSGMII:
2963 sds_mode = 0x12;
2964 break;
2965 case PHY_INTERFACE_MODE_1000BASEX:
2966 sds_mode = 0x04;
2967 break;
2968 case PHY_INTERFACE_MODE_XGMII:
2969 sds_mode = 0x10;
2970 break;
2971 case PHY_INTERFACE_MODE_10GBASER:
2972 sds_mode = 0x1a;
2973 break;
2974 case PHY_INTERFACE_MODE_USXGMII:
2975 sds_mode = 0x0d;
2976 break;
2977 default:
2978 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2979 return -EINVAL;
2980 }
2981
2982 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
2983
2984 // Turn Off Serdes
2985 rtl9300_sds_rst(sds_num, 0x1f);
2986
2987 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
2988 if (sds_num % 2) {
2989 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2990 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2991 rtl9300_a_sds_10gr_lane1[i].reg,
2992 rtl9300_a_sds_10gr_lane1[i].data);
2993 }
2994 } else {
2995 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
2996 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
2997 rtl9300_a_sds_10gr_lane0[i].reg,
2998 rtl9300_a_sds_10gr_lane0[i].data);
2999 }
3000 }
3001
3002 rtl9300_phy_enable_10g_1g(sds_num);
3003
3004 // Disable MAC
3005 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3006 mdelay(20);
3007
3008 // ----> dal_longan_sds_mode_set
3009 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3010
3011 // Configure link to MAC
3012 rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct
3013
3014 // Disable MAC
3015 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3016 mdelay(20);
3017
3018 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3019
3020 // Re-Enable MAC
3021 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3022
3023 rtl9300_force_sds_mode(sds_num, phy_mode);
3024
3025 // Do RX calibration
3026 do {
3027 rtl9300_do_rx_calibration(sds_num, phy_mode);
3028 calib_tries++;
3029 mdelay(50);
3030 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3031
3032 if (calib_tries >= 3)
3033 pr_err("%s CALIBTRATION FAILED\n", __func__);
3034
3035 rtl9300_sds_tx_config(sds_num, phy_mode);
3036
3037 // The clock needs only to be configured on the FPGA implementation
3038
3039 return 0;
3040 }
3041
3042 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3043 {
3044 int l = end_bit - start_bit + 1;
3045 u32 data = v;
3046
3047 if (l < 32) {
3048 u32 mask = BIT(l) - 1;
3049
3050 data = rtl930x_read_sds_phy(sds, page, reg);
3051 data &= ~(mask << start_bit);
3052 data |= (v & mask) << start_bit;
3053 }
3054
3055 rtl931x_write_sds_phy(sds, page, reg, data);
3056 }
3057
3058 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3059 {
3060 int l = end_bit - start_bit + 1;
3061 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3062
3063 if (l >= 32)
3064 return v;
3065
3066 return (v >> start_bit) & (BIT(l) - 1);
3067 }
3068
3069 static void rtl931x_sds_rst(u32 sds)
3070 {
3071 u32 o, v, o_mode;
3072 int shift = ((sds & 0x3) << 3);
3073
3074 // TODO: We need to lock this!
3075
3076 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3077 v = o | BIT(sds);
3078 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3079
3080 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3081 v = BIT(7) | 0x1F;
3082 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3083 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3084
3085 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3086 }
3087
3088 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3089 {
3090 u32 i;
3091 u32 xsg_sdsid_0, xsg_sdsid_1;
3092
3093 switch (mode) {
3094 case PHY_INTERFACE_MODE_NA:
3095 break;
3096 case PHY_INTERFACE_MODE_XGMII:
3097 if (sds < 2)
3098 xsg_sdsid_0 = sds;
3099 else
3100 xsg_sdsid_0 = (sds - 1) * 2;
3101 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3102
3103 for (i = 0; i < 4; ++i) {
3104 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3105 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3106 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3107 }
3108
3109 for (i = 0; i < 4; ++i) {
3110 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3111 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3112 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3113 }
3114
3115 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3116 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3117 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3118 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3119 break;
3120 default:
3121 break;
3122 }
3123
3124 return;
3125 }
3126
3127 static u32 rtl931x_get_analog_sds(u32 sds)
3128 {
3129 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3130
3131 if (sds < 14)
3132 return sds_map[sds];
3133
3134 return sds;
3135 }
3136
3137 void rtl931x_sds_fiber_disable(u32 sds)
3138 {
3139 u32 v = 0x3F;
3140 u32 asds = rtl931x_get_analog_sds(sds);
3141
3142 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3143 }
3144
3145 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3146 {
3147 u32 val, asds = rtl931x_get_analog_sds(sds);
3148
3149 /* clear symbol error count before changing mode */
3150 rtl931x_symerr_clear(sds, mode);
3151
3152 val = 0x9F;
3153 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3154
3155 switch (mode) {
3156 case PHY_INTERFACE_MODE_SGMII:
3157 val = 0x5;
3158 break;
3159
3160 case PHY_INTERFACE_MODE_1000BASEX:
3161 /* serdes mode FIBER1G */
3162 val = 0x9;
3163 break;
3164
3165 case PHY_INTERFACE_MODE_10GBASER:
3166 case PHY_INTERFACE_MODE_10GKR:
3167 val = 0x35;
3168 break;
3169 /* case MII_10GR1000BX_AUTO:
3170 val = 0x39;
3171 break; */
3172
3173
3174 case PHY_INTERFACE_MODE_USXGMII:
3175 val = 0x1B;
3176 break;
3177 default:
3178 val = 0x25;
3179 }
3180
3181 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3182 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3183
3184 return;
3185 }
3186
3187 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3188 {
3189 switch (mode) {
3190 case PHY_INTERFACE_MODE_SGMII:
3191 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO
3192 return 0x24;
3193 case PHY_INTERFACE_MODE_HSGMII:
3194 case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X:
3195 return 0x28;
3196 // case MII_HISGMII_5G:
3197 // return 0x2a;
3198 case PHY_INTERFACE_MODE_QSGMII:
3199 return 0x2a; // Code also has 0x34
3200 case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE:
3201 return 0x2c;
3202 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3203 case PHY_INTERFACE_MODE_10GKR:
3204 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR
3205 return 0x2e;
3206 default:
3207 return -1;
3208 }
3209
3210 return -1;
3211 }
3212
3213 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3214 {
3215 int cmu_type = 0; // Clock Management Unit
3216 u32 cmu_page = 0;
3217 u32 frc_cmu_spd;
3218 u32 evenSds;
3219 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3220
3221 switch (mode) {
3222 case PHY_INTERFACE_MODE_NA:
3223 case PHY_INTERFACE_MODE_10GKR:
3224 case PHY_INTERFACE_MODE_XGMII:
3225 case PHY_INTERFACE_MODE_10GBASER:
3226 case PHY_INTERFACE_MODE_USXGMII:
3227 return;
3228
3229 /* case MII_10GR1000BX_AUTO:
3230 if (chiptype)
3231 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3232 return; */
3233
3234 case PHY_INTERFACE_MODE_QSGMII:
3235 cmu_type = 1;
3236 frc_cmu_spd = 0;
3237 break;
3238
3239 case PHY_INTERFACE_MODE_HSGMII:
3240 cmu_type = 1;
3241 frc_cmu_spd = 1;
3242 break;
3243
3244 case PHY_INTERFACE_MODE_1000BASEX:
3245 cmu_type = 1;
3246 frc_cmu_spd = 0;
3247 break;
3248
3249 /* case MII_1000BX100BX_AUTO:
3250 cmu_type = 1;
3251 frc_cmu_spd = 0;
3252 break; */
3253
3254 case PHY_INTERFACE_MODE_SGMII:
3255 cmu_type = 1;
3256 frc_cmu_spd = 0;
3257 break;
3258
3259 case PHY_INTERFACE_MODE_2500BASEX:
3260 cmu_type = 1;
3261 frc_cmu_spd = 1;
3262 break;
3263
3264 default:
3265 pr_info("SerDes %d mode is invalid\n", asds);
3266 return;
3267 }
3268
3269 if (cmu_type == 1)
3270 cmu_page = rtl931x_sds_cmu_page_get(mode);
3271
3272 lane = asds % 2;
3273
3274 if (!lane) {
3275 frc_lc_mode_bitnum = 4;
3276 frc_lc_mode_val_bitnum = 5;
3277 } else {
3278 frc_lc_mode_bitnum = 6;
3279 frc_lc_mode_val_bitnum = 7;
3280 }
3281
3282 evenSds = asds - lane;
3283
3284 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3285 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3286
3287 if (cmu_type == 1) {
3288 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3289 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3290 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3291 if (chiptype) {
3292 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3293 }
3294
3295 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3296 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3297 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3298 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3299 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3300 }
3301
3302 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3303 return;
3304 }
3305
3306 static void rtl931x_sds_rx_rst(u32 sds)
3307 {
3308 u32 asds = rtl931x_get_analog_sds(sds);
3309
3310 if (sds < 2)
3311 return;
3312
3313 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3314 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3315 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3316 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3317
3318 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3319 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3320 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3321 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3322
3323 mdelay(50);
3324 }
3325
3326 static void rtl931x_sds_disable(u32 sds)
3327 {
3328 u32 v = 0x1f;
3329
3330 v |= BIT(7);
3331 sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3332 }
3333
3334 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3335 {
3336 u32 val;
3337
3338 switch (mode) {
3339 case PHY_INTERFACE_MODE_QSGMII:
3340 val = 0x6;
3341 break;
3342 case PHY_INTERFACE_MODE_XGMII:
3343 val = 0x10; // serdes mode XSGMII
3344 break;
3345 case PHY_INTERFACE_MODE_USXGMII:
3346 case PHY_INTERFACE_MODE_2500BASEX:
3347 val = 0xD;
3348 break;
3349 case PHY_INTERFACE_MODE_HSGMII:
3350 val = 0x12;
3351 break;
3352 case PHY_INTERFACE_MODE_SGMII:
3353 val = 0x2;
3354 break;
3355 default:
3356 return;
3357 }
3358
3359 val |= (1 << 7);
3360
3361 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3362 }
3363
3364 static sds_config sds_config_10p3125g_type1[] = {
3365 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3366 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3367 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3368 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3369 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3370 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3371 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3372 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3373 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3374 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3375 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3376 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3377 { 0x2F, 0x13, 0x0000 }
3378 };
3379
3380 static sds_config sds_config_10p3125g_cmu_type1[] = {
3381 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3382 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3383 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3384 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3385 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3386 };
3387
3388 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3389 {
3390 u32 board_sds_tx_type1[] = {
3391 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3392 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3393 };
3394 u32 board_sds_tx[] = {
3395 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3396 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3397 };
3398 u32 board_sds_tx2[] = {
3399 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3400 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3401 };
3402 u32 asds, dSds, ori, model_info, val;
3403 int chiptype = 0;
3404
3405 asds = rtl931x_get_analog_sds(sds);
3406
3407 if (sds > 13)
3408 return;
3409
3410 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3411 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3412
3413 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3414 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3415 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3416 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3417 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3418 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3419 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3420 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3421 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3422 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3423 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3424 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3425
3426 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3427 if ((model_info >> 4) & 0x1) {
3428 pr_info("detected chiptype 1\n");
3429 chiptype = 1;
3430 } else {
3431 pr_info("detected chiptype 0\n");
3432 }
3433
3434 if (sds < 2)
3435 dSds = sds;
3436 else
3437 dSds = (sds - 1) * 2;
3438
3439 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3440 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3441
3442 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3443 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3444 val = ori | (1 << sds);
3445 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3446
3447 switch (mode) {
3448 case PHY_INTERFACE_MODE_NA:
3449 break;
3450
3451 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3452
3453 if (chiptype) {
3454 u32 xsg_sdsid_1;
3455 xsg_sdsid_1 = dSds + 1;
3456 //fifo inv clk
3457 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3458 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3459
3460 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3461 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3462
3463 }
3464
3465 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3466 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3467 break;
3468
3469 case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:
3470 u32 i, evenSds;
3471 u32 op_code = 0x6003;
3472
3473 if (chiptype) {
3474 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3475
3476 for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3477 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3478 }
3479
3480 evenSds = asds - (asds % 2);
3481
3482 for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3483 rtl931x_write_sds_phy(evenSds,
3484 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3485 }
3486
3487 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3488 } else {
3489
3490 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3491 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3492
3493 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3494 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3495 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3496 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3497 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3498
3499 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3500 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3501
3502 rtl931x_sds_rx_rst(sds);
3503
3504 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3505 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3506 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3507 }
3508 break;
3509
3510 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO:
3511 // configure 10GR fiber mode=1
3512 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3513
3514 // init fiber_1g
3515 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3516
3517 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3518 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3519 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3520
3521 // init auto
3522 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3523 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3524 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3525 break;
3526
3527 case PHY_INTERFACE_MODE_HSGMII:
3528 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3529 break;
3530
3531 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER
3532 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3533
3534 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3535 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3536 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3537 break;
3538
3539 case PHY_INTERFACE_MODE_SGMII:
3540 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3541 break;
3542
3543 case PHY_INTERFACE_MODE_2500BASEX:
3544 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3545 break;
3546
3547 case PHY_INTERFACE_MODE_QSGMII:
3548 default:
3549 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3550 __func__, phy_modes(mode), sds);
3551 return;
3552 }
3553
3554 rtl931x_cmu_type_set(asds, mode, chiptype);
3555
3556 if (sds >= 2 && sds <= 13) {
3557 if (chiptype)
3558 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3559 else {
3560 val = 0xa0000;
3561 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3562 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3563 if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))
3564 {
3565 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3566 } else {
3567 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3568 }
3569 val = 0;
3570 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3571 }
3572 }
3573
3574 val = ori & ~BIT(sds);
3575 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3576 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3577
3578 if (mode == PHY_INTERFACE_MODE_XGMII ||
3579 mode == PHY_INTERFACE_MODE_QSGMII ||
3580 mode == PHY_INTERFACE_MODE_HSGMII ||
3581 mode == PHY_INTERFACE_MODE_SGMII ||
3582 mode == PHY_INTERFACE_MODE_USXGMII) {
3583 if (mode == PHY_INTERFACE_MODE_XGMII)
3584 rtl931x_sds_mii_mode_set(sds, mode);
3585 else
3586 rtl931x_sds_fiber_mode_set(sds, mode);
3587 }
3588 }
3589
3590 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3591 {
3592 u32 asds;
3593 int page = rtl931x_sds_cmu_page_get(mode);
3594
3595 sds -= (sds % 2);
3596 sds = sds & ~1;
3597 asds = rtl931x_get_analog_sds(sds);
3598 page += 1;
3599
3600 if (enable) {
3601 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3602 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3603 } else {
3604 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3605 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3606 }
3607
3608 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3609
3610 rtl931x_sds_rst(sds);
3611
3612 return 0;
3613 }
3614
3615 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3616 {
3617 int page = rtl931x_sds_cmu_page_get(mode);
3618 u32 asds, band;
3619
3620 sds -= (sds % 2);
3621 asds = rtl931x_get_analog_sds(sds);
3622 page += 1;
3623 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3624
3625 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3626 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3627 pr_info("%s band is: %d\n", __func__, band);
3628
3629 return band;
3630 }
3631
3632
3633 int rtl931x_link_sts_get(u32 sds)
3634 {
3635 u32 sts, sts1, latch_sts, latch_sts1;
3636 if (0){
3637 u32 xsg_sdsid_0, xsg_sdsid_1;
3638
3639 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3640 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3641
3642 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3643 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3644 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3645 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3646 } else {
3647 u32 asds, dsds;
3648
3649 asds = rtl931x_get_analog_sds(sds);
3650 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3651 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3652
3653 dsds = sds < 2 ? sds : (sds - 1) * 2;
3654 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3655 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3656 }
3657
3658 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3659 sds, sts, sts1, latch_sts, latch_sts1);
3660
3661 return sts1;
3662 }
3663
3664 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3665 {
3666 struct phy_device *phydev = upstream;
3667
3668 rtl8214fc_media_set(phydev, true);
3669
3670 return 0;
3671 }
3672
3673 static void rtl8214fc_sfp_remove(void *upstream)
3674 {
3675 struct phy_device *phydev = upstream;
3676
3677 rtl8214fc_media_set(phydev, false);
3678 }
3679
3680 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3681 .attach = phy_sfp_attach,
3682 .detach = phy_sfp_detach,
3683 .module_insert = rtl8214fc_sfp_insert,
3684 .module_remove = rtl8214fc_sfp_remove,
3685 };
3686
3687 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3688 {
3689 struct device *dev = &phydev->mdio.dev;
3690 int addr = phydev->mdio.addr;
3691 int ret = 0;
3692
3693 /* 839x has internal SerDes */
3694 if (soc_info.id == 0x8393)
3695 return -ENODEV;
3696
3697 /* All base addresses of the PHYs start at multiples of 8 */
3698 devm_phy_package_join(dev, phydev, addr & (~7),
3699 sizeof(struct rtl83xx_shared_private));
3700
3701 if (!(addr % 8)) {
3702 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3703 shared->name = "RTL8214FC";
3704 /* Configuration must be done while patching still possible */
3705 ret = rtl8380_configure_rtl8214fc(phydev);
3706 if (ret)
3707 return ret;
3708 }
3709
3710 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3711 }
3712
3713 static int rtl8214c_phy_probe(struct phy_device *phydev)
3714 {
3715 struct device *dev = &phydev->mdio.dev;
3716 int addr = phydev->mdio.addr;
3717
3718 /* All base addresses of the PHYs start at multiples of 8 */
3719 devm_phy_package_join(dev, phydev, addr & (~7),
3720 sizeof(struct rtl83xx_shared_private));
3721
3722 if (!(addr % 8)) {
3723 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3724 shared->name = "RTL8214C";
3725 /* Configuration must be done whil patching still possible */
3726 return rtl8380_configure_rtl8214c(phydev);
3727 }
3728
3729 return 0;
3730 }
3731
3732 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3733 {
3734 struct device *dev = &phydev->mdio.dev;
3735 int addr = phydev->mdio.addr;
3736
3737 /* All base addresses of the PHYs start at multiples of 8 */
3738 devm_phy_package_join(dev, phydev, addr & (~7),
3739 sizeof(struct rtl83xx_shared_private));
3740
3741 if (!(addr % 8)) {
3742 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3743 shared->name = "RTL8218B (external)";
3744 if (soc_info.family == RTL8380_FAMILY_ID) {
3745 /* Configuration must be done while patching still possible */
3746 return rtl8380_configure_ext_rtl8218b(phydev);
3747 }
3748 }
3749
3750 return 0;
3751 }
3752
3753 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3754 {
3755 struct device *dev = &phydev->mdio.dev;
3756 int addr = phydev->mdio.addr;
3757
3758 if (soc_info.family != RTL8380_FAMILY_ID)
3759 return -ENODEV;
3760 if (addr >= 24)
3761 return -ENODEV;
3762
3763 pr_debug("%s: id: %d\n", __func__, addr);
3764 /* All base addresses of the PHYs start at multiples of 8 */
3765 devm_phy_package_join(dev, phydev, addr & (~7),
3766 sizeof(struct rtl83xx_shared_private));
3767
3768 if (!(addr % 8)) {
3769 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3770 shared->name = "RTL8218B (internal)";
3771 /* Configuration must be done while patching still possible */
3772 return rtl8380_configure_int_rtl8218b(phydev);
3773 }
3774
3775 return 0;
3776 }
3777
3778 static int rtl8218d_phy_probe(struct phy_device *phydev)
3779 {
3780 struct device *dev = &phydev->mdio.dev;
3781 int addr = phydev->mdio.addr;
3782
3783 pr_debug("%s: id: %d\n", __func__, addr);
3784 /* All base addresses of the PHYs start at multiples of 8 */
3785 devm_phy_package_join(dev, phydev, addr & (~7),
3786 sizeof(struct rtl83xx_shared_private));
3787
3788 /* All base addresses of the PHYs start at multiples of 8 */
3789 if (!(addr % 8)) {
3790 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3791 shared->name = "RTL8218D";
3792 /* Configuration must be done while patching still possible */
3793 // TODO: return configure_rtl8218d(phydev);
3794 }
3795
3796 return 0;
3797 }
3798
3799 static int rtl838x_serdes_probe(struct phy_device *phydev)
3800 {
3801 int addr = phydev->mdio.addr;
3802
3803 if (soc_info.family != RTL8380_FAMILY_ID)
3804 return -ENODEV;
3805 if (addr < 24)
3806 return -ENODEV;
3807
3808 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3809 if (soc_info.id == 0x8380) {
3810 if (addr == 24)
3811 return rtl8380_configure_serdes(phydev);
3812 return 0;
3813 }
3814
3815 return -ENODEV;
3816 }
3817
3818 static int rtl8393_serdes_probe(struct phy_device *phydev)
3819 {
3820 int addr = phydev->mdio.addr;
3821
3822 pr_info("%s: id: %d\n", __func__, addr);
3823 if (soc_info.family != RTL8390_FAMILY_ID)
3824 return -ENODEV;
3825
3826 if (addr < 24)
3827 return -ENODEV;
3828
3829 return rtl8390_configure_serdes(phydev);
3830 }
3831
3832 static int rtl8390_serdes_probe(struct phy_device *phydev)
3833 {
3834 int addr = phydev->mdio.addr;
3835
3836 if (soc_info.family != RTL8390_FAMILY_ID)
3837 return -ENODEV;
3838
3839 if (addr < 24)
3840 return -ENODEV;
3841
3842 return rtl8390_configure_generic(phydev);
3843 }
3844
3845 static int rtl9300_serdes_probe(struct phy_device *phydev)
3846 {
3847 if (soc_info.family != RTL9300_FAMILY_ID)
3848 return -ENODEV;
3849
3850 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3851
3852 return rtl9300_configure_serdes(phydev);
3853 }
3854
3855 static struct phy_driver rtl83xx_phy_driver[] = {
3856 {
3857 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3858 .name = "Realtek RTL8214C",
3859 .features = PHY_GBIT_FEATURES,
3860 .flags = PHY_HAS_REALTEK_PAGES,
3861 .match_phy_device = rtl8214c_match_phy_device,
3862 .probe = rtl8214c_phy_probe,
3863 .suspend = genphy_suspend,
3864 .resume = genphy_resume,
3865 .set_loopback = genphy_loopback,
3866 },
3867 {
3868 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3869 .name = "Realtek RTL8214FC",
3870 .features = PHY_GBIT_FIBRE_FEATURES,
3871 .flags = PHY_HAS_REALTEK_PAGES,
3872 .match_phy_device = rtl8214fc_match_phy_device,
3873 .probe = rtl8214fc_phy_probe,
3874 .suspend = rtl8214fc_suspend,
3875 .resume = rtl8214fc_resume,
3876 .set_loopback = genphy_loopback,
3877 .set_port = rtl8214fc_set_port,
3878 .get_port = rtl8214fc_get_port,
3879 .set_eee = rtl8214fc_set_eee,
3880 .get_eee = rtl8214fc_get_eee,
3881 },
3882 {
3883 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3884 .name = "Realtek RTL8218B (external)",
3885 .features = PHY_GBIT_FEATURES,
3886 .flags = PHY_HAS_REALTEK_PAGES,
3887 .match_phy_device = rtl8218b_ext_match_phy_device,
3888 .probe = rtl8218b_ext_phy_probe,
3889 .suspend = genphy_suspend,
3890 .resume = genphy_resume,
3891 .set_loopback = genphy_loopback,
3892 .set_eee = rtl8218b_set_eee,
3893 .get_eee = rtl8218b_get_eee,
3894 },
3895 {
3896 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3897 .name = "REALTEK RTL8218D",
3898 .features = PHY_GBIT_FEATURES,
3899 .flags = PHY_HAS_REALTEK_PAGES,
3900 .probe = rtl8218d_phy_probe,
3901 .suspend = genphy_suspend,
3902 .resume = genphy_resume,
3903 .set_loopback = genphy_loopback,
3904 .set_eee = rtl8218d_set_eee,
3905 .get_eee = rtl8218d_get_eee,
3906 },
3907 {
3908 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3909 .name = "REALTEK RTL8221B",
3910 .features = PHY_GBIT_FEATURES,
3911 .flags = PHY_HAS_REALTEK_PAGES,
3912 .suspend = genphy_suspend,
3913 .resume = genphy_resume,
3914 .set_loopback = genphy_loopback,
3915 .read_page = rtl8226_read_page,
3916 .write_page = rtl8226_write_page,
3917 .read_status = rtl8226_read_status,
3918 .config_aneg = rtl8226_config_aneg,
3919 .set_eee = rtl8226_set_eee,
3920 .get_eee = rtl8226_get_eee,
3921 },
3922 {
3923 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3924 .name = "REALTEK RTL8226",
3925 .features = PHY_GBIT_FEATURES,
3926 .flags = PHY_HAS_REALTEK_PAGES,
3927 .suspend = genphy_suspend,
3928 .resume = genphy_resume,
3929 .set_loopback = genphy_loopback,
3930 .read_page = rtl8226_read_page,
3931 .write_page = rtl8226_write_page,
3932 .read_status = rtl8226_read_status,
3933 .config_aneg = rtl8226_config_aneg,
3934 .set_eee = rtl8226_set_eee,
3935 .get_eee = rtl8226_get_eee,
3936 },
3937 {
3938 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3939 .name = "Realtek RTL8218B (internal)",
3940 .features = PHY_GBIT_FEATURES,
3941 .flags = PHY_HAS_REALTEK_PAGES,
3942 .probe = rtl8218b_int_phy_probe,
3943 .suspend = genphy_suspend,
3944 .resume = genphy_resume,
3945 .set_loopback = genphy_loopback,
3946 .set_eee = rtl8218b_set_eee,
3947 .get_eee = rtl8218b_get_eee,
3948 },
3949 {
3950 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3951 .name = "Realtek RTL8380 SERDES",
3952 .features = PHY_GBIT_FIBRE_FEATURES,
3953 .flags = PHY_HAS_REALTEK_PAGES,
3954 .probe = rtl838x_serdes_probe,
3955 .suspend = genphy_suspend,
3956 .resume = genphy_resume,
3957 .set_loopback = genphy_loopback,
3958 .read_status = rtl8380_read_status,
3959 },
3960 {
3961 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3962 .name = "Realtek RTL8393 SERDES",
3963 .features = PHY_GBIT_FIBRE_FEATURES,
3964 .flags = PHY_HAS_REALTEK_PAGES,
3965 .probe = rtl8393_serdes_probe,
3966 .suspend = genphy_suspend,
3967 .resume = genphy_resume,
3968 .set_loopback = genphy_loopback,
3969 .read_status = rtl8393_read_status,
3970 },
3971 {
3972 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3973 .name = "Realtek RTL8390 Generic",
3974 .features = PHY_GBIT_FIBRE_FEATURES,
3975 .flags = PHY_HAS_REALTEK_PAGES,
3976 .probe = rtl8390_serdes_probe,
3977 .suspend = genphy_suspend,
3978 .resume = genphy_resume,
3979 .set_loopback = genphy_loopback,
3980 },
3981 {
3982 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3983 .name = "REALTEK RTL9300 SERDES",
3984 .features = PHY_GBIT_FIBRE_FEATURES,
3985 .flags = PHY_HAS_REALTEK_PAGES,
3986 .probe = rtl9300_serdes_probe,
3987 .suspend = genphy_suspend,
3988 .resume = genphy_resume,
3989 .set_loopback = genphy_loopback,
3990 .read_status = rtl9300_read_status,
3991 },
3992 };
3993
3994 module_phy_driver(rtl83xx_phy_driver);
3995
3996 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
3997 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
3998 { }
3999 };
4000
4001 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
4002
4003 MODULE_AUTHOR("B. Koblitz");
4004 MODULE_DESCRIPTION("RTL83xx PHY driver");
4005 MODULE_LICENSE("GPL");
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