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realtek: 5.15: rtl93xx: add 1000Base-X and 10GBase-CR support on SerDes
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
16 #include <linux/mdio.h>
17
18 #include <asm/mach-rtl838x/mach-rtl83xx.h>
19 #include "rtl83xx-phy.h"
20
21 extern struct rtl83xx_soc_info soc_info;
22 extern struct mutex smi_lock;
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /* Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_MEDIA_PAGE_AUTO 0
50 #define RTL821X_MEDIA_PAGE_COPPER 1
51 #define RTL821X_MEDIA_PAGE_FIBRE 3
52 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53
54 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55
56 /* RTL930X SerDes supports the following modes:
57 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
58 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
59 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
60 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
61 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
62 */
63 #define RTL930X_SDS_MODE_SGMII 0x02
64 #define RTL930X_SDS_MODE_1000BASEX 0x04
65 #define RTL930X_SDS_MODE_USXGMII 0x0d
66 #define RTL930X_SDS_MODE_XGMII 0x10
67 #define RTL930X_SDS_MODE_HSGMII 0x12
68 #define RTL930X_SDS_MODE_2500BASEX 0x16
69 #define RTL930X_SDS_MODE_10GBASER 0x1a
70 #define RTL930X_SDS_OFF 0x1f
71 #define RTL930X_SDS_MASK 0x1f
72
73 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
74 * bus to detect e.g. link and media changes. For operations on the PHYs such as
75 * patching or other configuration changes such as EEE, polling needs to be disabled
76 * since otherwise these operations may fails or lead to unpredictable results.
77 */
78 DEFINE_MUTEX(poll_lock);
79
80 static const struct firmware rtl838x_8380_fw;
81 static const struct firmware rtl838x_8214fc_fw;
82 static const struct firmware rtl838x_8218b_fw;
83
84 static u64 disable_polling(int port)
85 {
86 u64 saved_state;
87
88 mutex_lock(&poll_lock);
89
90 switch (soc_info.family) {
91 case RTL8380_FAMILY_ID:
92 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
93 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
94 break;
95 case RTL8390_FAMILY_ID:
96 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
97 saved_state <<= 32;
98 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
99 sw_w32_mask(BIT(port % 32), 0,
100 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
101 break;
102 case RTL9300_FAMILY_ID:
103 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
104 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
105 break;
106 case RTL9310_FAMILY_ID:
107 pr_warn("%s not implemented for RTL931X\n", __func__);
108 break;
109 }
110
111 mutex_unlock(&poll_lock);
112
113 return saved_state;
114 }
115
116 static int resume_polling(u64 saved_state)
117 {
118 mutex_lock(&poll_lock);
119
120 switch (soc_info.family) {
121 case RTL8380_FAMILY_ID:
122 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
123 break;
124 case RTL8390_FAMILY_ID:
125 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
126 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
127 break;
128 case RTL9300_FAMILY_ID:
129 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
130 break;
131 case RTL9310_FAMILY_ID:
132 pr_warn("%s not implemented for RTL931X\n", __func__);
133 break;
134 }
135
136 mutex_unlock(&poll_lock);
137
138 return 0;
139 }
140
141 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
142 {
143 phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
144 }
145
146 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
147 {
148 /* fiber ports */
149 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
150 phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
151
152 /* copper ports */
153 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
154 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
155 }
156
157 static void rtl8380_phy_reset(struct phy_device *phydev)
158 {
159 phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
160 }
161
162 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
163 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
164 0x02A4, 0x02A4, 0x0198, 0x0198 };
165 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
166
167 /* Reset the SerDes by powering it off and set a new operation mode
168 * of the SerDes.
169 */
170 void rtl9300_sds_rst(int sds_num, u32 mode)
171 {
172 pr_info("%s %d\n", __func__, mode);
173 if (sds_num < 0 || sds_num > 11) {
174 pr_err("Wrong SerDes number: %d\n", sds_num);
175 return;
176 }
177
178 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num],
179 RTL930X_SDS_OFF << rtl9300_sds_lsb[sds_num],
180 rtl9300_sds_regs[sds_num]);
181 mdelay(10);
182
183 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
184 rtl9300_sds_regs[sds_num]);
185 mdelay(10);
186
187 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
188 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
189 }
190
191 void rtl9300_sds_set(int sds_num, u32 mode)
192 {
193 pr_info("%s %d\n", __func__, mode);
194 if (sds_num < 0 || sds_num > 11) {
195 pr_err("Wrong SerDes number: %d\n", sds_num);
196 return;
197 }
198
199 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
200 rtl9300_sds_regs[sds_num]);
201 mdelay(10);
202
203 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
204 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
205 }
206
207 u32 rtl9300_sds_mode_get(int sds_num)
208 {
209 u32 v;
210
211 if (sds_num < 0 || sds_num > 11) {
212 pr_err("Wrong SerDes number: %d\n", sds_num);
213 return 0;
214 }
215
216 v = sw_r32(rtl9300_sds_regs[sds_num]);
217 v >>= rtl9300_sds_lsb[sds_num];
218
219 return v & RTL930X_SDS_MASK;
220 }
221
222 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
223 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
224 */
225 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
226 {
227 int offset = 0;
228 int reg;
229 u32 val;
230
231 if (phy_addr == 49)
232 offset = 0x100;
233
234 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
235 * which would otherwise read as 0.
236 */
237 if (soc_info.id == 0x8393) {
238 if (phy_reg == MII_PHYSID1)
239 return 0x1c;
240 if (phy_reg == MII_PHYSID2)
241 return 0x8393;
242 }
243
244 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
245 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
246 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
247 * one 32 bit register.
248 */
249 reg = (phy_reg << 1) & 0xfc;
250 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
251
252 if (phy_reg & 1)
253 val = (val >> 16) & 0xffff;
254 else
255 val &= 0xffff;
256
257 return val;
258 }
259
260 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
261 * register which simulates commands to an internal MDIO bus.
262 */
263 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
264 {
265 int i;
266 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
267
268 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
269
270 for (i = 0; i < 100; i++) {
271 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
272 break;
273 mdelay(1);
274 }
275
276 if (i >= 100)
277 return -EIO;
278
279 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
280 }
281
282 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
283 {
284 int i;
285 u32 cmd;
286
287 sw_w32(v, RTL930X_SDS_INDACS_DATA);
288 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
289
290 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
291
292 for (i = 0; i < 100; i++) {
293 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
294 break;
295 mdelay(1);
296 }
297
298
299 if (i >= 100) {
300 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
301 return -EIO;
302 }
303
304 return 0;
305 }
306
307 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
308 {
309 int i;
310 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
311
312 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
313 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
314
315 for (i = 0; i < 100; i++) {
316 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
317 break;
318 mdelay(1);
319 }
320
321 if (i >= 100)
322 return -EIO;
323
324 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
325
326 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
327 }
328
329 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
330 {
331 int i;
332 u32 cmd;
333
334 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
335 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
336
337 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
338
339 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
340 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
341
342 for (i = 0; i < 100; i++) {
343 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
344 break;
345 mdelay(1);
346 }
347
348 if (i >= 100)
349 return -EIO;
350
351 return 0;
352 }
353
354 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
355 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
356 * in a standard page 0 of a PHY
357 */
358 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
359 {
360 int offset = 0;
361 u32 val;
362
363 if (phy_addr == 26)
364 offset = 0x100;
365 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
366
367 return val;
368 }
369
370 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
371 {
372 int offset = 0;
373 int reg;
374 u32 val;
375
376 if (phy_addr == 49)
377 offset = 0x100;
378
379 reg = (phy_reg << 1) & 0xfc;
380 val = v;
381 if (phy_reg & 1) {
382 val = val << 16;
383 sw_w32_mask(0xffff0000, val,
384 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
385 } else {
386 sw_w32_mask(0xffff, val,
387 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
388 }
389
390 return 0;
391 }
392
393 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
394 * ports of the RTL838x SoCs
395 */
396 static int rtl8380_read_status(struct phy_device *phydev)
397 {
398 int err;
399
400 err = genphy_read_status(phydev);
401
402 if (phydev->link) {
403 phydev->speed = SPEED_1000;
404 phydev->duplex = DUPLEX_FULL;
405 }
406
407 return err;
408 }
409
410 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
411 * ports of the RTL8393 SoC
412 */
413 static int rtl8393_read_status(struct phy_device *phydev)
414 {
415 int offset = 0;
416 int err;
417 int phy_addr = phydev->mdio.addr;
418 u32 v;
419
420 err = genphy_read_status(phydev);
421 if (phy_addr == 49)
422 offset = 0x100;
423
424 if (phydev->link) {
425 phydev->speed = SPEED_100;
426 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
427 * PHY registers
428 */
429 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
430 if (!(v & (1 << 13)) && (v & (1 << 6)))
431 phydev->speed = SPEED_1000;
432 phydev->duplex = DUPLEX_FULL;
433 }
434
435 return err;
436 }
437
438 static int rtl8226_read_page(struct phy_device *phydev)
439 {
440 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
441 }
442
443 static int rtl8226_write_page(struct phy_device *phydev, int page)
444 {
445 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
446 }
447
448 static int rtl8226_read_status(struct phy_device *phydev)
449 {
450 int ret = 0;
451 u32 val;
452
453 /* TODO: ret = genphy_read_status(phydev);
454 * if (ret < 0) {
455 * pr_info("%s: genphy_read_status failed\n", __func__);
456 * return ret;
457 * }
458 */
459
460 /* Link status must be read twice */
461 for (int i = 0; i < 2; i++)
462 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
463
464 phydev->link = val & BIT(2) ? 1 : 0;
465 if (!phydev->link)
466 goto out;
467
468 /* Read duplex status */
469 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
470 if (val < 0)
471 goto out;
472 phydev->duplex = !!(val & BIT(3));
473
474 /* Read speed */
475 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
476 switch (val & 0x0630) {
477 case 0x0000:
478 phydev->speed = SPEED_10;
479 break;
480 case 0x0010:
481 phydev->speed = SPEED_100;
482 break;
483 case 0x0020:
484 phydev->speed = SPEED_1000;
485 break;
486 case 0x0200:
487 phydev->speed = SPEED_10000;
488 break;
489 case 0x0210:
490 phydev->speed = SPEED_2500;
491 break;
492 case 0x0220:
493 phydev->speed = SPEED_5000;
494 break;
495 default:
496 break;
497 }
498
499 out:
500 return ret;
501 }
502
503 static int rtl8226_advertise_aneg(struct phy_device *phydev)
504 {
505 int ret = 0;
506 u32 v;
507
508 pr_info("In %s\n", __func__);
509
510 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
511 if (v < 0)
512 goto out;
513
514 v |= ADVERTISE_10HALF;
515 v |= ADVERTISE_10FULL;
516 v |= ADVERTISE_100HALF;
517 v |= ADVERTISE_100FULL;
518
519 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
520
521 /* Allow 1GBit */
522 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
523 if (v < 0)
524 goto out;
525 v |= ADVERTISE_1000FULL;
526
527 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
528 if (ret < 0)
529 goto out;
530
531 /* Allow 2.5G */
532 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
533 if (v < 0)
534 goto out;
535
536 v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
537 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
538
539 out:
540 return ret;
541 }
542
543 static int rtl8226_config_aneg(struct phy_device *phydev)
544 {
545 int ret = 0;
546 u32 v;
547
548 pr_debug("In %s\n", __func__);
549 if (phydev->autoneg == AUTONEG_ENABLE) {
550 ret = rtl8226_advertise_aneg(phydev);
551 if (ret)
552 goto out;
553 /* AutoNegotiationEnable */
554 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
555 if (v < 0)
556 goto out;
557
558 v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
559 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
560 if (ret < 0)
561 goto out;
562
563 /* RestartAutoNegotiation */
564 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
565 if (v < 0)
566 goto out;
567 v |= MDIO_AN_CTRL1_RESTART;
568
569 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
570 }
571
572 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
573
574 out:
575 return ret;
576 }
577
578 static int rtl8226_get_eee(struct phy_device *phydev,
579 struct ethtool_eee *e)
580 {
581 u32 val;
582 int addr = phydev->mdio.addr;
583
584 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
585
586 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
587 if (e->eee_enabled) {
588 e->eee_enabled = !!(val & MDIO_EEE_100TX);
589 if (!e->eee_enabled) {
590 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
591 e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
592 }
593 }
594 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
595
596 return 0;
597 }
598
599 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
600 {
601 int port = phydev->mdio.addr;
602 u64 poll_state;
603 bool an_enabled;
604 u32 val;
605
606 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
607
608 poll_state = disable_polling(port);
609
610 /* Remember aneg state */
611 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
612 an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
613
614 /* Setup 100/1000MBit */
615 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
616 if (e->eee_enabled)
617 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
618 else
619 val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
620 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
621
622 /* Setup 2.5GBit */
623 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
624 if (e->eee_enabled)
625 val |= MDIO_EEE_2_5GT;
626 else
627 val &= MDIO_EEE_2_5GT;
628 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
629
630 /* RestartAutoNegotiation */
631 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
632 val |= MDIO_AN_CTRL1_RESTART;
633 phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
634
635 resume_polling(poll_state);
636
637 return 0;
638 }
639
640 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
641 const struct firmware *fw,
642 const char *name)
643 {
644 struct device *dev = &phydev->mdio.dev;
645 int err;
646 struct fw_header *h;
647 uint32_t checksum, my_checksum;
648
649 err = request_firmware(&fw, name, dev);
650 if (err < 0)
651 goto out;
652
653 if (fw->size < sizeof(struct fw_header)) {
654 pr_err("Firmware size too small.\n");
655 err = -EINVAL;
656 goto out;
657 }
658
659 h = (struct fw_header *) fw->data;
660 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
661
662 if (h->magic != 0x83808380) {
663 pr_err("Wrong firmware file: MAGIC mismatch.\n");
664 goto out;
665 }
666
667 checksum = h->checksum;
668 h->checksum = 0;
669 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
670 if (checksum != my_checksum) {
671 pr_err("Firmware checksum mismatch.\n");
672 err = -EINVAL;
673 goto out;
674 }
675 h->checksum = checksum;
676
677 return h;
678 out:
679 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
680 return NULL;
681 }
682
683 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
684 {
685 int mac = phydev->mdio.addr;
686
687 /* select main page 0 */
688 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
689 /* write to 0x8 to register 0x1d on main page 0 */
690 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
691 /* select page 0x266 */
692 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
693 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
694 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
695 /* return to main page 0 */
696 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
697 /* write to 0x0 to register 0x1d on main page 0 */
698 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
699 mdelay(1);
700 }
701
702 static int rtl8390_configure_generic(struct phy_device *phydev)
703 {
704 int mac = phydev->mdio.addr;
705 u32 val, phy_id;
706
707 val = phy_read(phydev, 2);
708 phy_id = val << 16;
709 val = phy_read(phydev, 3);
710 phy_id |= val;
711 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
712
713 /* Read internal PHY ID */
714 phy_write_paged(phydev, 31, 27, 0x0002);
715 val = phy_read_paged(phydev, 31, 28);
716
717 /* Internal RTL8218B, version 2 */
718 phydev_info(phydev, "Detected unknown %x\n", val);
719
720 return 0;
721 }
722
723 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
724 {
725 u32 val, phy_id;
726 int mac = phydev->mdio.addr;
727 struct fw_header *h;
728 u32 *rtl838x_6275B_intPhy_perport;
729 u32 *rtl8218b_6276B_hwEsd_perport;
730
731 val = phy_read(phydev, 2);
732 phy_id = val << 16;
733 val = phy_read(phydev, 3);
734 phy_id |= val;
735 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
736
737 /* Read internal PHY ID */
738 phy_write_paged(phydev, 31, 27, 0x0002);
739 val = phy_read_paged(phydev, 31, 28);
740 if (val != 0x6275) {
741 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
742 return -1;
743 }
744
745 /* Internal RTL8218B, version 2 */
746 phydev_info(phydev, "Detected internal RTL8218B\n");
747
748 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
749 if (!h)
750 return -1;
751
752 if (h->phy != 0x83800000) {
753 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
754 return -1;
755 }
756
757 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
758 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
759
760 // Currently not used
761 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
762 // int ipd_flag = 1;
763 // }
764
765 val = phy_read(phydev, MII_BMCR);
766 if (val & BMCR_PDOWN)
767 rtl8380_int_phy_on_off(phydev, true);
768 else
769 rtl8380_phy_reset(phydev);
770 msleep(100);
771
772 /* Ready PHY for patch */
773 for (int p = 0; p < 8; p++) {
774 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
775 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
776 }
777 msleep(500);
778 for (int p = 0; p < 8; p++) {
779 int i;
780
781 for (i = 0; i < 100 ; i++) {
782 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
783 if (val & 0x40)
784 break;
785 }
786 if (i >= 100) {
787 phydev_err(phydev,
788 "ERROR: Port %d not ready for patch.\n",
789 mac + p);
790 return -1;
791 }
792 }
793 for (int p = 0; p < 8; p++) {
794 int i;
795
796 i = 0;
797 while (rtl838x_6275B_intPhy_perport[i * 2]) {
798 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
799 rtl838x_6275B_intPhy_perport[i * 2],
800 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
801 i++;
802 }
803 i = 0;
804 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
805 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
806 rtl8218b_6276B_hwEsd_perport[i * 2],
807 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
808 i++;
809 }
810 }
811
812 return 0;
813 }
814
815 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
816 {
817 u32 val, ipd, phy_id;
818 int mac = phydev->mdio.addr;
819 struct fw_header *h;
820 u32 *rtl8380_rtl8218b_perchip;
821 u32 *rtl8218B_6276B_rtl8380_perport;
822 u32 *rtl8380_rtl8218b_perport;
823
824 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
825 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
826 return -1;
827 }
828 val = phy_read(phydev, 2);
829 phy_id = val << 16;
830 val = phy_read(phydev, 3);
831 phy_id |= val;
832 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
833
834 /* Read internal PHY ID */
835 phy_write_paged(phydev, 31, 27, 0x0002);
836 val = phy_read_paged(phydev, 31, 28);
837 if (val != 0x6276) {
838 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
839 return -1;
840 }
841 phydev_info(phydev, "Detected external RTL8218B\n");
842
843 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
844 if (!h)
845 return -1;
846
847 if (h->phy != 0x8218b000) {
848 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
849 return -1;
850 }
851
852 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
853 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
854 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
855
856 val = phy_read(phydev, MII_BMCR);
857 if (val & BMCR_PDOWN)
858 rtl8380_int_phy_on_off(phydev, true);
859 else
860 rtl8380_phy_reset(phydev);
861
862 msleep(100);
863
864 /* Get Chip revision */
865 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
866 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
867 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
868
869 phydev_info(phydev, "Detected chip revision %04x\n", val);
870
871 for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
872 rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
873 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
874 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
875 rtl8380_rtl8218b_perchip[i * 3 + 2]);
876 }
877
878 /* Enable PHY */
879 for (int i = 0; i < 8; i++) {
880 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
881 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
882 }
883 mdelay(100);
884
885 /* Request patch */
886 for (int i = 0; i < 8; i++) {
887 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
888 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
889 }
890
891 mdelay(300);
892
893 /* Verify patch readiness */
894 for (int i = 0; i < 8; i++) {
895 int l;
896
897 for (l = 0; l < 100; l++) {
898 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
899 if (val & 0x40)
900 break;
901 }
902 if (l >= 100) {
903 phydev_err(phydev, "Could not patch PHY\n");
904 return -1;
905 }
906 }
907
908 /* Use Broadcast ID method for patching */
909 rtl821x_phy_setup_package_broadcast(phydev, true);
910
911 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
912 phy_write_paged(phydev, 0x26e, 17, 0xb);
913 phy_write_paged(phydev, 0x26e, 16, 0x2);
914 mdelay(1);
915 ipd = phy_read_paged(phydev, 0x26e, 19);
916 phy_write_paged(phydev, 0, 30, 0);
917 ipd = (ipd >> 4) & 0xf; /* unused ? */
918
919 for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
920 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
921 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
922 }
923
924 /* Disable broadcast ID */
925 rtl821x_phy_setup_package_broadcast(phydev, false);
926
927 return 0;
928 }
929
930 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
931 {
932 int addr = phydev->mdio.addr;
933
934 /* Both the RTL8214FC and the external RTL8218B have the same
935 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
936 * at PHY IDs 0-7, while the RTL8214FC must be attached via
937 * the pair of SGMII/1000Base-X with higher PHY-IDs
938 */
939 if (soc_info.family == RTL8380_FAMILY_ID)
940 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
941 else
942 return phydev->phy_id == PHY_ID_RTL8218B_E;
943 }
944
945 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
946 {
947 int mac = phydev->mdio.addr;
948
949 static int reg[] = {16, 19, 20, 21};
950 u32 val;
951
952 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
953 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
954 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
955
956 if (val & BMCR_PDOWN)
957 return false;
958
959 return true;
960 }
961
962 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
963 {
964 char *state = on ? "on" : "off";
965
966 if (port == PORT_FIBRE) {
967 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
968 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
969 } else {
970 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
971 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
972 }
973
974 if (on) {
975 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
976 } else {
977 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
978 }
979
980 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
981 }
982
983 static int rtl8214fc_suspend(struct phy_device *phydev)
984 {
985 rtl8214fc_power_set(phydev, PORT_MII, false);
986 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
987
988 return 0;
989 }
990
991 static int rtl8214fc_resume(struct phy_device *phydev)
992 {
993 if (rtl8214fc_media_is_fibre(phydev)) {
994 rtl8214fc_power_set(phydev, PORT_MII, false);
995 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
996 } else {
997 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
998 rtl8214fc_power_set(phydev, PORT_MII, true);
999 }
1000
1001 return 0;
1002 }
1003
1004 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
1005 {
1006 int mac = phydev->mdio.addr;
1007
1008 static int reg[] = {16, 19, 20, 21};
1009 int val;
1010
1011 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1012 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1013 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1014
1015 val |= BIT(10);
1016 if (set_fibre) {
1017 val &= ~BMCR_PDOWN;
1018 } else {
1019 val |= BMCR_PDOWN;
1020 }
1021
1022 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1023 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1024 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1025
1026 if (!phydev->suspended) {
1027 if (set_fibre) {
1028 rtl8214fc_power_set(phydev, PORT_MII, false);
1029 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1030 } else {
1031 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1032 rtl8214fc_power_set(phydev, PORT_MII, true);
1033 }
1034 }
1035 }
1036
1037 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1038 {
1039 bool is_fibre = (port == PORT_FIBRE ? true : false);
1040 int addr = phydev->mdio.addr;
1041
1042 pr_debug("%s port %d to %d\n", __func__, addr, port);
1043
1044 rtl8214fc_media_set(phydev, is_fibre);
1045
1046 return 0;
1047 }
1048
1049 static int rtl8214fc_get_port(struct phy_device *phydev)
1050 {
1051 int addr = phydev->mdio.addr;
1052
1053 pr_debug("%s: port %d\n", __func__, addr);
1054 if (rtl8214fc_media_is_fibre(phydev))
1055 return PORT_FIBRE;
1056
1057 return PORT_MII;
1058 }
1059
1060 /* Enable EEE on the RTL8218B PHYs
1061 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1062 * but the only way that works since the kernel first enables EEE in the MAC
1063 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1064 */
1065 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1066 {
1067 u32 val;
1068 bool an_enabled;
1069
1070 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1071 /* Set GPHY page to copper */
1072 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1073
1074 val = phy_read(phydev, MII_BMCR);
1075 an_enabled = val & BMCR_ANENABLE;
1076
1077 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1078 val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
1079 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1080
1081 /* 500M EEE ability */
1082 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1083 if (enable)
1084 val |= BIT(7);
1085 else
1086 val &= ~BIT(7);
1087 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1088
1089 /* Restart AN if enabled */
1090 if (an_enabled) {
1091 val = phy_read(phydev, MII_BMCR);
1092 val |= BMCR_ANRESTART;
1093 phy_write(phydev, MII_BMCR, val);
1094 }
1095
1096 /* GPHY page back to auto */
1097 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1098 }
1099
1100 static int rtl8218b_get_eee(struct phy_device *phydev,
1101 struct ethtool_eee *e)
1102 {
1103 u32 val;
1104 int addr = phydev->mdio.addr;
1105
1106 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1107
1108 /* Set GPHY page to copper */
1109 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1110
1111 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1112 if (e->eee_enabled) {
1113 /* Verify vs MAC-based EEE */
1114 e->eee_enabled = !!(val & BIT(7));
1115 if (!e->eee_enabled) {
1116 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1117 e->eee_enabled = !!(val & BIT(4));
1118 }
1119 }
1120 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1121
1122 /* GPHY page to auto */
1123 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1124
1125 return 0;
1126 }
1127
1128 static int rtl8218d_get_eee(struct phy_device *phydev,
1129 struct ethtool_eee *e)
1130 {
1131 u32 val;
1132 int addr = phydev->mdio.addr;
1133
1134 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1135
1136 /* Set GPHY page to copper */
1137 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1138
1139 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1140 if (e->eee_enabled)
1141 e->eee_enabled = !!(val & BIT(7));
1142 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1143
1144 /* GPHY page to auto */
1145 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1146
1147 return 0;
1148 }
1149
1150 static int rtl8214fc_set_eee(struct phy_device *phydev,
1151 struct ethtool_eee *e)
1152 {
1153 u32 poll_state;
1154 int port = phydev->mdio.addr;
1155 bool an_enabled;
1156 u32 val;
1157
1158 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1159
1160 if (rtl8214fc_media_is_fibre(phydev)) {
1161 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1162 return -ENOTSUPP;
1163 }
1164
1165 poll_state = disable_polling(port);
1166
1167 /* Set GPHY page to copper */
1168 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1169
1170 /* Get auto-negotiation status */
1171 val = phy_read(phydev, MII_BMCR);
1172 an_enabled = val & BMCR_ANENABLE;
1173
1174 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1175 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1176 val &= ~BIT(5); /* Use MAC-based EEE */
1177 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1178
1179 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1180 phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1181
1182 /* 500M EEE ability */
1183 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1184 if (e->eee_enabled)
1185 val |= BIT(7);
1186 else
1187 val &= ~BIT(7);
1188
1189 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1190
1191 /* Restart AN if enabled */
1192 if (an_enabled) {
1193 pr_info("%s: doing aneg\n", __func__);
1194 val = phy_read(phydev, MII_BMCR);
1195 val |= BMCR_ANRESTART;
1196 phy_write(phydev, MII_BMCR, val);
1197 }
1198
1199 /* GPHY page back to auto */
1200 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1201
1202 resume_polling(poll_state);
1203
1204 return 0;
1205 }
1206
1207 static int rtl8214fc_get_eee(struct phy_device *phydev,
1208 struct ethtool_eee *e)
1209 {
1210 int addr = phydev->mdio.addr;
1211
1212 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1213 if (rtl8214fc_media_is_fibre(phydev)) {
1214 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1215 return -ENOTSUPP;
1216 }
1217
1218 return rtl8218b_get_eee(phydev, e);
1219 }
1220
1221 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1222 {
1223 int port = phydev->mdio.addr;
1224 u64 poll_state;
1225 u32 val;
1226 bool an_enabled;
1227
1228 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1229
1230 poll_state = disable_polling(port);
1231
1232 /* Set GPHY page to copper */
1233 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1234 val = phy_read(phydev, MII_BMCR);
1235 an_enabled = val & BMCR_ANENABLE;
1236
1237 if (e->eee_enabled) {
1238 /* 100/1000M EEE Capability */
1239 phy_write(phydev, 13, 0x0007);
1240 phy_write(phydev, 14, 0x003C);
1241 phy_write(phydev, 13, 0x4007);
1242 phy_write(phydev, 14, 0x0006);
1243
1244 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1245 val |= BIT(4);
1246 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1247 } else {
1248 /* 100/1000M EEE Capability */
1249 phy_write(phydev, 13, 0x0007);
1250 phy_write(phydev, 14, 0x003C);
1251 phy_write(phydev, 13, 0x0007);
1252 phy_write(phydev, 14, 0x0000);
1253
1254 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1255 val &= ~BIT(4);
1256 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1257 }
1258
1259 /* Restart AN if enabled */
1260 if (an_enabled) {
1261 val = phy_read(phydev, MII_BMCR);
1262 val |= BMCR_ANRESTART;
1263 phy_write(phydev, MII_BMCR, val);
1264 }
1265
1266 /* GPHY page back to auto */
1267 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1268
1269 pr_info("%s done\n", __func__);
1270 resume_polling(poll_state);
1271
1272 return 0;
1273 }
1274
1275 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1276 {
1277 int addr = phydev->mdio.addr;
1278 u64 poll_state;
1279
1280 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1281
1282 poll_state = disable_polling(addr);
1283
1284 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1285
1286 resume_polling(poll_state);
1287
1288 return 0;
1289 }
1290
1291 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1292 {
1293 return phydev->phy_id == PHY_ID_RTL8214C;
1294 }
1295
1296 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1297 {
1298 u32 phy_id, val;
1299 int mac = phydev->mdio.addr;
1300
1301 val = phy_read(phydev, 2);
1302 phy_id = val << 16;
1303 val = phy_read(phydev, 3);
1304 phy_id |= val;
1305 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1306
1307 phydev_info(phydev, "Detected external RTL8214C\n");
1308
1309 /* GPHY auto conf */
1310 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1311
1312 return 0;
1313 }
1314
1315 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1316 {
1317 int mac = phydev->mdio.addr;
1318 struct fw_header *h;
1319 u32 *rtl8380_rtl8214fc_perchip;
1320 u32 *rtl8380_rtl8214fc_perport;
1321 u32 phy_id;
1322 u32 val;
1323
1324 val = phy_read(phydev, 2);
1325 phy_id = val << 16;
1326 val = phy_read(phydev, 3);
1327 phy_id |= val;
1328 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1329
1330 /* Read internal PHY id */
1331 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1332 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1333 val = phy_read_paged(phydev, 0x1f, 0x1c);
1334 if (val != 0x6276) {
1335 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1336 return -1;
1337 }
1338 phydev_info(phydev, "Detected external RTL8214FC\n");
1339
1340 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1341 if (!h)
1342 return -1;
1343
1344 if (h->phy != 0x8214fc00) {
1345 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1346 return -1;
1347 }
1348
1349 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1350
1351 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1352
1353 /* detect phy version */
1354 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1355 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1356
1357 val = phy_read(phydev, 16);
1358 if (val & BMCR_PDOWN)
1359 rtl8380_rtl8214fc_on_off(phydev, true);
1360 else
1361 rtl8380_phy_reset(phydev);
1362
1363 msleep(100);
1364 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1365
1366 for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
1367 rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
1368 u32 page = 0;
1369
1370 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1371 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1372 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1373 val = phy_read_paged(phydev, 0x260, 13);
1374 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1375 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1376 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1377 } else {
1378 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1379 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1380 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1381 }
1382 }
1383
1384 /* Force copper medium */
1385 for (int i = 0; i < 4; i++) {
1386 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1387 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1388 }
1389
1390 /* Enable PHY */
1391 for (int i = 0; i < 4; i++) {
1392 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1393 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1394 }
1395 mdelay(100);
1396
1397 /* Disable Autosensing */
1398 for (int i = 0; i < 4; i++) {
1399 int l;
1400
1401 for (l = 0; l < 100; l++) {
1402 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1403 if ((val & 0x7) >= 3)
1404 break;
1405 }
1406 if (l >= 100) {
1407 phydev_err(phydev, "Could not disable autosensing\n");
1408 return -1;
1409 }
1410 }
1411
1412 /* Request patch */
1413 for (int i = 0; i < 4; i++) {
1414 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1415 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1416 }
1417 mdelay(300);
1418
1419 /* Verify patch readiness */
1420 for (int i = 0; i < 4; i++) {
1421 int l;
1422
1423 for (l = 0; l < 100; l++) {
1424 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1425 if (val & 0x40)
1426 break;
1427 }
1428 if (l >= 100) {
1429 phydev_err(phydev, "Could not patch PHY\n");
1430 return -1;
1431 }
1432 }
1433 /* Use Broadcast ID method for patching */
1434 rtl821x_phy_setup_package_broadcast(phydev, true);
1435
1436 for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
1437 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1438 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1439 }
1440
1441 /* Disable broadcast ID */
1442 rtl821x_phy_setup_package_broadcast(phydev, false);
1443
1444 /* Auto medium selection */
1445 for (int i = 0; i < 4; i++) {
1446 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1447 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1454 {
1455 int addr = phydev->mdio.addr;
1456
1457 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1458 }
1459
1460 static int rtl8380_configure_serdes(struct phy_device *phydev)
1461 {
1462 u32 v;
1463 u32 sds_conf_value;
1464 int i;
1465 struct fw_header *h;
1466 u32 *rtl8380_sds_take_reset;
1467 u32 *rtl8380_sds_common;
1468 u32 *rtl8380_sds01_qsgmii_6275b;
1469 u32 *rtl8380_sds23_qsgmii_6275b;
1470 u32 *rtl8380_sds4_fiber_6275b;
1471 u32 *rtl8380_sds5_fiber_6275b;
1472 u32 *rtl8380_sds_reset;
1473 u32 *rtl8380_sds_release_reset;
1474
1475 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1476
1477 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1478 if (!h)
1479 return -1;
1480
1481 if (h->magic != 0x83808380) {
1482 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1483 return -1;
1484 }
1485
1486 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1487
1488 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1489
1490 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1491
1492 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1493
1494 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1495
1496 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1497
1498 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1499
1500 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1501
1502 /* Back up serdes power off value */
1503 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1504 pr_info("SDS power down value: %x\n", sds_conf_value);
1505
1506 /* take serdes into reset */
1507 i = 0;
1508 while (rtl8380_sds_take_reset[2 * i]) {
1509 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1510 i++;
1511 udelay(1000);
1512 }
1513
1514 /* apply common serdes patch */
1515 i = 0;
1516 while (rtl8380_sds_common[2 * i]) {
1517 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1518 i++;
1519 udelay(1000);
1520 }
1521
1522 /* internal R/W enable */
1523 sw_w32(3, RTL838X_INT_RW_CTRL);
1524
1525 /* SerDes ports 4 and 5 are FIBRE ports */
1526 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1527
1528 /* SerDes module settings, SerDes 0-3 are QSGMII */
1529 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1530 /* SerDes 4 and 5 are 1000BX FIBRE */
1531 v |= 0x4 << 5 | 0x4;
1532 sw_w32(v, RTL838X_SDS_MODE_SEL);
1533
1534 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1535 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1536 i = 0;
1537 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1538 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1539 rtl8380_sds01_qsgmii_6275b[2 * i]);
1540 i++;
1541 }
1542
1543 i = 0;
1544 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1545 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1546 i++;
1547 }
1548
1549 i = 0;
1550 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1551 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1552 i++;
1553 }
1554
1555 i = 0;
1556 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1557 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1558 i++;
1559 }
1560
1561 i = 0;
1562 while (rtl8380_sds_reset[2 * i]) {
1563 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1564 i++;
1565 }
1566
1567 i = 0;
1568 while (rtl8380_sds_release_reset[2 * i]) {
1569 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1570 i++;
1571 }
1572
1573 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1574 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1575
1576 pr_info("Configuration of SERDES done\n");
1577
1578 return 0;
1579 }
1580
1581 static int rtl8390_configure_serdes(struct phy_device *phydev)
1582 {
1583 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1584
1585 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1586 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1587
1588 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1589 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1590 * and FRE16_EEE_QUIET_FIB1G
1591 */
1592 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1593
1594 return 0;
1595 }
1596
1597 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1598 {
1599 int l = end_bit - start_bit + 1;
1600 u32 data = v;
1601
1602 if (l < 32) {
1603 u32 mask = BIT(l) - 1;
1604
1605 data = rtl930x_read_sds_phy(sds, page, reg);
1606 data &= ~(mask << start_bit);
1607 data |= (v & mask) << start_bit;
1608 }
1609
1610 rtl930x_write_sds_phy(sds, page, reg, data);
1611 }
1612
1613 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1614 {
1615 int l = end_bit - start_bit + 1;
1616 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1617
1618 if (l >= 32)
1619 return v;
1620
1621 return (v >> start_bit) & (BIT(l) - 1);
1622 }
1623
1624 /* Read the link and speed status of the internal SerDes of the RTL9300
1625 */
1626 static int rtl9300_read_status(struct phy_device *phydev)
1627 {
1628 struct device *dev = &phydev->mdio.dev;
1629 int phy_addr = phydev->mdio.addr;
1630 struct device_node *dn;
1631 u32 sds_num = 0, status, latch_status, mode;
1632
1633 if (dev->of_node) {
1634 dn = dev->of_node;
1635
1636 if (of_property_read_u32(dn, "sds", &sds_num))
1637 sds_num = -1;
1638 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1639 } else {
1640 dev_err(dev, "No DT node.\n");
1641 return -EINVAL;
1642 }
1643
1644 if (sds_num < 0)
1645 return 0;
1646
1647 mode = rtl9300_sds_mode_get(sds_num);
1648 pr_info("%s got SDS mode %02x\n", __func__, mode);
1649 if (mode == RTL930X_SDS_OFF)
1650 mode = rtl9300_sds_field_r(sds_num, 0x1f, 9, 11, 7);
1651 if (mode == RTL930X_SDS_MODE_10GBASER) { /* 10GR mode */
1652 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1653 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1654 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1655 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1656 } else {
1657 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1658 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1659 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1660 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1661 }
1662
1663 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1664
1665 if (latch_status) {
1666 phydev->link = true;
1667 if (mode == RTL930X_SDS_MODE_10GBASER) {
1668 phydev->speed = SPEED_10000;
1669 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
1670 } else {
1671 phydev->speed = SPEED_1000;
1672 phydev->interface = PHY_INTERFACE_MODE_1000BASEX;
1673 }
1674
1675 phydev->duplex = DUPLEX_FULL;
1676 }
1677
1678 return 0;
1679 }
1680
1681 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1682 {
1683 int page = 0x2e; /* 10GR and USXGMII */
1684
1685 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1686 page = 0x24;
1687
1688 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1689 mdelay(5);
1690 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1691 }
1692
1693 /* Force PHY modes on 10GBit Serdes
1694 */
1695 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1696 {
1697 int lc_value;
1698 int sds_mode;
1699 bool lc_on;
1700 int lane_0 = (sds % 2) ? sds - 1 : sds;
1701 u32 v;
1702
1703 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1704 switch (phy_if) {
1705 case PHY_INTERFACE_MODE_SGMII:
1706 sds_mode = RTL930X_SDS_MODE_SGMII;
1707 lc_on = false;
1708 lc_value = 0x1;
1709 break;
1710
1711 case PHY_INTERFACE_MODE_HSGMII:
1712 sds_mode = RTL930X_SDS_MODE_HSGMII;
1713 lc_value = 0x3;
1714 /* Configure LC */
1715 break;
1716
1717 case PHY_INTERFACE_MODE_1000BASEX:
1718 sds_mode = RTL930X_SDS_MODE_1000BASEX;
1719 lc_on = false;
1720 break;
1721
1722 case PHY_INTERFACE_MODE_2500BASEX:
1723 sds_mode = RTL930X_SDS_MODE_2500BASEX;
1724 lc_value = 0x3;
1725 /* Configure LC */
1726 break;
1727
1728 case PHY_INTERFACE_MODE_10GBASER:
1729 sds_mode = RTL930X_SDS_MODE_10GBASER;
1730 lc_on = true;
1731 lc_value = 0x5;
1732 break;
1733
1734 case PHY_INTERFACE_MODE_NA:
1735 /* This will disable SerDes */
1736 sds_mode = RTL930X_SDS_OFF;
1737 break;
1738
1739 default:
1740 pr_err("%s: unknown serdes mode: %s\n",
1741 __func__, phy_modes(phy_if));
1742 return;
1743 }
1744
1745 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1746 /* Power down SerDes */
1747 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1748 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1749
1750 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1751 /* Force mode enable */
1752 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1753 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1754
1755 /* SerDes off */
1756 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, RTL930X_SDS_OFF);
1757
1758 if (phy_if == PHY_INTERFACE_MODE_NA)
1759 return;
1760
1761 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1762 /* Enable LC and ring */
1763 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1764
1765 if (sds == lane_0)
1766 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1767 else
1768 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1769
1770 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1771
1772 if (lc_on)
1773 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1774 else
1775 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1776
1777 /* Force analog LC & ring on */
1778 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1779
1780 v = lc_on ? 0x3 : 0x1;
1781
1782 if (sds == lane_0)
1783 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1784 else
1785 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1786
1787 /* Force SerDes mode */
1788 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1789 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1790
1791 /* Toggle LC or Ring */
1792 for (int i = 0; i < 20; i++) {
1793 u32 cr_0, cr_1, cr_2;
1794 u32 m_bit, l_bit;
1795
1796 mdelay(200);
1797
1798 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1799
1800 m_bit = (lane_0 == sds) ? (4) : (5);
1801 l_bit = (lane_0 == sds) ? (4) : (5);
1802
1803 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1804 mdelay(10);
1805 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1806 mdelay(10);
1807 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1808
1809 if (cr_0 && cr_1 && cr_2) {
1810 u32 t;
1811
1812 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1813 break;
1814
1815 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1816 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1817
1818 /* Reset FSM */
1819 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1820 mdelay(10);
1821 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1822 mdelay(10);
1823
1824 /* Need to read this twice */
1825 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1826 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1827
1828 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1829
1830 /* Reset FSM again */
1831 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1832 mdelay(10);
1833 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1834 mdelay(10);
1835
1836 if (v == 1)
1837 break;
1838 }
1839
1840 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1841 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1842
1843 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1844 mdelay(10);
1845 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1846 }
1847
1848 rtl930x_sds_rx_rst(sds, phy_if);
1849
1850 /* Re-enable power */
1851 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1852
1853 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1854 }
1855
1856 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1857 {
1858 /* parameters: rtl9303_80G_txParam_s2 */
1859 int impedance = 0x8;
1860 int pre_amp = 0x2;
1861 int main_amp = 0x9;
1862 int post_amp = 0x2;
1863 int pre_en = 0x1;
1864 int post_en = 0x1;
1865 int page;
1866
1867 switch(phy_if) {
1868 case PHY_INTERFACE_MODE_1000BASEX:
1869 pre_amp = 0x1;
1870 main_amp = 0x9;
1871 post_amp = 0x1;
1872 page = 0x25;
1873 break;
1874 case PHY_INTERFACE_MODE_HSGMII:
1875 case PHY_INTERFACE_MODE_2500BASEX:
1876 pre_amp = 0;
1877 post_amp = 0x8;
1878 pre_en = 0;
1879 page = 0x29;
1880 break;
1881 case PHY_INTERFACE_MODE_10GBASER:
1882 case PHY_INTERFACE_MODE_USXGMII:
1883 case PHY_INTERFACE_MODE_XGMII:
1884 pre_en = 0;
1885 pre_amp = 0;
1886 main_amp = 0x10;
1887 post_amp = 0;
1888 post_en = 0;
1889 page = 0x2f;
1890 break;
1891 default:
1892 pr_err("%s: unsupported PHY mode\n", __func__);
1893 return;
1894 }
1895
1896 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1897 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1898 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1899 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1900 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1901 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1902 }
1903
1904 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1905 * timeout is in ms
1906 */
1907 int rtl9300_sds_clock_wait(int timeout)
1908 {
1909 u32 v;
1910 unsigned long start = jiffies;
1911
1912 do {
1913 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1914 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1915 if (v == 3)
1916 return 0;
1917 } while (jiffies < start + (HZ / 1000) * timeout);
1918
1919 return 1;
1920 }
1921
1922 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1923 {
1924 u32 v10, v1;
1925
1926 v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
1927 v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
1928 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1929
1930 v10 &= ~(BIT(13) | BIT(14));
1931 v1 &= ~(BIT(8) | BIT(9));
1932
1933 v10 |= rx_normal ? 0 : BIT(13);
1934 v1 |= rx_normal ? 0 : BIT(9);
1935
1936 v10 |= tx_normal ? 0 : BIT(14);
1937 v1 |= tx_normal ? 0 : BIT(8);
1938
1939 rtl930x_write_sds_phy(sds, 6, 2, v10);
1940 rtl930x_write_sds_phy(sds, 0, 0, v1);
1941
1942 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1943 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1944 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1945 }
1946
1947 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1948 {
1949 if (manual) {
1950 switch(dcvs_id) {
1951 case 0:
1952 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1953 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1954 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1955 break;
1956 case 1:
1957 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1958 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1960 break;
1961 case 2:
1962 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1963 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1964 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1965 break;
1966 case 3:
1967 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1968 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1969 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1970 break;
1971 case 4:
1972 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1973 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1974 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1975 break;
1976 case 5:
1977 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1978 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1979 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1980 break;
1981 default:
1982 break;
1983 }
1984 } else {
1985 switch(dcvs_id) {
1986 case 0:
1987 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1988 break;
1989 case 1:
1990 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1991 break;
1992 case 2:
1993 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1994 break;
1995 case 3:
1996 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1997 break;
1998 case 4:
1999 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
2000 break;
2001 case 5:
2002 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
2003 break;
2004 default:
2005 break;
2006 }
2007 mdelay(1);
2008 }
2009 }
2010
2011 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
2012 {
2013 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
2014 bool dcvs_manual;
2015
2016 if (!(sds_num % 2))
2017 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2018 else
2019 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2020
2021 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2022 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2023
2024 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2025 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2026
2027 switch(dcvs_id) {
2028 case 0:
2029 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2030 mdelay(1);
2031
2032 /* ##DCVS0 Read Out */
2033 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2034 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2035 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2036 break;
2037
2038 case 1:
2039 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2040 mdelay(1);
2041
2042 /* ##DCVS0 Read Out */
2043 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2044 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2045 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2046 break;
2047
2048 case 2:
2049 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2050 mdelay(1);
2051
2052 /* ##DCVS0 Read Out */
2053 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2054 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2055 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2056 break;
2057 case 3:
2058 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2059 mdelay(1);
2060
2061 /* ##DCVS0 Read Out */
2062 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2063 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2064 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2065 break;
2066
2067 case 4:
2068 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2069 mdelay(1);
2070
2071 /* ##DCVS0 Read Out */
2072 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2073 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2074 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2075 break;
2076
2077 case 5:
2078 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2079 mdelay(1);
2080
2081 /* ##DCVS0 Read Out */
2082 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2083 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2084 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2085 break;
2086
2087 default:
2088 break;
2089 }
2090
2091 if (dcvs_sign_out)
2092 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2093 else
2094 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2095
2096 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2097 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2098
2099 dcvs_list[0] = dcvs_sign_out;
2100 dcvs_list[1] = dcvs_coef_bin;
2101 }
2102
2103 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2104 {
2105 if (manual) {
2106 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2107 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2108 } else {
2109 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2110 mdelay(100);
2111 }
2112 }
2113
2114 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2115 {
2116 if (manual) {
2117 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2118 } else {
2119 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2120 mdelay(1);
2121 }
2122 }
2123
2124 #define GRAY_BITS 5
2125 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2126 {
2127 int i, j, m;
2128 u32 g[GRAY_BITS];
2129 u32 c[GRAY_BITS];
2130 u32 leq_binary = 0;
2131
2132 for(i = 0; i < GRAY_BITS; i++)
2133 g[i] = (gray_code & BIT(i)) >> i;
2134
2135 m = GRAY_BITS - 1;
2136
2137 c[m] = g[m];
2138
2139 for(i = 0; i < m; i++) {
2140 c[i] = g[i];
2141 for(j = i + 1; j < GRAY_BITS; j++)
2142 c[i] = c[i] ^ g[j];
2143 }
2144
2145 for(i = 0; i < GRAY_BITS; i++)
2146 leq_binary += c[i] << i;
2147
2148 return leq_binary;
2149 }
2150
2151 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2152 {
2153 u32 leq_gray, leq_bin;
2154 bool leq_manual;
2155
2156 if (!(sds_num % 2))
2157 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2158 else
2159 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2160
2161 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2162 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2163
2164 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2165 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2166 mdelay(1);
2167
2168 /* ##LEQ Read Out */
2169 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2170 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2171 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2172
2173 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2174 pr_info("LEQ manual: %u", leq_manual);
2175
2176 return leq_bin;
2177 }
2178
2179 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2180 {
2181 if (manual) {
2182 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2183 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2184 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2185 } else {
2186 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2187 mdelay(10);
2188 }
2189 }
2190
2191 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2192 {
2193 u32 vth_manual;
2194
2195 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2196 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2197 if (!(sds_num % 2))
2198 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2199 else
2200 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2201
2202 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2203 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2204 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2205 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2206 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2207 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2208
2209 mdelay(1);
2210
2211 /* ##VthP & VthN Read Out */
2212 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2213 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2214
2215 pr_info("vth_set_bin = %d", vth_list[0]);
2216 pr_info("vth_set_bin = %d", vth_list[1]);
2217
2218 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2219 pr_info("Vth Maunal = %d", vth_manual);
2220 }
2221
2222 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2223 {
2224 if (manual) {
2225 switch(tap_id) {
2226 case 0:
2227 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2228 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2229 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2230 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2231 break;
2232 case 1:
2233 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2234 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2235 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2236 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2237 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2238 break;
2239 case 2:
2240 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2241 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2242 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2243 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2244 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2245 break;
2246 case 3:
2247 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2248 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2249 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2250 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2251 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2252 break;
2253 case 4:
2254 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2255 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2256 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2257 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2258 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2259 break;
2260 default:
2261 break;
2262 }
2263 } else {
2264 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2265 mdelay(10);
2266 }
2267 }
2268
2269 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2270 {
2271 u32 tap0_sign_out;
2272 u32 tap0_coef_bin;
2273 u32 tap_sign_out_even;
2274 u32 tap_coef_bin_even;
2275 u32 tap_sign_out_odd;
2276 u32 tap_coef_bin_odd;
2277 bool tap_manual;
2278
2279 if (!(sds_num % 2))
2280 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2281 else
2282 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2283
2284 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2285 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2286 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2287 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2288
2289 if (!tap_id) {
2290 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2291 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2292 /* ##Tap1 Even Read Out */
2293 mdelay(1);
2294 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2295 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2296
2297 if (tap0_sign_out == 1)
2298 pr_info("Tap0 Sign : -");
2299 else
2300 pr_info("Tap0 Sign : +");
2301
2302 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2303
2304 tap_list[0] = tap0_sign_out;
2305 tap_list[1] = tap0_coef_bin;
2306
2307 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2308 pr_info("tap0 manual = %u",tap_manual);
2309 } else {
2310 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2311 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2312 mdelay(1);
2313 /* ##Tap1 Even Read Out */
2314 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2315 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2316
2317 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2318 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2319 /* ##Tap1 Odd Read Out */
2320 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2321 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2322
2323 if (tap_sign_out_even == 1)
2324 pr_info("Tap %u even sign: -", tap_id);
2325 else
2326 pr_info("Tap %u even sign: +", tap_id);
2327
2328 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2329
2330 if (tap_sign_out_odd == 1)
2331 pr_info("Tap %u odd sign: -", tap_id);
2332 else
2333 pr_info("Tap %u odd sign: +", tap_id);
2334
2335 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2336
2337 tap_list[0] = tap_sign_out_even;
2338 tap_list[1] = tap_coef_bin_even;
2339 tap_list[2] = tap_sign_out_odd;
2340 tap_list[3] = tap_coef_bin_odd;
2341
2342 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2343 pr_info("tap %u manual = %d",tap_id, tap_manual);
2344 }
2345 }
2346
2347 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2348 {
2349 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2350 int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2351 int vth_min = 0x0;
2352
2353 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2354 rtl930x_write_sds_phy(sds, 6, 0, 0);
2355
2356 /* FGCAL */
2357 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2358 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2359 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2360
2361 /* DCVS */
2362 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2363 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2364 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2365 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2366 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2368 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2369 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2370 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2371 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2372 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2373 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2374
2375 /* LEQ (Long Term Equivalent signal level) */
2376 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2377
2378 /* DFE (Decision Fed Equalizer) */
2379 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2380 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2381 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2382 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2383 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2384 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2385 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2386 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2387 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2388
2389 /* Vth */
2390 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2391 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2392 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2393
2394 pr_info("end_1.1.1 --\n");
2395
2396 pr_info("start_1.1.2 Load DFE init. value\n");
2397
2398 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2399
2400 pr_info("end_1.1.2\n");
2401
2402 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2403
2404 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2405 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2406 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2407 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2408 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2409 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2410
2411 pr_info("end_1.1.3 --\n");
2412
2413 pr_info("start_1.1.4 offset cali setting\n");
2414
2415 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2416
2417 pr_info("end_1.1.4\n");
2418
2419 pr_info("start_1.1.5 LEQ and DFE setting\n");
2420
2421 /* TODO: make this work for DAC cables of different lengths */
2422 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2423 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2424 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2425 else
2426 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2427
2428 /* No serdes, check for Aquantia PHYs */
2429 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2430
2431 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2432 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2433 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2434 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2435 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2436
2437 pr_info("end_1.1.5\n");
2438 }
2439
2440 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2441 {
2442 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2443
2444 /* Gray config endis to 1 */
2445 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2446
2447 /* ForegroundOffsetCal_Manual(auto mode) */
2448 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2449
2450 pr_info("end_1.2.1");
2451 }
2452
2453 void rtl9300_do_rx_calibration_2_2(int sds_num)
2454 {
2455 /* Force Rx-Run = 0 */
2456 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2457
2458 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2459 }
2460
2461 void rtl9300_do_rx_calibration_2_3(int sds_num)
2462 {
2463 u32 fgcal_binary, fgcal_gray;
2464 u32 offset_range;
2465
2466 pr_info("start_1.2.3 Foreground Calibration\n");
2467
2468 while(1) {
2469 if (!(sds_num % 2))
2470 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2471 else
2472 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2473
2474 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2475 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2476 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2477 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2478 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2479 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2480 /* ##FGCAL read gray */
2481 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2482 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2483 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2484 /* ##FGCAL read binary */
2485 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2486
2487 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2488 __func__, fgcal_gray, fgcal_binary);
2489
2490 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2491
2492 if (fgcal_binary > 60 || fgcal_binary < 3) {
2493 if (offset_range == 3) {
2494 pr_info("%s: Foreground Calibration result marginal!", __func__);
2495 break;
2496 } else {
2497 offset_range++;
2498 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2499 rtl9300_do_rx_calibration_2_2(sds_num);
2500 }
2501 } else {
2502 break;
2503 }
2504 }
2505 pr_info("%s: end_1.2.3\n", __func__);
2506 }
2507
2508 void rtl9300_do_rx_calibration_2(int sds)
2509 {
2510 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2511 rtl9300_do_rx_calibration_2_1(sds);
2512 rtl9300_do_rx_calibration_2_2(sds);
2513 rtl9300_do_rx_calibration_2_3(sds);
2514 }
2515
2516 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2517 {
2518 pr_info("start_1.3.1");
2519
2520 /* ##1.3.1 */
2521 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2522 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2523
2524 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2525 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2526
2527 pr_info("end_1.3.1");
2528 }
2529
2530 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2531 {
2532 u32 sum10 = 0, avg10, int10;
2533 int dac_long_cable_offset;
2534 bool eq_hold_enabled;
2535 int i;
2536
2537 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2538 /* rtl9300_rxCaliConf_serdes_myParam */
2539 dac_long_cable_offset = 3;
2540 eq_hold_enabled = true;
2541 } else {
2542 /* rtl9300_rxCaliConf_phy_myParam */
2543 dac_long_cable_offset = 0;
2544 eq_hold_enabled = false;
2545 }
2546
2547 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2548 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2549
2550 pr_info("start_1.3.2");
2551
2552 for(i = 0; i < 10; i++) {
2553 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2554 mdelay(10);
2555 }
2556
2557 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2558 int10 = sum10 / 10;
2559
2560 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2561
2562 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2563 if (dac_long_cable_offset) {
2564 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2565 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2566 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2567 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2568 } else {
2569 if (sum10 >= 5) {
2570 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2571 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2572 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2573 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2574 } else {
2575 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2576 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2577 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2578 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2579 }
2580 }
2581 }
2582
2583 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2584
2585 pr_info("end_1.3.2");
2586 }
2587
2588 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2589 {
2590 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2591
2592 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2593 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2594 }
2595
2596 void rtl9300_do_rx_calibration_4_1(int sds_num)
2597 {
2598 u32 vth_list[2] = {0, 0};
2599 u32 tap0_list[4] = {0, 0, 0, 0};
2600
2601 pr_info("start_1.4.1");
2602
2603 /* ##1.4.1 */
2604 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2605 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2606 mdelay(200);
2607
2608 pr_info("end_1.4.1");
2609 }
2610
2611 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2612 {
2613 u32 vth_list[2];
2614 u32 tap_list[4];
2615
2616 pr_info("start_1.4.2");
2617
2618 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2619 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2620
2621 mdelay(100);
2622
2623 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2624 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2625
2626 pr_info("end_1.4.2");
2627 }
2628
2629 void rtl9300_do_rx_calibration_4(u32 sds_num)
2630 {
2631 rtl9300_do_rx_calibration_4_1(sds_num);
2632 rtl9300_do_rx_calibration_4_2(sds_num);
2633 }
2634
2635 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2636 {
2637 u32 tap1_list[4] = {0};
2638 u32 tap2_list[4] = {0};
2639 u32 tap3_list[4] = {0};
2640 u32 tap4_list[4] = {0};
2641
2642 pr_info("start_1.5.2");
2643
2644 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2645 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2646 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2647 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2648
2649 mdelay(30);
2650
2651 pr_info("end_1.5.2");
2652 }
2653
2654 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2655 {
2656 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */
2657 rtl9300_do_rx_calibration_5_2(sds_num);
2658 }
2659
2660
2661 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2662 {
2663 u32 tap1_list[4] = {0};
2664 u32 tap2_list[4] = {0};
2665 u32 tap3_list[4] = {0};
2666 u32 tap4_list[4] = {0};
2667
2668 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2669 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2670 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2671 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2672
2673 mdelay(10);
2674 }
2675
2676 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2677 {
2678 u32 latch_sts;
2679
2680 rtl9300_do_rx_calibration_1(sds, phy_mode);
2681 rtl9300_do_rx_calibration_2(sds);
2682 rtl9300_do_rx_calibration_4(sds);
2683 rtl9300_do_rx_calibration_5(sds, phy_mode);
2684 mdelay(20);
2685
2686 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2687 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == RTL930X_SDS_MODE_10GBASER) {
2688 pr_info("%s: SDS enabled\n", __func__);
2689 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2690 mdelay(1);
2691 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2692 if (latch_sts) {
2693 rtl9300_do_rx_calibration_dfe_disable(sds);
2694 rtl9300_do_rx_calibration_4(sds);
2695 rtl9300_do_rx_calibration_5(sds, phy_mode);
2696 }
2697 }
2698 }
2699
2700 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2701 {
2702 switch (phy_mode) {
2703 case PHY_INTERFACE_MODE_XGMII:
2704 break;
2705
2706 case PHY_INTERFACE_MODE_10GBASER:
2707 /* Read twice to clear */
2708 rtl930x_read_sds_phy(sds_num, 5, 1);
2709 rtl930x_read_sds_phy(sds_num, 5, 1);
2710 break;
2711
2712 case PHY_INTERFACE_MODE_1000BASEX:
2713 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2714 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2715 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2716 break;
2717
2718 default:
2719 pr_info("%s unsupported phy mode\n", __func__);
2720 return -1;
2721 }
2722
2723 return 0;
2724 }
2725
2726 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2727 {
2728 u32 v = 0;
2729
2730 switch (phy_mode) {
2731 case PHY_INTERFACE_MODE_XGMII:
2732 break;
2733
2734 case PHY_INTERFACE_MODE_1000BASEX:
2735 case PHY_INTERFACE_MODE_10GBASER:
2736 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2737 return v & 0xff;
2738
2739 default:
2740 pr_info("%s unsupported PHY-mode\n", __func__);
2741 }
2742
2743 return v;
2744 }
2745
2746 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2747 {
2748 u32 errors1, errors2;
2749
2750 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2751 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2752
2753 /* Count errors during 1ms */
2754 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2755 mdelay(1);
2756 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2757
2758 switch (phy_mode) {
2759 case PHY_INTERFACE_MODE_1000BASEX:
2760 case PHY_INTERFACE_MODE_XGMII:
2761 if ((errors2 - errors1 > 100) ||
2762 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2763 pr_info("%s XSGMII error rate too high\n", __func__);
2764 return 1;
2765 }
2766 break;
2767 case PHY_INTERFACE_MODE_10GBASER:
2768 if (errors2 > 0) {
2769 pr_info("%s 10GBASER error rate too high\n", __func__);
2770 return 1;
2771 }
2772 break;
2773 default:
2774 return 1;
2775 }
2776
2777 return 0;
2778 }
2779
2780 void rtl9300_phy_enable_10g_1g(int sds_num)
2781 {
2782 u32 v;
2783
2784 /* Enable 1GBit PHY */
2785 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
2786 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2787 v &= ~BMCR_PDOWN;
2788 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
2789 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2790
2791 /* Enable 10GBit PHY */
2792 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
2793 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2794 v &= ~BMCR_PDOWN;
2795 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
2796 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2797
2798 /* dal_longan_construct_mac_default_10gmedia_fiber */
2799 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2800 pr_info("%s set medium: %08x\n", __func__, v);
2801 v |= BIT(1);
2802 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2803 pr_info("%s set medium after: %08x\n", __func__, v);
2804 }
2805
2806 static int rtl9300_sds_10g_idle(int sds_num);
2807 static void rtl9300_serdes_patch(int sds_num);
2808
2809 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2810 int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode)
2811 {
2812 int calib_tries = 0;
2813
2814 /* Turn Off Serdes */
2815 rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
2816
2817 /* Apply serdes patches */
2818 rtl9300_serdes_patch(sds_num);
2819
2820 /* Maybe use dal_longan_sds_init */
2821
2822 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2823 rtl9300_phy_enable_10g_1g(sds_num);
2824
2825 /* Disable MAC */
2826 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
2827 mdelay(20);
2828
2829 /* ----> dal_longan_sds_mode_set */
2830 pr_info("%s: Configuring RTL9300 SERDES %d\n", __func__, sds_num);
2831
2832 /* Configure link to MAC */
2833 rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
2834
2835 /* Re-Enable MAC */
2836 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
2837
2838 /* Enable SDS in desired mode */
2839 rtl9300_force_sds_mode(sds_num, phy_mode);
2840
2841 /* Enable Fiber RX */
2842 rtl9300_sds_field_w(sds_num, 0x20, 2, 12, 12, 0);
2843
2844 /* Calibrate SerDes receiver in loopback mode */
2845 rtl9300_sds_10g_idle(sds_num);
2846 do {
2847 rtl9300_do_rx_calibration(sds_num, phy_mode);
2848 calib_tries++;
2849 mdelay(50);
2850 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2851 if (calib_tries >= 3)
2852 pr_warn("%s: SerDes RX calibration failed\n", __func__);
2853
2854 /* Leave loopback mode */
2855 rtl9300_sds_tx_config(sds_num, phy_mode);
2856
2857 return 0;
2858 }
2859
2860 static int rtl9300_sds_10g_idle(int sds_num)
2861 {
2862 bool busy;
2863 int i = 0;
2864
2865 do {
2866 if (sds_num % 2) {
2867 rtl9300_sds_field_w(sds_num - 1, 0x1f, 0x2, 15, 0, 53);
2868 busy = !!rtl9300_sds_field_r(sds_num - 1, 0x1f, 0x14, 1, 1);
2869 } else {
2870 rtl9300_sds_field_w(sds_num, 0x1f, 0x2, 15, 0, 53);
2871 busy = !!rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 0, 0);
2872 }
2873 i++;
2874 } while (busy && i < 100);
2875
2876 if (i < 100)
2877 return 0;
2878
2879 pr_warn("%s WARNING: Waiting for RX idle timed out, SDS %d\n", __func__, sds_num);
2880 return -EIO;
2881 }
2882
2883 typedef struct {
2884 u8 page;
2885 u8 reg;
2886 u16 data;
2887 } sds_config;
2888
2889 sds_config rtl9300_a_sds_10gr_lane0[] =
2890 {
2891 /* 1G */
2892 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2893 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2894 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2895 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2896 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2897 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2898 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2899 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2900 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2901 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2902 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2903 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2904 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2905 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2906 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2907 {0x2F, 0x1D, 0x66E1},
2908 /* 3.125G */
2909 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2910 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2911 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2912 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2913 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2914 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2915 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2916 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2917 /* 10G */
2918 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2919 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2920 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2921 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2922 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2923 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2924 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2925 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2926 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2927 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2928 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2929 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2930 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2931 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2932 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2933 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2934 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2935 };
2936
2937 sds_config rtl9300_a_sds_10gr_lane1[] =
2938 {
2939 /* 1G */
2940 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2941 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2942 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2943 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2944 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2945 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2946 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2947 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2948 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2949 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2950 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2951 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2952 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2953 {0x2D, 0x14, 0x1808},
2954 /* 3.125G */
2955 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2956 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2957 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2958 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2959 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2960 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2961 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2962 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2963 /* 10G */
2964 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2965 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2966 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2967 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2968 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2969 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2970 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2971 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2972 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2973 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2974 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2975 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2976 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2977 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2978 };
2979
2980 static void rtl9300_serdes_patch(int sds_num)
2981 {
2982 if (sds_num % 2) {
2983 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2984 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2985 rtl9300_a_sds_10gr_lane1[i].reg,
2986 rtl9300_a_sds_10gr_lane1[i].data);
2987 }
2988 } else {
2989 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
2990 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
2991 rtl9300_a_sds_10gr_lane0[i].reg,
2992 rtl9300_a_sds_10gr_lane0[i].data);
2993 }
2994 }
2995 }
2996
2997 int rtl9300_sds_cmu_band_get(int sds)
2998 {
2999 u32 page;
3000 u32 en;
3001 u32 cmu_band;
3002
3003 /* page = rtl9300_sds_cmu_page_get(sds); */
3004 page = 0x25; /* 10GR and 1000BX */
3005 sds = (sds % 2) ? (sds - 1) : (sds);
3006
3007 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
3008 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
3009
3010 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
3011 if(!en) { /* Auto mode */
3012 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
3013
3014 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
3015 } else {
3016 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
3017 }
3018
3019 return cmu_band;
3020 }
3021
3022 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3023 {
3024 int l = end_bit - start_bit + 1;
3025 u32 data = v;
3026
3027 if (l < 32) {
3028 u32 mask = BIT(l) - 1;
3029
3030 data = rtl930x_read_sds_phy(sds, page, reg);
3031 data &= ~(mask << start_bit);
3032 data |= (v & mask) << start_bit;
3033 }
3034
3035 rtl931x_write_sds_phy(sds, page, reg, data);
3036 }
3037
3038 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3039 {
3040 int l = end_bit - start_bit + 1;
3041 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3042
3043 if (l >= 32)
3044 return v;
3045
3046 return (v >> start_bit) & (BIT(l) - 1);
3047 }
3048
3049 static void rtl931x_sds_rst(u32 sds)
3050 {
3051 u32 o, v, o_mode;
3052 int shift = ((sds & 0x3) << 3);
3053
3054 /* TODO: We need to lock this! */
3055
3056 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3057 v = o | BIT(sds);
3058 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3059
3060 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3061 v = BIT(7) | 0x1F;
3062 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3063 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3064
3065 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3066 }
3067
3068 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3069 {
3070
3071 switch (mode) {
3072 case PHY_INTERFACE_MODE_NA:
3073 break;
3074 case PHY_INTERFACE_MODE_XGMII:
3075 u32 xsg_sdsid_0, xsg_sdsid_1;
3076
3077 if (sds < 2)
3078 xsg_sdsid_0 = sds;
3079 else
3080 xsg_sdsid_0 = (sds - 1) * 2;
3081 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3082
3083 for (int i = 0; i < 4; ++i) {
3084 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3085 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3086 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3087 }
3088
3089 for (int i = 0; i < 4; ++i) {
3090 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3091 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3092 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3093 }
3094
3095 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3096 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3097 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3098 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3099 break;
3100 default:
3101 break;
3102 }
3103
3104 return;
3105 }
3106
3107 static u32 rtl931x_get_analog_sds(u32 sds)
3108 {
3109 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3110
3111 if (sds < 14)
3112 return sds_map[sds];
3113
3114 return sds;
3115 }
3116
3117 void rtl931x_sds_fiber_disable(u32 sds)
3118 {
3119 u32 v = 0x3F;
3120 u32 asds = rtl931x_get_analog_sds(sds);
3121
3122 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3123 }
3124
3125 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3126 {
3127 u32 val, asds = rtl931x_get_analog_sds(sds);
3128
3129 /* clear symbol error count before changing mode */
3130 rtl931x_symerr_clear(sds, mode);
3131
3132 val = 0x9F;
3133 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3134
3135 switch (mode) {
3136 case PHY_INTERFACE_MODE_SGMII:
3137 val = 0x5;
3138 break;
3139
3140 case PHY_INTERFACE_MODE_1000BASEX:
3141 /* serdes mode FIBER1G */
3142 val = 0x9;
3143 break;
3144
3145 case PHY_INTERFACE_MODE_10GBASER:
3146 case PHY_INTERFACE_MODE_10GKR:
3147 val = 0x35;
3148 break;
3149 /* case MII_10GR1000BX_AUTO:
3150 val = 0x39;
3151 break; */
3152
3153
3154 case PHY_INTERFACE_MODE_USXGMII:
3155 val = 0x1B;
3156 break;
3157 default:
3158 val = 0x25;
3159 }
3160
3161 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3162 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3163
3164 return;
3165 }
3166
3167 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3168 {
3169 switch (mode) {
3170 case PHY_INTERFACE_MODE_SGMII:
3171 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3172 return 0x24;
3173 case PHY_INTERFACE_MODE_HSGMII:
3174 case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */
3175 return 0x28;
3176 /* case MII_HISGMII_5G: */
3177 /* return 0x2a; */
3178 case PHY_INTERFACE_MODE_QSGMII:
3179 return 0x2a; /* Code also has 0x34 */
3180 case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */
3181 return 0x2c;
3182 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3183 case PHY_INTERFACE_MODE_10GKR:
3184 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */
3185 return 0x2e;
3186 default:
3187 return -1;
3188 }
3189
3190 return -1;
3191 }
3192
3193 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3194 {
3195 int cmu_type = 0; /* Clock Management Unit */
3196 u32 cmu_page = 0;
3197 u32 frc_cmu_spd;
3198 u32 evenSds;
3199 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3200
3201 switch (mode) {
3202 case PHY_INTERFACE_MODE_NA:
3203 case PHY_INTERFACE_MODE_10GKR:
3204 case PHY_INTERFACE_MODE_XGMII:
3205 case PHY_INTERFACE_MODE_10GBASER:
3206 case PHY_INTERFACE_MODE_USXGMII:
3207 return;
3208
3209 /* case MII_10GR1000BX_AUTO:
3210 if (chiptype)
3211 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3212 return; */
3213
3214 case PHY_INTERFACE_MODE_QSGMII:
3215 cmu_type = 1;
3216 frc_cmu_spd = 0;
3217 break;
3218
3219 case PHY_INTERFACE_MODE_HSGMII:
3220 cmu_type = 1;
3221 frc_cmu_spd = 1;
3222 break;
3223
3224 case PHY_INTERFACE_MODE_1000BASEX:
3225 cmu_type = 1;
3226 frc_cmu_spd = 0;
3227 break;
3228
3229 /* case MII_1000BX100BX_AUTO:
3230 cmu_type = 1;
3231 frc_cmu_spd = 0;
3232 break; */
3233
3234 case PHY_INTERFACE_MODE_SGMII:
3235 cmu_type = 1;
3236 frc_cmu_spd = 0;
3237 break;
3238
3239 case PHY_INTERFACE_MODE_2500BASEX:
3240 cmu_type = 1;
3241 frc_cmu_spd = 1;
3242 break;
3243
3244 default:
3245 pr_info("SerDes %d mode is invalid\n", asds);
3246 return;
3247 }
3248
3249 if (cmu_type == 1)
3250 cmu_page = rtl931x_sds_cmu_page_get(mode);
3251
3252 lane = asds % 2;
3253
3254 if (!lane) {
3255 frc_lc_mode_bitnum = 4;
3256 frc_lc_mode_val_bitnum = 5;
3257 } else {
3258 frc_lc_mode_bitnum = 6;
3259 frc_lc_mode_val_bitnum = 7;
3260 }
3261
3262 evenSds = asds - lane;
3263
3264 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3265 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3266
3267 if (cmu_type == 1) {
3268 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3269 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3270 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3271 if (chiptype) {
3272 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3273 }
3274
3275 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3276 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3277 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3278 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3279 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3280 }
3281
3282 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3283 return;
3284 }
3285
3286 static void rtl931x_sds_rx_rst(u32 sds)
3287 {
3288 u32 asds = rtl931x_get_analog_sds(sds);
3289
3290 if (sds < 2)
3291 return;
3292
3293 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3294 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3295 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3296 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3297
3298 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3299 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3300 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3301 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3302
3303 mdelay(50);
3304 }
3305
3306 // Currently not used
3307 // static void rtl931x_sds_disable(u32 sds)
3308 // {
3309 // u32 v = 0x1f;
3310
3311 // v |= BIT(7);
3312 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3313 // }
3314
3315 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3316 {
3317 u32 val;
3318
3319 switch (mode) {
3320 case PHY_INTERFACE_MODE_QSGMII:
3321 val = 0x6;
3322 break;
3323 case PHY_INTERFACE_MODE_XGMII:
3324 val = 0x10; /* serdes mode XSGMII */
3325 break;
3326 case PHY_INTERFACE_MODE_USXGMII:
3327 case PHY_INTERFACE_MODE_2500BASEX:
3328 val = 0xD;
3329 break;
3330 case PHY_INTERFACE_MODE_HSGMII:
3331 val = 0x12;
3332 break;
3333 case PHY_INTERFACE_MODE_SGMII:
3334 val = 0x2;
3335 break;
3336 default:
3337 return;
3338 }
3339
3340 val |= (1 << 7);
3341
3342 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3343 }
3344
3345 static sds_config sds_config_10p3125g_type1[] = {
3346 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3347 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3348 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3349 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3350 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3351 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3352 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3353 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3354 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3355 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3356 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3357 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3358 { 0x2F, 0x13, 0x0000 }
3359 };
3360
3361 static sds_config sds_config_10p3125g_cmu_type1[] = {
3362 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3363 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3364 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3365 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3366 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3367 };
3368
3369 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3370 {
3371 u32 board_sds_tx_type1[] = {
3372 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3373 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3374 };
3375 u32 board_sds_tx[] = {
3376 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3377 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3378 };
3379 u32 board_sds_tx2[] = {
3380 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3381 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3382 };
3383 u32 asds, dSds, ori, model_info, val;
3384 int chiptype = 0;
3385
3386 asds = rtl931x_get_analog_sds(sds);
3387
3388 if (sds > 13)
3389 return;
3390
3391 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3392 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3393
3394 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3395 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3396 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3397 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3398 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3399 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3400 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3401 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3402 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3403 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3404 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3405 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3406
3407 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3408 if ((model_info >> 4) & 0x1) {
3409 pr_info("detected chiptype 1\n");
3410 chiptype = 1;
3411 } else {
3412 pr_info("detected chiptype 0\n");
3413 }
3414
3415 if (sds < 2)
3416 dSds = sds;
3417 else
3418 dSds = (sds - 1) * 2;
3419
3420 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3421 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3422
3423 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3424 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3425 val = ori | (1 << sds);
3426 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3427
3428 switch (mode) {
3429 case PHY_INTERFACE_MODE_NA:
3430 break;
3431
3432 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3433
3434 if (chiptype) {
3435 u32 xsg_sdsid_1;
3436 xsg_sdsid_1 = dSds + 1;
3437 /* fifo inv clk */
3438 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3439 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3440
3441 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3442 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3443
3444 }
3445
3446 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3447 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3448 break;
3449
3450 case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3451 u32 op_code = 0x6003;
3452 u32 evenSds;
3453
3454 if (chiptype) {
3455 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3456
3457 for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3458 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3459 }
3460
3461 evenSds = asds - (asds % 2);
3462
3463 for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3464 rtl931x_write_sds_phy(evenSds,
3465 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3466 }
3467
3468 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3469 } else {
3470
3471 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3472 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3473
3474 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3475 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3476 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3477 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3478 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3479
3480 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3481 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3482
3483 rtl931x_sds_rx_rst(sds);
3484
3485 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3486 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3487 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3488 }
3489 break;
3490
3491 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
3492 /* configure 10GR fiber mode=1 */
3493 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3494
3495 /* init fiber_1g */
3496 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3497
3498 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3499 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3500 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3501
3502 /* init auto */
3503 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3504 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3505 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3506 break;
3507
3508 case PHY_INTERFACE_MODE_HSGMII:
3509 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3510 break;
3511
3512 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */
3513 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3514
3515 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3516 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3517 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3518 break;
3519
3520 case PHY_INTERFACE_MODE_SGMII:
3521 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3522 break;
3523
3524 case PHY_INTERFACE_MODE_2500BASEX:
3525 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3526 break;
3527
3528 case PHY_INTERFACE_MODE_QSGMII:
3529 default:
3530 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3531 __func__, phy_modes(mode), sds);
3532 return;
3533 }
3534
3535 rtl931x_cmu_type_set(asds, mode, chiptype);
3536
3537 if (sds >= 2 && sds <= 13) {
3538 if (chiptype)
3539 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3540 else {
3541 val = 0xa0000;
3542 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3543 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3544 if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3545 {
3546 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3547 } else {
3548 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3549 }
3550 val = 0;
3551 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3552 }
3553 }
3554
3555 val = ori & ~BIT(sds);
3556 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3557 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3558
3559 if (mode == PHY_INTERFACE_MODE_XGMII ||
3560 mode == PHY_INTERFACE_MODE_QSGMII ||
3561 mode == PHY_INTERFACE_MODE_HSGMII ||
3562 mode == PHY_INTERFACE_MODE_SGMII ||
3563 mode == PHY_INTERFACE_MODE_USXGMII) {
3564 if (mode == PHY_INTERFACE_MODE_XGMII)
3565 rtl931x_sds_mii_mode_set(sds, mode);
3566 else
3567 rtl931x_sds_fiber_mode_set(sds, mode);
3568 }
3569 }
3570
3571 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3572 {
3573 u32 asds;
3574 int page = rtl931x_sds_cmu_page_get(mode);
3575
3576 sds -= (sds % 2);
3577 sds = sds & ~1;
3578 asds = rtl931x_get_analog_sds(sds);
3579 page += 1;
3580
3581 if (enable) {
3582 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3583 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3584 } else {
3585 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3586 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3587 }
3588
3589 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3590
3591 rtl931x_sds_rst(sds);
3592
3593 return 0;
3594 }
3595
3596 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3597 {
3598 int page = rtl931x_sds_cmu_page_get(mode);
3599 u32 asds, band;
3600
3601 sds -= (sds % 2);
3602 asds = rtl931x_get_analog_sds(sds);
3603 page += 1;
3604 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3605
3606 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3607 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3608 pr_info("%s band is: %d\n", __func__, band);
3609
3610 return band;
3611 }
3612
3613
3614 int rtl931x_link_sts_get(u32 sds)
3615 {
3616 u32 sts, sts1, latch_sts, latch_sts1;
3617 if (0){
3618 u32 xsg_sdsid_0, xsg_sdsid_1;
3619
3620 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3621 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3622
3623 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3624 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3625 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3626 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3627 } else {
3628 u32 asds, dsds;
3629
3630 asds = rtl931x_get_analog_sds(sds);
3631 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3632 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3633
3634 dsds = sds < 2 ? sds : (sds - 1) * 2;
3635 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3636 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3637 }
3638
3639 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3640 sds, sts, sts1, latch_sts, latch_sts1);
3641
3642 return sts1;
3643 }
3644
3645 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3646 {
3647 struct phy_device *phydev = upstream;
3648
3649 rtl8214fc_media_set(phydev, true);
3650
3651 return 0;
3652 }
3653
3654 static void rtl8214fc_sfp_remove(void *upstream)
3655 {
3656 struct phy_device *phydev = upstream;
3657
3658 rtl8214fc_media_set(phydev, false);
3659 }
3660
3661 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3662 .attach = phy_sfp_attach,
3663 .detach = phy_sfp_detach,
3664 .module_insert = rtl8214fc_sfp_insert,
3665 .module_remove = rtl8214fc_sfp_remove,
3666 };
3667
3668 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3669 {
3670 struct device *dev = &phydev->mdio.dev;
3671 int addr = phydev->mdio.addr;
3672 int ret = 0;
3673
3674 /* 839x has internal SerDes */
3675 if (soc_info.id == 0x8393)
3676 return -ENODEV;
3677
3678 /* All base addresses of the PHYs start at multiples of 8 */
3679 devm_phy_package_join(dev, phydev, addr & (~7),
3680 sizeof(struct rtl83xx_shared_private));
3681
3682 if (!(addr % 8)) {
3683 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3684 shared->name = "RTL8214FC";
3685 /* Configuration must be done while patching still possible */
3686 ret = rtl8380_configure_rtl8214fc(phydev);
3687 if (ret)
3688 return ret;
3689 }
3690
3691 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3692 }
3693
3694 static int rtl8214c_phy_probe(struct phy_device *phydev)
3695 {
3696 struct device *dev = &phydev->mdio.dev;
3697 int addr = phydev->mdio.addr;
3698
3699 /* All base addresses of the PHYs start at multiples of 8 */
3700 devm_phy_package_join(dev, phydev, addr & (~7),
3701 sizeof(struct rtl83xx_shared_private));
3702
3703 if (!(addr % 8)) {
3704 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3705 shared->name = "RTL8214C";
3706 /* Configuration must be done whil patching still possible */
3707 return rtl8380_configure_rtl8214c(phydev);
3708 }
3709
3710 return 0;
3711 }
3712
3713 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3714 {
3715 struct device *dev = &phydev->mdio.dev;
3716 int addr = phydev->mdio.addr;
3717
3718 /* All base addresses of the PHYs start at multiples of 8 */
3719 devm_phy_package_join(dev, phydev, addr & (~7),
3720 sizeof(struct rtl83xx_shared_private));
3721
3722 if (!(addr % 8)) {
3723 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3724 shared->name = "RTL8218B (external)";
3725 if (soc_info.family == RTL8380_FAMILY_ID) {
3726 /* Configuration must be done while patching still possible */
3727 return rtl8380_configure_ext_rtl8218b(phydev);
3728 }
3729 }
3730
3731 return 0;
3732 }
3733
3734 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3735 {
3736 struct device *dev = &phydev->mdio.dev;
3737 int addr = phydev->mdio.addr;
3738
3739 if (soc_info.family != RTL8380_FAMILY_ID)
3740 return -ENODEV;
3741 if (addr >= 24)
3742 return -ENODEV;
3743
3744 pr_debug("%s: id: %d\n", __func__, addr);
3745 /* All base addresses of the PHYs start at multiples of 8 */
3746 devm_phy_package_join(dev, phydev, addr & (~7),
3747 sizeof(struct rtl83xx_shared_private));
3748
3749 if (!(addr % 8)) {
3750 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3751 shared->name = "RTL8218B (internal)";
3752 /* Configuration must be done while patching still possible */
3753 return rtl8380_configure_int_rtl8218b(phydev);
3754 }
3755
3756 return 0;
3757 }
3758
3759 static int rtl8218d_phy_probe(struct phy_device *phydev)
3760 {
3761 struct device *dev = &phydev->mdio.dev;
3762 int addr = phydev->mdio.addr;
3763
3764 pr_debug("%s: id: %d\n", __func__, addr);
3765 /* All base addresses of the PHYs start at multiples of 8 */
3766 devm_phy_package_join(dev, phydev, addr & (~7),
3767 sizeof(struct rtl83xx_shared_private));
3768
3769 /* All base addresses of the PHYs start at multiples of 8 */
3770 if (!(addr % 8)) {
3771 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3772 shared->name = "RTL8218D";
3773 /* Configuration must be done while patching still possible */
3774 /* TODO: return configure_rtl8218d(phydev); */
3775 }
3776
3777 return 0;
3778 }
3779
3780 static int rtl838x_serdes_probe(struct phy_device *phydev)
3781 {
3782 int addr = phydev->mdio.addr;
3783
3784 if (soc_info.family != RTL8380_FAMILY_ID)
3785 return -ENODEV;
3786 if (addr < 24)
3787 return -ENODEV;
3788
3789 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3790 if (soc_info.id == 0x8380) {
3791 if (addr == 24)
3792 return rtl8380_configure_serdes(phydev);
3793 return 0;
3794 }
3795
3796 return -ENODEV;
3797 }
3798
3799 static int rtl8393_serdes_probe(struct phy_device *phydev)
3800 {
3801 int addr = phydev->mdio.addr;
3802
3803 pr_info("%s: id: %d\n", __func__, addr);
3804 if (soc_info.family != RTL8390_FAMILY_ID)
3805 return -ENODEV;
3806
3807 if (addr < 24)
3808 return -ENODEV;
3809
3810 return rtl8390_configure_serdes(phydev);
3811 }
3812
3813 static int rtl8390_serdes_probe(struct phy_device *phydev)
3814 {
3815 int addr = phydev->mdio.addr;
3816
3817 if (soc_info.family != RTL8390_FAMILY_ID)
3818 return -ENODEV;
3819
3820 if (addr < 24)
3821 return -ENODEV;
3822
3823 return rtl8390_configure_generic(phydev);
3824 }
3825
3826 static int rtl9300_serdes_probe(struct phy_device *phydev)
3827 {
3828 if (soc_info.family != RTL9300_FAMILY_ID)
3829 return -ENODEV;
3830
3831 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3832
3833 return 0;
3834 }
3835
3836 static struct phy_driver rtl83xx_phy_driver[] = {
3837 {
3838 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3839 .name = "Realtek RTL8214C",
3840 .features = PHY_GBIT_FEATURES,
3841 .flags = PHY_HAS_REALTEK_PAGES,
3842 .match_phy_device = rtl8214c_match_phy_device,
3843 .probe = rtl8214c_phy_probe,
3844 .suspend = genphy_suspend,
3845 .resume = genphy_resume,
3846 .set_loopback = genphy_loopback,
3847 },
3848 {
3849 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3850 .name = "Realtek RTL8214FC",
3851 .features = PHY_GBIT_FIBRE_FEATURES,
3852 .flags = PHY_HAS_REALTEK_PAGES,
3853 .match_phy_device = rtl8214fc_match_phy_device,
3854 .probe = rtl8214fc_phy_probe,
3855 .suspend = rtl8214fc_suspend,
3856 .resume = rtl8214fc_resume,
3857 .set_loopback = genphy_loopback,
3858 .set_port = rtl8214fc_set_port,
3859 .get_port = rtl8214fc_get_port,
3860 .set_eee = rtl8214fc_set_eee,
3861 .get_eee = rtl8214fc_get_eee,
3862 },
3863 {
3864 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3865 .name = "Realtek RTL8218B (external)",
3866 .features = PHY_GBIT_FEATURES,
3867 .flags = PHY_HAS_REALTEK_PAGES,
3868 .match_phy_device = rtl8218b_ext_match_phy_device,
3869 .probe = rtl8218b_ext_phy_probe,
3870 .suspend = genphy_suspend,
3871 .resume = genphy_resume,
3872 .set_loopback = genphy_loopback,
3873 .set_eee = rtl8218b_set_eee,
3874 .get_eee = rtl8218b_get_eee,
3875 },
3876 {
3877 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3878 .name = "REALTEK RTL8218D",
3879 .features = PHY_GBIT_FEATURES,
3880 .flags = PHY_HAS_REALTEK_PAGES,
3881 .probe = rtl8218d_phy_probe,
3882 .suspend = genphy_suspend,
3883 .resume = genphy_resume,
3884 .set_loopback = genphy_loopback,
3885 .set_eee = rtl8218d_set_eee,
3886 .get_eee = rtl8218d_get_eee,
3887 },
3888 {
3889 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3890 .name = "REALTEK RTL8221B",
3891 .features = PHY_GBIT_FEATURES,
3892 .flags = PHY_HAS_REALTEK_PAGES,
3893 .suspend = genphy_suspend,
3894 .resume = genphy_resume,
3895 .set_loopback = genphy_loopback,
3896 .read_page = rtl8226_read_page,
3897 .write_page = rtl8226_write_page,
3898 .read_status = rtl8226_read_status,
3899 .config_aneg = rtl8226_config_aneg,
3900 .set_eee = rtl8226_set_eee,
3901 .get_eee = rtl8226_get_eee,
3902 },
3903 {
3904 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3905 .name = "REALTEK RTL8226",
3906 .features = PHY_GBIT_FEATURES,
3907 .flags = PHY_HAS_REALTEK_PAGES,
3908 .suspend = genphy_suspend,
3909 .resume = genphy_resume,
3910 .set_loopback = genphy_loopback,
3911 .read_page = rtl8226_read_page,
3912 .write_page = rtl8226_write_page,
3913 .read_status = rtl8226_read_status,
3914 .config_aneg = rtl8226_config_aneg,
3915 .set_eee = rtl8226_set_eee,
3916 .get_eee = rtl8226_get_eee,
3917 },
3918 {
3919 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3920 .name = "Realtek RTL8218B (internal)",
3921 .features = PHY_GBIT_FEATURES,
3922 .flags = PHY_HAS_REALTEK_PAGES,
3923 .probe = rtl8218b_int_phy_probe,
3924 .suspend = genphy_suspend,
3925 .resume = genphy_resume,
3926 .set_loopback = genphy_loopback,
3927 .set_eee = rtl8218b_set_eee,
3928 .get_eee = rtl8218b_get_eee,
3929 },
3930 {
3931 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3932 .name = "Realtek RTL8380 SERDES",
3933 .features = PHY_GBIT_FIBRE_FEATURES,
3934 .flags = PHY_HAS_REALTEK_PAGES,
3935 .probe = rtl838x_serdes_probe,
3936 .suspend = genphy_suspend,
3937 .resume = genphy_resume,
3938 .set_loopback = genphy_loopback,
3939 .read_status = rtl8380_read_status,
3940 },
3941 {
3942 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3943 .name = "Realtek RTL8393 SERDES",
3944 .features = PHY_GBIT_FIBRE_FEATURES,
3945 .flags = PHY_HAS_REALTEK_PAGES,
3946 .probe = rtl8393_serdes_probe,
3947 .suspend = genphy_suspend,
3948 .resume = genphy_resume,
3949 .set_loopback = genphy_loopback,
3950 .read_status = rtl8393_read_status,
3951 },
3952 {
3953 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3954 .name = "Realtek RTL8390 Generic",
3955 .features = PHY_GBIT_FIBRE_FEATURES,
3956 .flags = PHY_HAS_REALTEK_PAGES,
3957 .probe = rtl8390_serdes_probe,
3958 .suspend = genphy_suspend,
3959 .resume = genphy_resume,
3960 .set_loopback = genphy_loopback,
3961 },
3962 {
3963 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3964 .name = "REALTEK RTL9300 SERDES",
3965 .features = PHY_GBIT_FIBRE_FEATURES,
3966 .flags = PHY_HAS_REALTEK_PAGES,
3967 .probe = rtl9300_serdes_probe,
3968 .suspend = genphy_suspend,
3969 .resume = genphy_resume,
3970 .set_loopback = genphy_loopback,
3971 .read_status = rtl9300_read_status,
3972 },
3973 };
3974
3975 module_phy_driver(rtl83xx_phy_driver);
3976
3977 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
3978 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
3979 { }
3980 };
3981
3982 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
3983
3984 MODULE_AUTHOR("B. Koblitz");
3985 MODULE_DESCRIPTION("RTL83xx PHY driver");
3986 MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich