projects / openwrt / staging / jow.git / blob
? search:


7e4a4dfc9059dfb9d13ece6beba3ab18a630bd8d
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
16 #include <linux/mdio.h>
17
18 #include <asm/mach-rtl838x/mach-rtl83xx.h>
19 #include "rtl83xx-phy.h"
20
21 extern struct rtl83xx_soc_info soc_info;
22 extern struct mutex smi_lock;
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /* Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_MEDIA_PAGE_AUTO 0
50 #define RTL821X_MEDIA_PAGE_COPPER 1
51 #define RTL821X_MEDIA_PAGE_FIBRE 3
52 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53
54 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55
56 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
57 * bus to detect e.g. link and media changes. For operations on the PHYs such as
58 * patching or other configuration changes such as EEE, polling needs to be disabled
59 * since otherwise these operations may fails or lead to unpredictable results.
60 */
61 DEFINE_MUTEX(poll_lock);
62
63 static const struct firmware rtl838x_8380_fw;
64 static const struct firmware rtl838x_8214fc_fw;
65 static const struct firmware rtl838x_8218b_fw;
66
67 static u64 disable_polling(int port)
68 {
69 u64 saved_state;
70
71 mutex_lock(&poll_lock);
72
73 switch (soc_info.family) {
74 case RTL8380_FAMILY_ID:
75 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
76 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
77 break;
78 case RTL8390_FAMILY_ID:
79 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
80 saved_state <<= 32;
81 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
82 sw_w32_mask(BIT(port % 32), 0,
83 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
84 break;
85 case RTL9300_FAMILY_ID:
86 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
87 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
88 break;
89 case RTL9310_FAMILY_ID:
90 pr_warn("%s not implemented for RTL931X\n", __func__);
91 break;
92 }
93
94 mutex_unlock(&poll_lock);
95
96 return saved_state;
97 }
98
99 static int resume_polling(u64 saved_state)
100 {
101 mutex_lock(&poll_lock);
102
103 switch (soc_info.family) {
104 case RTL8380_FAMILY_ID:
105 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
106 break;
107 case RTL8390_FAMILY_ID:
108 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
109 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
110 break;
111 case RTL9300_FAMILY_ID:
112 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
113 break;
114 case RTL9310_FAMILY_ID:
115 pr_warn("%s not implemented for RTL931X\n", __func__);
116 break;
117 }
118
119 mutex_unlock(&poll_lock);
120
121 return 0;
122 }
123
124 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
125 {
126 phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
127 }
128
129 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
130 {
131 /* fiber ports */
132 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
133 phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
134
135 /* copper ports */
136 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
137 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
138 }
139
140 static void rtl8380_phy_reset(struct phy_device *phydev)
141 {
142 phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
143 }
144
145 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
146 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
147 0x02A4, 0x02A4, 0x0198, 0x0198 };
148 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
149
150 /* Reset the SerDes by powering it off and set a new operations mode
151 * of the SerDes. 0x1f is off. Other modes are
152 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
153 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
154 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
155 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
156 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
157 */
158 void rtl9300_sds_rst(int sds_num, u32 mode)
159 {
160 pr_info("%s %d\n", __func__, mode);
161 if (sds_num < 0 || sds_num > 11) {
162 pr_err("Wrong SerDes number: %d\n", sds_num);
163 return;
164 }
165
166 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
167 rtl9300_sds_regs[sds_num]);
168 mdelay(10);
169
170 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
171 rtl9300_sds_regs[sds_num]);
172 mdelay(10);
173
174 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
175 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
176 }
177
178 void rtl9300_sds_set(int sds_num, u32 mode)
179 {
180 pr_info("%s %d\n", __func__, mode);
181 if (sds_num < 0 || sds_num > 11) {
182 pr_err("Wrong SerDes number: %d\n", sds_num);
183 return;
184 }
185
186 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
187 rtl9300_sds_regs[sds_num]);
188 mdelay(10);
189
190 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
191 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
192 }
193
194 u32 rtl9300_sds_mode_get(int sds_num)
195 {
196 u32 v;
197
198 if (sds_num < 0 || sds_num > 11) {
199 pr_err("Wrong SerDes number: %d\n", sds_num);
200 return 0;
201 }
202
203 v = sw_r32(rtl9300_sds_regs[sds_num]);
204 v >>= rtl9300_sds_lsb[sds_num];
205
206 return v & 0x1f;
207 }
208
209 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
210 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
211 */
212 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
213 {
214 int offset = 0;
215 int reg;
216 u32 val;
217
218 if (phy_addr == 49)
219 offset = 0x100;
220
221 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
222 * which would otherwise read as 0.
223 */
224 if (soc_info.id == 0x8393) {
225 if (phy_reg == MII_PHYSID1)
226 return 0x1c;
227 if (phy_reg == MII_PHYSID2)
228 return 0x8393;
229 }
230
231 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
232 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
233 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
234 * one 32 bit register.
235 */
236 reg = (phy_reg << 1) & 0xfc;
237 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
238
239 if (phy_reg & 1)
240 val = (val >> 16) & 0xffff;
241 else
242 val &= 0xffff;
243
244 return val;
245 }
246
247 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
248 * register which simulates commands to an internal MDIO bus.
249 */
250 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
251 {
252 int i;
253 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
254
255 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
256
257 for (i = 0; i < 100; i++) {
258 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
259 break;
260 mdelay(1);
261 }
262
263 if (i >= 100)
264 return -EIO;
265
266 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
267 }
268
269 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
270 {
271 int i;
272 u32 cmd;
273
274 sw_w32(v, RTL930X_SDS_INDACS_DATA);
275 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
276
277 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
278
279 for (i = 0; i < 100; i++) {
280 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
281 break;
282 mdelay(1);
283 }
284
285
286 if (i >= 100) {
287 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
288 return -EIO;
289 }
290
291 return 0;
292 }
293
294 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
295 {
296 int i;
297 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
298
299 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
300 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
301
302 for (i = 0; i < 100; i++) {
303 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
304 break;
305 mdelay(1);
306 }
307
308 if (i >= 100)
309 return -EIO;
310
311 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
312
313 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
314 }
315
316 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
317 {
318 int i;
319 u32 cmd;
320
321 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
322 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
323
324 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
325
326 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
327 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
328
329 for (i = 0; i < 100; i++) {
330 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
331 break;
332 mdelay(1);
333 }
334
335 if (i >= 100)
336 return -EIO;
337
338 return 0;
339 }
340
341 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
342 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
343 * in a standard page 0 of a PHY
344 */
345 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
346 {
347 int offset = 0;
348 u32 val;
349
350 if (phy_addr == 26)
351 offset = 0x100;
352 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
353
354 return val;
355 }
356
357 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
358 {
359 int offset = 0;
360 int reg;
361 u32 val;
362
363 if (phy_addr == 49)
364 offset = 0x100;
365
366 reg = (phy_reg << 1) & 0xfc;
367 val = v;
368 if (phy_reg & 1) {
369 val = val << 16;
370 sw_w32_mask(0xffff0000, val,
371 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
372 } else {
373 sw_w32_mask(0xffff, val,
374 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
375 }
376
377 return 0;
378 }
379
380 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
381 * ports of the RTL838x SoCs
382 */
383 static int rtl8380_read_status(struct phy_device *phydev)
384 {
385 int err;
386
387 err = genphy_read_status(phydev);
388
389 if (phydev->link) {
390 phydev->speed = SPEED_1000;
391 phydev->duplex = DUPLEX_FULL;
392 }
393
394 return err;
395 }
396
397 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
398 * ports of the RTL8393 SoC
399 */
400 static int rtl8393_read_status(struct phy_device *phydev)
401 {
402 int offset = 0;
403 int err;
404 int phy_addr = phydev->mdio.addr;
405 u32 v;
406
407 err = genphy_read_status(phydev);
408 if (phy_addr == 49)
409 offset = 0x100;
410
411 if (phydev->link) {
412 phydev->speed = SPEED_100;
413 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
414 * PHY registers
415 */
416 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
417 if (!(v & (1 << 13)) && (v & (1 << 6)))
418 phydev->speed = SPEED_1000;
419 phydev->duplex = DUPLEX_FULL;
420 }
421
422 return err;
423 }
424
425 static int rtl8226_read_page(struct phy_device *phydev)
426 {
427 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
428 }
429
430 static int rtl8226_write_page(struct phy_device *phydev, int page)
431 {
432 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
433 }
434
435 static int rtl8226_read_status(struct phy_device *phydev)
436 {
437 int ret = 0;
438 u32 val;
439
440 /* TODO: ret = genphy_read_status(phydev);
441 * if (ret < 0) {
442 * pr_info("%s: genphy_read_status failed\n", __func__);
443 * return ret;
444 * }
445 */
446
447 /* Link status must be read twice */
448 for (int i = 0; i < 2; i++)
449 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
450
451 phydev->link = val & BIT(2) ? 1 : 0;
452 if (!phydev->link)
453 goto out;
454
455 /* Read duplex status */
456 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
457 if (val < 0)
458 goto out;
459 phydev->duplex = !!(val & BIT(3));
460
461 /* Read speed */
462 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
463 switch (val & 0x0630) {
464 case 0x0000:
465 phydev->speed = SPEED_10;
466 break;
467 case 0x0010:
468 phydev->speed = SPEED_100;
469 break;
470 case 0x0020:
471 phydev->speed = SPEED_1000;
472 break;
473 case 0x0200:
474 phydev->speed = SPEED_10000;
475 break;
476 case 0x0210:
477 phydev->speed = SPEED_2500;
478 break;
479 case 0x0220:
480 phydev->speed = SPEED_5000;
481 break;
482 default:
483 break;
484 }
485
486 out:
487 return ret;
488 }
489
490 static int rtl8226_advertise_aneg(struct phy_device *phydev)
491 {
492 int ret = 0;
493 u32 v;
494
495 pr_info("In %s\n", __func__);
496
497 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
498 if (v < 0)
499 goto out;
500
501 v |= ADVERTISE_10HALF;
502 v |= ADVERTISE_10FULL;
503 v |= ADVERTISE_100HALF;
504 v |= ADVERTISE_100FULL;
505
506 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
507
508 /* Allow 1GBit */
509 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
510 if (v < 0)
511 goto out;
512 v |= ADVERTISE_1000FULL;
513
514 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
515 if (ret < 0)
516 goto out;
517
518 /* Allow 2.5G */
519 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
520 if (v < 0)
521 goto out;
522
523 v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
524 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
525
526 out:
527 return ret;
528 }
529
530 static int rtl8226_config_aneg(struct phy_device *phydev)
531 {
532 int ret = 0;
533 u32 v;
534
535 pr_debug("In %s\n", __func__);
536 if (phydev->autoneg == AUTONEG_ENABLE) {
537 ret = rtl8226_advertise_aneg(phydev);
538 if (ret)
539 goto out;
540 /* AutoNegotiationEnable */
541 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
542 if (v < 0)
543 goto out;
544
545 v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
546 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
547 if (ret < 0)
548 goto out;
549
550 /* RestartAutoNegotiation */
551 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
552 if (v < 0)
553 goto out;
554 v |= MDIO_AN_CTRL1_RESTART;
555
556 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
557 }
558
559 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
560
561 out:
562 return ret;
563 }
564
565 static int rtl8226_get_eee(struct phy_device *phydev,
566 struct ethtool_eee *e)
567 {
568 u32 val;
569 int addr = phydev->mdio.addr;
570
571 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
572
573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
574 if (e->eee_enabled) {
575 e->eee_enabled = !!(val & MDIO_EEE_100TX);
576 if (!e->eee_enabled) {
577 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
578 e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
579 }
580 }
581 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
582
583 return 0;
584 }
585
586 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
587 {
588 int port = phydev->mdio.addr;
589 u64 poll_state;
590 bool an_enabled;
591 u32 val;
592
593 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
594
595 poll_state = disable_polling(port);
596
597 /* Remember aneg state */
598 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
599 an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
600
601 /* Setup 100/1000MBit */
602 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
603 if (e->eee_enabled)
604 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
605 else
606 val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
607 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
608
609 /* Setup 2.5GBit */
610 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
611 if (e->eee_enabled)
612 val |= MDIO_EEE_2_5GT;
613 else
614 val &= MDIO_EEE_2_5GT;
615 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
616
617 /* RestartAutoNegotiation */
618 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
619 val |= MDIO_AN_CTRL1_RESTART;
620 phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
621
622 resume_polling(poll_state);
623
624 return 0;
625 }
626
627 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
628 const struct firmware *fw,
629 const char *name)
630 {
631 struct device *dev = &phydev->mdio.dev;
632 int err;
633 struct fw_header *h;
634 uint32_t checksum, my_checksum;
635
636 err = request_firmware(&fw, name, dev);
637 if (err < 0)
638 goto out;
639
640 if (fw->size < sizeof(struct fw_header)) {
641 pr_err("Firmware size too small.\n");
642 err = -EINVAL;
643 goto out;
644 }
645
646 h = (struct fw_header *) fw->data;
647 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
648
649 if (h->magic != 0x83808380) {
650 pr_err("Wrong firmware file: MAGIC mismatch.\n");
651 goto out;
652 }
653
654 checksum = h->checksum;
655 h->checksum = 0;
656 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
657 if (checksum != my_checksum) {
658 pr_err("Firmware checksum mismatch.\n");
659 err = -EINVAL;
660 goto out;
661 }
662 h->checksum = checksum;
663
664 return h;
665 out:
666 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
667 return NULL;
668 }
669
670 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
671 {
672 int mac = phydev->mdio.addr;
673
674 /* select main page 0 */
675 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
676 /* write to 0x8 to register 0x1d on main page 0 */
677 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
678 /* select page 0x266 */
679 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
680 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
681 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
682 /* return to main page 0 */
683 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
684 /* write to 0x0 to register 0x1d on main page 0 */
685 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
686 mdelay(1);
687 }
688
689 static int rtl8390_configure_generic(struct phy_device *phydev)
690 {
691 int mac = phydev->mdio.addr;
692 u32 val, phy_id;
693
694 val = phy_read(phydev, 2);
695 phy_id = val << 16;
696 val = phy_read(phydev, 3);
697 phy_id |= val;
698 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
699
700 /* Read internal PHY ID */
701 phy_write_paged(phydev, 31, 27, 0x0002);
702 val = phy_read_paged(phydev, 31, 28);
703
704 /* Internal RTL8218B, version 2 */
705 phydev_info(phydev, "Detected unknown %x\n", val);
706
707 return 0;
708 }
709
710 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
711 {
712 u32 val, phy_id;
713 int mac = phydev->mdio.addr;
714 struct fw_header *h;
715 u32 *rtl838x_6275B_intPhy_perport;
716 u32 *rtl8218b_6276B_hwEsd_perport;
717
718 val = phy_read(phydev, 2);
719 phy_id = val << 16;
720 val = phy_read(phydev, 3);
721 phy_id |= val;
722 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
723
724 /* Read internal PHY ID */
725 phy_write_paged(phydev, 31, 27, 0x0002);
726 val = phy_read_paged(phydev, 31, 28);
727 if (val != 0x6275) {
728 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
729 return -1;
730 }
731
732 /* Internal RTL8218B, version 2 */
733 phydev_info(phydev, "Detected internal RTL8218B\n");
734
735 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
736 if (!h)
737 return -1;
738
739 if (h->phy != 0x83800000) {
740 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
741 return -1;
742 }
743
744 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
745 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
746
747 // Currently not used
748 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
749 // int ipd_flag = 1;
750 // }
751
752 val = phy_read(phydev, MII_BMCR);
753 if (val & BMCR_PDOWN)
754 rtl8380_int_phy_on_off(phydev, true);
755 else
756 rtl8380_phy_reset(phydev);
757 msleep(100);
758
759 /* Ready PHY for patch */
760 for (int p = 0; p < 8; p++) {
761 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
762 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
763 }
764 msleep(500);
765 for (int p = 0; p < 8; p++) {
766 int i;
767
768 for (i = 0; i < 100 ; i++) {
769 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
770 if (val & 0x40)
771 break;
772 }
773 if (i >= 100) {
774 phydev_err(phydev,
775 "ERROR: Port %d not ready for patch.\n",
776 mac + p);
777 return -1;
778 }
779 }
780 for (int p = 0; p < 8; p++) {
781 int i;
782
783 i = 0;
784 while (rtl838x_6275B_intPhy_perport[i * 2]) {
785 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
786 rtl838x_6275B_intPhy_perport[i * 2],
787 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
788 i++;
789 }
790 i = 0;
791 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
792 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
793 rtl8218b_6276B_hwEsd_perport[i * 2],
794 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
795 i++;
796 }
797 }
798
799 return 0;
800 }
801
802 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
803 {
804 u32 val, ipd, phy_id;
805 int mac = phydev->mdio.addr;
806 struct fw_header *h;
807 u32 *rtl8380_rtl8218b_perchip;
808 u32 *rtl8218B_6276B_rtl8380_perport;
809 u32 *rtl8380_rtl8218b_perport;
810
811 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
812 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
813 return -1;
814 }
815 val = phy_read(phydev, 2);
816 phy_id = val << 16;
817 val = phy_read(phydev, 3);
818 phy_id |= val;
819 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
820
821 /* Read internal PHY ID */
822 phy_write_paged(phydev, 31, 27, 0x0002);
823 val = phy_read_paged(phydev, 31, 28);
824 if (val != 0x6276) {
825 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
826 return -1;
827 }
828 phydev_info(phydev, "Detected external RTL8218B\n");
829
830 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
831 if (!h)
832 return -1;
833
834 if (h->phy != 0x8218b000) {
835 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
836 return -1;
837 }
838
839 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
840 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
841 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
842
843 val = phy_read(phydev, MII_BMCR);
844 if (val & BMCR_PDOWN)
845 rtl8380_int_phy_on_off(phydev, true);
846 else
847 rtl8380_phy_reset(phydev);
848
849 msleep(100);
850
851 /* Get Chip revision */
852 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
853 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
854 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
855
856 phydev_info(phydev, "Detected chip revision %04x\n", val);
857
858 for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
859 rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
860 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
861 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
862 rtl8380_rtl8218b_perchip[i * 3 + 2]);
863 }
864
865 /* Enable PHY */
866 for (int i = 0; i < 8; i++) {
867 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
868 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
869 }
870 mdelay(100);
871
872 /* Request patch */
873 for (int i = 0; i < 8; i++) {
874 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
875 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
876 }
877
878 mdelay(300);
879
880 /* Verify patch readiness */
881 for (int i = 0; i < 8; i++) {
882 int l;
883
884 for (l = 0; l < 100; l++) {
885 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
886 if (val & 0x40)
887 break;
888 }
889 if (l >= 100) {
890 phydev_err(phydev, "Could not patch PHY\n");
891 return -1;
892 }
893 }
894
895 /* Use Broadcast ID method for patching */
896 rtl821x_phy_setup_package_broadcast(phydev, true);
897
898 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
899 phy_write_paged(phydev, 0x26e, 17, 0xb);
900 phy_write_paged(phydev, 0x26e, 16, 0x2);
901 mdelay(1);
902 ipd = phy_read_paged(phydev, 0x26e, 19);
903 phy_write_paged(phydev, 0, 30, 0);
904 ipd = (ipd >> 4) & 0xf; /* unused ? */
905
906 for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
907 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
908 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
909 }
910
911 /* Disable broadcast ID */
912 rtl821x_phy_setup_package_broadcast(phydev, false);
913
914 return 0;
915 }
916
917 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
918 {
919 int addr = phydev->mdio.addr;
920
921 /* Both the RTL8214FC and the external RTL8218B have the same
922 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
923 * at PHY IDs 0-7, while the RTL8214FC must be attached via
924 * the pair of SGMII/1000Base-X with higher PHY-IDs
925 */
926 if (soc_info.family == RTL8380_FAMILY_ID)
927 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
928 else
929 return phydev->phy_id == PHY_ID_RTL8218B_E;
930 }
931
932 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
933 {
934 int mac = phydev->mdio.addr;
935
936 static int reg[] = {16, 19, 20, 21};
937 u32 val;
938
939 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
940 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
941 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
942
943 if (val & BMCR_PDOWN)
944 return false;
945
946 return true;
947 }
948
949 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
950 {
951 char *state = on ? "on" : "off";
952
953 if (port == PORT_FIBRE) {
954 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
955 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
956 } else {
957 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
958 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
959 }
960
961 if (on) {
962 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
963 } else {
964 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
965 }
966
967 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
968 }
969
970 static int rtl8214fc_suspend(struct phy_device *phydev)
971 {
972 rtl8214fc_power_set(phydev, PORT_MII, false);
973 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
974
975 return 0;
976 }
977
978 static int rtl8214fc_resume(struct phy_device *phydev)
979 {
980 if (rtl8214fc_media_is_fibre(phydev)) {
981 rtl8214fc_power_set(phydev, PORT_MII, false);
982 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
983 } else {
984 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
985 rtl8214fc_power_set(phydev, PORT_MII, true);
986 }
987
988 return 0;
989 }
990
991 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
992 {
993 int mac = phydev->mdio.addr;
994
995 static int reg[] = {16, 19, 20, 21};
996 int val;
997
998 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
999 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1000 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1001
1002 val |= BIT(10);
1003 if (set_fibre) {
1004 val &= ~BMCR_PDOWN;
1005 } else {
1006 val |= BMCR_PDOWN;
1007 }
1008
1009 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1010 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1011 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1012
1013 if (!phydev->suspended) {
1014 if (set_fibre) {
1015 rtl8214fc_power_set(phydev, PORT_MII, false);
1016 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1017 } else {
1018 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1019 rtl8214fc_power_set(phydev, PORT_MII, true);
1020 }
1021 }
1022 }
1023
1024 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1025 {
1026 bool is_fibre = (port == PORT_FIBRE ? true : false);
1027 int addr = phydev->mdio.addr;
1028
1029 pr_debug("%s port %d to %d\n", __func__, addr, port);
1030
1031 rtl8214fc_media_set(phydev, is_fibre);
1032
1033 return 0;
1034 }
1035
1036 static int rtl8214fc_get_port(struct phy_device *phydev)
1037 {
1038 int addr = phydev->mdio.addr;
1039
1040 pr_debug("%s: port %d\n", __func__, addr);
1041 if (rtl8214fc_media_is_fibre(phydev))
1042 return PORT_FIBRE;
1043
1044 return PORT_MII;
1045 }
1046
1047 /* Enable EEE on the RTL8218B PHYs
1048 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1049 * but the only way that works since the kernel first enables EEE in the MAC
1050 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1051 */
1052 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1053 {
1054 u32 val;
1055 bool an_enabled;
1056
1057 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1058 /* Set GPHY page to copper */
1059 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1060
1061 val = phy_read(phydev, MII_BMCR);
1062 an_enabled = val & BMCR_ANENABLE;
1063
1064 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1065 val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
1066 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1067
1068 /* 500M EEE ability */
1069 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1070 if (enable)
1071 val |= BIT(7);
1072 else
1073 val &= ~BIT(7);
1074 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1075
1076 /* Restart AN if enabled */
1077 if (an_enabled) {
1078 val = phy_read(phydev, MII_BMCR);
1079 val |= BMCR_ANRESTART;
1080 phy_write(phydev, MII_BMCR, val);
1081 }
1082
1083 /* GPHY page back to auto */
1084 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1085 }
1086
1087 static int rtl8218b_get_eee(struct phy_device *phydev,
1088 struct ethtool_eee *e)
1089 {
1090 u32 val;
1091 int addr = phydev->mdio.addr;
1092
1093 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1094
1095 /* Set GPHY page to copper */
1096 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1097
1098 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1099 if (e->eee_enabled) {
1100 /* Verify vs MAC-based EEE */
1101 e->eee_enabled = !!(val & BIT(7));
1102 if (!e->eee_enabled) {
1103 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1104 e->eee_enabled = !!(val & BIT(4));
1105 }
1106 }
1107 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1108
1109 /* GPHY page to auto */
1110 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1111
1112 return 0;
1113 }
1114
1115 static int rtl8218d_get_eee(struct phy_device *phydev,
1116 struct ethtool_eee *e)
1117 {
1118 u32 val;
1119 int addr = phydev->mdio.addr;
1120
1121 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1122
1123 /* Set GPHY page to copper */
1124 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1125
1126 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1127 if (e->eee_enabled)
1128 e->eee_enabled = !!(val & BIT(7));
1129 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1130
1131 /* GPHY page to auto */
1132 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1133
1134 return 0;
1135 }
1136
1137 static int rtl8214fc_set_eee(struct phy_device *phydev,
1138 struct ethtool_eee *e)
1139 {
1140 u32 poll_state;
1141 int port = phydev->mdio.addr;
1142 bool an_enabled;
1143 u32 val;
1144
1145 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1146
1147 if (rtl8214fc_media_is_fibre(phydev)) {
1148 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1149 return -ENOTSUPP;
1150 }
1151
1152 poll_state = disable_polling(port);
1153
1154 /* Set GPHY page to copper */
1155 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1156
1157 /* Get auto-negotiation status */
1158 val = phy_read(phydev, MII_BMCR);
1159 an_enabled = val & BMCR_ANENABLE;
1160
1161 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1162 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1163 val &= ~BIT(5); /* Use MAC-based EEE */
1164 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1165
1166 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1167 phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1168
1169 /* 500M EEE ability */
1170 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1171 if (e->eee_enabled)
1172 val |= BIT(7);
1173 else
1174 val &= ~BIT(7);
1175
1176 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1177
1178 /* Restart AN if enabled */
1179 if (an_enabled) {
1180 pr_info("%s: doing aneg\n", __func__);
1181 val = phy_read(phydev, MII_BMCR);
1182 val |= BMCR_ANRESTART;
1183 phy_write(phydev, MII_BMCR, val);
1184 }
1185
1186 /* GPHY page back to auto */
1187 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1188
1189 resume_polling(poll_state);
1190
1191 return 0;
1192 }
1193
1194 static int rtl8214fc_get_eee(struct phy_device *phydev,
1195 struct ethtool_eee *e)
1196 {
1197 int addr = phydev->mdio.addr;
1198
1199 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1200 if (rtl8214fc_media_is_fibre(phydev)) {
1201 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1202 return -ENOTSUPP;
1203 }
1204
1205 return rtl8218b_get_eee(phydev, e);
1206 }
1207
1208 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1209 {
1210 int port = phydev->mdio.addr;
1211 u64 poll_state;
1212 u32 val;
1213 bool an_enabled;
1214
1215 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1216
1217 poll_state = disable_polling(port);
1218
1219 /* Set GPHY page to copper */
1220 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1221 val = phy_read(phydev, MII_BMCR);
1222 an_enabled = val & BMCR_ANENABLE;
1223
1224 if (e->eee_enabled) {
1225 /* 100/1000M EEE Capability */
1226 phy_write(phydev, 13, 0x0007);
1227 phy_write(phydev, 14, 0x003C);
1228 phy_write(phydev, 13, 0x4007);
1229 phy_write(phydev, 14, 0x0006);
1230
1231 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1232 val |= BIT(4);
1233 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1234 } else {
1235 /* 100/1000M EEE Capability */
1236 phy_write(phydev, 13, 0x0007);
1237 phy_write(phydev, 14, 0x003C);
1238 phy_write(phydev, 13, 0x0007);
1239 phy_write(phydev, 14, 0x0000);
1240
1241 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1242 val &= ~BIT(4);
1243 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1244 }
1245
1246 /* Restart AN if enabled */
1247 if (an_enabled) {
1248 val = phy_read(phydev, MII_BMCR);
1249 val |= BMCR_ANRESTART;
1250 phy_write(phydev, MII_BMCR, val);
1251 }
1252
1253 /* GPHY page back to auto */
1254 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1255
1256 pr_info("%s done\n", __func__);
1257 resume_polling(poll_state);
1258
1259 return 0;
1260 }
1261
1262 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1263 {
1264 int addr = phydev->mdio.addr;
1265 u64 poll_state;
1266
1267 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1268
1269 poll_state = disable_polling(addr);
1270
1271 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1272
1273 resume_polling(poll_state);
1274
1275 return 0;
1276 }
1277
1278 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1279 {
1280 return phydev->phy_id == PHY_ID_RTL8214C;
1281 }
1282
1283 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1284 {
1285 u32 phy_id, val;
1286 int mac = phydev->mdio.addr;
1287
1288 val = phy_read(phydev, 2);
1289 phy_id = val << 16;
1290 val = phy_read(phydev, 3);
1291 phy_id |= val;
1292 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1293
1294 phydev_info(phydev, "Detected external RTL8214C\n");
1295
1296 /* GPHY auto conf */
1297 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1298
1299 return 0;
1300 }
1301
1302 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1303 {
1304 int mac = phydev->mdio.addr;
1305 struct fw_header *h;
1306 u32 *rtl8380_rtl8214fc_perchip;
1307 u32 *rtl8380_rtl8214fc_perport;
1308 u32 phy_id;
1309 u32 val;
1310
1311 val = phy_read(phydev, 2);
1312 phy_id = val << 16;
1313 val = phy_read(phydev, 3);
1314 phy_id |= val;
1315 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1316
1317 /* Read internal PHY id */
1318 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1319 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1320 val = phy_read_paged(phydev, 0x1f, 0x1c);
1321 if (val != 0x6276) {
1322 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1323 return -1;
1324 }
1325 phydev_info(phydev, "Detected external RTL8214FC\n");
1326
1327 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1328 if (!h)
1329 return -1;
1330
1331 if (h->phy != 0x8214fc00) {
1332 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1333 return -1;
1334 }
1335
1336 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1337
1338 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1339
1340 /* detect phy version */
1341 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1342 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1343
1344 val = phy_read(phydev, 16);
1345 if (val & BMCR_PDOWN)
1346 rtl8380_rtl8214fc_on_off(phydev, true);
1347 else
1348 rtl8380_phy_reset(phydev);
1349
1350 msleep(100);
1351 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1352
1353 for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
1354 rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
1355 u32 page = 0;
1356
1357 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1358 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1359 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1360 val = phy_read_paged(phydev, 0x260, 13);
1361 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1362 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1363 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1364 } else {
1365 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1366 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1367 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1368 }
1369 }
1370
1371 /* Force copper medium */
1372 for (int i = 0; i < 4; i++) {
1373 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1374 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1375 }
1376
1377 /* Enable PHY */
1378 for (int i = 0; i < 4; i++) {
1379 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1380 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1381 }
1382 mdelay(100);
1383
1384 /* Disable Autosensing */
1385 for (int i = 0; i < 4; i++) {
1386 int l;
1387
1388 for (l = 0; l < 100; l++) {
1389 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1390 if ((val & 0x7) >= 3)
1391 break;
1392 }
1393 if (l >= 100) {
1394 phydev_err(phydev, "Could not disable autosensing\n");
1395 return -1;
1396 }
1397 }
1398
1399 /* Request patch */
1400 for (int i = 0; i < 4; i++) {
1401 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1402 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1403 }
1404 mdelay(300);
1405
1406 /* Verify patch readiness */
1407 for (int i = 0; i < 4; i++) {
1408 int l;
1409
1410 for (l = 0; l < 100; l++) {
1411 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1412 if (val & 0x40)
1413 break;
1414 }
1415 if (l >= 100) {
1416 phydev_err(phydev, "Could not patch PHY\n");
1417 return -1;
1418 }
1419 }
1420 /* Use Broadcast ID method for patching */
1421 rtl821x_phy_setup_package_broadcast(phydev, true);
1422
1423 for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
1424 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1425 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1426 }
1427
1428 /* Disable broadcast ID */
1429 rtl821x_phy_setup_package_broadcast(phydev, false);
1430
1431 /* Auto medium selection */
1432 for (int i = 0; i < 4; i++) {
1433 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1434 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1435 }
1436
1437 return 0;
1438 }
1439
1440 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1441 {
1442 int addr = phydev->mdio.addr;
1443
1444 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1445 }
1446
1447 static int rtl8380_configure_serdes(struct phy_device *phydev)
1448 {
1449 u32 v;
1450 u32 sds_conf_value;
1451 int i;
1452 struct fw_header *h;
1453 u32 *rtl8380_sds_take_reset;
1454 u32 *rtl8380_sds_common;
1455 u32 *rtl8380_sds01_qsgmii_6275b;
1456 u32 *rtl8380_sds23_qsgmii_6275b;
1457 u32 *rtl8380_sds4_fiber_6275b;
1458 u32 *rtl8380_sds5_fiber_6275b;
1459 u32 *rtl8380_sds_reset;
1460 u32 *rtl8380_sds_release_reset;
1461
1462 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1463
1464 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1465 if (!h)
1466 return -1;
1467
1468 if (h->magic != 0x83808380) {
1469 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1470 return -1;
1471 }
1472
1473 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1474
1475 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1476
1477 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1478
1479 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1480
1481 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1482
1483 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1484
1485 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1486
1487 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1488
1489 /* Back up serdes power off value */
1490 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1491 pr_info("SDS power down value: %x\n", sds_conf_value);
1492
1493 /* take serdes into reset */
1494 i = 0;
1495 while (rtl8380_sds_take_reset[2 * i]) {
1496 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1497 i++;
1498 udelay(1000);
1499 }
1500
1501 /* apply common serdes patch */
1502 i = 0;
1503 while (rtl8380_sds_common[2 * i]) {
1504 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1505 i++;
1506 udelay(1000);
1507 }
1508
1509 /* internal R/W enable */
1510 sw_w32(3, RTL838X_INT_RW_CTRL);
1511
1512 /* SerDes ports 4 and 5 are FIBRE ports */
1513 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1514
1515 /* SerDes module settings, SerDes 0-3 are QSGMII */
1516 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1517 /* SerDes 4 and 5 are 1000BX FIBRE */
1518 v |= 0x4 << 5 | 0x4;
1519 sw_w32(v, RTL838X_SDS_MODE_SEL);
1520
1521 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1522 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1523 i = 0;
1524 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1525 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1526 rtl8380_sds01_qsgmii_6275b[2 * i]);
1527 i++;
1528 }
1529
1530 i = 0;
1531 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1532 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1533 i++;
1534 }
1535
1536 i = 0;
1537 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1538 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1539 i++;
1540 }
1541
1542 i = 0;
1543 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1544 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1545 i++;
1546 }
1547
1548 i = 0;
1549 while (rtl8380_sds_reset[2 * i]) {
1550 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1551 i++;
1552 }
1553
1554 i = 0;
1555 while (rtl8380_sds_release_reset[2 * i]) {
1556 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1557 i++;
1558 }
1559
1560 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1561 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1562
1563 pr_info("Configuration of SERDES done\n");
1564
1565 return 0;
1566 }
1567
1568 static int rtl8390_configure_serdes(struct phy_device *phydev)
1569 {
1570 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1571
1572 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1573 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1574
1575 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1576 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1577 * and FRE16_EEE_QUIET_FIB1G
1578 */
1579 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1580
1581 return 0;
1582 }
1583
1584 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1585 {
1586 int l = end_bit - start_bit + 1;
1587 u32 data = v;
1588
1589 if (l < 32) {
1590 u32 mask = BIT(l) - 1;
1591
1592 data = rtl930x_read_sds_phy(sds, page, reg);
1593 data &= ~(mask << start_bit);
1594 data |= (v & mask) << start_bit;
1595 }
1596
1597 rtl930x_write_sds_phy(sds, page, reg, data);
1598 }
1599
1600 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1601 {
1602 int l = end_bit - start_bit + 1;
1603 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1604
1605 if (l >= 32)
1606 return v;
1607
1608 return (v >> start_bit) & (BIT(l) - 1);
1609 }
1610
1611 /* Read the link and speed status of the internal SerDes of the RTL9300
1612 */
1613 static int rtl9300_read_status(struct phy_device *phydev)
1614 {
1615 struct device *dev = &phydev->mdio.dev;
1616 int phy_addr = phydev->mdio.addr;
1617 struct device_node *dn;
1618 u32 sds_num = 0, status, latch_status, mode;
1619
1620 if (dev->of_node) {
1621 dn = dev->of_node;
1622
1623 if (of_property_read_u32(dn, "sds", &sds_num))
1624 sds_num = -1;
1625 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1626 } else {
1627 dev_err(dev, "No DT node.\n");
1628 return -EINVAL;
1629 }
1630
1631 if (sds_num < 0)
1632 return 0;
1633
1634 mode = rtl9300_sds_mode_get(sds_num);
1635 pr_info("%s got SDS mode %02x\n", __func__, mode);
1636 if (mode == 0x1a) { /* 10GR mode */
1637 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1638 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1639 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1640 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1641 } else {
1642 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1643 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1644 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1645 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1646 }
1647
1648 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1649
1650 if (latch_status) {
1651 phydev->link = true;
1652 if (mode == 0x1a)
1653 phydev->speed = SPEED_10000;
1654 else
1655 phydev->speed = SPEED_1000;
1656
1657 phydev->duplex = DUPLEX_FULL;
1658 }
1659
1660 return 0;
1661 }
1662
1663 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1664 {
1665 int page = 0x2e; /* 10GR and USXGMII */
1666
1667 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1668 page = 0x24;
1669
1670 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1671 mdelay(5);
1672 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1673 }
1674
1675 /* Force PHY modes on 10GBit Serdes
1676 */
1677 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1678 {
1679 int lc_value;
1680 int sds_mode;
1681 bool lc_on;
1682 int lane_0 = (sds % 2) ? sds - 1 : sds;
1683 u32 v;
1684
1685 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1686 switch (phy_if) {
1687 case PHY_INTERFACE_MODE_SGMII:
1688 sds_mode = 0x2;
1689 lc_on = false;
1690 lc_value = 0x1;
1691 break;
1692
1693 case PHY_INTERFACE_MODE_HSGMII:
1694 sds_mode = 0x12;
1695 lc_value = 0x3;
1696 /* Configure LC */
1697 break;
1698
1699 case PHY_INTERFACE_MODE_1000BASEX:
1700 sds_mode = 0x04;
1701 lc_on = false;
1702 break;
1703
1704 case PHY_INTERFACE_MODE_2500BASEX:
1705 sds_mode = 0x16;
1706 lc_value = 0x3;
1707 /* Configure LC */
1708 break;
1709
1710 case PHY_INTERFACE_MODE_10GBASER:
1711 sds_mode = 0x1a;
1712 lc_on = true;
1713 lc_value = 0x5;
1714 break;
1715
1716 case PHY_INTERFACE_MODE_NA:
1717 /* This will disable SerDes */
1718 sds_mode = 0x1f;
1719 break;
1720
1721 default:
1722 pr_err("%s: unknown serdes mode: %s\n",
1723 __func__, phy_modes(phy_if));
1724 return;
1725 }
1726
1727 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1728 /* Power down SerDes */
1729 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1730 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1731
1732 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1733 /* Force mode enable */
1734 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1735 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1736
1737 /* SerDes off */
1738 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1739
1740 if (phy_if == PHY_INTERFACE_MODE_NA)
1741 return;
1742
1743 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1744 /* Enable LC and ring */
1745 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1746
1747 if (sds == lane_0)
1748 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1749 else
1750 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1751
1752 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1753
1754 if (lc_on)
1755 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1756 else
1757 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1758
1759 /* Force analog LC & ring on */
1760 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1761
1762 v = lc_on ? 0x3 : 0x1;
1763
1764 if (sds == lane_0)
1765 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1766 else
1767 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1768
1769 /* Force SerDes mode */
1770 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1771 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1772
1773 /* Toggle LC or Ring */
1774 for (int i = 0; i < 20; i++) {
1775 u32 cr_0, cr_1, cr_2;
1776 u32 m_bit, l_bit;
1777
1778 mdelay(200);
1779
1780 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1781
1782 m_bit = (lane_0 == sds) ? (4) : (5);
1783 l_bit = (lane_0 == sds) ? (4) : (5);
1784
1785 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1786 mdelay(10);
1787 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1788 mdelay(10);
1789 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1790
1791 if (cr_0 && cr_1 && cr_2) {
1792 u32 t;
1793
1794 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1795 break;
1796
1797 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1798 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1799
1800 /* Reset FSM */
1801 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1802 mdelay(10);
1803 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1804 mdelay(10);
1805
1806 /* Need to read this twice */
1807 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1808 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1809
1810 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1811
1812 /* Reset FSM again */
1813 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1814 mdelay(10);
1815 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1816 mdelay(10);
1817
1818 if (v == 1)
1819 break;
1820 }
1821
1822 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1823 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1824
1825 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1826 mdelay(10);
1827 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1828 }
1829
1830 rtl930x_sds_rx_rst(sds, phy_if);
1831
1832 /* Re-enable power */
1833 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1834
1835 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1836 }
1837
1838 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1839 {
1840 /* parameters: rtl9303_80G_txParam_s2 */
1841 int impedance = 0x8;
1842 int pre_amp = 0x2;
1843 int main_amp = 0x9;
1844 int post_amp = 0x2;
1845 int pre_en = 0x1;
1846 int post_en = 0x1;
1847 int page;
1848
1849 switch(phy_if) {
1850 case PHY_INTERFACE_MODE_1000BASEX:
1851 page = 0x25;
1852 break;
1853 case PHY_INTERFACE_MODE_HSGMII:
1854 case PHY_INTERFACE_MODE_2500BASEX:
1855 page = 0x29;
1856 break;
1857 case PHY_INTERFACE_MODE_10GBASER:
1858 page = 0x2f;
1859 break;
1860 default:
1861 pr_err("%s: unsupported PHY mode\n", __func__);
1862 return;
1863 }
1864
1865 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1866 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1867 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1868 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1869 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1870 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1871 }
1872
1873 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1874 * timeout is in ms
1875 */
1876 int rtl9300_sds_clock_wait(int timeout)
1877 {
1878 u32 v;
1879 unsigned long start = jiffies;
1880
1881 do {
1882 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1883 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1884 if (v == 3)
1885 return 0;
1886 } while (jiffies < start + (HZ / 1000) * timeout);
1887
1888 return 1;
1889 }
1890
1891 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1892 {
1893 u32 v10, v1;
1894
1895 v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
1896 v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
1897 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1898
1899 v10 &= ~(BIT(13) | BIT(14));
1900 v1 &= ~(BIT(8) | BIT(9));
1901
1902 v10 |= rx_normal ? 0 : BIT(13);
1903 v1 |= rx_normal ? 0 : BIT(9);
1904
1905 v10 |= tx_normal ? 0 : BIT(14);
1906 v1 |= tx_normal ? 0 : BIT(8);
1907
1908 rtl930x_write_sds_phy(sds, 6, 2, v10);
1909 rtl930x_write_sds_phy(sds, 0, 0, v1);
1910
1911 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1912 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1913 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1914 }
1915
1916 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1917 {
1918 if (manual) {
1919 switch(dcvs_id) {
1920 case 0:
1921 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1922 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1923 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1924 break;
1925 case 1:
1926 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1927 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1928 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1929 break;
1930 case 2:
1931 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1932 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1933 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1934 break;
1935 case 3:
1936 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1937 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1938 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1939 break;
1940 case 4:
1941 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1942 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1943 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1944 break;
1945 case 5:
1946 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1947 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1948 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1949 break;
1950 default:
1951 break;
1952 }
1953 } else {
1954 switch(dcvs_id) {
1955 case 0:
1956 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1957 break;
1958 case 1:
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1960 break;
1961 case 2:
1962 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1963 break;
1964 case 3:
1965 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1966 break;
1967 case 4:
1968 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1969 break;
1970 case 5:
1971 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1972 break;
1973 default:
1974 break;
1975 }
1976 mdelay(1);
1977 }
1978 }
1979
1980 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1981 {
1982 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1983 bool dcvs_manual;
1984
1985 if (!(sds_num % 2))
1986 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
1987 else
1988 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
1989
1990 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
1991 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
1992
1993 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
1994 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
1995
1996 switch(dcvs_id) {
1997 case 0:
1998 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
1999 mdelay(1);
2000
2001 /* ##DCVS0 Read Out */
2002 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2003 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2004 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2005 break;
2006
2007 case 1:
2008 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2009 mdelay(1);
2010
2011 /* ##DCVS0 Read Out */
2012 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2013 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2014 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2015 break;
2016
2017 case 2:
2018 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2019 mdelay(1);
2020
2021 /* ##DCVS0 Read Out */
2022 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2023 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2024 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2025 break;
2026 case 3:
2027 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2028 mdelay(1);
2029
2030 /* ##DCVS0 Read Out */
2031 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2032 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2033 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2034 break;
2035
2036 case 4:
2037 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2038 mdelay(1);
2039
2040 /* ##DCVS0 Read Out */
2041 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2042 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2043 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2044 break;
2045
2046 case 5:
2047 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2048 mdelay(1);
2049
2050 /* ##DCVS0 Read Out */
2051 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2052 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2053 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2054 break;
2055
2056 default:
2057 break;
2058 }
2059
2060 if (dcvs_sign_out)
2061 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2062 else
2063 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2064
2065 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2066 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2067
2068 dcvs_list[0] = dcvs_sign_out;
2069 dcvs_list[1] = dcvs_coef_bin;
2070 }
2071
2072 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2073 {
2074 if (manual) {
2075 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2076 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2077 } else {
2078 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2079 mdelay(100);
2080 }
2081 }
2082
2083 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2084 {
2085 if (manual) {
2086 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2087 } else {
2088 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2089 mdelay(1);
2090 }
2091 }
2092
2093 #define GRAY_BITS 5
2094 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2095 {
2096 int i, j, m;
2097 u32 g[GRAY_BITS];
2098 u32 c[GRAY_BITS];
2099 u32 leq_binary = 0;
2100
2101 for(i = 0; i < GRAY_BITS; i++)
2102 g[i] = (gray_code & BIT(i)) >> i;
2103
2104 m = GRAY_BITS - 1;
2105
2106 c[m] = g[m];
2107
2108 for(i = 0; i < m; i++) {
2109 c[i] = g[i];
2110 for(j = i + 1; j < GRAY_BITS; j++)
2111 c[i] = c[i] ^ g[j];
2112 }
2113
2114 for(i = 0; i < GRAY_BITS; i++)
2115 leq_binary += c[i] << i;
2116
2117 return leq_binary;
2118 }
2119
2120 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2121 {
2122 u32 leq_gray, leq_bin;
2123 bool leq_manual;
2124
2125 if (!(sds_num % 2))
2126 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2127 else
2128 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2129
2130 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2131 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2132
2133 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2134 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2135 mdelay(1);
2136
2137 /* ##LEQ Read Out */
2138 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2139 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2140 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2141
2142 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2143 pr_info("LEQ manual: %u", leq_manual);
2144
2145 return leq_bin;
2146 }
2147
2148 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2149 {
2150 if (manual) {
2151 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2152 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2153 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2154 } else {
2155 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2156 mdelay(10);
2157 }
2158 }
2159
2160 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2161 {
2162 u32 vth_manual;
2163
2164 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2165 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2166 if (!(sds_num % 2))
2167 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2168 else
2169 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2170
2171 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2172 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2173 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2174 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2175 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2176 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2177
2178 mdelay(1);
2179
2180 /* ##VthP & VthN Read Out */
2181 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2182 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2183
2184 pr_info("vth_set_bin = %d", vth_list[0]);
2185 pr_info("vth_set_bin = %d", vth_list[1]);
2186
2187 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2188 pr_info("Vth Maunal = %d", vth_manual);
2189 }
2190
2191 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2192 {
2193 if (manual) {
2194 switch(tap_id) {
2195 case 0:
2196 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2197 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2198 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2199 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2200 break;
2201 case 1:
2202 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2203 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2204 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2205 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2206 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2207 break;
2208 case 2:
2209 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2210 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2211 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2212 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2213 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2214 break;
2215 case 3:
2216 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2217 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2218 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2219 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2220 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2221 break;
2222 case 4:
2223 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2224 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2225 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2226 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2227 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2228 break;
2229 default:
2230 break;
2231 }
2232 } else {
2233 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2234 mdelay(10);
2235 }
2236 }
2237
2238 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2239 {
2240 u32 tap0_sign_out;
2241 u32 tap0_coef_bin;
2242 u32 tap_sign_out_even;
2243 u32 tap_coef_bin_even;
2244 u32 tap_sign_out_odd;
2245 u32 tap_coef_bin_odd;
2246 bool tap_manual;
2247
2248 if (!(sds_num % 2))
2249 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2250 else
2251 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2252
2253 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2254 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2255 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2256 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2257
2258 if (!tap_id) {
2259 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2260 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2261 /* ##Tap1 Even Read Out */
2262 mdelay(1);
2263 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2264 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2265
2266 if (tap0_sign_out == 1)
2267 pr_info("Tap0 Sign : -");
2268 else
2269 pr_info("Tap0 Sign : +");
2270
2271 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2272
2273 tap_list[0] = tap0_sign_out;
2274 tap_list[1] = tap0_coef_bin;
2275
2276 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2277 pr_info("tap0 manual = %u",tap_manual);
2278 } else {
2279 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2280 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2281 mdelay(1);
2282 /* ##Tap1 Even Read Out */
2283 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2284 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2285
2286 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2287 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2288 /* ##Tap1 Odd Read Out */
2289 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2290 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2291
2292 if (tap_sign_out_even == 1)
2293 pr_info("Tap %u even sign: -", tap_id);
2294 else
2295 pr_info("Tap %u even sign: +", tap_id);
2296
2297 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2298
2299 if (tap_sign_out_odd == 1)
2300 pr_info("Tap %u odd sign: -", tap_id);
2301 else
2302 pr_info("Tap %u odd sign: +", tap_id);
2303
2304 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2305
2306 tap_list[0] = tap_sign_out_even;
2307 tap_list[1] = tap_coef_bin_even;
2308 tap_list[2] = tap_sign_out_odd;
2309 tap_list[3] = tap_coef_bin_odd;
2310
2311 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2312 pr_info("tap %u manual = %d",tap_id, tap_manual);
2313 }
2314 }
2315
2316 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2317 {
2318 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2319 int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2320 int vth_min = 0x0;
2321
2322 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2323 rtl930x_write_sds_phy(sds, 6, 0, 0);
2324
2325 /* FGCAL */
2326 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2327 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2328 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2329
2330 /* DCVS */
2331 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2332 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2333 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2334 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2335 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2336 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2337 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2338 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2339 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2340 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2341 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2342 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2343
2344 /* LEQ (Long Term Equivalent signal level) */
2345 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2346
2347 /* DFE (Decision Fed Equalizer) */
2348 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2349 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2350 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2351 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2352 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2353 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2354 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2355 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2356 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2357
2358 /* Vth */
2359 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2360 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2361 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2362
2363 pr_info("end_1.1.1 --\n");
2364
2365 pr_info("start_1.1.2 Load DFE init. value\n");
2366
2367 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2368
2369 pr_info("end_1.1.2\n");
2370
2371 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2372
2373 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2374 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2375 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2376 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2377 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2378 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2379
2380 pr_info("end_1.1.3 --\n");
2381
2382 pr_info("start_1.1.4 offset cali setting\n");
2383
2384 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2385
2386 pr_info("end_1.1.4\n");
2387
2388 pr_info("start_1.1.5 LEQ and DFE setting\n");
2389
2390 /* TODO: make this work for DAC cables of different lengths */
2391 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2392 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2393 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2394 else
2395 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2396
2397 /* No serdes, check for Aquantia PHYs */
2398 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2399
2400 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2401 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2402 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2403 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2404 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2405
2406 pr_info("end_1.1.5\n");
2407 }
2408
2409 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2410 {
2411 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2412
2413 /* Gray config endis to 1 */
2414 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2415
2416 /* ForegroundOffsetCal_Manual(auto mode) */
2417 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2418
2419 pr_info("end_1.2.1");
2420 }
2421
2422 void rtl9300_do_rx_calibration_2_2(int sds_num)
2423 {
2424 /* Force Rx-Run = 0 */
2425 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2426
2427 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2428 }
2429
2430 void rtl9300_do_rx_calibration_2_3(int sds_num)
2431 {
2432 u32 fgcal_binary, fgcal_gray;
2433 u32 offset_range;
2434
2435 pr_info("start_1.2.3 Foreground Calibration\n");
2436
2437 while(1) {
2438 if (!(sds_num % 2))
2439 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2440 else
2441 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2442
2443 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2444 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2445 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2446 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2447 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2448 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2449 /* ##FGCAL read gray */
2450 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2451 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2452 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2453 /* ##FGCAL read binary */
2454 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2455
2456 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2457 __func__, fgcal_gray, fgcal_binary);
2458
2459 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2460
2461 if (fgcal_binary > 60 || fgcal_binary < 3) {
2462 if (offset_range == 3) {
2463 pr_info("%s: Foreground Calibration result marginal!", __func__);
2464 break;
2465 } else {
2466 offset_range++;
2467 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2468 rtl9300_do_rx_calibration_2_2(sds_num);
2469 }
2470 } else {
2471 break;
2472 }
2473 }
2474 pr_info("%s: end_1.2.3\n", __func__);
2475 }
2476
2477 void rtl9300_do_rx_calibration_2(int sds)
2478 {
2479 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2480 rtl9300_do_rx_calibration_2_1(sds);
2481 rtl9300_do_rx_calibration_2_2(sds);
2482 rtl9300_do_rx_calibration_2_3(sds);
2483 }
2484
2485 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2486 {
2487 pr_info("start_1.3.1");
2488
2489 /* ##1.3.1 */
2490 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2491 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2492
2493 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2494 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2495
2496 pr_info("end_1.3.1");
2497 }
2498
2499 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2500 {
2501 u32 sum10 = 0, avg10, int10;
2502 int dac_long_cable_offset;
2503 bool eq_hold_enabled;
2504 int i;
2505
2506 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2507 /* rtl9300_rxCaliConf_serdes_myParam */
2508 dac_long_cable_offset = 3;
2509 eq_hold_enabled = true;
2510 } else {
2511 /* rtl9300_rxCaliConf_phy_myParam */
2512 dac_long_cable_offset = 0;
2513 eq_hold_enabled = false;
2514 }
2515
2516 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2517 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2518
2519 pr_info("start_1.3.2");
2520
2521 for(i = 0; i < 10; i++) {
2522 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2523 mdelay(10);
2524 }
2525
2526 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2527 int10 = sum10 / 10;
2528
2529 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2530
2531 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2532 if (dac_long_cable_offset) {
2533 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2534 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2535 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2536 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2537 } else {
2538 if (sum10 >= 5) {
2539 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2540 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2541 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2542 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2543 } else {
2544 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2545 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2546 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2547 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2548 }
2549 }
2550 }
2551
2552 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2553
2554 pr_info("end_1.3.2");
2555 }
2556
2557 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2558 {
2559 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2560
2561 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2562 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2563 }
2564
2565 void rtl9300_do_rx_calibration_4_1(int sds_num)
2566 {
2567 u32 vth_list[2] = {0, 0};
2568 u32 tap0_list[4] = {0, 0, 0, 0};
2569
2570 pr_info("start_1.4.1");
2571
2572 /* ##1.4.1 */
2573 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2574 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2575 mdelay(200);
2576
2577 pr_info("end_1.4.1");
2578 }
2579
2580 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2581 {
2582 u32 vth_list[2];
2583 u32 tap_list[4];
2584
2585 pr_info("start_1.4.2");
2586
2587 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2588 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2589
2590 mdelay(100);
2591
2592 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2593 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2594
2595 pr_info("end_1.4.2");
2596 }
2597
2598 void rtl9300_do_rx_calibration_4(u32 sds_num)
2599 {
2600 rtl9300_do_rx_calibration_4_1(sds_num);
2601 rtl9300_do_rx_calibration_4_2(sds_num);
2602 }
2603
2604 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2605 {
2606 u32 tap1_list[4] = {0};
2607 u32 tap2_list[4] = {0};
2608 u32 tap3_list[4] = {0};
2609 u32 tap4_list[4] = {0};
2610
2611 pr_info("start_1.5.2");
2612
2613 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2614 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2615 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2616 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2617
2618 mdelay(30);
2619
2620 pr_info("end_1.5.2");
2621 }
2622
2623 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2624 {
2625 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */
2626 rtl9300_do_rx_calibration_5_2(sds_num);
2627 }
2628
2629
2630 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2631 {
2632 u32 tap1_list[4] = {0};
2633 u32 tap2_list[4] = {0};
2634 u32 tap3_list[4] = {0};
2635 u32 tap4_list[4] = {0};
2636
2637 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2638 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2639 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2640 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2641
2642 mdelay(10);
2643 }
2644
2645 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2646 {
2647 u32 latch_sts;
2648
2649 rtl9300_do_rx_calibration_1(sds, phy_mode);
2650 rtl9300_do_rx_calibration_2(sds);
2651 rtl9300_do_rx_calibration_4(sds);
2652 rtl9300_do_rx_calibration_5(sds, phy_mode);
2653 mdelay(20);
2654
2655 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2656 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2657 pr_info("%s: SDS enabled\n", __func__);
2658 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2659 mdelay(1);
2660 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2661 if (latch_sts) {
2662 rtl9300_do_rx_calibration_dfe_disable(sds);
2663 rtl9300_do_rx_calibration_4(sds);
2664 rtl9300_do_rx_calibration_5(sds, phy_mode);
2665 }
2666 }
2667 }
2668
2669 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2670 {
2671 switch (phy_mode) {
2672 case PHY_INTERFACE_MODE_XGMII:
2673 break;
2674
2675 case PHY_INTERFACE_MODE_10GBASER:
2676 /* Read twice to clear */
2677 rtl930x_read_sds_phy(sds_num, 5, 1);
2678 rtl930x_read_sds_phy(sds_num, 5, 1);
2679 break;
2680
2681 case PHY_INTERFACE_MODE_1000BASEX:
2682 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2683 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2684 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2685 break;
2686
2687 default:
2688 pr_info("%s unsupported phy mode\n", __func__);
2689 return -1;
2690 }
2691
2692 return 0;
2693 }
2694
2695 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2696 {
2697 u32 v = 0;
2698
2699 switch (phy_mode) {
2700 case PHY_INTERFACE_MODE_XGMII:
2701 break;
2702
2703 case PHY_INTERFACE_MODE_10GBASER:
2704 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2705 return v & 0xff;
2706
2707 default:
2708 pr_info("%s unsupported PHY-mode\n", __func__);
2709 }
2710
2711 return v;
2712 }
2713
2714 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2715 {
2716 u32 errors1, errors2;
2717
2718 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2719 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2720
2721 /* Count errors during 1ms */
2722 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2723 mdelay(1);
2724 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2725
2726 switch (phy_mode) {
2727 case PHY_INTERFACE_MODE_XGMII:
2728 if ((errors2 - errors1 > 100) ||
2729 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2730 pr_info("%s XSGMII error rate too high\n", __func__);
2731 return 1;
2732 }
2733 break;
2734 case PHY_INTERFACE_MODE_10GBASER:
2735 if (errors2 > 0) {
2736 pr_info("%s 10GBASER error rate too high\n", __func__);
2737 return 1;
2738 }
2739 break;
2740 default:
2741 return 1;
2742 }
2743
2744 return 0;
2745 }
2746
2747 void rtl9300_phy_enable_10g_1g(int sds_num)
2748 {
2749 u32 v;
2750
2751 /* Enable 1GBit PHY */
2752 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
2753 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2754 v &= ~BMCR_PDOWN;
2755 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
2756 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2757
2758 /* Enable 10GBit PHY */
2759 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
2760 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2761 v &= ~BMCR_PDOWN;
2762 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
2763 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2764
2765 /* dal_longan_construct_mac_default_10gmedia_fiber */
2766 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2767 pr_info("%s set medium: %08x\n", __func__, v);
2768 v |= BIT(1);
2769 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2770 pr_info("%s set medium after: %08x\n", __func__, v);
2771 }
2772
2773 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2774 /* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */
2775 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2776 {
2777 int sds_mode;
2778 int calib_tries = 0;
2779
2780 switch (phy_mode) {
2781 case PHY_INTERFACE_MODE_HSGMII:
2782 sds_mode = 0x12;
2783 break;
2784 case PHY_INTERFACE_MODE_1000BASEX:
2785 sds_mode = 0x04;
2786 break;
2787 case PHY_INTERFACE_MODE_XGMII:
2788 sds_mode = 0x10;
2789 break;
2790 case PHY_INTERFACE_MODE_10GBASER:
2791 sds_mode = 0x1a;
2792 break;
2793 case PHY_INTERFACE_MODE_USXGMII:
2794 sds_mode = 0x0d;
2795 break;
2796 default:
2797 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2798 return -EINVAL;
2799 }
2800
2801 /* Maybe use dal_longan_sds_init */
2802
2803 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2804 rtl9300_phy_enable_10g_1g(sds_num);
2805
2806 /* Set Serdes Mode */
2807 rtl9300_sds_set(sds_num, 0x1a); /* 0x1b: RTK_MII_10GR1000BX_AUTO */
2808
2809 /* Do RX calibration */
2810 do {
2811 rtl9300_do_rx_calibration(sds_num, phy_mode);
2812 calib_tries++;
2813 mdelay(50);
2814 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2815
2816
2817 return 0;
2818 }
2819
2820 typedef struct {
2821 u8 page;
2822 u8 reg;
2823 u16 data;
2824 } sds_config;
2825
2826 sds_config rtl9300_a_sds_10gr_lane0[] =
2827 {
2828 /* 1G */
2829 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2830 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2831 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2832 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2833 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2834 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2835 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2836 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2837 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2838 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2839 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2840 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2841 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2842 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2843 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2844 {0x2F, 0x1D, 0x66E1},
2845 /* 3.125G */
2846 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2847 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2848 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2849 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2850 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2851 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2852 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2853 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2854 /* 10G */
2855 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2856 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2857 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2858 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2859 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2860 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2861 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2862 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2863 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2864 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2865 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2866 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2867 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2868 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2869 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2870 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2871 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2872 };
2873
2874 sds_config rtl9300_a_sds_10gr_lane1[] =
2875 {
2876 /* 1G */
2877 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2878 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2879 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2880 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2881 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2882 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2883 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2884 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2885 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2886 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2887 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2888 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2889 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2890 {0x2D, 0x14, 0x1808},
2891 /* 3.125G */
2892 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2893 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2894 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2895 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2896 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2897 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2898 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2899 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2900 /* 10G */
2901 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2902 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2903 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2904 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2905 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2906 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2907 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2908 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2909 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2910 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2911 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2912 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2913 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2914 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2915 };
2916
2917 int rtl9300_sds_cmu_band_get(int sds)
2918 {
2919 u32 page;
2920 u32 en;
2921 u32 cmu_band;
2922
2923 /* page = rtl9300_sds_cmu_page_get(sds); */
2924 page = 0x25; /* 10GR and 1000BX */
2925 sds = (sds % 2) ? (sds - 1) : (sds);
2926
2927 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2928 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2929
2930 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2931 if(!en) { /* Auto mode */
2932 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2933
2934 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2935 } else {
2936 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2937 }
2938
2939 return cmu_band;
2940 }
2941
2942 int rtl9300_configure_serdes(struct phy_device *phydev)
2943 {
2944 int phy_mode = PHY_INTERFACE_MODE_10GBASER;
2945 struct device *dev = &phydev->mdio.dev;
2946 int calib_tries = 0;
2947 u32 sds_num = 0;
2948 int sds_mode;
2949
2950 if (dev->of_node) {
2951 struct device_node *dn = dev->of_node;
2952 int phy_addr = phydev->mdio.addr;
2953
2954 if (of_property_read_u32(dn, "sds", &sds_num))
2955 sds_num = -1;
2956 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2957 } else {
2958 dev_err(dev, "No DT node.\n");
2959 return -EINVAL;
2960 }
2961
2962 if (sds_num < 0)
2963 return 0;
2964
2965 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) /* TODO: for now we only patch 10GR SerDes */
2966 return 0;
2967
2968 switch (phy_mode) {
2969 case PHY_INTERFACE_MODE_HSGMII:
2970 sds_mode = 0x12;
2971 break;
2972 case PHY_INTERFACE_MODE_1000BASEX:
2973 sds_mode = 0x04;
2974 break;
2975 case PHY_INTERFACE_MODE_XGMII:
2976 sds_mode = 0x10;
2977 break;
2978 case PHY_INTERFACE_MODE_10GBASER:
2979 sds_mode = 0x1a;
2980 break;
2981 case PHY_INTERFACE_MODE_USXGMII:
2982 sds_mode = 0x0d;
2983 break;
2984 default:
2985 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2986 return -EINVAL;
2987 }
2988
2989 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
2990
2991 /* Turn Off Serdes */
2992 rtl9300_sds_rst(sds_num, 0x1f);
2993
2994 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
2995 if (sds_num % 2) {
2996 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2997 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2998 rtl9300_a_sds_10gr_lane1[i].reg,
2999 rtl9300_a_sds_10gr_lane1[i].data);
3000 }
3001 } else {
3002 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
3003 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3004 rtl9300_a_sds_10gr_lane0[i].reg,
3005 rtl9300_a_sds_10gr_lane0[i].data);
3006 }
3007 }
3008
3009 rtl9300_phy_enable_10g_1g(sds_num);
3010
3011 /* Disable MAC */
3012 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3013 mdelay(20);
3014
3015 /* ----> dal_longan_sds_mode_set */
3016 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3017
3018 /* Configure link to MAC */
3019 rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
3020
3021 /* Disable MAC */
3022 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3023 mdelay(20);
3024
3025 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3026
3027 /* Re-Enable MAC */
3028 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3029
3030 rtl9300_force_sds_mode(sds_num, phy_mode);
3031
3032 /* Do RX calibration */
3033 do {
3034 rtl9300_do_rx_calibration(sds_num, phy_mode);
3035 calib_tries++;
3036 mdelay(50);
3037 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3038
3039 if (calib_tries >= 3)
3040 pr_err("%s CALIBTRATION FAILED\n", __func__);
3041
3042 rtl9300_sds_tx_config(sds_num, phy_mode);
3043
3044 /* The clock needs only to be configured on the FPGA implementation */
3045
3046 return 0;
3047 }
3048
3049 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3050 {
3051 int l = end_bit - start_bit + 1;
3052 u32 data = v;
3053
3054 if (l < 32) {
3055 u32 mask = BIT(l) - 1;
3056
3057 data = rtl930x_read_sds_phy(sds, page, reg);
3058 data &= ~(mask << start_bit);
3059 data |= (v & mask) << start_bit;
3060 }
3061
3062 rtl931x_write_sds_phy(sds, page, reg, data);
3063 }
3064
3065 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3066 {
3067 int l = end_bit - start_bit + 1;
3068 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3069
3070 if (l >= 32)
3071 return v;
3072
3073 return (v >> start_bit) & (BIT(l) - 1);
3074 }
3075
3076 static void rtl931x_sds_rst(u32 sds)
3077 {
3078 u32 o, v, o_mode;
3079 int shift = ((sds & 0x3) << 3);
3080
3081 /* TODO: We need to lock this! */
3082
3083 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3084 v = o | BIT(sds);
3085 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3086
3087 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3088 v = BIT(7) | 0x1F;
3089 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3090 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3091
3092 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3093 }
3094
3095 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3096 {
3097
3098 switch (mode) {
3099 case PHY_INTERFACE_MODE_NA:
3100 break;
3101 case PHY_INTERFACE_MODE_XGMII:
3102 u32 xsg_sdsid_0, xsg_sdsid_1;
3103
3104 if (sds < 2)
3105 xsg_sdsid_0 = sds;
3106 else
3107 xsg_sdsid_0 = (sds - 1) * 2;
3108 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3109
3110 for (int i = 0; i < 4; ++i) {
3111 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3112 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3113 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3114 }
3115
3116 for (int i = 0; i < 4; ++i) {
3117 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3118 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3119 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3120 }
3121
3122 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3123 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3124 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3125 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3126 break;
3127 default:
3128 break;
3129 }
3130
3131 return;
3132 }
3133
3134 static u32 rtl931x_get_analog_sds(u32 sds)
3135 {
3136 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3137
3138 if (sds < 14)
3139 return sds_map[sds];
3140
3141 return sds;
3142 }
3143
3144 void rtl931x_sds_fiber_disable(u32 sds)
3145 {
3146 u32 v = 0x3F;
3147 u32 asds = rtl931x_get_analog_sds(sds);
3148
3149 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3150 }
3151
3152 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3153 {
3154 u32 val, asds = rtl931x_get_analog_sds(sds);
3155
3156 /* clear symbol error count before changing mode */
3157 rtl931x_symerr_clear(sds, mode);
3158
3159 val = 0x9F;
3160 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3161
3162 switch (mode) {
3163 case PHY_INTERFACE_MODE_SGMII:
3164 val = 0x5;
3165 break;
3166
3167 case PHY_INTERFACE_MODE_1000BASEX:
3168 /* serdes mode FIBER1G */
3169 val = 0x9;
3170 break;
3171
3172 case PHY_INTERFACE_MODE_10GBASER:
3173 case PHY_INTERFACE_MODE_10GKR:
3174 val = 0x35;
3175 break;
3176 /* case MII_10GR1000BX_AUTO:
3177 val = 0x39;
3178 break; */
3179
3180
3181 case PHY_INTERFACE_MODE_USXGMII:
3182 val = 0x1B;
3183 break;
3184 default:
3185 val = 0x25;
3186 }
3187
3188 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3189 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3190
3191 return;
3192 }
3193
3194 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3195 {
3196 switch (mode) {
3197 case PHY_INTERFACE_MODE_SGMII:
3198 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3199 return 0x24;
3200 case PHY_INTERFACE_MODE_HSGMII:
3201 case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */
3202 return 0x28;
3203 /* case MII_HISGMII_5G: */
3204 /* return 0x2a; */
3205 case PHY_INTERFACE_MODE_QSGMII:
3206 return 0x2a; /* Code also has 0x34 */
3207 case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */
3208 return 0x2c;
3209 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3210 case PHY_INTERFACE_MODE_10GKR:
3211 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */
3212 return 0x2e;
3213 default:
3214 return -1;
3215 }
3216
3217 return -1;
3218 }
3219
3220 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3221 {
3222 int cmu_type = 0; /* Clock Management Unit */
3223 u32 cmu_page = 0;
3224 u32 frc_cmu_spd;
3225 u32 evenSds;
3226 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3227
3228 switch (mode) {
3229 case PHY_INTERFACE_MODE_NA:
3230 case PHY_INTERFACE_MODE_10GKR:
3231 case PHY_INTERFACE_MODE_XGMII:
3232 case PHY_INTERFACE_MODE_10GBASER:
3233 case PHY_INTERFACE_MODE_USXGMII:
3234 return;
3235
3236 /* case MII_10GR1000BX_AUTO:
3237 if (chiptype)
3238 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3239 return; */
3240
3241 case PHY_INTERFACE_MODE_QSGMII:
3242 cmu_type = 1;
3243 frc_cmu_spd = 0;
3244 break;
3245
3246 case PHY_INTERFACE_MODE_HSGMII:
3247 cmu_type = 1;
3248 frc_cmu_spd = 1;
3249 break;
3250
3251 case PHY_INTERFACE_MODE_1000BASEX:
3252 cmu_type = 1;
3253 frc_cmu_spd = 0;
3254 break;
3255
3256 /* case MII_1000BX100BX_AUTO:
3257 cmu_type = 1;
3258 frc_cmu_spd = 0;
3259 break; */
3260
3261 case PHY_INTERFACE_MODE_SGMII:
3262 cmu_type = 1;
3263 frc_cmu_spd = 0;
3264 break;
3265
3266 case PHY_INTERFACE_MODE_2500BASEX:
3267 cmu_type = 1;
3268 frc_cmu_spd = 1;
3269 break;
3270
3271 default:
3272 pr_info("SerDes %d mode is invalid\n", asds);
3273 return;
3274 }
3275
3276 if (cmu_type == 1)
3277 cmu_page = rtl931x_sds_cmu_page_get(mode);
3278
3279 lane = asds % 2;
3280
3281 if (!lane) {
3282 frc_lc_mode_bitnum = 4;
3283 frc_lc_mode_val_bitnum = 5;
3284 } else {
3285 frc_lc_mode_bitnum = 6;
3286 frc_lc_mode_val_bitnum = 7;
3287 }
3288
3289 evenSds = asds - lane;
3290
3291 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3292 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3293
3294 if (cmu_type == 1) {
3295 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3296 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3297 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3298 if (chiptype) {
3299 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3300 }
3301
3302 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3303 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3304 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3305 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3306 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3307 }
3308
3309 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3310 return;
3311 }
3312
3313 static void rtl931x_sds_rx_rst(u32 sds)
3314 {
3315 u32 asds = rtl931x_get_analog_sds(sds);
3316
3317 if (sds < 2)
3318 return;
3319
3320 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3321 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3322 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3323 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3324
3325 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3326 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3327 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3328 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3329
3330 mdelay(50);
3331 }
3332
3333 // Currently not used
3334 // static void rtl931x_sds_disable(u32 sds)
3335 // {
3336 // u32 v = 0x1f;
3337
3338 // v |= BIT(7);
3339 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3340 // }
3341
3342 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3343 {
3344 u32 val;
3345
3346 switch (mode) {
3347 case PHY_INTERFACE_MODE_QSGMII:
3348 val = 0x6;
3349 break;
3350 case PHY_INTERFACE_MODE_XGMII:
3351 val = 0x10; /* serdes mode XSGMII */
3352 break;
3353 case PHY_INTERFACE_MODE_USXGMII:
3354 case PHY_INTERFACE_MODE_2500BASEX:
3355 val = 0xD;
3356 break;
3357 case PHY_INTERFACE_MODE_HSGMII:
3358 val = 0x12;
3359 break;
3360 case PHY_INTERFACE_MODE_SGMII:
3361 val = 0x2;
3362 break;
3363 default:
3364 return;
3365 }
3366
3367 val |= (1 << 7);
3368
3369 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3370 }
3371
3372 static sds_config sds_config_10p3125g_type1[] = {
3373 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3374 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3375 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3376 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3377 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3378 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3379 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3380 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3381 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3382 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3383 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3384 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3385 { 0x2F, 0x13, 0x0000 }
3386 };
3387
3388 static sds_config sds_config_10p3125g_cmu_type1[] = {
3389 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3390 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3391 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3392 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3393 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3394 };
3395
3396 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3397 {
3398 u32 board_sds_tx_type1[] = {
3399 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3400 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3401 };
3402 u32 board_sds_tx[] = {
3403 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3404 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3405 };
3406 u32 board_sds_tx2[] = {
3407 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3408 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3409 };
3410 u32 asds, dSds, ori, model_info, val;
3411 int chiptype = 0;
3412
3413 asds = rtl931x_get_analog_sds(sds);
3414
3415 if (sds > 13)
3416 return;
3417
3418 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3419 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3420
3421 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3422 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3423 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3424 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3425 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3426 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3427 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3428 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3429 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3430 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3431 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3432 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3433
3434 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3435 if ((model_info >> 4) & 0x1) {
3436 pr_info("detected chiptype 1\n");
3437 chiptype = 1;
3438 } else {
3439 pr_info("detected chiptype 0\n");
3440 }
3441
3442 if (sds < 2)
3443 dSds = sds;
3444 else
3445 dSds = (sds - 1) * 2;
3446
3447 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3448 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3449
3450 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3451 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3452 val = ori | (1 << sds);
3453 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3454
3455 switch (mode) {
3456 case PHY_INTERFACE_MODE_NA:
3457 break;
3458
3459 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3460
3461 if (chiptype) {
3462 u32 xsg_sdsid_1;
3463 xsg_sdsid_1 = dSds + 1;
3464 /* fifo inv clk */
3465 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3466 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3467
3468 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3469 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3470
3471 }
3472
3473 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3474 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3475 break;
3476
3477 case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3478 u32 op_code = 0x6003;
3479 u32 evenSds;
3480
3481 if (chiptype) {
3482 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3483
3484 for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3485 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3486 }
3487
3488 evenSds = asds - (asds % 2);
3489
3490 for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3491 rtl931x_write_sds_phy(evenSds,
3492 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3493 }
3494
3495 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3496 } else {
3497
3498 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3499 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3500
3501 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3502 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3503 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3504 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3505 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3506
3507 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3508 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3509
3510 rtl931x_sds_rx_rst(sds);
3511
3512 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3513 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3514 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3515 }
3516 break;
3517
3518 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
3519 /* configure 10GR fiber mode=1 */
3520 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3521
3522 /* init fiber_1g */
3523 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3524
3525 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3526 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3527 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3528
3529 /* init auto */
3530 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3531 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3532 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3533 break;
3534
3535 case PHY_INTERFACE_MODE_HSGMII:
3536 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3537 break;
3538
3539 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */
3540 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3541
3542 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3543 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3544 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3545 break;
3546
3547 case PHY_INTERFACE_MODE_SGMII:
3548 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3549 break;
3550
3551 case PHY_INTERFACE_MODE_2500BASEX:
3552 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3553 break;
3554
3555 case PHY_INTERFACE_MODE_QSGMII:
3556 default:
3557 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3558 __func__, phy_modes(mode), sds);
3559 return;
3560 }
3561
3562 rtl931x_cmu_type_set(asds, mode, chiptype);
3563
3564 if (sds >= 2 && sds <= 13) {
3565 if (chiptype)
3566 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3567 else {
3568 val = 0xa0000;
3569 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3570 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3571 if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3572 {
3573 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3574 } else {
3575 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3576 }
3577 val = 0;
3578 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3579 }
3580 }
3581
3582 val = ori & ~BIT(sds);
3583 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3584 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3585
3586 if (mode == PHY_INTERFACE_MODE_XGMII ||
3587 mode == PHY_INTERFACE_MODE_QSGMII ||
3588 mode == PHY_INTERFACE_MODE_HSGMII ||
3589 mode == PHY_INTERFACE_MODE_SGMII ||
3590 mode == PHY_INTERFACE_MODE_USXGMII) {
3591 if (mode == PHY_INTERFACE_MODE_XGMII)
3592 rtl931x_sds_mii_mode_set(sds, mode);
3593 else
3594 rtl931x_sds_fiber_mode_set(sds, mode);
3595 }
3596 }
3597
3598 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3599 {
3600 u32 asds;
3601 int page = rtl931x_sds_cmu_page_get(mode);
3602
3603 sds -= (sds % 2);
3604 sds = sds & ~1;
3605 asds = rtl931x_get_analog_sds(sds);
3606 page += 1;
3607
3608 if (enable) {
3609 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3610 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3611 } else {
3612 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3613 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3614 }
3615
3616 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3617
3618 rtl931x_sds_rst(sds);
3619
3620 return 0;
3621 }
3622
3623 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3624 {
3625 int page = rtl931x_sds_cmu_page_get(mode);
3626 u32 asds, band;
3627
3628 sds -= (sds % 2);
3629 asds = rtl931x_get_analog_sds(sds);
3630 page += 1;
3631 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3632
3633 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3634 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3635 pr_info("%s band is: %d\n", __func__, band);
3636
3637 return band;
3638 }
3639
3640
3641 int rtl931x_link_sts_get(u32 sds)
3642 {
3643 u32 sts, sts1, latch_sts, latch_sts1;
3644 if (0){
3645 u32 xsg_sdsid_0, xsg_sdsid_1;
3646
3647 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3648 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3649
3650 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3651 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3652 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3653 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3654 } else {
3655 u32 asds, dsds;
3656
3657 asds = rtl931x_get_analog_sds(sds);
3658 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3659 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3660
3661 dsds = sds < 2 ? sds : (sds - 1) * 2;
3662 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3663 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3664 }
3665
3666 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3667 sds, sts, sts1, latch_sts, latch_sts1);
3668
3669 return sts1;
3670 }
3671
3672 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3673 {
3674 struct phy_device *phydev = upstream;
3675
3676 rtl8214fc_media_set(phydev, true);
3677
3678 return 0;
3679 }
3680
3681 static void rtl8214fc_sfp_remove(void *upstream)
3682 {
3683 struct phy_device *phydev = upstream;
3684
3685 rtl8214fc_media_set(phydev, false);
3686 }
3687
3688 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3689 .attach = phy_sfp_attach,
3690 .detach = phy_sfp_detach,
3691 .module_insert = rtl8214fc_sfp_insert,
3692 .module_remove = rtl8214fc_sfp_remove,
3693 };
3694
3695 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3696 {
3697 struct device *dev = &phydev->mdio.dev;
3698 int addr = phydev->mdio.addr;
3699 int ret = 0;
3700
3701 /* 839x has internal SerDes */
3702 if (soc_info.id == 0x8393)
3703 return -ENODEV;
3704
3705 /* All base addresses of the PHYs start at multiples of 8 */
3706 devm_phy_package_join(dev, phydev, addr & (~7),
3707 sizeof(struct rtl83xx_shared_private));
3708
3709 if (!(addr % 8)) {
3710 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3711 shared->name = "RTL8214FC";
3712 /* Configuration must be done while patching still possible */
3713 ret = rtl8380_configure_rtl8214fc(phydev);
3714 if (ret)
3715 return ret;
3716 }
3717
3718 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3719 }
3720
3721 static int rtl8214c_phy_probe(struct phy_device *phydev)
3722 {
3723 struct device *dev = &phydev->mdio.dev;
3724 int addr = phydev->mdio.addr;
3725
3726 /* All base addresses of the PHYs start at multiples of 8 */
3727 devm_phy_package_join(dev, phydev, addr & (~7),
3728 sizeof(struct rtl83xx_shared_private));
3729
3730 if (!(addr % 8)) {
3731 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3732 shared->name = "RTL8214C";
3733 /* Configuration must be done whil patching still possible */
3734 return rtl8380_configure_rtl8214c(phydev);
3735 }
3736
3737 return 0;
3738 }
3739
3740 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3741 {
3742 struct device *dev = &phydev->mdio.dev;
3743 int addr = phydev->mdio.addr;
3744
3745 /* All base addresses of the PHYs start at multiples of 8 */
3746 devm_phy_package_join(dev, phydev, addr & (~7),
3747 sizeof(struct rtl83xx_shared_private));
3748
3749 if (!(addr % 8)) {
3750 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3751 shared->name = "RTL8218B (external)";
3752 if (soc_info.family == RTL8380_FAMILY_ID) {
3753 /* Configuration must be done while patching still possible */
3754 return rtl8380_configure_ext_rtl8218b(phydev);
3755 }
3756 }
3757
3758 return 0;
3759 }
3760
3761 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3762 {
3763 struct device *dev = &phydev->mdio.dev;
3764 int addr = phydev->mdio.addr;
3765
3766 if (soc_info.family != RTL8380_FAMILY_ID)
3767 return -ENODEV;
3768 if (addr >= 24)
3769 return -ENODEV;
3770
3771 pr_debug("%s: id: %d\n", __func__, addr);
3772 /* All base addresses of the PHYs start at multiples of 8 */
3773 devm_phy_package_join(dev, phydev, addr & (~7),
3774 sizeof(struct rtl83xx_shared_private));
3775
3776 if (!(addr % 8)) {
3777 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3778 shared->name = "RTL8218B (internal)";
3779 /* Configuration must be done while patching still possible */
3780 return rtl8380_configure_int_rtl8218b(phydev);
3781 }
3782
3783 return 0;
3784 }
3785
3786 static int rtl8218d_phy_probe(struct phy_device *phydev)
3787 {
3788 struct device *dev = &phydev->mdio.dev;
3789 int addr = phydev->mdio.addr;
3790
3791 pr_debug("%s: id: %d\n", __func__, addr);
3792 /* All base addresses of the PHYs start at multiples of 8 */
3793 devm_phy_package_join(dev, phydev, addr & (~7),
3794 sizeof(struct rtl83xx_shared_private));
3795
3796 /* All base addresses of the PHYs start at multiples of 8 */
3797 if (!(addr % 8)) {
3798 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3799 shared->name = "RTL8218D";
3800 /* Configuration must be done while patching still possible */
3801 /* TODO: return configure_rtl8218d(phydev); */
3802 }
3803
3804 return 0;
3805 }
3806
3807 static int rtl838x_serdes_probe(struct phy_device *phydev)
3808 {
3809 int addr = phydev->mdio.addr;
3810
3811 if (soc_info.family != RTL8380_FAMILY_ID)
3812 return -ENODEV;
3813 if (addr < 24)
3814 return -ENODEV;
3815
3816 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3817 if (soc_info.id == 0x8380) {
3818 if (addr == 24)
3819 return rtl8380_configure_serdes(phydev);
3820 return 0;
3821 }
3822
3823 return -ENODEV;
3824 }
3825
3826 static int rtl8393_serdes_probe(struct phy_device *phydev)
3827 {
3828 int addr = phydev->mdio.addr;
3829
3830 pr_info("%s: id: %d\n", __func__, addr);
3831 if (soc_info.family != RTL8390_FAMILY_ID)
3832 return -ENODEV;
3833
3834 if (addr < 24)
3835 return -ENODEV;
3836
3837 return rtl8390_configure_serdes(phydev);
3838 }
3839
3840 static int rtl8390_serdes_probe(struct phy_device *phydev)
3841 {
3842 int addr = phydev->mdio.addr;
3843
3844 if (soc_info.family != RTL8390_FAMILY_ID)
3845 return -ENODEV;
3846
3847 if (addr < 24)
3848 return -ENODEV;
3849
3850 return rtl8390_configure_generic(phydev);
3851 }
3852
3853 static int rtl9300_serdes_probe(struct phy_device *phydev)
3854 {
3855 if (soc_info.family != RTL9300_FAMILY_ID)
3856 return -ENODEV;
3857
3858 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3859
3860 return rtl9300_configure_serdes(phydev);
3861 }
3862
3863 static struct phy_driver rtl83xx_phy_driver[] = {
3864 {
3865 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3866 .name = "Realtek RTL8214C",
3867 .features = PHY_GBIT_FEATURES,
3868 .flags = PHY_HAS_REALTEK_PAGES,
3869 .match_phy_device = rtl8214c_match_phy_device,
3870 .probe = rtl8214c_phy_probe,
3871 .suspend = genphy_suspend,
3872 .resume = genphy_resume,
3873 .set_loopback = genphy_loopback,
3874 },
3875 {
3876 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3877 .name = "Realtek RTL8214FC",
3878 .features = PHY_GBIT_FIBRE_FEATURES,
3879 .flags = PHY_HAS_REALTEK_PAGES,
3880 .match_phy_device = rtl8214fc_match_phy_device,
3881 .probe = rtl8214fc_phy_probe,
3882 .suspend = rtl8214fc_suspend,
3883 .resume = rtl8214fc_resume,
3884 .set_loopback = genphy_loopback,
3885 .set_port = rtl8214fc_set_port,
3886 .get_port = rtl8214fc_get_port,
3887 .set_eee = rtl8214fc_set_eee,
3888 .get_eee = rtl8214fc_get_eee,
3889 },
3890 {
3891 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3892 .name = "Realtek RTL8218B (external)",
3893 .features = PHY_GBIT_FEATURES,
3894 .flags = PHY_HAS_REALTEK_PAGES,
3895 .match_phy_device = rtl8218b_ext_match_phy_device,
3896 .probe = rtl8218b_ext_phy_probe,
3897 .suspend = genphy_suspend,
3898 .resume = genphy_resume,
3899 .set_loopback = genphy_loopback,
3900 .set_eee = rtl8218b_set_eee,
3901 .get_eee = rtl8218b_get_eee,
3902 },
3903 {
3904 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3905 .name = "REALTEK RTL8218D",
3906 .features = PHY_GBIT_FEATURES,
3907 .flags = PHY_HAS_REALTEK_PAGES,
3908 .probe = rtl8218d_phy_probe,
3909 .suspend = genphy_suspend,
3910 .resume = genphy_resume,
3911 .set_loopback = genphy_loopback,
3912 .set_eee = rtl8218d_set_eee,
3913 .get_eee = rtl8218d_get_eee,
3914 },
3915 {
3916 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3917 .name = "REALTEK RTL8221B",
3918 .features = PHY_GBIT_FEATURES,
3919 .flags = PHY_HAS_REALTEK_PAGES,
3920 .suspend = genphy_suspend,
3921 .resume = genphy_resume,
3922 .set_loopback = genphy_loopback,
3923 .read_page = rtl8226_read_page,
3924 .write_page = rtl8226_write_page,
3925 .read_status = rtl8226_read_status,
3926 .config_aneg = rtl8226_config_aneg,
3927 .set_eee = rtl8226_set_eee,
3928 .get_eee = rtl8226_get_eee,
3929 },
3930 {
3931 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3932 .name = "REALTEK RTL8226",
3933 .features = PHY_GBIT_FEATURES,
3934 .flags = PHY_HAS_REALTEK_PAGES,
3935 .suspend = genphy_suspend,
3936 .resume = genphy_resume,
3937 .set_loopback = genphy_loopback,
3938 .read_page = rtl8226_read_page,
3939 .write_page = rtl8226_write_page,
3940 .read_status = rtl8226_read_status,
3941 .config_aneg = rtl8226_config_aneg,
3942 .set_eee = rtl8226_set_eee,
3943 .get_eee = rtl8226_get_eee,
3944 },
3945 {
3946 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3947 .name = "Realtek RTL8218B (internal)",
3948 .features = PHY_GBIT_FEATURES,
3949 .flags = PHY_HAS_REALTEK_PAGES,
3950 .probe = rtl8218b_int_phy_probe,
3951 .suspend = genphy_suspend,
3952 .resume = genphy_resume,
3953 .set_loopback = genphy_loopback,
3954 .set_eee = rtl8218b_set_eee,
3955 .get_eee = rtl8218b_get_eee,
3956 },
3957 {
3958 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3959 .name = "Realtek RTL8380 SERDES",
3960 .features = PHY_GBIT_FIBRE_FEATURES,
3961 .flags = PHY_HAS_REALTEK_PAGES,
3962 .probe = rtl838x_serdes_probe,
3963 .suspend = genphy_suspend,
3964 .resume = genphy_resume,
3965 .set_loopback = genphy_loopback,
3966 .read_status = rtl8380_read_status,
3967 },
3968 {
3969 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3970 .name = "Realtek RTL8393 SERDES",
3971 .features = PHY_GBIT_FIBRE_FEATURES,
3972 .flags = PHY_HAS_REALTEK_PAGES,
3973 .probe = rtl8393_serdes_probe,
3974 .suspend = genphy_suspend,
3975 .resume = genphy_resume,
3976 .set_loopback = genphy_loopback,
3977 .read_status = rtl8393_read_status,
3978 },
3979 {
3980 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3981 .name = "Realtek RTL8390 Generic",
3982 .features = PHY_GBIT_FIBRE_FEATURES,
3983 .flags = PHY_HAS_REALTEK_PAGES,
3984 .probe = rtl8390_serdes_probe,
3985 .suspend = genphy_suspend,
3986 .resume = genphy_resume,
3987 .set_loopback = genphy_loopback,
3988 },
3989 {
3990 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3991 .name = "REALTEK RTL9300 SERDES",
3992 .features = PHY_GBIT_FIBRE_FEATURES,
3993 .flags = PHY_HAS_REALTEK_PAGES,
3994 .probe = rtl9300_serdes_probe,
3995 .suspend = genphy_suspend,
3996 .resume = genphy_resume,
3997 .set_loopback = genphy_loopback,
3998 .read_status = rtl9300_read_status,
3999 },
4000 };
4001
4002 module_phy_driver(rtl83xx_phy_driver);
4003
4004 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
4005 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
4006 { }
4007 };
4008
4009 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
4010
4011 MODULE_AUTHOR("B. Koblitz");
4012 MODULE_DESCRIPTION("RTL83xx PHY driver");
4013 MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich