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realtek: 5.15: rtl930x: introduce SerDes mode macros
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
16 #include <linux/mdio.h>
17
18 #include <asm/mach-rtl838x/mach-rtl83xx.h>
19 #include "rtl83xx-phy.h"
20
21 extern struct rtl83xx_soc_info soc_info;
22 extern struct mutex smi_lock;
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /* Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_MEDIA_PAGE_AUTO 0
50 #define RTL821X_MEDIA_PAGE_COPPER 1
51 #define RTL821X_MEDIA_PAGE_FIBRE 3
52 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53
54 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55
56 /* RTL930X SerDes supports the following modes:
57 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
58 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
59 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
60 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
61 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
62 */
63 #define RTL930X_SDS_MODE_SGMII 0x02
64 #define RTL930X_SDS_MODE_1000BASEX 0x04
65 #define RTL930X_SDS_MODE_USXGMII 0x0d
66 #define RTL930X_SDS_MODE_XGMII 0x10
67 #define RTL930X_SDS_MODE_HSGMII 0x12
68 #define RTL930X_SDS_MODE_2500BASEX 0x16
69 #define RTL930X_SDS_MODE_10GBASER 0x1a
70 #define RTL930X_SDS_OFF 0x1f
71 #define RTL930X_SDS_MASK 0x1f
72
73 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
74 * bus to detect e.g. link and media changes. For operations on the PHYs such as
75 * patching or other configuration changes such as EEE, polling needs to be disabled
76 * since otherwise these operations may fails or lead to unpredictable results.
77 */
78 DEFINE_MUTEX(poll_lock);
79
80 static const struct firmware rtl838x_8380_fw;
81 static const struct firmware rtl838x_8214fc_fw;
82 static const struct firmware rtl838x_8218b_fw;
83
84 static u64 disable_polling(int port)
85 {
86 u64 saved_state;
87
88 mutex_lock(&poll_lock);
89
90 switch (soc_info.family) {
91 case RTL8380_FAMILY_ID:
92 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
93 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
94 break;
95 case RTL8390_FAMILY_ID:
96 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
97 saved_state <<= 32;
98 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
99 sw_w32_mask(BIT(port % 32), 0,
100 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
101 break;
102 case RTL9300_FAMILY_ID:
103 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
104 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
105 break;
106 case RTL9310_FAMILY_ID:
107 pr_warn("%s not implemented for RTL931X\n", __func__);
108 break;
109 }
110
111 mutex_unlock(&poll_lock);
112
113 return saved_state;
114 }
115
116 static int resume_polling(u64 saved_state)
117 {
118 mutex_lock(&poll_lock);
119
120 switch (soc_info.family) {
121 case RTL8380_FAMILY_ID:
122 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
123 break;
124 case RTL8390_FAMILY_ID:
125 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
126 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
127 break;
128 case RTL9300_FAMILY_ID:
129 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
130 break;
131 case RTL9310_FAMILY_ID:
132 pr_warn("%s not implemented for RTL931X\n", __func__);
133 break;
134 }
135
136 mutex_unlock(&poll_lock);
137
138 return 0;
139 }
140
141 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
142 {
143 phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
144 }
145
146 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
147 {
148 /* fiber ports */
149 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
150 phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
151
152 /* copper ports */
153 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
154 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
155 }
156
157 static void rtl8380_phy_reset(struct phy_device *phydev)
158 {
159 phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
160 }
161
162 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
163 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
164 0x02A4, 0x02A4, 0x0198, 0x0198 };
165 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
166
167 /* Reset the SerDes by powering it off and set a new operation mode
168 * of the SerDes.
169 */
170 void rtl9300_sds_rst(int sds_num, u32 mode)
171 {
172 pr_info("%s %d\n", __func__, mode);
173 if (sds_num < 0 || sds_num > 11) {
174 pr_err("Wrong SerDes number: %d\n", sds_num);
175 return;
176 }
177
178 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num],
179 RTL930X_SDS_OFF << rtl9300_sds_lsb[sds_num],
180 rtl9300_sds_regs[sds_num]);
181 mdelay(10);
182
183 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
184 rtl9300_sds_regs[sds_num]);
185 mdelay(10);
186
187 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
188 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
189 }
190
191 void rtl9300_sds_set(int sds_num, u32 mode)
192 {
193 pr_info("%s %d\n", __func__, mode);
194 if (sds_num < 0 || sds_num > 11) {
195 pr_err("Wrong SerDes number: %d\n", sds_num);
196 return;
197 }
198
199 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
200 rtl9300_sds_regs[sds_num]);
201 mdelay(10);
202
203 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
204 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
205 }
206
207 u32 rtl9300_sds_mode_get(int sds_num)
208 {
209 u32 v;
210
211 if (sds_num < 0 || sds_num > 11) {
212 pr_err("Wrong SerDes number: %d\n", sds_num);
213 return 0;
214 }
215
216 v = sw_r32(rtl9300_sds_regs[sds_num]);
217 v >>= rtl9300_sds_lsb[sds_num];
218
219 return v & RTL930X_SDS_MASK;
220 }
221
222 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
223 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
224 */
225 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
226 {
227 int offset = 0;
228 int reg;
229 u32 val;
230
231 if (phy_addr == 49)
232 offset = 0x100;
233
234 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
235 * which would otherwise read as 0.
236 */
237 if (soc_info.id == 0x8393) {
238 if (phy_reg == MII_PHYSID1)
239 return 0x1c;
240 if (phy_reg == MII_PHYSID2)
241 return 0x8393;
242 }
243
244 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
245 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
246 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
247 * one 32 bit register.
248 */
249 reg = (phy_reg << 1) & 0xfc;
250 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
251
252 if (phy_reg & 1)
253 val = (val >> 16) & 0xffff;
254 else
255 val &= 0xffff;
256
257 return val;
258 }
259
260 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
261 * register which simulates commands to an internal MDIO bus.
262 */
263 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
264 {
265 int i;
266 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
267
268 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
269
270 for (i = 0; i < 100; i++) {
271 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
272 break;
273 mdelay(1);
274 }
275
276 if (i >= 100)
277 return -EIO;
278
279 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
280 }
281
282 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
283 {
284 int i;
285 u32 cmd;
286
287 sw_w32(v, RTL930X_SDS_INDACS_DATA);
288 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
289
290 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
291
292 for (i = 0; i < 100; i++) {
293 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
294 break;
295 mdelay(1);
296 }
297
298
299 if (i >= 100) {
300 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
301 return -EIO;
302 }
303
304 return 0;
305 }
306
307 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
308 {
309 int i;
310 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
311
312 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
313 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
314
315 for (i = 0; i < 100; i++) {
316 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
317 break;
318 mdelay(1);
319 }
320
321 if (i >= 100)
322 return -EIO;
323
324 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
325
326 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
327 }
328
329 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
330 {
331 int i;
332 u32 cmd;
333
334 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
335 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
336
337 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
338
339 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
340 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
341
342 for (i = 0; i < 100; i++) {
343 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
344 break;
345 mdelay(1);
346 }
347
348 if (i >= 100)
349 return -EIO;
350
351 return 0;
352 }
353
354 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
355 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
356 * in a standard page 0 of a PHY
357 */
358 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
359 {
360 int offset = 0;
361 u32 val;
362
363 if (phy_addr == 26)
364 offset = 0x100;
365 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
366
367 return val;
368 }
369
370 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
371 {
372 int offset = 0;
373 int reg;
374 u32 val;
375
376 if (phy_addr == 49)
377 offset = 0x100;
378
379 reg = (phy_reg << 1) & 0xfc;
380 val = v;
381 if (phy_reg & 1) {
382 val = val << 16;
383 sw_w32_mask(0xffff0000, val,
384 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
385 } else {
386 sw_w32_mask(0xffff, val,
387 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
388 }
389
390 return 0;
391 }
392
393 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
394 * ports of the RTL838x SoCs
395 */
396 static int rtl8380_read_status(struct phy_device *phydev)
397 {
398 int err;
399
400 err = genphy_read_status(phydev);
401
402 if (phydev->link) {
403 phydev->speed = SPEED_1000;
404 phydev->duplex = DUPLEX_FULL;
405 }
406
407 return err;
408 }
409
410 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
411 * ports of the RTL8393 SoC
412 */
413 static int rtl8393_read_status(struct phy_device *phydev)
414 {
415 int offset = 0;
416 int err;
417 int phy_addr = phydev->mdio.addr;
418 u32 v;
419
420 err = genphy_read_status(phydev);
421 if (phy_addr == 49)
422 offset = 0x100;
423
424 if (phydev->link) {
425 phydev->speed = SPEED_100;
426 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
427 * PHY registers
428 */
429 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
430 if (!(v & (1 << 13)) && (v & (1 << 6)))
431 phydev->speed = SPEED_1000;
432 phydev->duplex = DUPLEX_FULL;
433 }
434
435 return err;
436 }
437
438 static int rtl8226_read_page(struct phy_device *phydev)
439 {
440 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
441 }
442
443 static int rtl8226_write_page(struct phy_device *phydev, int page)
444 {
445 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
446 }
447
448 static int rtl8226_read_status(struct phy_device *phydev)
449 {
450 int ret = 0;
451 u32 val;
452
453 /* TODO: ret = genphy_read_status(phydev);
454 * if (ret < 0) {
455 * pr_info("%s: genphy_read_status failed\n", __func__);
456 * return ret;
457 * }
458 */
459
460 /* Link status must be read twice */
461 for (int i = 0; i < 2; i++)
462 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
463
464 phydev->link = val & BIT(2) ? 1 : 0;
465 if (!phydev->link)
466 goto out;
467
468 /* Read duplex status */
469 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
470 if (val < 0)
471 goto out;
472 phydev->duplex = !!(val & BIT(3));
473
474 /* Read speed */
475 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
476 switch (val & 0x0630) {
477 case 0x0000:
478 phydev->speed = SPEED_10;
479 break;
480 case 0x0010:
481 phydev->speed = SPEED_100;
482 break;
483 case 0x0020:
484 phydev->speed = SPEED_1000;
485 break;
486 case 0x0200:
487 phydev->speed = SPEED_10000;
488 break;
489 case 0x0210:
490 phydev->speed = SPEED_2500;
491 break;
492 case 0x0220:
493 phydev->speed = SPEED_5000;
494 break;
495 default:
496 break;
497 }
498
499 out:
500 return ret;
501 }
502
503 static int rtl8226_advertise_aneg(struct phy_device *phydev)
504 {
505 int ret = 0;
506 u32 v;
507
508 pr_info("In %s\n", __func__);
509
510 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
511 if (v < 0)
512 goto out;
513
514 v |= ADVERTISE_10HALF;
515 v |= ADVERTISE_10FULL;
516 v |= ADVERTISE_100HALF;
517 v |= ADVERTISE_100FULL;
518
519 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
520
521 /* Allow 1GBit */
522 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
523 if (v < 0)
524 goto out;
525 v |= ADVERTISE_1000FULL;
526
527 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
528 if (ret < 0)
529 goto out;
530
531 /* Allow 2.5G */
532 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
533 if (v < 0)
534 goto out;
535
536 v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
537 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
538
539 out:
540 return ret;
541 }
542
543 static int rtl8226_config_aneg(struct phy_device *phydev)
544 {
545 int ret = 0;
546 u32 v;
547
548 pr_debug("In %s\n", __func__);
549 if (phydev->autoneg == AUTONEG_ENABLE) {
550 ret = rtl8226_advertise_aneg(phydev);
551 if (ret)
552 goto out;
553 /* AutoNegotiationEnable */
554 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
555 if (v < 0)
556 goto out;
557
558 v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
559 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
560 if (ret < 0)
561 goto out;
562
563 /* RestartAutoNegotiation */
564 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
565 if (v < 0)
566 goto out;
567 v |= MDIO_AN_CTRL1_RESTART;
568
569 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
570 }
571
572 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
573
574 out:
575 return ret;
576 }
577
578 static int rtl8226_get_eee(struct phy_device *phydev,
579 struct ethtool_eee *e)
580 {
581 u32 val;
582 int addr = phydev->mdio.addr;
583
584 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
585
586 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
587 if (e->eee_enabled) {
588 e->eee_enabled = !!(val & MDIO_EEE_100TX);
589 if (!e->eee_enabled) {
590 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
591 e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
592 }
593 }
594 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
595
596 return 0;
597 }
598
599 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
600 {
601 int port = phydev->mdio.addr;
602 u64 poll_state;
603 bool an_enabled;
604 u32 val;
605
606 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
607
608 poll_state = disable_polling(port);
609
610 /* Remember aneg state */
611 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
612 an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
613
614 /* Setup 100/1000MBit */
615 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
616 if (e->eee_enabled)
617 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
618 else
619 val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
620 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
621
622 /* Setup 2.5GBit */
623 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
624 if (e->eee_enabled)
625 val |= MDIO_EEE_2_5GT;
626 else
627 val &= MDIO_EEE_2_5GT;
628 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
629
630 /* RestartAutoNegotiation */
631 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
632 val |= MDIO_AN_CTRL1_RESTART;
633 phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
634
635 resume_polling(poll_state);
636
637 return 0;
638 }
639
640 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
641 const struct firmware *fw,
642 const char *name)
643 {
644 struct device *dev = &phydev->mdio.dev;
645 int err;
646 struct fw_header *h;
647 uint32_t checksum, my_checksum;
648
649 err = request_firmware(&fw, name, dev);
650 if (err < 0)
651 goto out;
652
653 if (fw->size < sizeof(struct fw_header)) {
654 pr_err("Firmware size too small.\n");
655 err = -EINVAL;
656 goto out;
657 }
658
659 h = (struct fw_header *) fw->data;
660 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
661
662 if (h->magic != 0x83808380) {
663 pr_err("Wrong firmware file: MAGIC mismatch.\n");
664 goto out;
665 }
666
667 checksum = h->checksum;
668 h->checksum = 0;
669 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
670 if (checksum != my_checksum) {
671 pr_err("Firmware checksum mismatch.\n");
672 err = -EINVAL;
673 goto out;
674 }
675 h->checksum = checksum;
676
677 return h;
678 out:
679 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
680 return NULL;
681 }
682
683 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
684 {
685 int mac = phydev->mdio.addr;
686
687 /* select main page 0 */
688 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
689 /* write to 0x8 to register 0x1d on main page 0 */
690 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
691 /* select page 0x266 */
692 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
693 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
694 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
695 /* return to main page 0 */
696 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
697 /* write to 0x0 to register 0x1d on main page 0 */
698 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
699 mdelay(1);
700 }
701
702 static int rtl8390_configure_generic(struct phy_device *phydev)
703 {
704 int mac = phydev->mdio.addr;
705 u32 val, phy_id;
706
707 val = phy_read(phydev, 2);
708 phy_id = val << 16;
709 val = phy_read(phydev, 3);
710 phy_id |= val;
711 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
712
713 /* Read internal PHY ID */
714 phy_write_paged(phydev, 31, 27, 0x0002);
715 val = phy_read_paged(phydev, 31, 28);
716
717 /* Internal RTL8218B, version 2 */
718 phydev_info(phydev, "Detected unknown %x\n", val);
719
720 return 0;
721 }
722
723 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
724 {
725 u32 val, phy_id;
726 int mac = phydev->mdio.addr;
727 struct fw_header *h;
728 u32 *rtl838x_6275B_intPhy_perport;
729 u32 *rtl8218b_6276B_hwEsd_perport;
730
731 val = phy_read(phydev, 2);
732 phy_id = val << 16;
733 val = phy_read(phydev, 3);
734 phy_id |= val;
735 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
736
737 /* Read internal PHY ID */
738 phy_write_paged(phydev, 31, 27, 0x0002);
739 val = phy_read_paged(phydev, 31, 28);
740 if (val != 0x6275) {
741 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
742 return -1;
743 }
744
745 /* Internal RTL8218B, version 2 */
746 phydev_info(phydev, "Detected internal RTL8218B\n");
747
748 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
749 if (!h)
750 return -1;
751
752 if (h->phy != 0x83800000) {
753 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
754 return -1;
755 }
756
757 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
758 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
759
760 // Currently not used
761 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
762 // int ipd_flag = 1;
763 // }
764
765 val = phy_read(phydev, MII_BMCR);
766 if (val & BMCR_PDOWN)
767 rtl8380_int_phy_on_off(phydev, true);
768 else
769 rtl8380_phy_reset(phydev);
770 msleep(100);
771
772 /* Ready PHY for patch */
773 for (int p = 0; p < 8; p++) {
774 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
775 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
776 }
777 msleep(500);
778 for (int p = 0; p < 8; p++) {
779 int i;
780
781 for (i = 0; i < 100 ; i++) {
782 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
783 if (val & 0x40)
784 break;
785 }
786 if (i >= 100) {
787 phydev_err(phydev,
788 "ERROR: Port %d not ready for patch.\n",
789 mac + p);
790 return -1;
791 }
792 }
793 for (int p = 0; p < 8; p++) {
794 int i;
795
796 i = 0;
797 while (rtl838x_6275B_intPhy_perport[i * 2]) {
798 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
799 rtl838x_6275B_intPhy_perport[i * 2],
800 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
801 i++;
802 }
803 i = 0;
804 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
805 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
806 rtl8218b_6276B_hwEsd_perport[i * 2],
807 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
808 i++;
809 }
810 }
811
812 return 0;
813 }
814
815 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
816 {
817 u32 val, ipd, phy_id;
818 int mac = phydev->mdio.addr;
819 struct fw_header *h;
820 u32 *rtl8380_rtl8218b_perchip;
821 u32 *rtl8218B_6276B_rtl8380_perport;
822 u32 *rtl8380_rtl8218b_perport;
823
824 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
825 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
826 return -1;
827 }
828 val = phy_read(phydev, 2);
829 phy_id = val << 16;
830 val = phy_read(phydev, 3);
831 phy_id |= val;
832 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
833
834 /* Read internal PHY ID */
835 phy_write_paged(phydev, 31, 27, 0x0002);
836 val = phy_read_paged(phydev, 31, 28);
837 if (val != 0x6276) {
838 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
839 return -1;
840 }
841 phydev_info(phydev, "Detected external RTL8218B\n");
842
843 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
844 if (!h)
845 return -1;
846
847 if (h->phy != 0x8218b000) {
848 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
849 return -1;
850 }
851
852 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
853 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
854 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
855
856 val = phy_read(phydev, MII_BMCR);
857 if (val & BMCR_PDOWN)
858 rtl8380_int_phy_on_off(phydev, true);
859 else
860 rtl8380_phy_reset(phydev);
861
862 msleep(100);
863
864 /* Get Chip revision */
865 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
866 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
867 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
868
869 phydev_info(phydev, "Detected chip revision %04x\n", val);
870
871 for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
872 rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
873 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
874 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
875 rtl8380_rtl8218b_perchip[i * 3 + 2]);
876 }
877
878 /* Enable PHY */
879 for (int i = 0; i < 8; i++) {
880 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
881 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
882 }
883 mdelay(100);
884
885 /* Request patch */
886 for (int i = 0; i < 8; i++) {
887 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
888 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
889 }
890
891 mdelay(300);
892
893 /* Verify patch readiness */
894 for (int i = 0; i < 8; i++) {
895 int l;
896
897 for (l = 0; l < 100; l++) {
898 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
899 if (val & 0x40)
900 break;
901 }
902 if (l >= 100) {
903 phydev_err(phydev, "Could not patch PHY\n");
904 return -1;
905 }
906 }
907
908 /* Use Broadcast ID method for patching */
909 rtl821x_phy_setup_package_broadcast(phydev, true);
910
911 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
912 phy_write_paged(phydev, 0x26e, 17, 0xb);
913 phy_write_paged(phydev, 0x26e, 16, 0x2);
914 mdelay(1);
915 ipd = phy_read_paged(phydev, 0x26e, 19);
916 phy_write_paged(phydev, 0, 30, 0);
917 ipd = (ipd >> 4) & 0xf; /* unused ? */
918
919 for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
920 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
921 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
922 }
923
924 /* Disable broadcast ID */
925 rtl821x_phy_setup_package_broadcast(phydev, false);
926
927 return 0;
928 }
929
930 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
931 {
932 int addr = phydev->mdio.addr;
933
934 /* Both the RTL8214FC and the external RTL8218B have the same
935 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
936 * at PHY IDs 0-7, while the RTL8214FC must be attached via
937 * the pair of SGMII/1000Base-X with higher PHY-IDs
938 */
939 if (soc_info.family == RTL8380_FAMILY_ID)
940 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
941 else
942 return phydev->phy_id == PHY_ID_RTL8218B_E;
943 }
944
945 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
946 {
947 int mac = phydev->mdio.addr;
948
949 static int reg[] = {16, 19, 20, 21};
950 u32 val;
951
952 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
953 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
954 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
955
956 if (val & BMCR_PDOWN)
957 return false;
958
959 return true;
960 }
961
962 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
963 {
964 char *state = on ? "on" : "off";
965
966 if (port == PORT_FIBRE) {
967 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
968 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
969 } else {
970 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
971 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
972 }
973
974 if (on) {
975 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
976 } else {
977 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
978 }
979
980 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
981 }
982
983 static int rtl8214fc_suspend(struct phy_device *phydev)
984 {
985 rtl8214fc_power_set(phydev, PORT_MII, false);
986 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
987
988 return 0;
989 }
990
991 static int rtl8214fc_resume(struct phy_device *phydev)
992 {
993 if (rtl8214fc_media_is_fibre(phydev)) {
994 rtl8214fc_power_set(phydev, PORT_MII, false);
995 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
996 } else {
997 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
998 rtl8214fc_power_set(phydev, PORT_MII, true);
999 }
1000
1001 return 0;
1002 }
1003
1004 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
1005 {
1006 int mac = phydev->mdio.addr;
1007
1008 static int reg[] = {16, 19, 20, 21};
1009 int val;
1010
1011 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1012 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1013 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1014
1015 val |= BIT(10);
1016 if (set_fibre) {
1017 val &= ~BMCR_PDOWN;
1018 } else {
1019 val |= BMCR_PDOWN;
1020 }
1021
1022 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1023 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1024 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1025
1026 if (!phydev->suspended) {
1027 if (set_fibre) {
1028 rtl8214fc_power_set(phydev, PORT_MII, false);
1029 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1030 } else {
1031 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1032 rtl8214fc_power_set(phydev, PORT_MII, true);
1033 }
1034 }
1035 }
1036
1037 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1038 {
1039 bool is_fibre = (port == PORT_FIBRE ? true : false);
1040 int addr = phydev->mdio.addr;
1041
1042 pr_debug("%s port %d to %d\n", __func__, addr, port);
1043
1044 rtl8214fc_media_set(phydev, is_fibre);
1045
1046 return 0;
1047 }
1048
1049 static int rtl8214fc_get_port(struct phy_device *phydev)
1050 {
1051 int addr = phydev->mdio.addr;
1052
1053 pr_debug("%s: port %d\n", __func__, addr);
1054 if (rtl8214fc_media_is_fibre(phydev))
1055 return PORT_FIBRE;
1056
1057 return PORT_MII;
1058 }
1059
1060 /* Enable EEE on the RTL8218B PHYs
1061 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1062 * but the only way that works since the kernel first enables EEE in the MAC
1063 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1064 */
1065 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1066 {
1067 u32 val;
1068 bool an_enabled;
1069
1070 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1071 /* Set GPHY page to copper */
1072 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1073
1074 val = phy_read(phydev, MII_BMCR);
1075 an_enabled = val & BMCR_ANENABLE;
1076
1077 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1078 val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
1079 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1080
1081 /* 500M EEE ability */
1082 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1083 if (enable)
1084 val |= BIT(7);
1085 else
1086 val &= ~BIT(7);
1087 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1088
1089 /* Restart AN if enabled */
1090 if (an_enabled) {
1091 val = phy_read(phydev, MII_BMCR);
1092 val |= BMCR_ANRESTART;
1093 phy_write(phydev, MII_BMCR, val);
1094 }
1095
1096 /* GPHY page back to auto */
1097 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1098 }
1099
1100 static int rtl8218b_get_eee(struct phy_device *phydev,
1101 struct ethtool_eee *e)
1102 {
1103 u32 val;
1104 int addr = phydev->mdio.addr;
1105
1106 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1107
1108 /* Set GPHY page to copper */
1109 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1110
1111 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1112 if (e->eee_enabled) {
1113 /* Verify vs MAC-based EEE */
1114 e->eee_enabled = !!(val & BIT(7));
1115 if (!e->eee_enabled) {
1116 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1117 e->eee_enabled = !!(val & BIT(4));
1118 }
1119 }
1120 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1121
1122 /* GPHY page to auto */
1123 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1124
1125 return 0;
1126 }
1127
1128 static int rtl8218d_get_eee(struct phy_device *phydev,
1129 struct ethtool_eee *e)
1130 {
1131 u32 val;
1132 int addr = phydev->mdio.addr;
1133
1134 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1135
1136 /* Set GPHY page to copper */
1137 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1138
1139 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1140 if (e->eee_enabled)
1141 e->eee_enabled = !!(val & BIT(7));
1142 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1143
1144 /* GPHY page to auto */
1145 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1146
1147 return 0;
1148 }
1149
1150 static int rtl8214fc_set_eee(struct phy_device *phydev,
1151 struct ethtool_eee *e)
1152 {
1153 u32 poll_state;
1154 int port = phydev->mdio.addr;
1155 bool an_enabled;
1156 u32 val;
1157
1158 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1159
1160 if (rtl8214fc_media_is_fibre(phydev)) {
1161 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1162 return -ENOTSUPP;
1163 }
1164
1165 poll_state = disable_polling(port);
1166
1167 /* Set GPHY page to copper */
1168 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1169
1170 /* Get auto-negotiation status */
1171 val = phy_read(phydev, MII_BMCR);
1172 an_enabled = val & BMCR_ANENABLE;
1173
1174 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1175 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1176 val &= ~BIT(5); /* Use MAC-based EEE */
1177 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1178
1179 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1180 phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1181
1182 /* 500M EEE ability */
1183 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1184 if (e->eee_enabled)
1185 val |= BIT(7);
1186 else
1187 val &= ~BIT(7);
1188
1189 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1190
1191 /* Restart AN if enabled */
1192 if (an_enabled) {
1193 pr_info("%s: doing aneg\n", __func__);
1194 val = phy_read(phydev, MII_BMCR);
1195 val |= BMCR_ANRESTART;
1196 phy_write(phydev, MII_BMCR, val);
1197 }
1198
1199 /* GPHY page back to auto */
1200 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1201
1202 resume_polling(poll_state);
1203
1204 return 0;
1205 }
1206
1207 static int rtl8214fc_get_eee(struct phy_device *phydev,
1208 struct ethtool_eee *e)
1209 {
1210 int addr = phydev->mdio.addr;
1211
1212 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1213 if (rtl8214fc_media_is_fibre(phydev)) {
1214 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1215 return -ENOTSUPP;
1216 }
1217
1218 return rtl8218b_get_eee(phydev, e);
1219 }
1220
1221 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1222 {
1223 int port = phydev->mdio.addr;
1224 u64 poll_state;
1225 u32 val;
1226 bool an_enabled;
1227
1228 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1229
1230 poll_state = disable_polling(port);
1231
1232 /* Set GPHY page to copper */
1233 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1234 val = phy_read(phydev, MII_BMCR);
1235 an_enabled = val & BMCR_ANENABLE;
1236
1237 if (e->eee_enabled) {
1238 /* 100/1000M EEE Capability */
1239 phy_write(phydev, 13, 0x0007);
1240 phy_write(phydev, 14, 0x003C);
1241 phy_write(phydev, 13, 0x4007);
1242 phy_write(phydev, 14, 0x0006);
1243
1244 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1245 val |= BIT(4);
1246 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1247 } else {
1248 /* 100/1000M EEE Capability */
1249 phy_write(phydev, 13, 0x0007);
1250 phy_write(phydev, 14, 0x003C);
1251 phy_write(phydev, 13, 0x0007);
1252 phy_write(phydev, 14, 0x0000);
1253
1254 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1255 val &= ~BIT(4);
1256 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1257 }
1258
1259 /* Restart AN if enabled */
1260 if (an_enabled) {
1261 val = phy_read(phydev, MII_BMCR);
1262 val |= BMCR_ANRESTART;
1263 phy_write(phydev, MII_BMCR, val);
1264 }
1265
1266 /* GPHY page back to auto */
1267 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1268
1269 pr_info("%s done\n", __func__);
1270 resume_polling(poll_state);
1271
1272 return 0;
1273 }
1274
1275 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1276 {
1277 int addr = phydev->mdio.addr;
1278 u64 poll_state;
1279
1280 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1281
1282 poll_state = disable_polling(addr);
1283
1284 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1285
1286 resume_polling(poll_state);
1287
1288 return 0;
1289 }
1290
1291 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1292 {
1293 return phydev->phy_id == PHY_ID_RTL8214C;
1294 }
1295
1296 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1297 {
1298 u32 phy_id, val;
1299 int mac = phydev->mdio.addr;
1300
1301 val = phy_read(phydev, 2);
1302 phy_id = val << 16;
1303 val = phy_read(phydev, 3);
1304 phy_id |= val;
1305 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1306
1307 phydev_info(phydev, "Detected external RTL8214C\n");
1308
1309 /* GPHY auto conf */
1310 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1311
1312 return 0;
1313 }
1314
1315 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1316 {
1317 int mac = phydev->mdio.addr;
1318 struct fw_header *h;
1319 u32 *rtl8380_rtl8214fc_perchip;
1320 u32 *rtl8380_rtl8214fc_perport;
1321 u32 phy_id;
1322 u32 val;
1323
1324 val = phy_read(phydev, 2);
1325 phy_id = val << 16;
1326 val = phy_read(phydev, 3);
1327 phy_id |= val;
1328 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1329
1330 /* Read internal PHY id */
1331 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1332 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1333 val = phy_read_paged(phydev, 0x1f, 0x1c);
1334 if (val != 0x6276) {
1335 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1336 return -1;
1337 }
1338 phydev_info(phydev, "Detected external RTL8214FC\n");
1339
1340 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1341 if (!h)
1342 return -1;
1343
1344 if (h->phy != 0x8214fc00) {
1345 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1346 return -1;
1347 }
1348
1349 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1350
1351 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1352
1353 /* detect phy version */
1354 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1355 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1356
1357 val = phy_read(phydev, 16);
1358 if (val & BMCR_PDOWN)
1359 rtl8380_rtl8214fc_on_off(phydev, true);
1360 else
1361 rtl8380_phy_reset(phydev);
1362
1363 msleep(100);
1364 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1365
1366 for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
1367 rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
1368 u32 page = 0;
1369
1370 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1371 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1372 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1373 val = phy_read_paged(phydev, 0x260, 13);
1374 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1375 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1376 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1377 } else {
1378 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1379 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1380 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1381 }
1382 }
1383
1384 /* Force copper medium */
1385 for (int i = 0; i < 4; i++) {
1386 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1387 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1388 }
1389
1390 /* Enable PHY */
1391 for (int i = 0; i < 4; i++) {
1392 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1393 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1394 }
1395 mdelay(100);
1396
1397 /* Disable Autosensing */
1398 for (int i = 0; i < 4; i++) {
1399 int l;
1400
1401 for (l = 0; l < 100; l++) {
1402 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1403 if ((val & 0x7) >= 3)
1404 break;
1405 }
1406 if (l >= 100) {
1407 phydev_err(phydev, "Could not disable autosensing\n");
1408 return -1;
1409 }
1410 }
1411
1412 /* Request patch */
1413 for (int i = 0; i < 4; i++) {
1414 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1415 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1416 }
1417 mdelay(300);
1418
1419 /* Verify patch readiness */
1420 for (int i = 0; i < 4; i++) {
1421 int l;
1422
1423 for (l = 0; l < 100; l++) {
1424 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1425 if (val & 0x40)
1426 break;
1427 }
1428 if (l >= 100) {
1429 phydev_err(phydev, "Could not patch PHY\n");
1430 return -1;
1431 }
1432 }
1433 /* Use Broadcast ID method for patching */
1434 rtl821x_phy_setup_package_broadcast(phydev, true);
1435
1436 for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
1437 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1438 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1439 }
1440
1441 /* Disable broadcast ID */
1442 rtl821x_phy_setup_package_broadcast(phydev, false);
1443
1444 /* Auto medium selection */
1445 for (int i = 0; i < 4; i++) {
1446 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1447 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1454 {
1455 int addr = phydev->mdio.addr;
1456
1457 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1458 }
1459
1460 static int rtl8380_configure_serdes(struct phy_device *phydev)
1461 {
1462 u32 v;
1463 u32 sds_conf_value;
1464 int i;
1465 struct fw_header *h;
1466 u32 *rtl8380_sds_take_reset;
1467 u32 *rtl8380_sds_common;
1468 u32 *rtl8380_sds01_qsgmii_6275b;
1469 u32 *rtl8380_sds23_qsgmii_6275b;
1470 u32 *rtl8380_sds4_fiber_6275b;
1471 u32 *rtl8380_sds5_fiber_6275b;
1472 u32 *rtl8380_sds_reset;
1473 u32 *rtl8380_sds_release_reset;
1474
1475 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1476
1477 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1478 if (!h)
1479 return -1;
1480
1481 if (h->magic != 0x83808380) {
1482 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1483 return -1;
1484 }
1485
1486 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1487
1488 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1489
1490 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1491
1492 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1493
1494 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1495
1496 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1497
1498 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1499
1500 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1501
1502 /* Back up serdes power off value */
1503 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1504 pr_info("SDS power down value: %x\n", sds_conf_value);
1505
1506 /* take serdes into reset */
1507 i = 0;
1508 while (rtl8380_sds_take_reset[2 * i]) {
1509 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1510 i++;
1511 udelay(1000);
1512 }
1513
1514 /* apply common serdes patch */
1515 i = 0;
1516 while (rtl8380_sds_common[2 * i]) {
1517 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1518 i++;
1519 udelay(1000);
1520 }
1521
1522 /* internal R/W enable */
1523 sw_w32(3, RTL838X_INT_RW_CTRL);
1524
1525 /* SerDes ports 4 and 5 are FIBRE ports */
1526 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1527
1528 /* SerDes module settings, SerDes 0-3 are QSGMII */
1529 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1530 /* SerDes 4 and 5 are 1000BX FIBRE */
1531 v |= 0x4 << 5 | 0x4;
1532 sw_w32(v, RTL838X_SDS_MODE_SEL);
1533
1534 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1535 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1536 i = 0;
1537 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1538 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1539 rtl8380_sds01_qsgmii_6275b[2 * i]);
1540 i++;
1541 }
1542
1543 i = 0;
1544 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1545 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1546 i++;
1547 }
1548
1549 i = 0;
1550 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1551 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1552 i++;
1553 }
1554
1555 i = 0;
1556 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1557 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1558 i++;
1559 }
1560
1561 i = 0;
1562 while (rtl8380_sds_reset[2 * i]) {
1563 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1564 i++;
1565 }
1566
1567 i = 0;
1568 while (rtl8380_sds_release_reset[2 * i]) {
1569 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1570 i++;
1571 }
1572
1573 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1574 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1575
1576 pr_info("Configuration of SERDES done\n");
1577
1578 return 0;
1579 }
1580
1581 static int rtl8390_configure_serdes(struct phy_device *phydev)
1582 {
1583 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1584
1585 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1586 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1587
1588 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1589 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1590 * and FRE16_EEE_QUIET_FIB1G
1591 */
1592 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1593
1594 return 0;
1595 }
1596
1597 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1598 {
1599 int l = end_bit - start_bit + 1;
1600 u32 data = v;
1601
1602 if (l < 32) {
1603 u32 mask = BIT(l) - 1;
1604
1605 data = rtl930x_read_sds_phy(sds, page, reg);
1606 data &= ~(mask << start_bit);
1607 data |= (v & mask) << start_bit;
1608 }
1609
1610 rtl930x_write_sds_phy(sds, page, reg, data);
1611 }
1612
1613 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1614 {
1615 int l = end_bit - start_bit + 1;
1616 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1617
1618 if (l >= 32)
1619 return v;
1620
1621 return (v >> start_bit) & (BIT(l) - 1);
1622 }
1623
1624 /* Read the link and speed status of the internal SerDes of the RTL9300
1625 */
1626 static int rtl9300_read_status(struct phy_device *phydev)
1627 {
1628 struct device *dev = &phydev->mdio.dev;
1629 int phy_addr = phydev->mdio.addr;
1630 struct device_node *dn;
1631 u32 sds_num = 0, status, latch_status, mode;
1632
1633 if (dev->of_node) {
1634 dn = dev->of_node;
1635
1636 if (of_property_read_u32(dn, "sds", &sds_num))
1637 sds_num = -1;
1638 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1639 } else {
1640 dev_err(dev, "No DT node.\n");
1641 return -EINVAL;
1642 }
1643
1644 if (sds_num < 0)
1645 return 0;
1646
1647 mode = rtl9300_sds_mode_get(sds_num);
1648 pr_info("%s got SDS mode %02x\n", __func__, mode);
1649 if (mode == RTL930X_SDS_MODE_10GBASER) { /* 10GR mode */
1650 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1651 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1652 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1653 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1654 } else {
1655 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1656 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1657 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1658 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1659 }
1660
1661 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1662
1663 if (latch_status) {
1664 phydev->link = true;
1665 if (mode == RTL930X_SDS_MODE_10GBASER)
1666 phydev->speed = SPEED_10000;
1667 else
1668 phydev->speed = SPEED_1000;
1669
1670 phydev->duplex = DUPLEX_FULL;
1671 }
1672
1673 return 0;
1674 }
1675
1676 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1677 {
1678 int page = 0x2e; /* 10GR and USXGMII */
1679
1680 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1681 page = 0x24;
1682
1683 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1684 mdelay(5);
1685 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1686 }
1687
1688 /* Force PHY modes on 10GBit Serdes
1689 */
1690 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1691 {
1692 int lc_value;
1693 int sds_mode;
1694 bool lc_on;
1695 int lane_0 = (sds % 2) ? sds - 1 : sds;
1696 u32 v;
1697
1698 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1699 switch (phy_if) {
1700 case PHY_INTERFACE_MODE_SGMII:
1701 sds_mode = RTL930X_SDS_MODE_SGMII;
1702 lc_on = false;
1703 lc_value = 0x1;
1704 break;
1705
1706 case PHY_INTERFACE_MODE_HSGMII:
1707 sds_mode = RTL930X_SDS_MODE_HSGMII;
1708 lc_value = 0x3;
1709 /* Configure LC */
1710 break;
1711
1712 case PHY_INTERFACE_MODE_1000BASEX:
1713 sds_mode = RTL930X_SDS_MODE_1000BASEX;
1714 lc_on = false;
1715 break;
1716
1717 case PHY_INTERFACE_MODE_2500BASEX:
1718 sds_mode = RTL930X_SDS_MODE_2500BASEX;
1719 lc_value = 0x3;
1720 /* Configure LC */
1721 break;
1722
1723 case PHY_INTERFACE_MODE_10GBASER:
1724 sds_mode = RTL930X_SDS_MODE_10GBASER;
1725 lc_on = true;
1726 lc_value = 0x5;
1727 break;
1728
1729 case PHY_INTERFACE_MODE_NA:
1730 /* This will disable SerDes */
1731 sds_mode = RTL930X_SDS_OFF;
1732 break;
1733
1734 default:
1735 pr_err("%s: unknown serdes mode: %s\n",
1736 __func__, phy_modes(phy_if));
1737 return;
1738 }
1739
1740 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1741 /* Power down SerDes */
1742 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1743 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1744
1745 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1746 /* Force mode enable */
1747 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1748 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1749
1750 /* SerDes off */
1751 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, RTL930X_SDS_OFF);
1752
1753 if (phy_if == PHY_INTERFACE_MODE_NA)
1754 return;
1755
1756 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1757 /* Enable LC and ring */
1758 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1759
1760 if (sds == lane_0)
1761 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1762 else
1763 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1764
1765 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1766
1767 if (lc_on)
1768 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1769 else
1770 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1771
1772 /* Force analog LC & ring on */
1773 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1774
1775 v = lc_on ? 0x3 : 0x1;
1776
1777 if (sds == lane_0)
1778 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1779 else
1780 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1781
1782 /* Force SerDes mode */
1783 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1784 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1785
1786 /* Toggle LC or Ring */
1787 for (int i = 0; i < 20; i++) {
1788 u32 cr_0, cr_1, cr_2;
1789 u32 m_bit, l_bit;
1790
1791 mdelay(200);
1792
1793 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1794
1795 m_bit = (lane_0 == sds) ? (4) : (5);
1796 l_bit = (lane_0 == sds) ? (4) : (5);
1797
1798 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1799 mdelay(10);
1800 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1801 mdelay(10);
1802 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1803
1804 if (cr_0 && cr_1 && cr_2) {
1805 u32 t;
1806
1807 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1808 break;
1809
1810 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1811 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1812
1813 /* Reset FSM */
1814 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1815 mdelay(10);
1816 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1817 mdelay(10);
1818
1819 /* Need to read this twice */
1820 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1821 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1822
1823 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1824
1825 /* Reset FSM again */
1826 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1827 mdelay(10);
1828 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1829 mdelay(10);
1830
1831 if (v == 1)
1832 break;
1833 }
1834
1835 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1836 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1837
1838 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1839 mdelay(10);
1840 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1841 }
1842
1843 rtl930x_sds_rx_rst(sds, phy_if);
1844
1845 /* Re-enable power */
1846 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1847
1848 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1849 }
1850
1851 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1852 {
1853 /* parameters: rtl9303_80G_txParam_s2 */
1854 int impedance = 0x8;
1855 int pre_amp = 0x2;
1856 int main_amp = 0x9;
1857 int post_amp = 0x2;
1858 int pre_en = 0x1;
1859 int post_en = 0x1;
1860 int page;
1861
1862 switch(phy_if) {
1863 case PHY_INTERFACE_MODE_1000BASEX:
1864 page = 0x25;
1865 break;
1866 case PHY_INTERFACE_MODE_HSGMII:
1867 case PHY_INTERFACE_MODE_2500BASEX:
1868 page = 0x29;
1869 break;
1870 case PHY_INTERFACE_MODE_10GBASER:
1871 page = 0x2f;
1872 break;
1873 default:
1874 pr_err("%s: unsupported PHY mode\n", __func__);
1875 return;
1876 }
1877
1878 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1879 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1880 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1881 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1882 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1883 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1884 }
1885
1886 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1887 * timeout is in ms
1888 */
1889 int rtl9300_sds_clock_wait(int timeout)
1890 {
1891 u32 v;
1892 unsigned long start = jiffies;
1893
1894 do {
1895 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1896 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1897 if (v == 3)
1898 return 0;
1899 } while (jiffies < start + (HZ / 1000) * timeout);
1900
1901 return 1;
1902 }
1903
1904 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1905 {
1906 u32 v10, v1;
1907
1908 v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
1909 v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
1910 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1911
1912 v10 &= ~(BIT(13) | BIT(14));
1913 v1 &= ~(BIT(8) | BIT(9));
1914
1915 v10 |= rx_normal ? 0 : BIT(13);
1916 v1 |= rx_normal ? 0 : BIT(9);
1917
1918 v10 |= tx_normal ? 0 : BIT(14);
1919 v1 |= tx_normal ? 0 : BIT(8);
1920
1921 rtl930x_write_sds_phy(sds, 6, 2, v10);
1922 rtl930x_write_sds_phy(sds, 0, 0, v1);
1923
1924 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1925 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1926 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1927 }
1928
1929 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1930 {
1931 if (manual) {
1932 switch(dcvs_id) {
1933 case 0:
1934 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1935 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1936 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1937 break;
1938 case 1:
1939 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1940 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1941 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1942 break;
1943 case 2:
1944 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1945 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1946 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1947 break;
1948 case 3:
1949 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1950 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1951 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1952 break;
1953 case 4:
1954 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1955 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1956 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1957 break;
1958 case 5:
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1960 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1961 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1962 break;
1963 default:
1964 break;
1965 }
1966 } else {
1967 switch(dcvs_id) {
1968 case 0:
1969 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1970 break;
1971 case 1:
1972 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1973 break;
1974 case 2:
1975 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1976 break;
1977 case 3:
1978 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1979 break;
1980 case 4:
1981 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1982 break;
1983 case 5:
1984 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1985 break;
1986 default:
1987 break;
1988 }
1989 mdelay(1);
1990 }
1991 }
1992
1993 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1994 {
1995 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1996 bool dcvs_manual;
1997
1998 if (!(sds_num % 2))
1999 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2000 else
2001 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2002
2003 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2004 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2005
2006 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2007 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2008
2009 switch(dcvs_id) {
2010 case 0:
2011 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2012 mdelay(1);
2013
2014 /* ##DCVS0 Read Out */
2015 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2016 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2017 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2018 break;
2019
2020 case 1:
2021 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2022 mdelay(1);
2023
2024 /* ##DCVS0 Read Out */
2025 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2026 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2027 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2028 break;
2029
2030 case 2:
2031 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2032 mdelay(1);
2033
2034 /* ##DCVS0 Read Out */
2035 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2036 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2037 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2038 break;
2039 case 3:
2040 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2041 mdelay(1);
2042
2043 /* ##DCVS0 Read Out */
2044 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2045 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2046 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2047 break;
2048
2049 case 4:
2050 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2051 mdelay(1);
2052
2053 /* ##DCVS0 Read Out */
2054 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2055 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2056 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2057 break;
2058
2059 case 5:
2060 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2061 mdelay(1);
2062
2063 /* ##DCVS0 Read Out */
2064 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2065 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2066 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 if (dcvs_sign_out)
2074 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2075 else
2076 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2077
2078 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2079 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2080
2081 dcvs_list[0] = dcvs_sign_out;
2082 dcvs_list[1] = dcvs_coef_bin;
2083 }
2084
2085 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2086 {
2087 if (manual) {
2088 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2089 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2090 } else {
2091 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2092 mdelay(100);
2093 }
2094 }
2095
2096 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2097 {
2098 if (manual) {
2099 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2100 } else {
2101 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2102 mdelay(1);
2103 }
2104 }
2105
2106 #define GRAY_BITS 5
2107 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2108 {
2109 int i, j, m;
2110 u32 g[GRAY_BITS];
2111 u32 c[GRAY_BITS];
2112 u32 leq_binary = 0;
2113
2114 for(i = 0; i < GRAY_BITS; i++)
2115 g[i] = (gray_code & BIT(i)) >> i;
2116
2117 m = GRAY_BITS - 1;
2118
2119 c[m] = g[m];
2120
2121 for(i = 0; i < m; i++) {
2122 c[i] = g[i];
2123 for(j = i + 1; j < GRAY_BITS; j++)
2124 c[i] = c[i] ^ g[j];
2125 }
2126
2127 for(i = 0; i < GRAY_BITS; i++)
2128 leq_binary += c[i] << i;
2129
2130 return leq_binary;
2131 }
2132
2133 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2134 {
2135 u32 leq_gray, leq_bin;
2136 bool leq_manual;
2137
2138 if (!(sds_num % 2))
2139 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2140 else
2141 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2142
2143 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2144 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2145
2146 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2147 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2148 mdelay(1);
2149
2150 /* ##LEQ Read Out */
2151 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2152 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2153 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2154
2155 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2156 pr_info("LEQ manual: %u", leq_manual);
2157
2158 return leq_bin;
2159 }
2160
2161 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2162 {
2163 if (manual) {
2164 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2165 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2166 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2167 } else {
2168 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2169 mdelay(10);
2170 }
2171 }
2172
2173 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2174 {
2175 u32 vth_manual;
2176
2177 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2178 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2179 if (!(sds_num % 2))
2180 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2181 else
2182 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2183
2184 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2185 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2186 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2187 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2188 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2189 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2190
2191 mdelay(1);
2192
2193 /* ##VthP & VthN Read Out */
2194 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2195 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2196
2197 pr_info("vth_set_bin = %d", vth_list[0]);
2198 pr_info("vth_set_bin = %d", vth_list[1]);
2199
2200 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2201 pr_info("Vth Maunal = %d", vth_manual);
2202 }
2203
2204 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2205 {
2206 if (manual) {
2207 switch(tap_id) {
2208 case 0:
2209 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2210 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2211 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2212 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2213 break;
2214 case 1:
2215 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2216 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2217 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2218 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2219 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2220 break;
2221 case 2:
2222 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2223 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2224 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2225 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2226 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2227 break;
2228 case 3:
2229 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2230 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2231 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2232 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2233 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2234 break;
2235 case 4:
2236 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2237 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2238 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2239 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2240 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2241 break;
2242 default:
2243 break;
2244 }
2245 } else {
2246 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2247 mdelay(10);
2248 }
2249 }
2250
2251 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2252 {
2253 u32 tap0_sign_out;
2254 u32 tap0_coef_bin;
2255 u32 tap_sign_out_even;
2256 u32 tap_coef_bin_even;
2257 u32 tap_sign_out_odd;
2258 u32 tap_coef_bin_odd;
2259 bool tap_manual;
2260
2261 if (!(sds_num % 2))
2262 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2263 else
2264 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2265
2266 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2267 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2268 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2269 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2270
2271 if (!tap_id) {
2272 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2273 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2274 /* ##Tap1 Even Read Out */
2275 mdelay(1);
2276 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2277 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2278
2279 if (tap0_sign_out == 1)
2280 pr_info("Tap0 Sign : -");
2281 else
2282 pr_info("Tap0 Sign : +");
2283
2284 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2285
2286 tap_list[0] = tap0_sign_out;
2287 tap_list[1] = tap0_coef_bin;
2288
2289 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2290 pr_info("tap0 manual = %u",tap_manual);
2291 } else {
2292 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2293 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2294 mdelay(1);
2295 /* ##Tap1 Even Read Out */
2296 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2297 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2298
2299 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2300 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2301 /* ##Tap1 Odd Read Out */
2302 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2303 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2304
2305 if (tap_sign_out_even == 1)
2306 pr_info("Tap %u even sign: -", tap_id);
2307 else
2308 pr_info("Tap %u even sign: +", tap_id);
2309
2310 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2311
2312 if (tap_sign_out_odd == 1)
2313 pr_info("Tap %u odd sign: -", tap_id);
2314 else
2315 pr_info("Tap %u odd sign: +", tap_id);
2316
2317 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2318
2319 tap_list[0] = tap_sign_out_even;
2320 tap_list[1] = tap_coef_bin_even;
2321 tap_list[2] = tap_sign_out_odd;
2322 tap_list[3] = tap_coef_bin_odd;
2323
2324 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2325 pr_info("tap %u manual = %d",tap_id, tap_manual);
2326 }
2327 }
2328
2329 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2330 {
2331 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2332 int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2333 int vth_min = 0x0;
2334
2335 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2336 rtl930x_write_sds_phy(sds, 6, 0, 0);
2337
2338 /* FGCAL */
2339 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2340 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2341 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2342
2343 /* DCVS */
2344 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2345 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2346 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2347 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2348 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2349 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2350 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2351 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2352 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2353 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2354 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2355 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2356
2357 /* LEQ (Long Term Equivalent signal level) */
2358 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2359
2360 /* DFE (Decision Fed Equalizer) */
2361 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2362 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2363 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2364 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2365 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2366 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2368 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2369 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2370
2371 /* Vth */
2372 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2373 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2374 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2375
2376 pr_info("end_1.1.1 --\n");
2377
2378 pr_info("start_1.1.2 Load DFE init. value\n");
2379
2380 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2381
2382 pr_info("end_1.1.2\n");
2383
2384 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2385
2386 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2387 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2388 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2389 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2390 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2391 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2392
2393 pr_info("end_1.1.3 --\n");
2394
2395 pr_info("start_1.1.4 offset cali setting\n");
2396
2397 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2398
2399 pr_info("end_1.1.4\n");
2400
2401 pr_info("start_1.1.5 LEQ and DFE setting\n");
2402
2403 /* TODO: make this work for DAC cables of different lengths */
2404 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2405 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2406 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2407 else
2408 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2409
2410 /* No serdes, check for Aquantia PHYs */
2411 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2412
2413 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2414 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2415 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2416 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2417 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2418
2419 pr_info("end_1.1.5\n");
2420 }
2421
2422 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2423 {
2424 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2425
2426 /* Gray config endis to 1 */
2427 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2428
2429 /* ForegroundOffsetCal_Manual(auto mode) */
2430 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2431
2432 pr_info("end_1.2.1");
2433 }
2434
2435 void rtl9300_do_rx_calibration_2_2(int sds_num)
2436 {
2437 /* Force Rx-Run = 0 */
2438 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2439
2440 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2441 }
2442
2443 void rtl9300_do_rx_calibration_2_3(int sds_num)
2444 {
2445 u32 fgcal_binary, fgcal_gray;
2446 u32 offset_range;
2447
2448 pr_info("start_1.2.3 Foreground Calibration\n");
2449
2450 while(1) {
2451 if (!(sds_num % 2))
2452 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2453 else
2454 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2455
2456 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2457 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2458 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2459 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2460 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2461 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2462 /* ##FGCAL read gray */
2463 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2464 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2465 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2466 /* ##FGCAL read binary */
2467 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2468
2469 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2470 __func__, fgcal_gray, fgcal_binary);
2471
2472 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2473
2474 if (fgcal_binary > 60 || fgcal_binary < 3) {
2475 if (offset_range == 3) {
2476 pr_info("%s: Foreground Calibration result marginal!", __func__);
2477 break;
2478 } else {
2479 offset_range++;
2480 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2481 rtl9300_do_rx_calibration_2_2(sds_num);
2482 }
2483 } else {
2484 break;
2485 }
2486 }
2487 pr_info("%s: end_1.2.3\n", __func__);
2488 }
2489
2490 void rtl9300_do_rx_calibration_2(int sds)
2491 {
2492 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2493 rtl9300_do_rx_calibration_2_1(sds);
2494 rtl9300_do_rx_calibration_2_2(sds);
2495 rtl9300_do_rx_calibration_2_3(sds);
2496 }
2497
2498 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2499 {
2500 pr_info("start_1.3.1");
2501
2502 /* ##1.3.1 */
2503 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2504 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2505
2506 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2507 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2508
2509 pr_info("end_1.3.1");
2510 }
2511
2512 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2513 {
2514 u32 sum10 = 0, avg10, int10;
2515 int dac_long_cable_offset;
2516 bool eq_hold_enabled;
2517 int i;
2518
2519 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2520 /* rtl9300_rxCaliConf_serdes_myParam */
2521 dac_long_cable_offset = 3;
2522 eq_hold_enabled = true;
2523 } else {
2524 /* rtl9300_rxCaliConf_phy_myParam */
2525 dac_long_cable_offset = 0;
2526 eq_hold_enabled = false;
2527 }
2528
2529 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2530 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2531
2532 pr_info("start_1.3.2");
2533
2534 for(i = 0; i < 10; i++) {
2535 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2536 mdelay(10);
2537 }
2538
2539 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2540 int10 = sum10 / 10;
2541
2542 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2543
2544 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2545 if (dac_long_cable_offset) {
2546 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2547 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2548 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2549 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2550 } else {
2551 if (sum10 >= 5) {
2552 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2553 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2554 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2555 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2556 } else {
2557 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2558 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2559 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2560 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2561 }
2562 }
2563 }
2564
2565 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2566
2567 pr_info("end_1.3.2");
2568 }
2569
2570 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2571 {
2572 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2573
2574 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2575 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2576 }
2577
2578 void rtl9300_do_rx_calibration_4_1(int sds_num)
2579 {
2580 u32 vth_list[2] = {0, 0};
2581 u32 tap0_list[4] = {0, 0, 0, 0};
2582
2583 pr_info("start_1.4.1");
2584
2585 /* ##1.4.1 */
2586 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2587 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2588 mdelay(200);
2589
2590 pr_info("end_1.4.1");
2591 }
2592
2593 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2594 {
2595 u32 vth_list[2];
2596 u32 tap_list[4];
2597
2598 pr_info("start_1.4.2");
2599
2600 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2601 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2602
2603 mdelay(100);
2604
2605 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2606 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2607
2608 pr_info("end_1.4.2");
2609 }
2610
2611 void rtl9300_do_rx_calibration_4(u32 sds_num)
2612 {
2613 rtl9300_do_rx_calibration_4_1(sds_num);
2614 rtl9300_do_rx_calibration_4_2(sds_num);
2615 }
2616
2617 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2618 {
2619 u32 tap1_list[4] = {0};
2620 u32 tap2_list[4] = {0};
2621 u32 tap3_list[4] = {0};
2622 u32 tap4_list[4] = {0};
2623
2624 pr_info("start_1.5.2");
2625
2626 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2627 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2628 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2629 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2630
2631 mdelay(30);
2632
2633 pr_info("end_1.5.2");
2634 }
2635
2636 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2637 {
2638 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */
2639 rtl9300_do_rx_calibration_5_2(sds_num);
2640 }
2641
2642
2643 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2644 {
2645 u32 tap1_list[4] = {0};
2646 u32 tap2_list[4] = {0};
2647 u32 tap3_list[4] = {0};
2648 u32 tap4_list[4] = {0};
2649
2650 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2651 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2652 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2653 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2654
2655 mdelay(10);
2656 }
2657
2658 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2659 {
2660 u32 latch_sts;
2661
2662 rtl9300_do_rx_calibration_1(sds, phy_mode);
2663 rtl9300_do_rx_calibration_2(sds);
2664 rtl9300_do_rx_calibration_4(sds);
2665 rtl9300_do_rx_calibration_5(sds, phy_mode);
2666 mdelay(20);
2667
2668 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2669 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == RTL930X_SDS_MODE_10GBASER) {
2670 pr_info("%s: SDS enabled\n", __func__);
2671 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2672 mdelay(1);
2673 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2674 if (latch_sts) {
2675 rtl9300_do_rx_calibration_dfe_disable(sds);
2676 rtl9300_do_rx_calibration_4(sds);
2677 rtl9300_do_rx_calibration_5(sds, phy_mode);
2678 }
2679 }
2680 }
2681
2682 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2683 {
2684 switch (phy_mode) {
2685 case PHY_INTERFACE_MODE_XGMII:
2686 break;
2687
2688 case PHY_INTERFACE_MODE_10GBASER:
2689 /* Read twice to clear */
2690 rtl930x_read_sds_phy(sds_num, 5, 1);
2691 rtl930x_read_sds_phy(sds_num, 5, 1);
2692 break;
2693
2694 case PHY_INTERFACE_MODE_1000BASEX:
2695 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2696 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2697 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2698 break;
2699
2700 default:
2701 pr_info("%s unsupported phy mode\n", __func__);
2702 return -1;
2703 }
2704
2705 return 0;
2706 }
2707
2708 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2709 {
2710 u32 v = 0;
2711
2712 switch (phy_mode) {
2713 case PHY_INTERFACE_MODE_XGMII:
2714 break;
2715
2716 case PHY_INTERFACE_MODE_10GBASER:
2717 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2718 return v & 0xff;
2719
2720 default:
2721 pr_info("%s unsupported PHY-mode\n", __func__);
2722 }
2723
2724 return v;
2725 }
2726
2727 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2728 {
2729 u32 errors1, errors2;
2730
2731 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2732 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2733
2734 /* Count errors during 1ms */
2735 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2736 mdelay(1);
2737 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2738
2739 switch (phy_mode) {
2740 case PHY_INTERFACE_MODE_XGMII:
2741 if ((errors2 - errors1 > 100) ||
2742 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2743 pr_info("%s XSGMII error rate too high\n", __func__);
2744 return 1;
2745 }
2746 break;
2747 case PHY_INTERFACE_MODE_10GBASER:
2748 if (errors2 > 0) {
2749 pr_info("%s 10GBASER error rate too high\n", __func__);
2750 return 1;
2751 }
2752 break;
2753 default:
2754 return 1;
2755 }
2756
2757 return 0;
2758 }
2759
2760 void rtl9300_phy_enable_10g_1g(int sds_num)
2761 {
2762 u32 v;
2763
2764 /* Enable 1GBit PHY */
2765 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
2766 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2767 v &= ~BMCR_PDOWN;
2768 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
2769 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2770
2771 /* Enable 10GBit PHY */
2772 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
2773 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2774 v &= ~BMCR_PDOWN;
2775 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
2776 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2777
2778 /* dal_longan_construct_mac_default_10gmedia_fiber */
2779 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2780 pr_info("%s set medium: %08x\n", __func__, v);
2781 v |= BIT(1);
2782 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2783 pr_info("%s set medium after: %08x\n", __func__, v);
2784 }
2785
2786 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2787 /* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */
2788 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2789 {
2790 int sds_mode;
2791 int calib_tries = 0;
2792
2793 switch (phy_mode) {
2794 case PHY_INTERFACE_MODE_HSGMII:
2795 sds_mode = RTL930X_SDS_MODE_HSGMII;
2796 break;
2797 case PHY_INTERFACE_MODE_1000BASEX:
2798 sds_mode = RTL930X_SDS_MODE_1000BASEX;
2799 break;
2800 case PHY_INTERFACE_MODE_XGMII:
2801 sds_mode = RTL930X_SDS_MODE_XGMII;
2802 break;
2803 case PHY_INTERFACE_MODE_10GBASER:
2804 sds_mode = RTL930X_SDS_MODE_10GBASER;
2805 break;
2806 case PHY_INTERFACE_MODE_USXGMII:
2807 sds_mode = RTL930X_SDS_MODE_USXGMII;
2808 break;
2809 default:
2810 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2811 return -EINVAL;
2812 }
2813
2814 /* Maybe use dal_longan_sds_init */
2815
2816 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2817 rtl9300_phy_enable_10g_1g(sds_num);
2818
2819 /* Set Serdes Mode */
2820 rtl9300_sds_set(sds_num, RTL930X_SDS_MODE_10GBASER); /* 0x1b: RTK_MII_10GR1000BX_AUTO */
2821
2822 /* Do RX calibration */
2823 do {
2824 rtl9300_do_rx_calibration(sds_num, phy_mode);
2825 calib_tries++;
2826 mdelay(50);
2827 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2828
2829
2830 return 0;
2831 }
2832
2833 typedef struct {
2834 u8 page;
2835 u8 reg;
2836 u16 data;
2837 } sds_config;
2838
2839 sds_config rtl9300_a_sds_10gr_lane0[] =
2840 {
2841 /* 1G */
2842 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2843 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2844 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2845 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2846 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2847 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2848 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2849 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2850 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2851 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2852 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2853 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2854 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2855 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2856 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2857 {0x2F, 0x1D, 0x66E1},
2858 /* 3.125G */
2859 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2860 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2861 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2862 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2863 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2864 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2865 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2866 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2867 /* 10G */
2868 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2869 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2870 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2871 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2872 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2873 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2874 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2875 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2876 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2877 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2878 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2879 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2880 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2881 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2882 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2883 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2884 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2885 };
2886
2887 sds_config rtl9300_a_sds_10gr_lane1[] =
2888 {
2889 /* 1G */
2890 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2891 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2892 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2893 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2894 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2895 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2896 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2897 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2898 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2899 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2900 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2901 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2902 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2903 {0x2D, 0x14, 0x1808},
2904 /* 3.125G */
2905 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2906 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2907 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2908 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2909 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2910 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2911 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2912 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2913 /* 10G */
2914 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2915 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2916 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2917 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2918 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2919 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2920 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2921 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2922 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2923 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2924 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2925 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2926 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2927 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2928 };
2929
2930 int rtl9300_sds_cmu_band_get(int sds)
2931 {
2932 u32 page;
2933 u32 en;
2934 u32 cmu_band;
2935
2936 /* page = rtl9300_sds_cmu_page_get(sds); */
2937 page = 0x25; /* 10GR and 1000BX */
2938 sds = (sds % 2) ? (sds - 1) : (sds);
2939
2940 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2941 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2942
2943 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2944 if(!en) { /* Auto mode */
2945 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2946
2947 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2948 } else {
2949 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2950 }
2951
2952 return cmu_band;
2953 }
2954
2955 int rtl9300_configure_serdes(struct phy_device *phydev)
2956 {
2957 int phy_mode = PHY_INTERFACE_MODE_10GBASER;
2958 struct device *dev = &phydev->mdio.dev;
2959 int calib_tries = 0;
2960 u32 sds_num = 0;
2961 int sds_mode;
2962
2963 if (dev->of_node) {
2964 struct device_node *dn = dev->of_node;
2965 int phy_addr = phydev->mdio.addr;
2966
2967 if (of_property_read_u32(dn, "sds", &sds_num))
2968 sds_num = -1;
2969 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2970 } else {
2971 dev_err(dev, "No DT node.\n");
2972 return -EINVAL;
2973 }
2974
2975 if (sds_num < 0)
2976 return 0;
2977
2978 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) /* TODO: for now we only patch 10GR SerDes */
2979 return 0;
2980
2981 switch (phy_mode) {
2982 case PHY_INTERFACE_MODE_HSGMII:
2983 sds_mode = RTL930X_SDS_MODE_HSGMII;
2984 break;
2985 case PHY_INTERFACE_MODE_1000BASEX:
2986 sds_mode = RTL930X_SDS_MODE_1000BASEX;
2987 break;
2988 case PHY_INTERFACE_MODE_XGMII:
2989 sds_mode = RTL930X_SDS_MODE_XGMII;
2990 break;
2991 case PHY_INTERFACE_MODE_10GBASER:
2992 sds_mode = RTL930X_SDS_MODE_10GBASER;
2993 break;
2994 case PHY_INTERFACE_MODE_USXGMII:
2995 sds_mode = RTL930X_SDS_MODE_USXGMII;
2996 break;
2997 default:
2998 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2999 return -EINVAL;
3000 }
3001
3002 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
3003
3004 /* Turn Off Serdes */
3005 rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
3006
3007 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
3008 if (sds_num % 2) {
3009 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
3010 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
3011 rtl9300_a_sds_10gr_lane1[i].reg,
3012 rtl9300_a_sds_10gr_lane1[i].data);
3013 }
3014 } else {
3015 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
3016 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3017 rtl9300_a_sds_10gr_lane0[i].reg,
3018 rtl9300_a_sds_10gr_lane0[i].data);
3019 }
3020 }
3021
3022 rtl9300_phy_enable_10g_1g(sds_num);
3023
3024 /* Disable MAC */
3025 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3026 mdelay(20);
3027
3028 /* ----> dal_longan_sds_mode_set */
3029 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3030
3031 /* Configure link to MAC */
3032 rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
3033
3034 /* Disable MAC */
3035 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3036 mdelay(20);
3037
3038 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3039
3040 /* Re-Enable MAC */
3041 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3042
3043 rtl9300_force_sds_mode(sds_num, phy_mode);
3044
3045 /* Do RX calibration */
3046 do {
3047 rtl9300_do_rx_calibration(sds_num, phy_mode);
3048 calib_tries++;
3049 mdelay(50);
3050 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3051
3052 if (calib_tries >= 3)
3053 pr_err("%s CALIBTRATION FAILED\n", __func__);
3054
3055 rtl9300_sds_tx_config(sds_num, phy_mode);
3056
3057 /* The clock needs only to be configured on the FPGA implementation */
3058
3059 return 0;
3060 }
3061
3062 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3063 {
3064 int l = end_bit - start_bit + 1;
3065 u32 data = v;
3066
3067 if (l < 32) {
3068 u32 mask = BIT(l) - 1;
3069
3070 data = rtl930x_read_sds_phy(sds, page, reg);
3071 data &= ~(mask << start_bit);
3072 data |= (v & mask) << start_bit;
3073 }
3074
3075 rtl931x_write_sds_phy(sds, page, reg, data);
3076 }
3077
3078 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3079 {
3080 int l = end_bit - start_bit + 1;
3081 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3082
3083 if (l >= 32)
3084 return v;
3085
3086 return (v >> start_bit) & (BIT(l) - 1);
3087 }
3088
3089 static void rtl931x_sds_rst(u32 sds)
3090 {
3091 u32 o, v, o_mode;
3092 int shift = ((sds & 0x3) << 3);
3093
3094 /* TODO: We need to lock this! */
3095
3096 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3097 v = o | BIT(sds);
3098 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3099
3100 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3101 v = BIT(7) | 0x1F;
3102 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3103 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3104
3105 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3106 }
3107
3108 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3109 {
3110
3111 switch (mode) {
3112 case PHY_INTERFACE_MODE_NA:
3113 break;
3114 case PHY_INTERFACE_MODE_XGMII:
3115 u32 xsg_sdsid_0, xsg_sdsid_1;
3116
3117 if (sds < 2)
3118 xsg_sdsid_0 = sds;
3119 else
3120 xsg_sdsid_0 = (sds - 1) * 2;
3121 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3122
3123 for (int i = 0; i < 4; ++i) {
3124 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3125 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3126 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3127 }
3128
3129 for (int i = 0; i < 4; ++i) {
3130 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3131 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3132 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3133 }
3134
3135 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3136 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3137 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3138 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3139 break;
3140 default:
3141 break;
3142 }
3143
3144 return;
3145 }
3146
3147 static u32 rtl931x_get_analog_sds(u32 sds)
3148 {
3149 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3150
3151 if (sds < 14)
3152 return sds_map[sds];
3153
3154 return sds;
3155 }
3156
3157 void rtl931x_sds_fiber_disable(u32 sds)
3158 {
3159 u32 v = 0x3F;
3160 u32 asds = rtl931x_get_analog_sds(sds);
3161
3162 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3163 }
3164
3165 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3166 {
3167 u32 val, asds = rtl931x_get_analog_sds(sds);
3168
3169 /* clear symbol error count before changing mode */
3170 rtl931x_symerr_clear(sds, mode);
3171
3172 val = 0x9F;
3173 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3174
3175 switch (mode) {
3176 case PHY_INTERFACE_MODE_SGMII:
3177 val = 0x5;
3178 break;
3179
3180 case PHY_INTERFACE_MODE_1000BASEX:
3181 /* serdes mode FIBER1G */
3182 val = 0x9;
3183 break;
3184
3185 case PHY_INTERFACE_MODE_10GBASER:
3186 case PHY_INTERFACE_MODE_10GKR:
3187 val = 0x35;
3188 break;
3189 /* case MII_10GR1000BX_AUTO:
3190 val = 0x39;
3191 break; */
3192
3193
3194 case PHY_INTERFACE_MODE_USXGMII:
3195 val = 0x1B;
3196 break;
3197 default:
3198 val = 0x25;
3199 }
3200
3201 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3202 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3203
3204 return;
3205 }
3206
3207 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3208 {
3209 switch (mode) {
3210 case PHY_INTERFACE_MODE_SGMII:
3211 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3212 return 0x24;
3213 case PHY_INTERFACE_MODE_HSGMII:
3214 case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */
3215 return 0x28;
3216 /* case MII_HISGMII_5G: */
3217 /* return 0x2a; */
3218 case PHY_INTERFACE_MODE_QSGMII:
3219 return 0x2a; /* Code also has 0x34 */
3220 case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */
3221 return 0x2c;
3222 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3223 case PHY_INTERFACE_MODE_10GKR:
3224 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */
3225 return 0x2e;
3226 default:
3227 return -1;
3228 }
3229
3230 return -1;
3231 }
3232
3233 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3234 {
3235 int cmu_type = 0; /* Clock Management Unit */
3236 u32 cmu_page = 0;
3237 u32 frc_cmu_spd;
3238 u32 evenSds;
3239 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3240
3241 switch (mode) {
3242 case PHY_INTERFACE_MODE_NA:
3243 case PHY_INTERFACE_MODE_10GKR:
3244 case PHY_INTERFACE_MODE_XGMII:
3245 case PHY_INTERFACE_MODE_10GBASER:
3246 case PHY_INTERFACE_MODE_USXGMII:
3247 return;
3248
3249 /* case MII_10GR1000BX_AUTO:
3250 if (chiptype)
3251 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3252 return; */
3253
3254 case PHY_INTERFACE_MODE_QSGMII:
3255 cmu_type = 1;
3256 frc_cmu_spd = 0;
3257 break;
3258
3259 case PHY_INTERFACE_MODE_HSGMII:
3260 cmu_type = 1;
3261 frc_cmu_spd = 1;
3262 break;
3263
3264 case PHY_INTERFACE_MODE_1000BASEX:
3265 cmu_type = 1;
3266 frc_cmu_spd = 0;
3267 break;
3268
3269 /* case MII_1000BX100BX_AUTO:
3270 cmu_type = 1;
3271 frc_cmu_spd = 0;
3272 break; */
3273
3274 case PHY_INTERFACE_MODE_SGMII:
3275 cmu_type = 1;
3276 frc_cmu_spd = 0;
3277 break;
3278
3279 case PHY_INTERFACE_MODE_2500BASEX:
3280 cmu_type = 1;
3281 frc_cmu_spd = 1;
3282 break;
3283
3284 default:
3285 pr_info("SerDes %d mode is invalid\n", asds);
3286 return;
3287 }
3288
3289 if (cmu_type == 1)
3290 cmu_page = rtl931x_sds_cmu_page_get(mode);
3291
3292 lane = asds % 2;
3293
3294 if (!lane) {
3295 frc_lc_mode_bitnum = 4;
3296 frc_lc_mode_val_bitnum = 5;
3297 } else {
3298 frc_lc_mode_bitnum = 6;
3299 frc_lc_mode_val_bitnum = 7;
3300 }
3301
3302 evenSds = asds - lane;
3303
3304 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3305 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3306
3307 if (cmu_type == 1) {
3308 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3309 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3310 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3311 if (chiptype) {
3312 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3313 }
3314
3315 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3316 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3317 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3318 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3319 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3320 }
3321
3322 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3323 return;
3324 }
3325
3326 static void rtl931x_sds_rx_rst(u32 sds)
3327 {
3328 u32 asds = rtl931x_get_analog_sds(sds);
3329
3330 if (sds < 2)
3331 return;
3332
3333 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3334 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3335 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3336 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3337
3338 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3339 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3340 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3341 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3342
3343 mdelay(50);
3344 }
3345
3346 // Currently not used
3347 // static void rtl931x_sds_disable(u32 sds)
3348 // {
3349 // u32 v = 0x1f;
3350
3351 // v |= BIT(7);
3352 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3353 // }
3354
3355 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3356 {
3357 u32 val;
3358
3359 switch (mode) {
3360 case PHY_INTERFACE_MODE_QSGMII:
3361 val = 0x6;
3362 break;
3363 case PHY_INTERFACE_MODE_XGMII:
3364 val = 0x10; /* serdes mode XSGMII */
3365 break;
3366 case PHY_INTERFACE_MODE_USXGMII:
3367 case PHY_INTERFACE_MODE_2500BASEX:
3368 val = 0xD;
3369 break;
3370 case PHY_INTERFACE_MODE_HSGMII:
3371 val = 0x12;
3372 break;
3373 case PHY_INTERFACE_MODE_SGMII:
3374 val = 0x2;
3375 break;
3376 default:
3377 return;
3378 }
3379
3380 val |= (1 << 7);
3381
3382 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3383 }
3384
3385 static sds_config sds_config_10p3125g_type1[] = {
3386 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3387 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3388 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3389 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3390 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3391 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3392 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3393 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3394 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3395 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3396 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3397 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3398 { 0x2F, 0x13, 0x0000 }
3399 };
3400
3401 static sds_config sds_config_10p3125g_cmu_type1[] = {
3402 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3403 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3404 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3405 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3406 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3407 };
3408
3409 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3410 {
3411 u32 board_sds_tx_type1[] = {
3412 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3413 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3414 };
3415 u32 board_sds_tx[] = {
3416 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3417 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3418 };
3419 u32 board_sds_tx2[] = {
3420 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3421 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3422 };
3423 u32 asds, dSds, ori, model_info, val;
3424 int chiptype = 0;
3425
3426 asds = rtl931x_get_analog_sds(sds);
3427
3428 if (sds > 13)
3429 return;
3430
3431 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3432 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3433
3434 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3435 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3436 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3437 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3438 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3439 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3440 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3441 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3442 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3443 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3444 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3445 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3446
3447 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3448 if ((model_info >> 4) & 0x1) {
3449 pr_info("detected chiptype 1\n");
3450 chiptype = 1;
3451 } else {
3452 pr_info("detected chiptype 0\n");
3453 }
3454
3455 if (sds < 2)
3456 dSds = sds;
3457 else
3458 dSds = (sds - 1) * 2;
3459
3460 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3461 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3462
3463 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3464 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3465 val = ori | (1 << sds);
3466 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3467
3468 switch (mode) {
3469 case PHY_INTERFACE_MODE_NA:
3470 break;
3471
3472 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3473
3474 if (chiptype) {
3475 u32 xsg_sdsid_1;
3476 xsg_sdsid_1 = dSds + 1;
3477 /* fifo inv clk */
3478 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3479 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3480
3481 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3482 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3483
3484 }
3485
3486 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3487 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3488 break;
3489
3490 case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3491 u32 op_code = 0x6003;
3492 u32 evenSds;
3493
3494 if (chiptype) {
3495 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3496
3497 for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3498 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3499 }
3500
3501 evenSds = asds - (asds % 2);
3502
3503 for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3504 rtl931x_write_sds_phy(evenSds,
3505 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3506 }
3507
3508 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3509 } else {
3510
3511 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3512 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3513
3514 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3515 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3516 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3517 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3518 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3519
3520 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3521 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3522
3523 rtl931x_sds_rx_rst(sds);
3524
3525 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3526 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3527 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3528 }
3529 break;
3530
3531 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
3532 /* configure 10GR fiber mode=1 */
3533 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3534
3535 /* init fiber_1g */
3536 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3537
3538 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3539 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3540 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3541
3542 /* init auto */
3543 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3544 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3545 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3546 break;
3547
3548 case PHY_INTERFACE_MODE_HSGMII:
3549 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3550 break;
3551
3552 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */
3553 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3554
3555 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3556 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3557 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3558 break;
3559
3560 case PHY_INTERFACE_MODE_SGMII:
3561 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3562 break;
3563
3564 case PHY_INTERFACE_MODE_2500BASEX:
3565 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3566 break;
3567
3568 case PHY_INTERFACE_MODE_QSGMII:
3569 default:
3570 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3571 __func__, phy_modes(mode), sds);
3572 return;
3573 }
3574
3575 rtl931x_cmu_type_set(asds, mode, chiptype);
3576
3577 if (sds >= 2 && sds <= 13) {
3578 if (chiptype)
3579 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3580 else {
3581 val = 0xa0000;
3582 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3583 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3584 if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3585 {
3586 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3587 } else {
3588 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3589 }
3590 val = 0;
3591 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3592 }
3593 }
3594
3595 val = ori & ~BIT(sds);
3596 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3597 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3598
3599 if (mode == PHY_INTERFACE_MODE_XGMII ||
3600 mode == PHY_INTERFACE_MODE_QSGMII ||
3601 mode == PHY_INTERFACE_MODE_HSGMII ||
3602 mode == PHY_INTERFACE_MODE_SGMII ||
3603 mode == PHY_INTERFACE_MODE_USXGMII) {
3604 if (mode == PHY_INTERFACE_MODE_XGMII)
3605 rtl931x_sds_mii_mode_set(sds, mode);
3606 else
3607 rtl931x_sds_fiber_mode_set(sds, mode);
3608 }
3609 }
3610
3611 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3612 {
3613 u32 asds;
3614 int page = rtl931x_sds_cmu_page_get(mode);
3615
3616 sds -= (sds % 2);
3617 sds = sds & ~1;
3618 asds = rtl931x_get_analog_sds(sds);
3619 page += 1;
3620
3621 if (enable) {
3622 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3623 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3624 } else {
3625 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3626 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3627 }
3628
3629 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3630
3631 rtl931x_sds_rst(sds);
3632
3633 return 0;
3634 }
3635
3636 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3637 {
3638 int page = rtl931x_sds_cmu_page_get(mode);
3639 u32 asds, band;
3640
3641 sds -= (sds % 2);
3642 asds = rtl931x_get_analog_sds(sds);
3643 page += 1;
3644 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3645
3646 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3647 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3648 pr_info("%s band is: %d\n", __func__, band);
3649
3650 return band;
3651 }
3652
3653
3654 int rtl931x_link_sts_get(u32 sds)
3655 {
3656 u32 sts, sts1, latch_sts, latch_sts1;
3657 if (0){
3658 u32 xsg_sdsid_0, xsg_sdsid_1;
3659
3660 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3661 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3662
3663 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3664 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3665 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3666 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3667 } else {
3668 u32 asds, dsds;
3669
3670 asds = rtl931x_get_analog_sds(sds);
3671 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3672 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3673
3674 dsds = sds < 2 ? sds : (sds - 1) * 2;
3675 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3676 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3677 }
3678
3679 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3680 sds, sts, sts1, latch_sts, latch_sts1);
3681
3682 return sts1;
3683 }
3684
3685 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3686 {
3687 struct phy_device *phydev = upstream;
3688
3689 rtl8214fc_media_set(phydev, true);
3690
3691 return 0;
3692 }
3693
3694 static void rtl8214fc_sfp_remove(void *upstream)
3695 {
3696 struct phy_device *phydev = upstream;
3697
3698 rtl8214fc_media_set(phydev, false);
3699 }
3700
3701 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3702 .attach = phy_sfp_attach,
3703 .detach = phy_sfp_detach,
3704 .module_insert = rtl8214fc_sfp_insert,
3705 .module_remove = rtl8214fc_sfp_remove,
3706 };
3707
3708 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3709 {
3710 struct device *dev = &phydev->mdio.dev;
3711 int addr = phydev->mdio.addr;
3712 int ret = 0;
3713
3714 /* 839x has internal SerDes */
3715 if (soc_info.id == 0x8393)
3716 return -ENODEV;
3717
3718 /* All base addresses of the PHYs start at multiples of 8 */
3719 devm_phy_package_join(dev, phydev, addr & (~7),
3720 sizeof(struct rtl83xx_shared_private));
3721
3722 if (!(addr % 8)) {
3723 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3724 shared->name = "RTL8214FC";
3725 /* Configuration must be done while patching still possible */
3726 ret = rtl8380_configure_rtl8214fc(phydev);
3727 if (ret)
3728 return ret;
3729 }
3730
3731 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3732 }
3733
3734 static int rtl8214c_phy_probe(struct phy_device *phydev)
3735 {
3736 struct device *dev = &phydev->mdio.dev;
3737 int addr = phydev->mdio.addr;
3738
3739 /* All base addresses of the PHYs start at multiples of 8 */
3740 devm_phy_package_join(dev, phydev, addr & (~7),
3741 sizeof(struct rtl83xx_shared_private));
3742
3743 if (!(addr % 8)) {
3744 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3745 shared->name = "RTL8214C";
3746 /* Configuration must be done whil patching still possible */
3747 return rtl8380_configure_rtl8214c(phydev);
3748 }
3749
3750 return 0;
3751 }
3752
3753 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3754 {
3755 struct device *dev = &phydev->mdio.dev;
3756 int addr = phydev->mdio.addr;
3757
3758 /* All base addresses of the PHYs start at multiples of 8 */
3759 devm_phy_package_join(dev, phydev, addr & (~7),
3760 sizeof(struct rtl83xx_shared_private));
3761
3762 if (!(addr % 8)) {
3763 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3764 shared->name = "RTL8218B (external)";
3765 if (soc_info.family == RTL8380_FAMILY_ID) {
3766 /* Configuration must be done while patching still possible */
3767 return rtl8380_configure_ext_rtl8218b(phydev);
3768 }
3769 }
3770
3771 return 0;
3772 }
3773
3774 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3775 {
3776 struct device *dev = &phydev->mdio.dev;
3777 int addr = phydev->mdio.addr;
3778
3779 if (soc_info.family != RTL8380_FAMILY_ID)
3780 return -ENODEV;
3781 if (addr >= 24)
3782 return -ENODEV;
3783
3784 pr_debug("%s: id: %d\n", __func__, addr);
3785 /* All base addresses of the PHYs start at multiples of 8 */
3786 devm_phy_package_join(dev, phydev, addr & (~7),
3787 sizeof(struct rtl83xx_shared_private));
3788
3789 if (!(addr % 8)) {
3790 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3791 shared->name = "RTL8218B (internal)";
3792 /* Configuration must be done while patching still possible */
3793 return rtl8380_configure_int_rtl8218b(phydev);
3794 }
3795
3796 return 0;
3797 }
3798
3799 static int rtl8218d_phy_probe(struct phy_device *phydev)
3800 {
3801 struct device *dev = &phydev->mdio.dev;
3802 int addr = phydev->mdio.addr;
3803
3804 pr_debug("%s: id: %d\n", __func__, addr);
3805 /* All base addresses of the PHYs start at multiples of 8 */
3806 devm_phy_package_join(dev, phydev, addr & (~7),
3807 sizeof(struct rtl83xx_shared_private));
3808
3809 /* All base addresses of the PHYs start at multiples of 8 */
3810 if (!(addr % 8)) {
3811 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3812 shared->name = "RTL8218D";
3813 /* Configuration must be done while patching still possible */
3814 /* TODO: return configure_rtl8218d(phydev); */
3815 }
3816
3817 return 0;
3818 }
3819
3820 static int rtl838x_serdes_probe(struct phy_device *phydev)
3821 {
3822 int addr = phydev->mdio.addr;
3823
3824 if (soc_info.family != RTL8380_FAMILY_ID)
3825 return -ENODEV;
3826 if (addr < 24)
3827 return -ENODEV;
3828
3829 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3830 if (soc_info.id == 0x8380) {
3831 if (addr == 24)
3832 return rtl8380_configure_serdes(phydev);
3833 return 0;
3834 }
3835
3836 return -ENODEV;
3837 }
3838
3839 static int rtl8393_serdes_probe(struct phy_device *phydev)
3840 {
3841 int addr = phydev->mdio.addr;
3842
3843 pr_info("%s: id: %d\n", __func__, addr);
3844 if (soc_info.family != RTL8390_FAMILY_ID)
3845 return -ENODEV;
3846
3847 if (addr < 24)
3848 return -ENODEV;
3849
3850 return rtl8390_configure_serdes(phydev);
3851 }
3852
3853 static int rtl8390_serdes_probe(struct phy_device *phydev)
3854 {
3855 int addr = phydev->mdio.addr;
3856
3857 if (soc_info.family != RTL8390_FAMILY_ID)
3858 return -ENODEV;
3859
3860 if (addr < 24)
3861 return -ENODEV;
3862
3863 return rtl8390_configure_generic(phydev);
3864 }
3865
3866 static int rtl9300_serdes_probe(struct phy_device *phydev)
3867 {
3868 if (soc_info.family != RTL9300_FAMILY_ID)
3869 return -ENODEV;
3870
3871 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3872
3873 return rtl9300_configure_serdes(phydev);
3874 }
3875
3876 static struct phy_driver rtl83xx_phy_driver[] = {
3877 {
3878 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3879 .name = "Realtek RTL8214C",
3880 .features = PHY_GBIT_FEATURES,
3881 .flags = PHY_HAS_REALTEK_PAGES,
3882 .match_phy_device = rtl8214c_match_phy_device,
3883 .probe = rtl8214c_phy_probe,
3884 .suspend = genphy_suspend,
3885 .resume = genphy_resume,
3886 .set_loopback = genphy_loopback,
3887 },
3888 {
3889 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3890 .name = "Realtek RTL8214FC",
3891 .features = PHY_GBIT_FIBRE_FEATURES,
3892 .flags = PHY_HAS_REALTEK_PAGES,
3893 .match_phy_device = rtl8214fc_match_phy_device,
3894 .probe = rtl8214fc_phy_probe,
3895 .suspend = rtl8214fc_suspend,
3896 .resume = rtl8214fc_resume,
3897 .set_loopback = genphy_loopback,
3898 .set_port = rtl8214fc_set_port,
3899 .get_port = rtl8214fc_get_port,
3900 .set_eee = rtl8214fc_set_eee,
3901 .get_eee = rtl8214fc_get_eee,
3902 },
3903 {
3904 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3905 .name = "Realtek RTL8218B (external)",
3906 .features = PHY_GBIT_FEATURES,
3907 .flags = PHY_HAS_REALTEK_PAGES,
3908 .match_phy_device = rtl8218b_ext_match_phy_device,
3909 .probe = rtl8218b_ext_phy_probe,
3910 .suspend = genphy_suspend,
3911 .resume = genphy_resume,
3912 .set_loopback = genphy_loopback,
3913 .set_eee = rtl8218b_set_eee,
3914 .get_eee = rtl8218b_get_eee,
3915 },
3916 {
3917 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3918 .name = "REALTEK RTL8218D",
3919 .features = PHY_GBIT_FEATURES,
3920 .flags = PHY_HAS_REALTEK_PAGES,
3921 .probe = rtl8218d_phy_probe,
3922 .suspend = genphy_suspend,
3923 .resume = genphy_resume,
3924 .set_loopback = genphy_loopback,
3925 .set_eee = rtl8218d_set_eee,
3926 .get_eee = rtl8218d_get_eee,
3927 },
3928 {
3929 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3930 .name = "REALTEK RTL8221B",
3931 .features = PHY_GBIT_FEATURES,
3932 .flags = PHY_HAS_REALTEK_PAGES,
3933 .suspend = genphy_suspend,
3934 .resume = genphy_resume,
3935 .set_loopback = genphy_loopback,
3936 .read_page = rtl8226_read_page,
3937 .write_page = rtl8226_write_page,
3938 .read_status = rtl8226_read_status,
3939 .config_aneg = rtl8226_config_aneg,
3940 .set_eee = rtl8226_set_eee,
3941 .get_eee = rtl8226_get_eee,
3942 },
3943 {
3944 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3945 .name = "REALTEK RTL8226",
3946 .features = PHY_GBIT_FEATURES,
3947 .flags = PHY_HAS_REALTEK_PAGES,
3948 .suspend = genphy_suspend,
3949 .resume = genphy_resume,
3950 .set_loopback = genphy_loopback,
3951 .read_page = rtl8226_read_page,
3952 .write_page = rtl8226_write_page,
3953 .read_status = rtl8226_read_status,
3954 .config_aneg = rtl8226_config_aneg,
3955 .set_eee = rtl8226_set_eee,
3956 .get_eee = rtl8226_get_eee,
3957 },
3958 {
3959 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3960 .name = "Realtek RTL8218B (internal)",
3961 .features = PHY_GBIT_FEATURES,
3962 .flags = PHY_HAS_REALTEK_PAGES,
3963 .probe = rtl8218b_int_phy_probe,
3964 .suspend = genphy_suspend,
3965 .resume = genphy_resume,
3966 .set_loopback = genphy_loopback,
3967 .set_eee = rtl8218b_set_eee,
3968 .get_eee = rtl8218b_get_eee,
3969 },
3970 {
3971 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3972 .name = "Realtek RTL8380 SERDES",
3973 .features = PHY_GBIT_FIBRE_FEATURES,
3974 .flags = PHY_HAS_REALTEK_PAGES,
3975 .probe = rtl838x_serdes_probe,
3976 .suspend = genphy_suspend,
3977 .resume = genphy_resume,
3978 .set_loopback = genphy_loopback,
3979 .read_status = rtl8380_read_status,
3980 },
3981 {
3982 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3983 .name = "Realtek RTL8393 SERDES",
3984 .features = PHY_GBIT_FIBRE_FEATURES,
3985 .flags = PHY_HAS_REALTEK_PAGES,
3986 .probe = rtl8393_serdes_probe,
3987 .suspend = genphy_suspend,
3988 .resume = genphy_resume,
3989 .set_loopback = genphy_loopback,
3990 .read_status = rtl8393_read_status,
3991 },
3992 {
3993 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3994 .name = "Realtek RTL8390 Generic",
3995 .features = PHY_GBIT_FIBRE_FEATURES,
3996 .flags = PHY_HAS_REALTEK_PAGES,
3997 .probe = rtl8390_serdes_probe,
3998 .suspend = genphy_suspend,
3999 .resume = genphy_resume,
4000 .set_loopback = genphy_loopback,
4001 },
4002 {
4003 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
4004 .name = "REALTEK RTL9300 SERDES",
4005 .features = PHY_GBIT_FIBRE_FEATURES,
4006 .flags = PHY_HAS_REALTEK_PAGES,
4007 .probe = rtl9300_serdes_probe,
4008 .suspend = genphy_suspend,
4009 .resume = genphy_resume,
4010 .set_loopback = genphy_loopback,
4011 .read_status = rtl9300_read_status,
4012 },
4013 };
4014
4015 module_phy_driver(rtl83xx_phy_driver);
4016
4017 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
4018 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
4019 { }
4020 };
4021
4022 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
4023
4024 MODULE_AUTHOR("B. Koblitz");
4025 MODULE_DESCRIPTION("RTL83xx PHY driver");
4026 MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich